ICS9112A-16 Integrated Circuit Systems, Inc. Low Skew Output Buffer General Description Features The ICS9112A-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz. • • • ICS9112A-16 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. • • • • • Zero input - output delay Frequency range 25 - 133 MHz (3.3V) High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 ps Jitter between outputs Skew controlled outputs Skew less than 250 ps between outputs Available in 8 pin 150 mil SOIC or 173 mil TSSOP package. 3.3V ±10% operation The ICS9112A-16 comes in an eight pin 150 mil SOIC or 173 mil TSSOP package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. Block Diagram Pin Configuration 8 pin SOIC, TSSOP 1337K—08/03/07 ICS9112A-16 Pin Descriptions PIN NUMBER 1 PIN NAME 2 REF TYPE IN DESCRIPTION Input reference frequency. 2 CLK2 3 OUT Buffered clock output 3 CLK13 OUT Buffered clock output 4 GND PWR Ground 5 CLK33 OUT Buffered clock output 6 VDD PWR Power Supply (3.3V) OUT Buffered clock output OUT Buffered clock output. Internal feedback on this pin 7 8 CLK4 3 CLKOUT 3 Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 1337K—08/03/07 2 ICS9112A-16 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 – 3.6 V, TA = 0 – 70° C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 0.8 V Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL VIN=0V 19 50.0 µA Input High Current IIH 2.0 V VIN=VDD 0.10 100.0 µA Voltage1 VOL IOL = 25mA 0.25 0.4 V Output High Voltage1 VOH IOH = 25mA Power Down Supply Current IDD REF = 0 MHz 0.3 50.0 µA Supply Current IDD Unloaded oututs at 66.66 MHz SEL inputs at VDD or GND 30.0 40.0 mA Output Low 2.4 2.9 V Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V. 3. Duty cycle measured at 1.4V. 4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs. 1337K—08/03/07 3 ICS9112A-16 Switching Characteristics PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Output period t1 With CL=30pF 40.00 (25) 7.5 (133) ns (MHz) Input period t1 With CL=30pF 40.00 (25) 7.5 (133) ns (MHz) Duty Cycle1 Dt1 Measured at 1.4V; CL=30pF 40.0 50 60 % Duty Cycle1 Dt2 Measured at VDD/2 Fout <66.6MHz 45 50 55 % Rise Time1 tr1 Measured between 0.8V and 2.0V: CL=30pF 1.2 1.5 ns Fall Time1 tf1 Measured between 2.0V and 0.8V; CL=30pF 1.2 1.5 ns Rise Time1 tr1 Measured between 0.8V and 2.0V: CL=5pF 1 ns Fall Time1 tf1 Measured between 2.0V and 0.8V; CL=5pF 1 ns Delay, REF Rising Edge to CLKOUT Rising Edge1, 2 Dr1 Measured at 1.4V Output to Output Skew1 Tskew All outputs equally loaded, CL=20pF Device to Device Skew1 Tdsk-Tdsk Measured at VDD/2 on the CLKOUT pins of devices Cycle to Cycle Jitter1 Tcyc-Tcyc PLL Lock Time1 0 ±350 ps 250 ps 700 ps Measured at 66.66 MHz, loaded outputs 200 ps tLOCK Stable power supply, valid clock presented on REF pin 1.0 ms Jitter ; Absolute Jitter1 Tjabs @ 10,000 cycles CL=30pF 70 100 ps Jitter ; 1 - Sigma1 Tj1s @ 10,000 cycles CL=30pF 14 30 ps 0 -100 Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. REF input has a threshold voltage of 1.4V 3. All parameters expected with loaded outputs 1337K—08/03/07 4 ICS9112A-16 Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. REF input and all outputs loaded Equally REF input and CLK(1_4) outputs loaded equally, with CLKOUT loaded Less. REF input and CLK(1-4) outputs loaded equally, with CLKOUT loaded More. Timing diagrams with different loading configurations 1337K—08/03/07 5 ICS9112A-16 150 mil (Narrow Body) SOIC C N SYMBOL A A1 B C D E e H h L N a L INDEX AREA H E h x 45° 1 2 α D A N B In Inches COMMON DIMENSIONS MIN MAX .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 SEE VARIATIONS .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 SEE VARIATIONS 0° 8° VARIATIONS A1 e In Millimeters COMMON DIMENSIONS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 SEE VARIATIONS 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 SEE VARIATIONS 0° 8° SEATING PLANE .10 (.004) 8 D mm. MIN 4.80 D (inch) MAX 5.00 MIN .1890 MAX .1968 Reference Doc.: JEDEC Publication 95, MS-012 10-0030 150 mil (Narrow Body) SOIC Ordering Information ICS9112AM-16LF-T Example: ICS XXXX A M PPP LF-T Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M = SOIC Revision Designator Device Type Prefix ICS, AV = Standard Device 1337K—08/03/07 6 ICS9112A-16 In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D SEE VARIATIONS E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS α 0° 8° aaa -0.10 c N L E1 E INDEX AREA 1 2 α D In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 A A2 VARIATIONS A1 N -Ce 8 SEATING PLANE b D mm. MIN 2.90 D (inch) MAX 3.10 MIN .114 MAX .122 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 aaa C 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS9112AG-16LF-T Example: ICS XXXX A G PPP LF-T Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator Device Type 1337K—08/03/07 Prefix ICS, AV = Standard Device 7 ICS9112A-16 Revision History Rev. H I J K Issue Date 09/01/04 11/02/04 04/26/07 08/03/07 Description Updated Lead Free information Added LN option Removed LN option superceded by LF. Updated Switching Characteristics Rise/Fall time. 1337K—08/03/07 8 Page # 6-7 6-7 6-7 4