M MCP3021 Low Power 10-Bit A/D Converter With I2C™ Interface Features Description • • • • • The Microchip Technology Inc. MCP3021 is a successive approximation A/D converter (ADC) with 10-bit resolution. Available in the SOT-23 package, this device provides one single-ended input with very low power consumption. Based on an advanced CMOS technology, the MCP3021 provides a low maximum conversion current and standby current of 250 µA and 1 µA, respectively. Low current consumption, combined with the small SOT-23 package, make this device ideal for battery-powered and remote data acquisition applications. • • • • • • • • 10-bit resolution ±1 LSB DNL, ±1 LSB INL max. 250 µA max conversion current 5 nA typical standby current, 1 µA max. I2C™ compatible serial interface - 100 kHz I2C Standard mode - 400 kHz I2C Fast mode Up to 8 devices on single 2-wire bus 22.3 ksps in I2C Fast mode Single-ended analog input channel On-chip sample and hold On-chip conversion clock Single supply specified operation: 2.7V to 5.5V Temperature range: - Extended: -40°C to +125°C Small SOT-23 package The MCP3021 runs on a single supply voltage that operates over a broad range of 2.7V to 5.5V. This device also provides excellent linearity of ±1 LSB differential non-linearity (DNL) and ±1 LSB integral nonlinearity (INL), maximum. Applications • • • • • Communication to the MCP3021 is performed using a 2-wire I2C compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are available with the device. An on-chip conversion clock enables independent timing for the I2C and conversion clocks. The device is also addressable, allowing up to eight devices on a single 2-wire bus. Data Logging Multi-zone Monitoring Hand Held Portable Applications Battery Powered Test Equipment Remote or Isolated Data Acquisition Functional Block Diagram VDD VSS Package Type DAC 5-Pin SOT-23A VSS 2 MCP3021 VDD 1 5 SCL AIN – Sample and Hold Comparator + Clock Control Logic AIN 3 10-Bit SAR 4 SDA I2C™ Interface SCL 2003 Microchip Technology Inc. SDA DS21805A-page 1 MCP3021 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name Absolute Maximum Ratings † VDD...................................................................................7.0V Analog input pin w.r.t. V SS .......... ............. -0.6V to VDD +0.6V SDA and SCL pins w.r.t. VSS........... .........-0.6V to VDD +1.0V Storage temperature .....................................-65°C to +150°C Function VDD +2.7V to 5.5V Power Supply VSS Ground AIN Analog Input SDA Serial Data In/Out SCL Serial Clock In Ambient temp. with power applied ................-65°C to +125°C Maximum Junction Temperature .......... .........................150°C ESD protection on all pins (HBM) ......... ........................≥ 4 kV † Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5.0V, VSS = GND, R PU = 2 kΩ TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameters Sym Min Typ Max Units Conditions DC Accuracy Resolution 10 bits Integral Nonlinearity INL — ±0.25 ±1 LSB Differential Nonlinearity DNL — ±0.25 ±1 LSB Offset Error — ±0.75 ±3 LSB Gain Error — -1 ±3 LSB — -70 — dB No missing codes Dynamic Performance Total Harmonic Distortion THD VIN = 0.1V to 4.9V @ 1 kHz Signal to Noise and Distortion SINAD — 60 — dB VIN = 0.1V to 4.9V @ 1 kHz Spurious Free Dynamic Range SFDR — 74 — dB VIN = 0.1V to 4.9V @ 1 kHz VSS-0.3 — VDD+0.3 V 2.7V ≤ VDD ≤ 5.5V -1 — +1 µA V Analog Input Input Voltage Range Leakage Current SDA/SCL (open-drain output) Data Coding Format High-level input voltage Straight Binary VIH 0.7 VDD — — Low-level input voltage VIL — — 0.3 VDD V Low-level output voltage VOL — — 0.4 V IOL = 3 mA, RPU = 1.53 kΩ VHYST — 0.05VDD — V fSCL = 400 kHz only Hysteresis of Schmitt trigger inputs Note 1: 2: 3: 4: 5: Sample time is the time between conversions after the address byte has been sent to the converter. Refer to Figure 5-6. This parameter is periodically sampled and not 100% tested. RPU = Pull-up resistor on SDA and SCL. SDA and SCL = VSS to VDD at 400 kHz. tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to SCL. DS21805A-page 2 2003 Microchip Technology Inc. MCP3021 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5.0V, VSS = GND, R PU = 2 kΩ TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameters Input leakage current Output leakage current Sym Min Typ Max Units Conditions ILI -1 — +1 µA VIN = VSS to VDD ILO -1 — +1 µA VOUT = VSS to VDD CIN, C OUT — — 10 pF TAMB = 25°C, f = 1 MHz; (Note 2) CB — — 400 pF SDA drive low, 0.4V Operating Voltage VDD 2.7 — 5.5 V Conversion Current IDD — 175 250 µA Standby Current IDDS — 0.005 1 µA SDA, SCL = VDD Active bus current IDDA — — 120 µA Note 4 Conversion Time tCONV — 8.96 — µs Note 5 Analog Input Acquisition Time tACQ — 1.12 — µs Note 5 Sample Rate fSAMP — — 22.3 ksps Pin capacitance (all inputs/outputs) Bus Capacitance Power Requirements Conversion Rate Note 1: 2: 3: 4: 5: fSCL = 400 kHz (Note 1) Sample time is the time between conversions after the address byte has been sent to the converter. Refer to Figure 5-6. This parameter is periodically sampled and not 100% tested. RPU = Pull-up resistor on SDA and SCL. SDA and SCL = VSS to VDD at 400 kHz. tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to SCL. TEMPERATURE SPECIFICATIONS Electrical Characteristics: All parameters apply across the operating voltage range. Parameters Symbol Min Typ Max Units Extended Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C θJA — 256 — °C/W Conditions Temperature Ranges Thermal Package Resistances Thermal Resistance, 5L-SOT23A 2003 Microchip Technology Inc. DS21805A-page 3 MCP3021 TIMING SPECIFICATIONS Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TA = -40°C to +85°C. Parameters Sym Min Typ Max Units Clock frequency fSCL 0 — 100 kHz Clock high time THIGH 4000 — — ns Clock low time TLOW 4700 — — ns SDA and SCL rise time TR — — 1000 ns From VIL to VIH (Note 1) SDA and SCL fall time TF — — 300 ns From VIL to VIH (Note 1) THD:STA 4000 — — ns START condition setup time TSU:STA 4700 — — ns Data input setup time TSU:DAT 250 — — ns STOP condition setup time TSU:STO 4000 — — ns STOP condition hold time 2C I Conditions Standard Mode START condition hold time THD:STD 4000 — — ns Output valid from clock TAA — — 3500 ns Bus free time TBUF 4700 — — ns Note 2 Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1) I2C Fast Mode Clock frequency FSCL 0 — 400 kHz Clock high time THIGH 600 — — ns Clock low time TLOW 1300 — — ns SDA and SCL rise time TR 20 + 0.1CB — 300 ns From VIL to VIH (Note 1) SDA and SCL fall time TF 20 + 0.1CB — 300 ns From VIL to VIH (Note 1) START condition hold time THD:STA 600 — — ns START condition setup time TSU:STA 600 — — ns Data input hold time THD:DAT 0 — 0.9 ms Data input setup time TSU:DAT 100 — — ns STOP condition setup time TSU:STO 600 — — ns STOP condition hold time THD:STD 600 — — ns Output valid from clock TAA — — 900 ns Bus free time TBUF 1300 — — ns Note 2 Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1) Note 1: 2: This parameter is periodically sampled and not 100% tested. Time the bus must be free before a new transmission can start. THIGH TF SCL SDA OUT FIGURE 1-1: DS21805A-page 4 TR TSU:STA TLOW SDA IN VHYS TSP THD:DAT TSU:DAT TSU:STO THD:STA TAA TBUF Standard and Fast Mode Bus Timing Data. 2003 Microchip Technology Inc. MCP3021 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.25 1 0.251 0.20 0.8 0.20 0.8 0.15 0.6 0.15 0.6 Positive INL 0.10 0.4 INL (LSB) INL (LSB) 0.10 0.4 0.005 0.2 0 -0.005 -0.2 Negative INL -0.10 -0.4 0 -0.005 -0.2 -0.10 -0.4 -0.15 -0.6 -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 Negative INL -0.25 -1 -0.25 -1 0 100 FIGURE 2-1: 200 2 I C Bus Rate (kHz) 300 0 400 FIGURE 2-4: (VDD = 2.7V). 300 400 INL vs. Clock Rate 0.25 1 0.20 0.8 Positive INL 0.15 0.6 0.15 0.6 0.10 0.4 0.005 0.2 0.005 0.2 INL (LSB) 0.10 0.4 0 -0.005 -0.2 Negative INL -0.10 -0.4 Positive INL 0 -0.005 -0.2 -0.10 -0.4 -0.15 -0.6 -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 Negative INL -0.25 -1 3 3.5 4 4.5 5 2.5 5.5 3 3.5 VDD (V) 4 4.5 5 5.5 VDD (V) FIGURE 2-2: INL vs. VDD - I2C Standard Mode (fSCL = 100 kHz). FIGURE 2-5: (fSCL = 400 kHz). 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 INL (LSB) INL (LSB) 200 2 INL vs. Clock Rate. 0.20 0.8 -0.25 -1 2.5 100 I C Bus Rate (kHz) 0.25 1 INL (LSB) Positive INL 0.005 0.2 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 INL vs. VDD - I2C Fast Mode -0.5 0 256 512 Digital Code FIGURE 2-3: INL vs. Code (Representative Part). 2003 Microchip Technology Inc. 768 1024 0 256 512 768 1024 Digital Code FIGURE 2-6: INL vs. Code (Representative Part, VDD = 2.7V). DS21805A-page 5 MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.25 1 0.20 0.8 0.25 1 0.15 0.6 Positive INL 0.10 0.4 0.005 0.2 INL (LSB) INL (LSB) 0.20 0.8 Positive INL 0.15 0.6 0.10 0.4 0 -0.005 -0.2 -0.10 -0.4 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative INL -0.15 -0.6 -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 -0.25 -1 Negative INL -0.25 -1 -50 -25 0 25 50 75 100 125 -50 -25 0 FIGURE 2-7: INL vs. Temperature. FIGURE 2-10: (VDD = 2.7V). 0.25 1 1 0.25 0.20 0.8 0.20 0.8 0.15 0.6 50 75 100 125 INL vs. Temperature 0.15 0.6 Positive DNL 0.10 0.4 DNL (LSB) 0.10 0.4 DNL (LSB) 25 Temperature (°C) Temperature (°C) 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 0 -0.005 -0.2 -0.10 -0.4 -0.15 -0.6 Negative DNL -0.15 -0.6 -0.20 -0.8 Positive DNL 0.005 0.2 Negative DNL -0.20 -0.8 -0.25 -1 -0.25 -1 0 100 200 300 400 0 100 200 300 400 2 I C Bus Rate (kHz) FIGURE 2-8: 2 I C Bus Rate (kHz) DNL vs. Clock Rate. FIGURE 2-11: (VDD = 2.7V). 1 0.25 1 0.25 0.20 0.8 0.20 0.8 0.15 0.6 0.15 0.6 Positive DNL 0.10 0.4 0.10 0.4 0.005 0.2 DNL (LSB) DNL (LSB) DNL vs. Clock Rate 0 -0.005 -0.2 Negative DNL -0.10 -0.4 Positive DNL 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.6 -0.20 -0.8 -0.15 -0.6 -0.20 -0.8 -0.25 -1 -0.25 -1 2.5 3 3.5 4 4.5 5 5.5 V DD (V) FIGURE 2-9: DNL vs. VDD - I2C Standard Mode (fSCL = 100 kHz). DS21805A-page 6 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 2-12: DNL vs. VDD - I2C Fast Mode (fSCL = 400 kHz). 2003 Microchip Technology Inc. MCP3021 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 DNL (LSB) DNL (LSB) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.1 0 -0.1 0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 256 512 768 1024 0 256 512 Digital Code 0.25 1 1 0.25 0.20 0.8 0.20 0.8 0.15 0.6 0.15 0.6 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.6 0 25 50 0 -0.005 -0.2 -0.10 -0.4 -0.25 -1 -50 -0.25 -1 -25 0.005 0.2 Negative DNL -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 -50 Positive DNL 0.10 0.4 Positive DNL DNL (LSB) DNL (LSB) 0.10 0.4 75 100 125 -25 0 25 Temperature (°C) FIGURE 2-14: DNL vs. Temperature. FIGURE 2-17: (VDD = 2.7V). 0 0.251 -0.025 -0.1 0.225 0.9 -0.05 -0.2 0.20.8 -0.075 -0.3 -0.1 -0.4 -0.125 -0.5 Fast Mode (f SCL=100 kHz) Standard Mode (f SCL=400 kHz) -0.15 -0.6 -0.175 -0.7 -0.2 -0.8 100 125 DNL vs. Temperature fSCL = 100 kHz & 400 kHz 0.175 0.7 0.15 0.6 0.125 0.5 0.10.4 0.075 0.3 0.025 0.1 -0.25 -1 3 3.5 4 4.5 5 5.5 0 0 2.5 3 VDD (V) FIGURE 2-15: 75 0.05 0.2 -0.225 -0.9 2.5 50 Temperature (°C) Offset Error (LSB) Gain Error (LSB) 1024 FIGURE 2-16: DNL vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-13: DNL vs. Code (Representative Part). 0 768 Digital Code Gain Error vs. VDD. 2003 Microchip Technology Inc. FIGURE 2-18: 3.5 4 VDD (V) 4.5 5 5.5 Offset Error vs. VDD. DS21805A-page 7 MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 1.5 0.375 0.50 2 0.45 1.8 0.40 1.6 Offset Error (LSB) Gain Error (LSB) 0.2501 0.5 0.125 0 VDD = 2.7V -0.125 -0.5 -0.250 -1 -25 0 25 50 75 100 VDD = 5V 0.30 1.2 0.25 1 0.20 0.8 0.15 0.6 0.10 0.4 0.05 0.2 00 VDD = 5V -0.375 -1.5 -50 0.35 1.4 125 -50 VDD = 2.7V -25 0 Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Temperature. 84 96 75 100 125 Offset Error vs. 84 96 72 84 60 72 VDD = 5V 60 72 48 60 SINAD (dB) SNR (dB) 50 VDD = 5V 72 84 VDD = 2.7V 36 48 Y 48 60 24 36 12 24 12 24 1 VDD = 2.7V 36 48 24 36 120 120 10 1 10 Input Frequency (kHz) FIGURE 2-20: Input Frequency (kHz) SNR vs. Input Frequency. FIGURE 2-23: -120 84 96 -12 -24 72 84 -24 -36 60 72 -36 -48 SINAD (dB) THD (dB) 25 Temperature (°C) V DD = 5V VDD = 2.7V -48 -60 -60 -72 SINAD vs. Input Frequency. VDD = 5V 48 60 VDD = 2.7V 36 48 24 36 -72 -84 12 24 -84 -96 1 10 120 -40 Input Frequency (kHz) FIGURE 2-21: DS21805A-page 8 THD vs. Input Frequency. -30 -20 -10 0 Input Signal Level (dB) FIGURE 2-24: Level. SINAD vs. Input Signal 2003 Microchip Technology Inc. MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 10 12 10 12 9.95 11.95 9.5 11.5 9.90 11.9 ENOB (rms) ENOB (rms) 9.85 11.85 9.80 11.8 9.75 11.75 9.70 11.7 9.60 11.6 9.55 11.55 8.0 10 7.7 9.5 9.50 11.5 7.0 9 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 96 84 1 10 Input Frequency (kHz) ENOB vs. VDD. FIGURE 2-25: FIGURE 2-28: ENOB vs. Input Frequency. 10 VDD = 5 V 84 72 -10 Amplitude (dB) 72 60 VDD = 2.7V 48 60 36 48 24 36 -30 -50 -70 -90 -110 12 24 -130 120 1 0 10 500 1000 FIGURE 2-26: 1500 2000 2500 Frequency (Hz) Input Frequency (kHz) SFDR vs. Input Frequency. 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 FIGURE 2-29: Spectrum Using I2C Standard Mode (Representative Part, 1 kHz Input Frequency). 250 200 IDD (µA) Amplitude (dB) VDD = 5V 8.5 10.5 9.65 11.65 SFDR (dB) VDD = 2.7V 9.0 11 150 100 50 0 0 2000 4000 6000 8000 10000 2.5 3 FIGURE 2-27: Spectrum Using I2C Fast Mode (Representative Part, 1 kHz Input Frequency). 2003 Microchip Technology Inc. 3.5 4 4.5 5 5.5 VDD (V) Frequency (Hz) FIGURE 2-30: IDD (Conversion) vs. VDD. DS21805A-page 9 MCP3021 200 100 180 90 160 80 140 70 120 100 IDDA (µA) IDD (µA) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. VDD = 5V 80 60 50 VDD = 5V 40 30 60 VDD = 2.7V 20 40 VDD = 2.7V 20 10 0 0 0 100 200 300 0 400 100 200 2 400 I C Clock Rate (kHz) IDD (Conversion) vs. Clock FIGURE 2-31: Rate. 300 2 I C Clock Rate (kHz) FIGURE 2-34: Rate. IDDA (Active Bus) vs. Clock 100 250 90 80 200 150 100 VDD = 5V 70 IDDA (µA) IDD (µA) VDD = 5V V DD = 2.7V 60 50 40 30 VDD = 2.7V 20 50 10 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 FIGURE 2-32: Temperature. 50 75 100 125 Temperature (°C) Temperature (°C) IDD (Conversion) vs. FIGURE 2-35: Temperature. IDDA (Active Bus) vs. 60 100 90 50 80 40 60 IDDS (pA) IDDA (µA) 70 50 40 30 20 30 20 10 10 0 0 2.5 3 3.5 4 4.5 5 5.5 2.5 3 VDD (V) FIGURE 2-33: DS21805A-page 10 IDDA (Active Bus) vs. VDD. 3.5 4 4.5 5 5.5 V DD (V) FIGURE 2-36: IDDS (Standby) vs. VDD. 2003 Microchip Technology Inc. MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 2.1 Test Circuit 1000 100 VDD = 5V IDDS (nA) 10 1 0.1 10 µF 0.01 0.1 µF 2 kΩ 0.001 AIN 0.0001 -50 -25 0 25 50 75 100 125 VIN Temperature (°C) VDD MCP3021 2 kΩ SDA VSS SCL IDDS (Standby) vs. FIGURE 2-37: Temperature. VCM = 2.5V 2 Analog Input Leakage (nA) 1.8 1.6 FIGURE 2-39: 1.4 Typical Test Configuration. 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 Temperature (°C) FIGURE 2-38: Temperature. Analog Input Leakage vs. 2003 Microchip Technology Inc. DS21805A-page 11 MCP3021 3.0 PIN FUNCTIONS TABLE 3-1: PIN FUNCTION TABLE Name 3.1 Function VDD +2.7V to 5.5V Power Supply VSS Ground AIN Analog Input SDA Serial Data In/Out SCL Serial Clock In VDD and VSS The VDD pin, with respect to VSS, provides power to the device, as well as a voltage reference for the conversion process. Refer to Section 6.4, “Device Power and Layout Considerations”, for tips on power and grounding. 3.2 Analog Input (AIN) AIN is the input pin to the sample and hold circuitry of the Successive Approximation Register (SAR) converter. Care should be taken in driving this pin. Refer to Section 6.1, “Driving the Analog Input”. For proper conversions, the voltage on this pin can vary from VSS to VDD. DS21805A-page 12 3.3 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VDD (typically 10 kΩ for 100 kHz and 2 kΩ for 400 kHz SCL clock speeds (refer to Section 6.2, “Connecting to the I2C Bus”). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions (refer to Section 5.1, “I2C Bus Characteristics”). 3.4 Serial Clock (SCL) SCL is an input pin used to synchronize the data transfer to and from the device on the SDA pin and is an open-drain terminal. Therefore, the SCL bus requires a pull-up resistor to VDD (typically, 10 kΩ for 100 kHz and 2 kΩ for 400 kHz SCL clock speeds. Refer to Section 6.2, “Connecting to the I2C Bus”). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions (refer to Section 6.1, “Driving the Analog Input”). 2003 Microchip Technology Inc. MCP3021 4.0 DEVICE OPERATION 4.2 The conversion time is the time required to obtain the digital result once the analog input is disconnected from the holding capacitor. With the MCP3021, the specified conversion time is typically 8.96 µs. This time is dependent on the internal oscillator and independent of SCL. The MCP3021 employs a classic SAR architecture. This architecture uses an internal sample and hold capacitor to store the analog input while the conversion is taking place. At the end of the acquisition time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. The acquisition time and conversion is self-timed using an internal clock. After each conversion, the results are stored in a 10-bit register that can be read at any time. 4.3 Acquisition Time (tACQ) The acquisition time is the amount of time the sample cap array is acquiring charge. Communication with the device is accomplished with a 2-wire I2C interface. Maximum sample rates of 22.3 ksps are possible with the MCP3021 in a continuous conversion mode and an SCL clock rate of 400 kHz. 4.1 Conversion Time (tCONV) The acquisition time is, typically, 1.12 µs. This time is dependent on the internal oscillator and independent of SCL. 4.4 Digital Output Code Sample Rate Sample rate is the inverse of the maximum amount of time that is required from the point of acquisition of the first conversion to the point of acquisition of the second conversion. The digital output code produced by the MCP3021 is a function of the input signal and power supply voltage (VDD). As the V DD level is reduced, the LSB size is reduced accordingly. The theoretical LSB size is shown below. The sample rate can be measured either by single or continuous conversions. A single conversion includes a Start Bit, Address Byte, Two Data Bytes and a Stop bit. This sample rate is measured from one Start Bit to the next Start Bit. EQUATION VD D LSB SIZE = -----------1024 For continuous conversions (requested by the Master by issuing an acknowledge after a conversion), the maximum sample rate is measured from conversion to conversion, or a total of 18 clocks (two data bytes and two Acknowledge bits). Refer to Section 5-2, “Device Addressing”. VDD = Supply voltage The output code of the MCP3021 is transmitted serially with MSB first, the format of the code being straight binary. Output Code 11 1111 1111 11 1111 1110 (1023) (1022) 00 0000 0011 (3) 00 0000 0010 (2) 00 0000 0001 (1) 00 0000 0000 (0) .5 LSB 1.5 LSB 2.5 LSB FIGURE 4-1: AIN VDD-1.5 LSB VDD-2.5 LSB Transfer Function. 2003 Microchip Technology Inc. DS21805A-page 13 MCP3021 4.5 Differential Non-Linearity (DNL) In the ideal ADC transfer function, each code has a uniform width. That is, the difference in analog input voltage is constant from one code transition point to the next. DNL specifies the deviation of any code in the transfer function from an ideal code width of 1 LSB. The DNL is determined by subtracting the locations of successive code transition points after compensating for any gain and offset errors. A positive DNL implies that a code is longer than the ideal code width, while a negative DNL implies that a code is shorter than the ideal width. 4.6 Integral Non-Linearity (INL) INL is a result of cumulative DNL errors and specifies how much the overall transfer function deviates from a linear response. The method of measurement used in the MCP3021 ADC to determine INL is the “end-point” method. 4.7 Offset Error Offset error is defined as a deviation of the code transition points that are present across all output codes. This has the effect of shifting the entire A/D transfer function. The offset error is measured by finding the difference between the actual location of the first code transition and the desired location of the first transition. The ideal location of the first code transition is located at 1/2 LSB above VSS. 4.8 Gain Error The gain error determines the amount of deviation from the ideal slope of the ADC transfer function. Before the gain error is determined, the offset error is measured and subtracted from the conversion result. The gain error can then be determined by finding the location of the last code transition and comparing that location to the ideal location. The ideal location of the last code transition is 1.5 LSBs below full-scale or VDD. 4.9 Conversion Current (IDD) The average amount of current over the time required to perform a 10-bit conversion. 4.10 Active Bus Current (IDDA) The average amount of current over the time required to monitor the I2C bus. Any current the device consumes while it is not being addressed is referred to as Active Bus current. 4.11 Standby Current (IDDS) The average amount of current required while no conversion is occurring and while no data is being output (i.e., SCL and SDA lines are quiet). 4.12 I2C Standard Mode Timing I2C specification where the frequency of SCL is 100 kHz. 4.13 I2C Fast Mode Timing I2C specification where the frequency of SCL is 400 kHz. DS21805A-page 14 2003 Microchip Technology Inc. MCP3021 5.0 SERIAL COMMUNICATIONS 5.1 I2C Bus Characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (refer to Figure 5-1). 5.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 5.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a START condition. All commands must be preceded by a START condition. 5.1.3 STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a STOP condition. All operations must be ended with a STOP condition. 5.1.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is determined by the master device and is unlimited. 5.1.5 ACKNOWLEDGE Each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During reads, a master device must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave (NAK). In this case, the slave (MCP3021) will release the bus to allow the master device to generate the STOP condition. The MCP3021 supports a bidirectional 2-wire bus and data transmission protocol. The device that sends data onto the bus is the transmitter and the device receiving data is the receiver. The bus has to be controlled by a master device that generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions, while the MCP3021 works as a slave device. Both master and slave devices can operate as either transmitter or receiver, but the master device determines which mode is activated. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. (A) (B) (D) (D) (C) (A) SCL SDA START CONDITION FIGURE 5-1: ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE STOP CONDITION Data Transfer Sequence on the Serial Bus. 2003 Microchip Technology Inc. DS21805A-page 15 MCP3021 Device Addressing 5.3 The address byte is the first byte received following the START condition from the master device. The first part of the control byte consists of a 4-bit device code, which is set to 1001 for the MCP3021. The device code is followed by three address bits: A2, A1 and A0. The default address bits are 101 (contact the Microchip factory for additional address bit options).The address bits allow up to eight MCP3021 devices on the same bus and are used to determine which device is accessed. The eighth bit of the slave address determines if the master device wants to read conversion data or write to the MCP3021. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected. There are no writable registers on the MCP3021, therefore, this bit must be set to a ’1’ to initiate a conversion. The MCP3021 is a slave device that is compatible with the 2-wire I2C serial interface protocol. A hardware connection diagram is shown in Figure 6-2. Communication is initiated by the microcontroller (master device), which sends a START bit followed by the address byte. On completion of the conversion(s) performed by the MCP3021, the microcontroller must send a STOP bit to stop the communication. The last bit in the device address byte is the R/W bit. When this bit is a logic ‘1’, a conversion will be executed. Setting this bit to logic ‘0’ will also result in an “acknowledge” (ACK) from the MCP3021, with the device then releasing the bus. This can be used for device polling (refer to Section 6.3, “Device Polling”). START Executing a Conversion This section will describe the details of communicating with the MCP3021 device. Initiating the sample and hold acquisition, reading the conversion data and executing multiple conversions will be discussed. 5.3.1 INITIATING THE SAMPLE AND HOLD The acquisition and conversion of the input signal begins with the falling edge of the R/W bit of the address byte. At this point, the internal clock initiates the sample, hold and conversion cycle, all of which are internal to the ADC. tACQ + tCONV is initiated here Address Byte SCL 1 2 3 4 5 SDA 1 0 0 1 A2 A1 A0 R/W Start Bit Device bits FIGURE 5-3: Address Byte. 6 7 8 9 ACK 5.2 Address bits Initiating the Conversion, tACQ + tCONV is initiated here READ/WRITE Lower Data Byte (n) SLAVE ADDRESS R/W A 17 18 19 20 21 22 23 24 25 26 0 1 0 Device Code 1 1 0 1 Address Bits1 Contact Microchip for additional address bits. FIGURE 5-2: DS21805A-page 16 SDA D6 D5 D4 D3 D2 D1 D0 X X ACK 1 ACK SCL FIGURE 5-4: Initiating the Conversion, Continuous Conversions. Device Addressing. 2003 Microchip Technology Inc. MCP3021 The input signal will initially be sampled with the first falling edge of the clock following the transmission of a logic-high R/W bit. Additionally, with the rising edge of the SCL, the ADC will transmit an acknowledge bit (ACK = 0). The master must release the data bus during this clock pulse to allow the MCP3021 to pull the line low (refer to Figure 5-3). For consecutive samples, sampling begins on the last bit of the lower data byte. Refer to Figure 5-6 for timing diagram. 5.3.2 READING THE CONVERSION DATA After the MCP3021 acknowledges the address byte, the device will transmit four ‘0’ bits followed by the upper four data bits of the conversion. The master device will then acknowledge this byte with an ACK = low. With the following six clock pulses, the MCP3021 will transmit the lower six data bits from the conversion. The last two bits are “don’t cares”, and do not contain valid data. The master then sends an ACK = high, indicating to the MCP3021 that no more data is requested. The master can then send a stop bit to end the transmission. tACQ + tCONV is initiated here 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL S T A R T Address Byte S T O P Lower Data Byte A N D D D D A A A R C D D D D D D / C S 1 0 0 1 A P 2 1 0 W K 0 0 0 0 9 8 7 6 K 5 4 3 2 1 0 X X A K SDA Device bits FIGURE 5-5: 5.3.3 Upper Data Byte Address bits Executing a Conversion. CONSECUTIVE CONVERSIONS For consecutive samples, sampling begins on the falling edge of the last bit of the lower data byte. See Figure 5-6 for timing. tACQ + tCONV is initiated here tACQ + t CONV is initiated here fSAMP = 22.3 ksps (fCLK = 400 kHz) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL S T A R T SDA Address Byte Lower Data Byte (n) A R A D D D A C D D D D D D C 0 S 1 0 0 1 A2 A1 A0 / C 0 0 0 0 D 7 6 5 4 3 2 1 0 X X 9 8 K K K W Device bits FIGURE 5-6: Upper Data Byte (n) Address bits Continuous Conversion. 2003 Microchip Technology Inc. DS21805A-page 17 MCP3021 6.0 APPLICATIONS INFORMATION 6.1 Driving the Analog Input The MCP3021 has a single-ended analog input (AIN). For proper conversion results, the voltage at the AIN pin must be kept between VSS and VDD. If the converter has no offset error, gain error, INL or DNL errors and the voltage level of AIN is equal to or less than VSS + 1/2 LSB, the resultant code will be 000h. Additionally, if the voltage at AIN is equal to or greater than VDD - 1.5 LSB, the output code will be 1FFh. The analog input model is shown in Figure 6-1. In this diagram, the source impedance (RSS) adds to the internal sampling switch (RS) impedance, directly affecting the time required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance increases the offset error, gain error and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP6022, which has a closed-loop output impedance of tens of ohms. VDD RSS Sampling Switch VT = 0.6V AIN CPIN 7 pF VA VT = 0.6V SS RS = 1 kΩ C SAMPLE = DAC capacitance = 20 pF ILEAKAGE ±1 nA VSS Legend VA RSS AIN CPIN VT ILEAKAGE SS RS CSAMPLE = = = = = = = = = signal source source impedance analog input pad analog input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance FIGURE 6-1: 6.2 Analog Input Model, AIN. Connecting to the I2C Bus The I2C bus is an open collector bus, requiring pull-up resistors connected to the SDA and SCL lines. This configuration is shown in Figure 6-2. The number of devices connected to the bus is limited only by the maximum bus capacitance of 400 pF. A possible configuration using multiple devices is shown in Figure 6-3. SDA SCL VDD PICmicro® Microcontroller PIC16F876 Microcontroller RPU RPU MCP3021 SDA AIN SCL 24LC01 EEPROM Analog Input Signal MCP3021 10-bit ADC TC74 Temperature Sensor RPU is typically: 10 kΩ for fSCL = 100 kHz 2 kΩ for fSCL = 400 kHz FIGURE 6-2: Bus. DS21805A-page 18 Pull-up Resistors on I2C FIGURE 6-3: Multiple Devices on I2C Bus. 2003 Microchip Technology Inc. MCP3021 6.3 Device Polling In some instances, it may be necessary to test for MCP3021 presence on the I2C bus without performing a conversion, described in Figure 6-4. Here we are setting the R/W bit in the address byte to a zero. The MCP3021 will then acknowledge by pulling SDA low during the ACK clock and then release the bus back to the I2C master. A stop or repeated start bit can then be issued from the master and I2C communication can continue. SCL SDA Start Bit 1 2 3 4 8 9 1 0 0 1 A2 A1 A0 0 ACK Address Byte Device bits 5 6 7 precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. The MCP3021 should be connected entirely to the analog ground place, as well as the analog power trace. The pull-up resistors can be placed close to the microcontroller and tied to the digital power or VCC. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors (Figure 6-6). For more information on layout tips when using the MCP3021 or other ADC devices, refer to AN688, “Layout Tips for 12-Bit A/D Converter Applications”. VDD Start Bit Address bits R/W Connection MCP3021 response FIGURE 6-4: 6.4.1 Device Power and Layout Considerations POWERING THE MCP3021 VDD supplies the power to the device as well as the reference voltage. A bypass capacitor value of 0.1 µF is recommended. Adding a 10 µF capacitor in parallel is recommended to attenuate higher frequency noise present in some systems. VDD VCC 10 µF 0.1 µF VDD AIN FIGURE 6-5: 6.4.2 Device 4 Device 1 MCP3021 SCL SDA RPU RPU To Microcontroller Device 3 Device 2 FIGURE 6-6: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. 6.4.3 The MCP3021 uses VDD as power and also as a reference. In some applications, it may be necessary to use a stable reference to achieve the required accuracy. Figure 6-7 shows an example using the MCP1541 as a 4.096V 2% reference. VDD Powering the MCP3021. LAYOUT CONSIDERATIONS When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from VDD to ground should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra 2003 Microchip Technology Inc. USING A REFERENCE FOR SUPPLY 0.1 µF MCP1541 4.096V Reference VCC 1 µF CL VDD AIN MCP3021 SCL SDA RPU To Microcontroller 6.4 Device Polling. FIGURE 6-7: Stable Power and Reference Configuration. DS21805A-page 19 MCP3021 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 5-Pin SOT-23A (EIAJ SC-74) Device 3 2 1 cdef 4 Part Number 5 Address Option SOT-23 MCP3021A0T-E/OT 000 GP MCP3021A1T-E/OT 001 GS MCP3021A2T-E/OT 010 GK MCP3021A3T-E/OT 011 GL MCP3021A4T-E/OT 100 GM MCP3021A5T-E/OT 101 GJ * MCP3021A6T-E/OT 110 GQ MCP3021A7T-E/OT 111 GR * Default option. Contact Microchip Factory for other address options. Legend: Note: * 1 2 3 4 Part Number code + temperature range Part Number code + temperature range Year and work week Lot ID In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard device marking consists of Microchip part number, year code, week code, and traceability code. DS21805A-page 20 2003 Microchip Technology Inc. MCP3021 5-Lead Plastic Small Outline Transistor (OT) (SOT23) E E1 p B p1 n D 1 α c A φ L β Units Dimension Limits n p Number of Pins Pitch Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic MIN p1 A A2 A1 E E1 D L φ c B α β .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 A2 A1 INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 MILLIMETERS NOM 5 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MIN MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091 2003 Microchip Technology Inc. DS21805A-page 21 MCP3021 NOTES: DS21805A-page 22 2003 Microchip Technology Inc. MCP3021 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X /XX Device Address Options Temperature Range Package Device: Examples: a) b) MCP3021T: 10-Bit 2-Wire Serial A/D Converter (Tape and Reel) c) d) Temperature Range: Address Options: E = -40°C to +125°C XX e) A2 A1 A0 A0 = 0 0 0 A1 = 0 0 1 A2 = 0 1 0 A3 = 0 1 1 0 A4 = 1 0 A5 * = 1 0 1 A6 = 1 1 0 A7 = 1 1 1 f) g) h) MCP3021A0T-E/OT: Tape and Reel MCP3021A1T-E/OT: Tape and Reel MCP3021A2T-E/OT: Tape and Reel MCP3021A3T-E/OT: Tape and Reel MCP3021A4T-E/OT: Tape and Reel MCP3021A5T-E/OT: Tape and Reel MCP3021A6T-E/OT: Tape and Reel MCP3021A7T-IE/OT: Tape and Reel Extended, A0 Address, Extended, A1 Address, Extended, A2 Address, Extended, A3 Address, Extended, A4 Address, Extended, A5 Address, Extended, A6 Address, Extended, A7 Address, * Default option. Contact Microchip factory for other address options Package: OT = SOT-23, 5-lead (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. DS21805A-page 23 MCP3021 NOTES: DS21805A-page 24 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPIC, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. 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