AD AD8067ART-REEL High gain bandwidth product precision fast fetâ ¢ op amp Datasheet

High Gain Bandwidth Product
Precision Fast FET ™ Op Amp
AD8067
FEATURES
• FET input amplifier: 0.6 pA input bias current
• Stable for gains ≥8
• High speed
• 54 MHz, –3 dB bandwidth (G = +10)
• 640 V/µs slew rate
• Low noise
• 6.6 nV/√Hz
• 0.6 fA/√Hz
• Low offset voltage (1.0 mV max)
• Wide supply voltage range: 5 V to 24 V
• No phase reversal
• Low input capacitance
• Single-supply and rail-to-rail output
• Excellent distortion specs: SFDR 95 dBc @ 1 MHz
• High common-mode rejection ratio: –106 dB
• Low power: 6.5 mA typical supply current
• Low cost
• Small packaging: SOT-23-5
APPLICATIONS
CONNECTION DIAGRAM
SOT-23-5 (RT-5)
VOUT 1
5 +VS
–VS 2
+IN 3
4 –IN
Figure 1. Connection Diagram (Top View)
The FET input bias current (5 pA max) and low voltage noise
(6.6 nV/√Hz) also contribute to making it appropriate for precision
applications. With a wide supply voltage range (5 V to 24 V) and
rail-to-rail output, the AD8067 is well suited to a variety of
applications that require wide dynamic range and low distortion.
The AD8067 amplifier consumes only 6.5 mA of supply current,
while capable of delivering 30 mA of load current and driving
capacitive loads of 100 pF. The AD8067 amplifier is available in a
SOT-23-5 package and is rated to operate over the industrial
temperature range, –40°C to +85°C.
• Photodiode preamplifier
• Precision high gain amplifier
• High gain, high bandwidth composite amplifier
28
26
G = +20
24
GENERAL DESCRIPTION
The AD8067 is designed to work in applications that require high
speed and low input bias current, such as fast photodiode
preamplifiers. As required by photodiode applications, the laser
trimmed AD8067 has excellent dc voltage offset (1.0 mV max)
and drift (15 µV/°C max).
GAIN – dB
22
The AD8067 Fast FET amp is a voltage feedback amplifier with
FET inputs offering wide bandwidth (54 MHz @ G = +10) and high
slew rate (640 V/µs). The AD8067 is fabricated in a proprietary,
dielectrically isolated eXtra Fast Complementary Bipolar process
(XFCB) that enables high speed, low power, and high performance
FET input amplifiers.
20
18
G = +10
G = +8
16
14
12
10
8
0.1
1
10
FREQUENCY – MHz
100
Figure 2. Small Signal Frequency Response
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2002 Analog Devices, Inc. All rights reserved.
AD8067
TABLE OF CONTENTS
AD8067–Specifications for ±5 V...........................................................4
Input Protection ................................................................................18
AD8067–Specifications for +5 V...........................................................5
Capacitive Load Drive ......................................................................18
AD8067–Specifications for ±12 V.........................................................6
Layout, Grounding, and Bypassing Considerations .....................18
Absolute Maximum Ratings ..................................................................7
Applications............................................................................................20
Maximum Power Dissipation............................................................7
Wideband Photodiode Preamp.......................................................20
Typical Performance Characteristics ....................................................8
Using the AD8067 at Gains of Less Than 8 ...................................21
Test Circuits............................................................................................13
Single-Supply Operation ..................................................................22
Theory of Operation .............................................................................15
High Gain, High Bandwidth Composite Amplifier......................22
Basic Frequency Response...............................................................15
Outline Dimensions ..............................................................................24
Resistor Selection for Wideband Operation..................................16
Ordering Guide .................................................................................24
Input and Output Overload Behavior............................................17
TABLES
Table 1. Recommended Values of RG and RF .....................................15
Table 3. Ordering Guide........................................................................24
Table 2. RMS Noise Contributions of Photodiode Preamp.............20
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8067
FIGURES
Figure 1. Connection Diagram (Top View)..........................................1
Figure 32. Output Saturation Voltage vs. Temperature .................... 12
Figure 2. Small Signal Frequency Response .........................................1
Figure 33. Open-Loop Gain vs. Load Current for Various
Supplies.......................................................................................... 12
Figure 3. Maximum Power Dissipation vs. Temperature for
a 4-Layer Board ...............................................................................7
Figure 34. Standard Test Circuit.......................................................... 13
Figure 4. Small Signal Frequency Response for Various Gains .........8
Figure 35. Open-Loop Gain Test Circuit ........................................... 13
Figure 5. Small Signal Frequency Response for Various Supplies.....8
Figure 36. Test Circuit for Capacitive Load....................................... 13
Figure 6. Large Signal Frequency Response for Various Supplies.....8
Figure 37. CMRR Test Circuit ............................................................. 14
Figure 7. 0.1 dB Flatness Frequency Response ...................................8
Figure 38. Positive PSRR Test Circuit................................................. 14
Figure 8. Small Signal Frequency Response for Various CLOAD .........8
Figure 39. Output Impedance Test Circuit ........................................ 14
Figure 9. Frequency Response for Various Output Amplitudes ........8
Figure 40. Noninverting Gain Configuration ................................... 15
Figure 10. Small Signal Frequency Response for Various RF .............9
Figure 41. Open-Loop Frequency Response .................................... 15
Figure 11. Distortion vs. Frequency for Various Loads ......................9
Figure 42. Inverting Gain Configuration........................................... 15
Figure 12. Distortion vs. Frequency for Various Amplitudes.............9
Figure 43. Input and Board Capacitances.......................................... 16
Figure 13. Open-Loop Gain and Phase ................................................9
Figure 44. Op Amp DC Error Sources .............................................. 17
Figure 14. Distortion vs. Frequency for Various Supplies ..................9
Figure 45. Simplified Input Schematic ............................................. 17
Figure 15. Distortion vs. Output Amplitude for Various Loads ........9
Figure 46 Current Limiting Resistor .................................................. 18
Figure 16. Small Signal Transient Response 5 V Supply...................10
Figure 47. Guard-Ring Configurations .............................................. 18
Figure 17. Output Overdrive Recovery...............................................10
Figure 48. Guard-Ring Layout SOT-23-5 .......................................... 18
Figure 18. Long-Term Settling Time ...................................................10
Figure 49. Wideband Photodiode Preamp......................................... 20
Figure 19. Small Signal Transient Response ± 5 V Supply ...............10
Figure 50. Photodiode Voltage Noise Contributions ....................... 20
Figure 20. Large Signal Transient Response.......................................10
Figure 51. Photodiode Preamplifier ................................................... 21
Figure 21. 0.1% Short-Term Settling Time........................................10
Figure 52. Photodiode Preamplifier Frequency Response .............. 21
Figure 22. Input Bias Current vs. Temperature..................................11
Figure 53. Photodiode Preamplifier Pulse Response ....................... 21
Figure 23. Input Offset Voltage Histogram ........................................11
Figure 54. Gain of Less than 2 Schematic .......................................... 21
Figure 24. Voltage Noise........................................................................11
Figure 55. Gain of 2 Pulse Response .................................................. 22
Figure 25. Input Bias Current vs. Common-Mode Voltage..............11
Figure 56. Single-Supply Operation Schematic ................................ 22
Figure 26. Input Offset Voltage vs. Common-Mode Voltage ...........11
Figure 57. AD8067/AD8009 Composite ........................................... 23
Figure 27. CMRR vs. Frequency ..........................................................11
Figure 58. Gain Bandwidth Response ................................................ 23
Figure 28. Output Impedance vs. Frequency .....................................12
Figure 59. Large Signal Response........................................................ 23
Figure 29. Output Saturation Voltage vs. Output Load Current......12
Figure 60. Small Signal Response........................................................ 23
Figure 30. PSRR vs. Frequency.............................................................12
Figure 61. 5-Lead Plastic Surface Mount Package ........................... 24
Figure 31. Quiescent Current vs. Temperature for Various
Supply Voltages..............................................................................12
Rev. 0 | Page 3 of 24
AD8067
AD8067–SPECIFICATIONS FOR ±5 V
VS = ±5 V (@ TA = +25°C, G = +10, RF = RL =1 kΩ, Unless Otherwise Noted.)
Parameter
Min
Typ
39
54
MHz
VO = 2 V p-p
54
MHz
Bandwidth for 0.1 dB Flatness
VO = 0.2 V p-p
8
MHz
Output Overdrive Recovery Time
(Pos/Neg)
VI = ±0.6 V
115/190
ns
Slew Rate
VO = 5 V Step
640
V/µs
Settling Time to 0.1%
VO = 5 V Step
27
ns
fC = 1 MHz, 2 V p-p
fC = 1 MHz, 8 V p-p
fC = 5 MHz, 2 V p-p
95
84
82
72
6.6
0.6
0.2
dBc
dBc
dBc
dBc
nV/√Hz
fA/√Hz
mV
–3 dB Bandwidth
DYNAMIC
PERFORMANCE
NOISE/DISTORTION
PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Input Offset Voltage
Conditions
VO = 0.2 V p-p
500
fC = 1 MHz, 2 V p-p, RL = 150 Ω
f = 10 kHz
f = 10 kHz
Input Offset Voltage Drift
DC PERFORMANCE
Input Bias Current
Input Offset Current
INPUT
CHARACTERISTICS
OUTPUT
CHARACTERISTICS
POWER SUPPLY
TMIN to TMAX
TMIN to TMAX
VO = ±3 V
Open-Loop Gain
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR) VCM = –1 V to +1 V
RL = 1 kΩ
Output Voltage Swing
RL = 150 Ω
Output Current
Short Circuit Current
Capacitive Load Drive
Operating Range
Quiescent Current
103
1
0.6
25
0.2
1
119
1000||1.5
1000||2.5
1
–4.67 to +4.72
30
105
120
30% over shoot
5
6.5
–90
Rev. 0 | Page 4 of 24
1.0
15
5
–5.0
2.0
–85
–106
–4.86 to +4.83 –4.92 to +4.92
SFDR > 60 dBc, f = 1 MHz
Power Supply Rejection Ratio (PSRR)
Max
–109
24
6.8
Unit
µV/°C
pA
pA
pA
pA
dB
GΩ||pF
GΩ||pF
V
dB
V
V
mA
mA
pF
V
mA
dB
AD8067
AD8067–SPECIFICATIONS FOR +5 V
VS = +5 V (@ TA = +25°C, G = +10, RL =RF = 1 kΩ, Unless Otherwise Noted.)
Parameter
Conditions
VO = 0.2 V p-p
Min
Typ
36
54
MHz
VO = 2 V p-p
54
MHz
Bandwidth for 0.1 dB Flatness
VO = 0.2 V p-p
8
MHz
Output Overdrive Recovery Time (Pos/Neg)
VI = +0.6 V
150/200
ns
Slew Rate
VO = 3 V Step
490
V/µs
VO = 2 V Step
25
ns
fC = 1 MHz, 2 V p-p
fC = 1 MHz, 4 V p-p
fC = 5 MHz, 2 V p-p
fC = 1 MHz, 2 V p-p, RL = 150 Ω
f = 10 kHz
f = 10 kHz
86
74
60
72
6.6
0.6
0.2
dBc
dBc
dBc
dBc
nV/√Hz
fA/√Hz
mV
–3 dB Bandwidth
DYNAMIC
PERFORMANCE
Settling Time to 0.1%
NOISE/DISTORTION
PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Input Offset Voltage
390
Input Offset Voltage Drift
DC PERFORMANCE
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT
CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
Output Voltage Swing
OUTPUT
CHARACTERISTICS
POWER SUPPLY
Output Current
Short Circuit Current
Capacitive Load Drive
Operating Range
Quiescent Current
1
0.5
25
0.1
TMIN to TMAX
TMIN to TMAX
VO = 0.5 V to 4.5 V
VCM = 0.5 Vto 1.5 V
RL = 1 kΩ
100
Max
1.0
15
5
1
Unit
µV/°C
pA
pA
pA
pA
117
dB
1000||2.3
1000||2.5
GΩ||pF
GΩ||pF
V
dB
V
0
–81
–98
0.07 to 4.89 0.03 to 4.94
2.0
RL =150 Ω
0.08 to 4.83
V
SFDR > 60 dBc, f = 1 MHz
22
95
120
mA
mA
pF
V
mA
30% over shoot
5
6.4
Power Supply Rejection Ratio (PSRR)
–87
Rev. 0 | Page 5 of 24
–103
24
6.7
dB
AD8067
AD8067–SPECIFICATIONS FOR ±12 V
VS = ±12 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, Unless Otherwise Noted.)
Parameter
Min
Typ
39
54
MHz
VO = 2 V p-p
53
MHz
Bandwidth for 0.1 dB Flatness
VO = 0.2 V p-p
8
MHz
Output Overdrive Recovery Time
(Pos/Neg)
VI = ±1.5 V
75/180
ns
Slew Rate
VO = 5 V Step
640
V/µs
Settling Time to 0.1%
VO = 5 V Step
27
ns
fC = 1 MHz, 2 V p-p
fC = 1 MHz, 20 V p-p
fC = 5 MHz, 2 V p-p
fC = 1 MHz, 2V p-p, RL = 150 Ω
f = 10 kHz
f = 10 kHz
92
84
74
72
6.6
0.6
0.2
dBc
dBc
dBc
dBc
nV/√Hz
fA/√Hz
mV
–3 dB Bandwidth
DYNAMIC
PERFORMANCE
NOISE/DISTORTION
PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Input Offset Voltage
Conditions
VO = 0.2 V p-p
500
Input Offset Voltage Drift
DC PERFORMANCE
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT
CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
Output Voltage Swing
OUTPUT
CHARACTERISTICS
POWER SUPPLY
Output Current
Short Circuit Current
Capacitive Load Drive
Operating Range
Quiescent Current
1
1.0
25
0.2
TMIN to TMAX
TMIN to TMAX
VO = ±10 V
VCM = –1 V to +1 V
RL = 1 kΩ
107
15
5
1
30% over shoot
µV/°C
pA
pA
pA
pA
dB
1000||1.5
1000||2.5
GΩ||pF
GΩ||pF
V
dB
V
5
6.6
–86
Unit
119
–11.31 to +11.73
26
125
120
SFDR > 60 dBc, f = 1 MHz
Rev. 0 | Page 6 of 24
1.0
–12.0
9.0
–89
–108
–11.70 to +11.70 –11.85 to +11.84
RL = 500 Ω
Power Supply Rejection Ratio (PSRR)
Max
–97
24
7.0
V
mA
mA
pF
V
mA
dB
AD8067
ABSOLUTE MAXIMUM RATINGS
Rating
26.4 V
See Figure 3
VEE – 0.5 V to VCC + 0.5 V
1.8 V
–65°C to +125°C
–40°C to +85°C
300°C
If the RMS signal levels are indeterminate, then consider the worst
case, when VOUT = VS/4 for RL to midsupply:
PD = (VS × I S ) +
150°C
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Maximum Power Dissipation
The associated raise in junction temperature (TJ) on the die limits
the maximum safe power dissipation in the AD8067 package. At
approximately 150°C, which is the glass transition temperature, the
plastic will change its properties. Even temporarily exceeding this
temperature limit may change the stresses that the package exerts
on the die, permanently shifting the parametric performance of the
AD8067. Exceeding a junction temperature of 175°C for an
extended period of time can result in changes in the silicon devices,
potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
Assuming the load (RL) is referenced to midsupply, the total drive
power is VS/2 × IOUT, some of which is dissipated in the package
and some in the load (VOUT × IOUT). The difference between the
total drive power and the load power is the drive power dissipated
in the package. RMS output voltages should be considered.
 VOUT 2
–

RL

RL
Airflow will increase heat dissipation effectively, reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA.
Figure 3 shows the maximum safe power dissipation in the package versus ambient temperature for the SOT-23-5 (180°C/W)
package on a JEDEC standard 4-layer board. θJA values are
approximations.
It should be noted that for every 10°C rise in temperature, IB
approximately doubles (See Figure 22).
2.0
1.5
1.0
SOT-23-5
0.5
0
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE – °C
PD = Quiescent Power + (Total Drive Power – Load Power )
V V
PD = (VS × I S ) +  S × OUT
RL
 2
(VS / 4 )2
In single-supply operation with RL referenced to VS–, worst case is
VOUT = VS/2.
MAXIMUM POWER DISSAPATION – W
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
If RL is referenced to VS– as in single-supply operation, then the
total drive power is VS × IOUT.
Rev. 0 | Page 7 of 24
AD8067
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions VS = ±5 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, Unless Otherwise Noted.)
20.7
28
26
24
20.5
22
20.4
G = +10
20
G = +8
18
G = +6
16
VOUT = 0.2V p-p
20.6
GAIN – dB
GAIN – dB
VOUT = 200mV p-p
G = +20
VOUT = 0.7V p-p
VOUT = 1.4V p-p
20.3
20.2
20.1
14
20.0
12
19.9
10
8
19.8
1
10
FREQUENCY – MHz
100
1
24
VOUT = 200mV p-p
VS = +5V
21
22
VS = ±5V
GAIN – dB
GAIN – dB
VS = ±12V
18
20
CL = 100pF
RSNUB = 24.9Ω
19
18
17
17
16
16
CL = 5pF
15
15
14
1
10
FREQUENCY – MHz
1
100
10
FREQUENCY – MHz
100
Figure 8. Small Signal Frequency Response for Various CLOAD
Figure 5. Small Signal Frequency Response for Various Supplies
22
22
VOUT = 2V p-p
VS = +5V
21
21
VS = ±5V
VOUT = 4V p-p
GAIN – dB
VS = ±12V
19
VOUT = 0.2V p-p, 2V p-p
20
20
GAIN – dB
CL = 25pF
21
19
18
19
18
17
17
16
16
15
15
14
CL = 100pF
VOUT = 200mV p-p
23
20
14
100
Figure 7. 0.1 dB Flatness Frequency Response
Figure 4. Small Signal Frequency Response for Various Gains
22
10
FREQUENCY – MHz
14
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
Figure 9. Frequency Response for Various Output Amplitudes
Figure 6. Large Signal Frequency Response for Various Supplies
Rev. 0 | Page 8 of 24
AD8067
VOUT = 200mV p-p
RF = 2kΩ
21
RF = 1kΩ
90
120
80
90
70
60
PHASE
60
RF = 499Ω
19
GAIN – dB
GAIN – dB
20
18
17
30
50
0
40
–30
GAIN
30
–60
PHASE – Degrees
22
20
–90
10
–120
0
–150
16
15
14
1
10
FREQUENCY – MHz
–10
0.01
100
0.1
Figure 10. Small Signal Frequency Response for Various RF
–40
HD2 RLOAD = 150Ω
–70
HD3 RLOAD = 150Ω
–80
HD2
RLOAD = 1kΩ
–90
–100
–110
DISTORTION – dBc
DISTORTION – dBc
–60
VOUT = 2V p-p
HD3 RLOAD = 1kΩ
–120
G = +10
VS = ±5V
–140
0.1
1
–70
–90
–100
HD2 VS = ±5V
–110
HD3 VS = ±12V
10
FREQUENCY – MHz
HD3 VS = ±5V
–130
–140
0.1
100
Figure 11. Distortion vs. Frequency for Various Loads
–20
HD2 VS = ±12V
–80
–120
–130
1
–30
VS = ±12V
G = +10
DISTORTION – dBc
–50
–60
HD2 VOUT = 20V p-p
HD3 VOUT = 2V p-p
HD2 VOUT = 2V p-p
HD3 VOUT = 20V p-p
–120
HD2 RLOAD = 150Ω
–60
–70
HD3 RLOAD = 150Ω
–80
–90
HD2 RLOAD = 1kΩ
–100
–110
HD3 RLOAD = 1kΩ
–120
–140
0.1
1
10
FREQUENCY – MHz
100
VS = ±12V
f = 1MHz
G = +10
–40
–100
10
FREQUENCY – MHz
Figure 14. Distortion vs. Frequency for Various Supplies
–40
DISTORTION – dBc
G = +10
VOUT = 2V p-p
–50
–60
–80
–180
1k
100
Figure 13. Open-Loop Gain and Phase
–40
–50
1
10
FREQUENCY – MHz
–130
100
Figure 12. Distortion vs. Frequency for Various Amplitudes
0
2
4
6
8
10 12 14 16 18
OUTPUT AMPLITUDE – V p-p
20
22
24
Figure 15. Distortion vs. Output Amplitude for Various Loads
Rev. 0 | Page 9 of 24
AD8067
G = +10
VIN = 20mV p-p
G = +10
VIN = 20mV p-p
CL = 100pF
CL = 0pF
1.5V
50mV/DIV
50mV/DIV
25ns/DIV
Figure 16. Small Signal Transient Response 5 V Supply
10VIN
Figure 19. Small Signal Transient Response ± 5 V Supply
G = +10
VOUT
VS = ±12V
VIN = 2V p-p
G = +10
200ns/DIV
2V/DIV
25ns/DIV
5V/DIV
Figure 17. Output Overdrive Recovery
50ns/DIV
Figure 20. Large Signal Transient Response
VOUT (1V/DIV)
G = +10
VIN (100mV/DIV)
VOUT – 10VIN (5mV/DIV)
+0.1%
+0.1%
VIN (100mV/DIV)
VOUT – 10VIN (5mV/DIV)
–0.1%
–0.1%
t=0
5µs/DIV
Figure 18. Long-Term Settling Time
5ns/DIV
Figure 21. 0.1% Short-Term Settling Time
Rev. 0 | Page 10 of 24
AD8067
14
10
8
INPUT BIAS CURRENT – pA
INPUT BIAS CURRENT – pA
12
10
8
6
VS = ±12V
4
VS = ±12V
VS = ±5V
VS = +5V
6
4
2
0
–2
–4
–6
2
–8
VS = ±5V
0
25
35
45
55
65
TEMPERATURE – °C
75
–10
–14 –12 –10 –8 –6 –4 –2 0 2 4 6 8
COMMON-MODE VOLTAGE – V
85
Figure 25. Input Bias Current vs. Common-Mode Voltage
Figure 22. Input Bias Current vs. Temperature
1800
5
N = 12255
SD = 0.203
MEAN = –0.033
4
INPUT OFFSET VOLTAGE – mV
1600
1400
COUNT
1200
1000
800
600
400
200
0
10 12 14
VS = ±12V
3
VS = ±5V
2
1
VS = +5V
0
–1
–2
–6
–4
–1
0
INPUT OFFSET VOLTAGE – mV
–5
–14 –12 –10 –8 –6 –4 –2 0
2 4
6
8
COMMON-MODE VOLTAGE – V
1
10 12 14
Figure 26. Input Offset Voltage vs. Common-Mode Voltage
Figure 23. Input Offset Voltage Histogram
–40
1000
–50
100
CMRR – dB
NOISE – nV/ Hz
–60
10
–70
–80
–90
–100
–110
1
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
–120
0.1
100M
1
10
FREQUENCY – MHz
Figure 27. CMRR vs. Frequency
Figure 24. Voltage Noise
Rev. 0 | Page 11 of 24
100
AD8067
6.7
100
G = +10
VS = ±12V
QUIESCENT CURRENT – mA
6.6
OUTPUT IMPEDANCE – Ω
10
1
0.1
6.3
6.2
6.0
–40
0.001
0.01
0.1
1
10
FREQUENCY – MHz
100
200
OUTPUT SATURATION VOLTAGE – mV
0.25
VCC – VOH
0.20
VOL – VEE
0.15
0.10
0.05
0
5
10
15
20
25
ILOAD – mA
30
80
35
(VCC – VOH), (VOL – VEE), VS = ±12V
140
120
100
(VCC – VOH), (VOL – VEE), VS = ±5V
80
VCC – VOH, VS = +5V
60
40
VOL – VEE, VS = +5V
20
0
–40
40
130
–20
120
OPEN-LOOP GAIN – dB
–10
–PSRR
–10
–50
–60
+PSRR
–20
0
20
40
TEMPERATURE – °C
60
80
Figure 32. Output Saturation Voltage vs. Temperature
140
VS = ±12V
110
100
90
VS = ±5V
80
VS = +5V
70
–80
60
–90
–100
0.01
60
160
0
–70
20
40
TEMPERATURE – °C
RL = 1kΩ
180
Figure 29. Output Saturation Voltage vs. Output Load Current
–30
0
Figure 31. Quiescent Current vs. Temperature for Various Supply Voltages
0.30
0
–20
1000
Figure 28. Output Impedance vs. Frequency
OUTPUT SATURATION VOLTAGE – V
VS = +5V
6.4
6.1
0.01
PSRR – dB
VS = ±5V
6.5
50
0.1
1
FREQUENCY – MHz
10
100
Figure 30. PSRR vs. Frequency
0
5
10
15
20
25
ILOAD – mA
30
35
40
Figure 33. Open-Loop Gain vs. Load Current for Various Supplies
Rev. 0 | Page 12 of 24
AD8067
TEST CIRCUITS
+VCC
10µF
+
0.1µF
1kΩ
110Ω
5
4
VIN
AD8067
49.9Ω
3
VOUT
1
RL = 1kΩ
2
0.1µF
10µF
+
AV = 10
–VEE
Figure 34. Standard Test Circuit
+VCC
10µF
+
0.1µF
110Ω
V–
1kΩ
5
4
AD8067
100Ω
3
VOUT
1
1kΩ
2
0.1µF
10µF
AOL =
VOUT
V–
+
–VEE
Figure 35. Open-Loop Gain Test Circuit
+VCC
10µF
+
0.1µF
110Ω
1kΩ
4
VIN
49.9Ω
5
AD8067
3
2
RSNUB
0.1µF
CLOAD
10µF
+
AV = 10
VOUT
1
–VEE
Figure 36. Test Circuit for Capacitive Load
Rev. 0 | Page 13 of 24
1kΩ
AD8067
+VCC
10µF
+
0.1µF
110Ω
1kΩ
VIN
5
4
AD8067
110Ω
3
2
1kΩ
VOUT
1
1kΩ
0.1µF
10µF
+
–VEE
Figure 37. CMRR Test Circuit
VIN
110Ω
1kΩ
+VCC
5
4
AD8067
3
VOUT
1
1kΩ
2
0.1µF
100Ω
10µF
+
–VEE
Figure 38. Positive PSRR Test Circuit
+VCC
10µF
+
0.1µF
110Ω
1kΩ
4
100Ω
5
AD8067
3
2
VOUT
1
NETWORK ANALYZER
0.1µF
10µF
+
–VEE
Figure 39. Output Impedance Test Circuit
Rev. 0 | Page 14 of 24
AD8067
THEORY OF OPERATION
The combination of low noise, dc precision, and high bandwidth
makes the AD8067 uniquely suited for wideband, very high input
impedance, high gain buffer applications. It will also prove useful
in wideband transimpedance applications, such as a photodiode
interface, that require very low input currents and dc precision.
Basic Frequency Response
The AD8067’s typical open-loop response (see Figure 41) shows a
phase margin of 60° at a gain of +10. Typical configurations for
noninverting and inverting voltage gain applications are shown in
Figure 40 and Figure 42.
The closed-loop frequency response of a basic noninverting gain
configuration can be approximated using the equation:
Closed Loop – 3 dB Frequency = (GBP ) ×
RG
(RF + RG )
DC Gain = RF /RG + 1
GBP is the gain bandwidth product of the amplifier. Typical GBP
for the AD8067 is 300 MHz. See Table 1 for recommended values
of RG and RF.
Noninverting Configuration Noise Gain =
+VS
RS
RX
0.1µF
90
120
80
90
60
30
50
0
40
–30
GAIN
30
–60
20
–90
10
–120
0
–150
–10
0.01
0.1
1
10
FREQUENCY – MHz
Gain
10
20
50
100
RG (Ω)
110
49.9
20
10
0.1µF
BW (MHz)
54
15
6
3
+VS
0.1µF
RX
+
10µF
+
AD8067
RLOAD
10µF
+
0.1µF
+
VOUT
–
RS
–VS
RG
RF (kΩ)
1
1
1
1
–
RLOAD
–180
Table 1. Recommended Values of RG and RF
RF
+1
RG
+
10µF
–
1k
The bandwidth formula only holds true when the phase margin of
the application approaches 90°, which it will in high gain configurations. The bandwidth of the AD8067 used in a G = +10 buffer
is 54 MHz, considerably faster than the 30 MHz predicted by the
closed loop –3 dB frequency equation. This extended bandwidth is
due to the phase margin being at 60° instead of 90°. Gains lower
than +10 will show an increased amount of peaking, as shown in
Figure 4. For gains lower than +7, use the AD8065, a unity gain
stable JFET input op amp with a unity gain bandwidth of 145 MHz,
or refer to the Applications section for using the AD8067 in a gain
of 2 configuration.
+
SIGNAL
SOURCE
100
Figure 41. Open-Loop Frequency Response
AD8067
VI
60
PHASE
PHASE – Degrees
70
GAIN – dB
The AD8067 is a low noise, wideband, voltage feedback operational
amplifier that combines a precision JFET input stage with Analog
Devices’ dielectrically isolated eXtra Fast Complementary Bipolar
(XFCB) process BJTs. Operating supply voltages range from 5 V
to 24 V. The amplifier features a patented rail-to-rail output stage
capable of driving within 0.25 V of either power supply while
sourcing or sinking 30 mA. The JFET input, composed of
N-channel devices, has a common-mode input range that includes
the negative supply rail and extends to 3 V below the positive
supply. In addition, the potential for phase reversal behavior has
been eliminated for all input voltages within the power supplies.
RG
10µF
+
+
VOUT
–
–VS
RF
VI
RF
FOR BEST PERFORMANCE,
SET RS + RX = RG || RF
SIGNAL
SOURCE
FOR BEST PERFORMANCE, SET RX = (RS + RG) || RF
Figure 40. Noninverting Gain Configuration
Figure 42. Inverting Gain Configuration
Rev. 0 | Page 15 of 24
AD8067
For inverting voltage gain applications, the source impedance of the
input signal must be considered because that will set the application’s noise gain as well as the apparent closed-loop gain. The basic
frequency equation for inverting applications is below.
Closed Loop – 3 dB Frequency = (GBP) ×
DC Gain = –
+
CPAR
VI
CM
CD
CM
–
–
RG + R S
RF + R G + R S
+
VOUT
–
RF
SIGNAL SOURCE
CPAR
RG
RF
RG + R S
GBP is the gain bandwidth product of the amplifier, and RS is the
signal source resistance.
Inverting Configuration Noise Gain =
+
RS
R F + RG + R S
RG + R S
It is important that the noise gain for inverting applications be kept
above 6 for stability reasons. If the signal source driving the inverter
is another amplifier, take care that the driving amplifier shows low
output impedance through the frequency span of the expected
closed-loop bandwidth of the AD8067.
Figure 43. Input and Board Capacitances
There will be a pole in the feedback loop response formed by the
source impedance seen by the amplifier’s negative input (RG RF)
and the sum of the amplifier’s differential input capacitance,
common-mode input capacitance, and any board parasitic
capacitance. This will decrease the loop phase margin and can
cause stability problems, i.e., unacceptable peaking and ringing
in the response. To avoid this problem it is recommended that the
resistance at the AD8067’s negative input be kept below 200 Ω for
all wideband voltage gain applications.
Matching the impedances at the inputs of the AD8067 is also
recommended for wideband voltage gain applications. This will
minimize nonlinear common-mode capacitive effects that can
significantly degrade settling time and distortion performance.
Resistor Selection for Wideband
Operation
Voltage feedback amplifiers can use a wide range of resistor values
to set their gain. Proper design of the application’s feedback
network requires consideration of the following issues:
• Poles formed by the amplifier’s input capacitances with the
resistances seen at the amplifier’s input terminals
• Effects of mismatched source impedances
• Resistor value impact on the application’s output
voltage noise
• Amplifier loading effects
The AD8067 has common-mode input capacitances (CM) of 1.5 pF
and a differential input capacitance (CD) of 2.5 pF. This is illustrated
in Figure 43. The source impedance driving the positive input of a
noninverting buffer will form a pole primarily with the amplifier’s
common-mode input capacitance as well as any parasitic
capacitance due to the board layout (CPAR). This will limit the
obtainable bandwidth. For G = +10 buffers, this bandwidth limit
will become apparent for source impedances >1 kΩ.
The AD8067 has a low input voltage noise of 6.6 nV/√Hz. Source
resistances greater than 500 Ω at either input terminal will notably
increase the apparent Referred to Input (RTI) voltage noise of the
application.
The amplifier must supply output current to its feedback network,
as well as to the identified load. For instance, the load resistance
presented to the amplifier in Figure 40 is RLOAD  (RF + RG). For an
RLOAD of 100 Ω, RF of 1 kΩ, and RG of 100 Ω, the amplifier will be
driving a total load resistance of about 92 Ω. This becomes more of
an issue as RF decreases. The AD8067 is rated to provide 30 mA of
low distortion output current. Heavy output drive requirements
also increase the part’s power dissipation and should be taken
into account.
Rev. 0 | Page 16 of 24
AD8067
DC ERROR CALCULATIONS
Input and Output Overload Behavior
Figure 44 illustrates the primary dc errors associated with a voltage
feedback amplifier. For both inverting and noninverting
configurations:
 R + RF
Output Voltage Error due to VOS = VOS  G
 RG
 R + RG
Output Voltage Error due to I B = I B + × R S  F
 RG





 – I B – × RF


Total error is the sum of the two.
DC common-mode and power supply effects can be added by
modeling the total VOS with the expression:
VOS (tot) = VOS (nom) +
∆VS ∆VCM
+
PSR
CMR
VOS (nom) is the offset voltage specified at nominal conditions
(1 mV max). ∆VS is the change in power supply voltage from
nominal conditions. PSR is power supply rejection (90 dB
minimum). ∆VCM is the change in common-mode voltage from
nominal test conditions. CMR is common-mode rejection (85 dB
minimum for the AD8067).
A simplified schematic of the AD8067 input stage is shown in
Figure 45. This shows the cascoded N-channel JFET input pair,
the ESD and other protection diodes, and the auxiliary NPN
input stage that eliminates phase inversion behavior.
When the common-mode input voltage to the amplifier is driven
to within approximately 3 V of the positive power supply, the input
JFET’s bias current will turn off, and the bias of the NPN pair will
turn on, taking over control of the amplifier. The NPN differential
pair now sets the amplifier’s offset, and the input bias current is
now in the range of several tens of microamps. This behavior is
illustrated in Figure 25 and Figure 26. Normal operation resumes
when the common-mode voltage goes below the 3 V from the
positive supply threshold.
The output transistors have circuitry included to limit the extent
of their saturation when the output is overdriven. This improves
output recovery time. A plot of the output recovery time for the
AD8067 used as a G = +10 buffer is shown in Figure 17.
VCC
VTHRESHOLD
RF
SWITCH
CONTROL
+VOS–
RG
TO REST OF AMP
VCC
VCC
VN
VP
–
+ VOUT –
IB–
– VI +
RS
+
VEE
VEE
IB +
Figure 44. Op Amp DC Error Sources
VEE
Figure 45. Simplified Input Schematic
Rev. 0 | Page 17 of 24
VBIAS
AD8067
Input Protection
The inputs of the AD8067 are protected with back-to-back diodes
between the input terminals as well as ESD diodes to either power
supply. The result is an input stage with picoamp level input
currents that can withstand 2 kV ESD events (human body model)
with no degradation.
Excessive power dissipation through the protection devices will
destroy or degrade the performance of the amplifier. Differential
voltages greater than 0.7 V will result in an input current of
approximately (| V+ – V– | – 0.7 V)/(RI + RG)), where RI and RG are
the resistors (see Figure 46). For input voltages beyond the positive
supply, the input current will be about (VI – VCC – 0.7 V)/RI. For
input voltages beyond the negative supply, the input current will be
about (VI – VEE + 0.7 V)/RI. For any of these conditions, RI should
be sized to limit the resulting input current to 50 mA or less.
–
VI
+ RI
AD8067
RI > ( |V+ – V– | –0.7V)/50mA
FOR LARGE |V+ – V– |
RG
RF
RI > (VI – VEE + 0.7V)/50mA
RI > (VI – VCC – 0.7V)/50mA
FOR VI BEYOND
+ SUPPLY VOLTAGES
VOUT
–
Figure 46. Current Limiting Resistor
Capacitive Load Drive
Capacitive load introduces a pole in the amplifier loop response
due to the finite output impedance of the amplifier. This can cause
excessive peaking and ringing in the response. The AD8067 with a
gain of +10 will handle up to a 30 pF capacitive load without an
excessive amount of peaking (see Figure 8). If greater capacitive
load drive is required, consider inserting a small resistor in series
with the load (24.9 Ω is a good value to start with). Capacitive load
drive capability also increases as the gain of the amplifier increases.
Layout, Grounding, and Bypassing
Considerations
LAYOUT
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces will set
up a leakage path through the PCB. Consider a 1 V signal and
100GΩ to ground present at the input of the amplifier. The resultant
leakage current is 10 pA; this is ten times the input bias current of
the amplifier. Poor PCB layout, contamination, and the board
material can create large leakage currents. Common contaminants
on boards are skin oils, moisture, solder flux, and cleaning agents.
Therefore, it is imperative that the board be thoroughly cleaned and
the board surface be free of contaminants to fully take advantage of
the AD8067’s low input bias currents.
To significantly reduce leakage paths, a guard ring/shield around
the inputs should be used. The guard ring circles the input pins and
is driven to the same potential as the input signal, thereby reducing
the potential difference between pins. For the guard ring to be completely effective, it must be driven by a relatively low impedance
source and should completely surround the input leads on all sides,
above, and below, using a multilayer board (see Figure 47). The
SOT-23-5 package presents a challenge in keeping the leakage paths
to a minimum. The pin spacing is very tight, so extra care must be
used when constructing the guard ring (see Figure 48 for
recommended guard-ring construction).
GUARD RING
GUARD RING
NON-INVERTING
INVERTING
Figure 47. Guard-Ring Configurations
VOUT
AD8067
+V
VOUT
AD8067
–V
–V
+IN
–IN
INVERTING
+IN
–IN
NONINVERTING
Figure 48. Guard-Ring Layout SOT-23-5
Rev. 0 | Page 18 of 24
+V
AD8067
GROUNDING
POWER SUPPLY BYPASSING
To minimize parasitic inductances and ground loops in high speed,
densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in the
implementation of high speed circuit design. The length of the
current path is directly proportional to the magnitude of the
parasitic inductances and thus the high frequency impedance of the
path. Fast current changes in an inductive ground return will create
unwanted noise and ringing.
The length of the high frequency bypass capacitor leads is critical.
A parasitic inductance in the bypass grounding will work against
the low impedance created by the bypass capacitor. Because load
currents flow from supplies as well as ground, the load should be
placed at the same physical location as the bypass capacitor ground.
For large values of capacitors, which are intended to be effective at
lower frequencies, the current return path length is less critical.
Power supply pins are actually inputs and care must be taken to
provide a clean, low noise dc voltage source to these inputs. The
bypass capacitors have two functions:
1.
Provide a low impedance path for unwanted frequencies
from the supply inputs to ground, thereby reducing the
effect of noise on the supply lines
2.
Provide localized charge storage—this is usually
accomplished with larger electrolytic capacitors
Decoupling methods are designed to minimize the bypassing
impedance at all frequencies. This can be accomplished with a
combination of capacitors in parallel to ground. Good quality
ceramic chip capacitors (X7R or NPO) should be used and always
kept as close to the amplifier package as possible. A parallel
combination of a 0.1 µF ceramic and a 10 µF electrolytic, covers a
wide range of rejection for unwanted noise. The 10 µF capacitor is
less critical for high frequency bypassing, and in most cases, one
per supply line is sufficient.
Rev. 0 | Page 19 of 24
AD8067
bandwidth in half will result in a flat frequency response, with
about 5% transient overshoot.
APPLICATIONS
Wideband Photodiode Preamp
The preamp’s output noise over frequency is shown in Figure 50.
CF
Contributor
RF
2 × 4kT × RF × f 2 × 1.57
RF × 2
–
CM
CS
IPHOTO
+
Amp to f1
Vnoise × f 1
Amp (f2–f1)
Vnoise ×
Amp (Past f2)
Vnoise ×
VOUT
CD
RSH = 1011Ω
CM
VB
AD8067
C F + CS
RF
RMS
Noise
(µV)1
Expression
152
4.3
(C S + C M + C F + 2C D ) ×
CF
(C S + C M + C F + 2C D ) ×
CF
f 2 – f1
f 3 × 1.57
RSS Total
96
684
708
Table 2. RMS Noise Contributions of Photodiode Preamp
Figure 49. Wideband Photodiode Preamp
1
Figure 49 shows an I/V converter with an electrical model of a
photodiode.
RMS noise with RF = 50 kΩ, CS = 0.67 pF, CF = 0.33 pF,
CM = 1.5 pF, and CD = 2.5 pF.
The basic transfer function is:
1 + sC F RF
f2 =
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF sets the signal bandwidth.
The stable bandwidth attainable with this preamp is a function of
RF, the gain bandwidth product of the amplifier, and the total
capacitance at the amplifier’s summing junction, including CS and
the amplifier input capacitance. RF and the total capacitance
produce a pole in the amplifier’s loop transmission that can result
in peaking and instability. Adding CF creates a zero in the loop
transmission that compensates for the pole’s effect and reduces the
signal bandwidth. It can be shown that the signal bandwidth
resulting in a 45° phase margin (f(45)) is defined by the expression:
f(45 ) =
GBP
2 π × RF × C S
GBP is the unit gain bandwidth product, RF is the feedback
resistance, and CS is the total capacitance at the amplifier summing
junction (amplifier + photodiode + board parasitics).
VOLTAGE NOISE – nV/ Hz
VOUT =
1
f1 = 2 π R (C + C + C + 2C )
F F
S
M
D
I PHOTO × RF
GBP
f3 = (C + C + 2C + C )/C
S
M
D
F
F
RF NOISE
f2
VEN (C F + C S + C M + 2C D )/C F
f3
f1
VEN
NOISE DUE TO AMPLIFIER
FREQUENCY – Hz
Figure 50. Photodiode Voltage Noise Contributions
Figure 51 shows the AD8067 configured as a transimpedance
photodiode amplifier. The amplifier is used in conjunction with a
JDS Uniphase photodiode detector. This amplifier has a bandwidth
of 9.6 MHz as shown in Figure 52 and is verified by the design
equations shown in Figure 50.
The value of CF that produces f(45) can be shown to be:
CF =
1
2πRFCF
CS
2π × RF × GBP
The frequency response in this case will show about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
Rev. 0 | Page 20 of 24
AD8067
Using the AD8067 at Gains of Less Than 8
0.33pF
49.9kΩ
+5V
10µF
0.1µF
–5V
50Ω
AD8067
EPM 605 LL
The signal and noise gain equations for a noninverting amplifier
are shown below.
10µF
0.33pF
NOTES
ID @ –5V = 0.074nA
CD @ –5V = 0.690pF
RB @ 1550nm = –49dB
VOUT
A common technique used to stabilize decompensated amplifiers is
to increase the noise gain, independent of the signal gain. The
AD8067 can be used for signal gains of less than 8, provided that
proper care is taken to ensure that the noise gain of the amplifier
is set to at least the recommended minimum signal gain of 8
(See Figure 54).
49.9kΩ
0.1µF
–5V
Figure 51. Photodiode Preamplifier
Signal Gain = 1 +
R3
R1
Noise Gain = 1 +
R3
R1
Test data for the preamp is shown in Figure 52 and Figure 53.
The addition of resistor R2 modifies the noise gain equation, as
shown below. Note the signal gain equation has not changed.
100
TRANSIMPEDANCE GAIN – dB
95
Noise Gain = 1 +
90
R3
R1 || R2
R3
600Ω
85
+5V
80
C1
10µF
75
R1
301Ω
70
65
VIN
60
0.01
0.1
1
FREQUENCY – MHz
10
4
R2
50Ω
3
5
AD8067
2
100
Figure 52. Photodiode Preamplifier Frequency Response
–5V
C2
0.1µF
1
R4
51Ω
C3
10µF
VOUT
RL
C4
0.1µF
Figure 54. Gain of Less than 2 Schematic
C1 RISE
31.2ns
T
C1 FALL
31.6ns
CH1 500mV
M 50ns CH1
This technique allows the designer to use the AD8067 in gain
configurations of less than 8. The drawback to this type of
compensation is that the input noise and offset voltages are also
amplified by the value of the noise gain. In addition, the distortion
performance will be degraded. To avoid excessive overshoot and
ringing when driving a capacitive load, the AD8067 should be
buffered by a small series resistor; in this case, a 51 Ω resistor
was used.
830mV
Figure 53. Photodiode Preamplifier Pulse Response
Rev. 0 | Page 21 of 24
AD8067
VOUT
Reference network:
VIN
T
V+REF − 3 dB Bandwidth =
1
2π(R2 || R 3)C 2
Resistors R4 and R1 set the gain, in this case an inverting gain of 10
was selected. In this application, the input and output bandwidths
were set for approximately 10 Hz. The reference network was set for
a tenth of the input and output bandwidth, at approximately 1 Hz.
CH1 200mV
CH2 200mV
M 50ns CH1
R4
2.7kΩ
288mV
Figure 55. Gain of 2 Pulse Response
C1
47µF
Single-Supply Operation
VIN
R1
300Ω
4
+5V
C3
10µF
5
C4
0.1µF
AD8067
The AD8067 is well suited for low voltage single-supply
applications, given its N-channel JFET input stage and rail-to-rail
output stage. It is fully specified for 5 V supplies. Successful singlesupply applications require attention to keep signal voltages within
the input and output headroom limits of the amplifier. The input
stage headroom extends to 1.7 V (minimum) on a 5 V supply. The
center of the input range is 0.85 V. The output saturation limit
defines the hard limit of the output headroom. This limit depends
on the amount of current the amplifier is sourcing or sinking, as
shown in Figure 29.
Traditionally, an offset voltage is introduced in the input network
replacing ground as a reference. This allows the output to swing
about a dc reference point, typically midsupply. Attention to the
required headroom of the amplifier is important, in this case the
required headroom from the positive supply is 3 V; therefore 1.5 V
was selected as a reference, which allows for a 100 mV signal at the
input. Figure 56 shows the AD8067 configured for 5 V supply
operation with a reference voltage of 1.5 V. Capacitors C1 and C5
ac-couple the signal into an out of the amplifier and partially
determine the bandwidth of the input and output structures.
VINPUT – 3 dB Bandwidth =
VOUTPUT – 3 dB Bandwidth =
1
2πR1C1
3
+5V
R2
70kΩ
C5
15µF
VOUT
1
2
R3
30kΩ
RL
1kΩ
C2
6.8µF
Figure 56. Single-Supply Operation Schematic
High Gain, High Bandwidth Composite
Amplifier
The composite amplifier takes advantage of combining key
parameters that may otherwise be mutually exclusive of a
conventional single amplifier. For example, most precision
amplifiers have good dc characteristics but lack high speed ac
characteristics. Composite amplifiers combine the best of both
amplifiers to achieve superior performance over their single op
amp counterparts. The AD8067 and the AD8009 are well suited for
a composite amplifier circuit, combining dc precision with high
gain and bandwidth. The circuit runs off a ±5 V power supply at
approximately 20 mA of bias current. With a gain of approximately
40 dB, the composite amplifier offers <1 pA input current, a gain
bandwidth product of 6.1 GHz, and a slew rate of 630 V/µsec.
1
2πRL C 5
Resistors R2 and R3 set a 1.5 V output bias point for the output
signal to swing about. It is critical to have adequate bypassing to
provide a good ac ground for the reference voltage. Generally the
bandwidth of the reference network (R2, R3, and C2) is selected to
be one tenth that of the input bandwidth. This ensures that any
frequencies below the input bandwidth do not pass through the
reference network into the amplifier.
Rev. 0 | Page 22 of 24
AD8067
R2
4.99kΩ
C1
10µF
+5V
R1
51.1Ω
INPUT
4
5
AD8067
3
2
–5V
C2
1 0.1µF
C3
10µF
C4
0.1µF
3
C5
5pF
7
AD8009
6
C8
0.1µF
4
C9
10µF
C10
0.001µF –5V
C11
0.1µF
2
C1 AMPL
4V
C7
10µF
C6 +5V
0.001µF
R4
200Ω
OUTPUT
T
R5
50Ω
CH1 1V
R3
21.5Ω
M 25ns CH1
0V
Figure 59. Large Signal Response
Figure 57. AD8067/AD8009 Composite Amplifier AV = 100, GBWP = 6.1 GHz
The composite amplifier is set for a gain of 100. The overall gain is
set by the following equation:
C1 AMPL
480mV
VO R2
=
+1
VI
R1
T
The output stage is set for a gain of +10; therefore, the AD8067 has
an effective gain of +10, thereby allowing it to a maintain
bandwidth in excess of 55 MHz.
The circuit can be tailored for different gain values; keeping the
ratios roughly the same will ensure that the bandwidth integrity is
maintained. Depending on the board layout, capacitor C5 may be
required to reduce ringing on the output. The gain bandwidth and
pulse responses are shown in Figure 58, Figure 59, and Figure 60.
Layout of this circuit requires attention to the routing and length of
the feedback path. It should be kept as short as possible to
minimize stray capacitance.
44
42
40
38
dB
36
34
32
30
28
26
24
0.1
1
10
FREQUENCY – MHz
100
Figure 58. Gain Bandwidth Response
Rev. 0 | Page 23 of 24
CH1 200mV
M 25ns CH1
Figure 60. Small Signal Response
0V
AD8067
OUTLINE DIMENSIONS
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.15 MAX
0.50
0.30
SEATING
PLANE
0.22
0.08
10°
0°
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 61. 5-Lead Plastic Surface Mount Package [SOT-23}
(RT-5)
Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary
ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Ordering Guide
Model
AD8067ART-REEL
AD8067ART-REEL7
AD8067ART-R2
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
Table 3. Ordering Guide
© 2002 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
C03205-0-11/02(0)
Rev. 0 | Page 24 of 24
Package Outline
RT-5
RT-5
RT-5
Branding Information
HAB
HAB
HAB