MC10E451, MC100E451 5VECL 6−Bit D Register Differential Data and Clock Description The MC10E/100E451 contains six D−type flip−flops with single−ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Master Reset (MR) input resets all Q outputs to LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip−flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below VCC. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. Features • • • • • • • • • • • Differential Inputs: Data and Clock VBB Output http://onsemi.com PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 28 MCxxxE451FNG AWLYYWW xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. 1100 MHz Min. Toggle Frequency Asynchronous Master Reset ORDERING INFORMATION PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Transistor Count = 348 devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. • Moisture Sensitivity Level: • Pb = 1; Pb−Free = 3 For Additional Information, see Application Note AND8003/D Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 9 1 Publication Order Number: MC10E451/D MC10E451, MC100E451 CLK D5 D5 D4 D4 D3 D3 25 24 23 22 21 20 VCCO D0 D0 D 18 26 D1 D1 D D2 D2 D Q3 D3 D3 D VCCO D4 D4 D D5 D5 D Q5 VBB 27 17 Q4 CLK 28 16 VCC 15 VEE 1 MR 2 14 NC 3 13 Q2 D0 4 12 Q1 MC10E451/MC100E451 5 6 7 8 9 10 D0 D1 D1 D2 D2 VCCO Q0 FUNCTION ECL Differential Clock Input MR ECL Master Reset Input Q0 − Q5 ECL Data Outputs VBB Reference Voltage Output VCC, VCCO Positive Supply VEE Negative Supply NC No Connect Q3 R Q4 R Q5 R Figure 2. Logic Diagram Table 1. PIN DESCRIPTION CLK, CLK R MR Figure 1. 28−Lean Pinout Assignment (Top View) ECL Differential Data Input Q2 VBB Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. D0 − D5, D0 − D5 Q1 R CLK CLK 11 * All VCC and VCCO pins are tied together on the die. PIN Q0 R 19 http://onsemi.com 2 MC10E451, MC100E451 Table 2. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm PLCC−28 PLCC−28 63.5 43.5 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W Tsol Wave Solder 265 265 °C Pb Pb−Free Condition 2 VI v VCC VI w VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 MC10E451, MC100E451 Table 3. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1) 0°C Symbol Characteristic Min 25°C Typ Max 84 101 Min 85°C Typ Max 84 101 Min Typ Max Unit 84 101 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mV VOL Output LOW Voltage (Note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV VIH Input HIGH Voltage (Single−Ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV VIL Input LOW Voltage (Single−Ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV VBB Output Voltage Reference 3.62 3.74 3.65 3.75 3.69 3.81 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) 2.2 4.6 2.2 4.6 2.2 4.6 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 0.3 150 0.5 0.25 0.3 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. Table 4. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4) 0°C Symbol Characteristic Typ Max 84 101 −1020 −930 −840 Output LOW Voltage (Note 5) −1950 −1790 VIH Input HIGH Voltage (Single−Ended) −1170 VIL Input LOW Voltage (Single−Ended) −1950 VBB Output Voltage Reference VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) IIH Input HIGH Current IIL Input LOW Current IEE Power Supply Current VOH Output HIGH Voltage (Note 5) VOL Min 25°C Min 85°C Typ Max 84 101 −980 −895 −810 −1630 −1950 −1790 −1005 −840 −1130 −1715 −1480 −1950 −1.38 −1.27 −2.8 −0.4 Typ Max Unit 84 101 mA −910 −815 −720 mV −1630 −1950 −1773 −1595 mV −970 −810 −1060 −890 −720 mV −1715 −1480 −1950 −1698 −1445 mV −1.35 −1.25 −1.31 −1.19 V −2.8 −0.4 −2.8 −0.4 V 150 mA 150 0.5 0.3 Min 150 0.5 0.065 0.3 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V. 5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. http://onsemi.com 4 MC10E451, MC100E451 Table 5. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7) 0°C Symbol Characteristic Min 25°C Typ Max 84 101 Min 85°C Typ Max 84 101 Min Typ Max Unit 97 116 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 8) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 8) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV VIH Input HIGH Voltage (Single−Ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 2.2 4.6 2.2 4.6 2.2 4.6 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 0.3 150 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. Table 6. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 10) 0°C Symbol Characteristic Typ Max 84 101 −1025 −950 −880 Output LOW Voltage (Note 11) −1810 −1705 VIH Input HIGH Voltage (Single−Ended) −1165 VIL Input LOW Voltage (Single−Ended) −1810 VBB Output Voltage Reference VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) IIH Input HIGH Current IIL Input LOW Current IEE Power Supply Current VOH Output HIGH Voltage (Note 11) VOL Min 25°C Min 85°C Typ Max 84 101 −1025 −950 −880 −1620 −1810 −1745 −1025 −880 −1165 −1645 −1475 −1810 −1.38 −1.26 −2.8 −0.4 Typ Max Unit 97 116 mA −1025 −950 −880 mV −1620 −1810 −1740 −1620 mV −1025 −880 −1165 −1025 −880 mV −1645 −1475 −1810 −1645 −1475 mV −1.38 −1.26 −1.38 −1.26 V −2.8 −0.4 −2.8 −0.4 V 150 mA 150 0.5 0.3 Min 150 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.8 V. 11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. http://onsemi.com 5 MC10E451, MC100E451 Table 7. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 13) 0°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max 1.1 Min Typ Max fMAX Maximum Toggle Frequency 1.1 tPLH tPHL Propagation Delay to Output CLK (Differential), CLK (Single−Ended), MR 625 ts Setup Time D 150 −100 150 −100 150 −100 ps th Hold Time D 250 100 250 100 250 100 ps tRR Reset Recovery Time 750 600 750 600 750 600 ps tPW Minimum Pulse Width 1050 1.1 Unit 625 1050 GHz 625 1050 ps ps CLK, MR 400 400 400 tSKEW Within−Device Skew (Note 14) 100 100 100 ps tJITTER Random Clock Jitter (RMS) <1.0 <1.0 <1.0 ps VPP Input Voltage Swing (Differential Configuration) tr tf Rise/Fall Times 150 1000 150 1000 150 1000 mV ps (20 − 80%) 275 450 800 275 450 800 275 450 800 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. 10 Series: VEE can vary −0.46 V / +0.06 V. 100 Series: VEE can vary −0.46 V / +0.8 V. 14. Within−device skew is defined as identical transitions on similar paths through a device. http://onsemi.com 6 MC10E451, MC100E451 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping † MC10E451FN PLCC−28 37 Units / Rail MC10E451FNG PLCC−28 (Pb−Free) 37 Units / Rail MC10E451FNR2 PLCC−28 500 / Tape & Reel MC10E451FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel MC100E451FN PLCC−28 37 Units / Rail MC100E451FNG PLCC−28 (Pb−Free) 37 Units / Rail MC100E451FNR2 PLCC−28 500 / Tape & Reel MC100E451FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 7 MC10E451, MC100E451 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE E −N− 0.007 (0.180) B Y BRK T L−M M 0.007 (0.180) U M N S T L−M S S N S D Z −M− −L− W 28 D X V 1 A 0.007 (0.180) R 0.007 (0.180) C M M T L−M T L−M S S N S N S 0.007 (0.180) H N S S G J 0.004 (0.100) −T− SEATING T L−M S N T L−M S N S K PLANE F VIEW S G1 M K1 E S T L−M S VIEW D−D Z 0.010 (0.250) 0.010 (0.250) G1 VIEW S S NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10_ 0.410 0.430 0.040 −−− http://onsemi.com 8 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10_ 10.42 10.92 1.02 −−− 0.007 (0.180) M T L−M S N S MC10E451, MC100E451 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10E451/D