ALSC AS7C332MPFD18A 3.3v 2m x 18 pipelined burst synchronous sram Datasheet

February 2005
AS7C332MPFD18A
®
3.3V 2M × 18 pipelined burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Organization: 2,097,152 words × 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.1/3.5/3.8 ns
Fast OE access time: 3.1/3.5/3.8 ns
Fully synchronous register-to-register operation
Double-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate VDDQ
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
CLR
21
A[20:0]
2M x 18
Memory
array
Burst logic
Q
D
21
19 21
CS Address
register
CLK
18
18
GWE
BWb
D DQb
BWE
CLK
D DQa Q
Q
Byte Write
registers
BWa
2
Byte Write
registers
CLK
CE0
CE1
CE2
D
Enable Q
register
CE
CLK
ZZ
Power
down
OE
Input
registers
Output
registers
CLK
CLK
D Enable Q
delay
register
CLK
18
OE
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
2/10/05, v.1.1
-200
5
200
3.1
450
170
90
Alliance Semiconductor
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
AS7C332MPFD18A
®
32 Mb Synchronous SRAM products list1,2
Org
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
2MX18
Part Number
AS7C332MPFS18A
AS7C331MPFS32A
AS7C331MPFS36A
AS7C332MPFD18A
AS7C331MPFD32A
AS7C331MPFD36A
AS7C332MFT18A
AS7C331MFT32A
AS7C331MFT36A
AS7C332MNTD18A
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
Speed
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
200/166/133 MHz
1MX32
1MX36
2MX18
1MX32
1MX36
AS7C331MNTD32A
AS7C331MNTD36A
AS7C332MNTF18A
AS7C331MNTF32A
AS7C331MNTF36A
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
200/166/133 MHz
200/166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
NTD1-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTDTM
Flow-through Burst Synchronous SRAM with NTDTM
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
2/10/05, v.1.1
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AS7C332MPFD18A
®
Pin assignment
NC
NC
NC
TQFP 14 x 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
NC
NC
VSSQ
VDDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
NC
VDD
NC
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP - top view
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AS7C332MPFD18A
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Functional description
The AS7C332MPFD18A is a high-performance CMOS 32-Mbit Synchronous Static Random Access Memory (SRAM) device
organized as 2,097,152 words × 18 bits. It incorporates a two-stage register-register pipeline for highest frequency on any given
technology.
Fast cycle times of 5/6/7.5 ns with clock access times (tCD) of 3.1/3.5/3.8 ns enable 200,166 and 133MHz bus frequencies.
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input.
With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device
uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes
may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.
Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in doublecycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C332MPFD18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at
2.5V or 3.3V. These devices are available in a 100-pin TQFP package.
TQFP capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN*
CI/O*
Test conditions
VIN = 0V
VOUT = 0V
Min
-
Max
5
7
Unit
pF
pF
* Guaranteed not tested
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)1
Thermal resistance
(junction to top of case)1
Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
Symbol
θJA
Typical
40
Units
°C/W
4–layer
θJA
22
°C/W
θJC
8
°C/W
1 This parameter is sampled
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AS7C332MPFD18A
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Signal descriptions
Pin
CLK
A,A0,A1
DQ[a,b]
I/O
I
I
I/O
Properties
CLOCK
SYNC
SYNC
CE0
I
SYNC
CE1, CE2
I
SYNC
ADSP
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
GWE
I
SYNC
BWE
I
SYNC
BW[a,b]
I
SYNC
OE
I
ASYNC
LBO
I
STATIC
ZZ
NC
I
-
ASYNC
-
Description
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 18 bits. When high, BWE and BW[a,b] control write
enable.
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,
the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
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AS7C332MPFD18A
®
Write enable truth table (per byte)
Function
Write All Bytes
Write Byte a
Write Byte b
Read
GWE
L
H
H
H
H
H
BWE
X
L
L
L
H
L
BWa
X
L
L
H
X
H
BWb
X
L
H
L
X
H
Key: X = don’t care, L = low, H = high, n = a, b; BWE, BWn = internal write signal.
Asynchronous Truth Table
Operation
Snooze mode
Read
Write
Deselected
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O Status
High-Z
Dout
High-Z
Din, High-Z
High-Z
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Interleaved burst address(LBO = 1)
Starting Address
First Increment
Second Increment
Third Increment
2/10/05, v.1.1
Linear burst address(LBO = 0)
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Starting Address
First Increment
Second Increment
Third Increment
Alliance Semiconductor
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
10
11
10
10
11
00
01
11
00
01
10
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AS7C332MPFD18A
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Synchronous truth table[4]
CE01
CE1
CE2
ADSP
ADSC
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV WRITE[2]
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
OE
Address accessed
CLK
Operation
DQ
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
D3
D
D
D
D
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE,
GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time.
4. ZZ pin is always Low.
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AS7C332MPFD18A
®
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Symbol
VDD, VDDQ
VIN
Min
–0.5
–0.5
Max
+4.6
VDD + 0.5
Unit
V
V
VIN
Pd
IOUT
Tstg
Tbias
–0.5
–
–
–65
–65
VDDQ + 0.5
1.8
20
+150
+135
V
W
mA
o
C
o
C
Input voltage relative to GND (I/O pins)
Power dissipation
Short circuit output current
Storage temperature
Temperature under bias
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
VDDQ
Vss
Min
3.135
3.135
0
Nominal
3.3
3.3
0
Max
3.465
3.465
0
Unit
V
V
V
Min
3.135
2.375
0
Nominal
3.3
2.5
0
Max
3.465
2.625
0
Unit
V
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
2/10/05, v.1.1
Symbol
VDD
VDDQ
Vss
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AS7C332MPFD18A
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
|ILI|
|ILO|
Input high (logic 1) voltage
VIH
Input low (logic 0) voltage
VIL
Output high voltage
Output low voltage
VOH
VOL
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Address and control pins
I/O pins
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
Min
-2
-2
Max
2
2
Unit
µA
µA
2*
2*
-0.3**
-0.5**
2.4
–
VDD+0.3
VDDQ+0.3
0.8
0.8
–
0.4
V
V
V
V
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current†
Output leakage current
Sym
|ILI|
|ILO|
Input high (logic 1) voltage
VIH
Input low (logic 0) voltage
VIL
Output high voltage
Output low voltage
VOH
VOL
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Address and control pins
I/O pins
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
Min
-2
-2
1.7*
1.7*
-0.3**
-0.3**
1.7
–
Max
2
2
VDD+0.3
VDDQ+0.3
0.7
0.7
–
0.7
Unit
µA
µA
V
V
V
V
V
V
† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*V max < VDD +1.5V for pulse width less than 0.2 X t
IH
CYC
**V
IL min
= -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter
Operating power supply current1
Sym
ICC
ISB
Standby power supply current
Conditions
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or > VDD – 0.2V, Deselected,
f = fMax, ZZ < VIL
-200
-166
-133
450
400
350
170
150
140
ISB1
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
90
90
90
ISB2
Deselected, f = fMax, ZZ ≥ VDD – 0.2V,
all VIN ≤ VIL or ≥ VIH
80
80
80
Unit
mA
mA
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
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AS7C332MPFD18A
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Timing characteristics over operating range
Parameter
Sym
fMax
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tOHOE
tCH
tCL
tAS
tDS
tWS
tCSS
tAH
tDH
tWH
tCSH
tADVS
tADSPS
tADSCS
tADVH
tADSPH
tADSCH
Clock frequency
Cycle time
Clock access time
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
–200
Min
Max
–
200
5
–
–
3.1
–
3.1
0
–
1.5
–
0
–
–
3.0
–
3.0
0
–
2.0
–
2.0
–
1.4
–
1.4
–
1.4
–
1.4
–
0.4
–
0.4
–
0.4
–
0.4
–
1.4
–
1.4
–
1.4
–
0.4
–
0.4
–
0.4
–
–166
Min
Max
–
166
6
–
–
3.5
–
3.5
0
–
1.5
–
0
–
–
3.4
–
3.4
0
–
2.4
–
2.4
–
1.5
–
1.5
–
1.5
–
1.5
–
0.5
–
0.5
–
0.5
–
0.5
–
1.5
–
1.5
–
1.5
–
0.5
–
0.5
–
0.5
–
-133
Min
–
7.5
–
–
0
1.5
0
–
–
0
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
Max
133
–
3.8
3.8
–
–
–
3.8
3.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes1
2,3,4
2
2,3,4
2,3,4
2,3,4
5
5
6
6
6,7
6,8
6
6
6,7
6,8
6
6
6
6
6
6
1 See “Notes” on page 16.
Snooze Mode Electrical Characteristics
Description
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2/10/05, v.1.1
Conditions
Symbol
ZZ > VIH
ISB2
tPDS
tPUS
tZZI
tRZZI
Alliance Semiconductor
Min
Max
Units
80
mA
cycle
cycle
cycle
2
2
2
0
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Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
LOAD NEW ADDRESS
tAH
tAS
A1
Address
A2
tWS
A3
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
ADV inserts wait states
OE
tOE
tHZOE
tLZOE
Dout
Q(A1)
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
tCD
tHZC
tOH
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Burst
Burst
Read
Suspend
Burst
Burst
Burst
Burst
Read
Read
Q(A3)
DSEL*
Read
Read
Read
Read
Read
Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11)
Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
*Outputs are disabled within two clk cycles after DSEL command
2/10/05, v.1.1
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Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
A1
Address
A3
A2
tWS
tWH
tADVS
tADVH
tDS
tDH
BWE
BW[a:d]
tCSS
tCSH
CE0, CE2
CE1
ADV SUSPENDS BURST
ADV
OE
Din
D(A1)
Read
Q(A1)
Suspend
Write
D(A1)
D(A2)
Read
Q(A2)
D(A2Ý01)
Suspend
Write
D(A 2)
D(A2Ý01)
D(A2Ý10)
D(A2Ý11)
D(A3)
ADV
ADV
ADV
Suspend
Burst
Burst
Burst
Write
Write
Write
D(A 2Ý01) Write
D(A 2Ý01)
D(A 2Ý10) D(A 2Ý11)
D(A3Ý01)
Write
D(A 3)
D(A3Ý10)
Burst
Write
D(A 3Ý01)
ADV
Burst
Write
D(A 3Ý10)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
2/10/05, v.1.1
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AS7C332MPFD18A
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCL
tCH
CLK
tADSPH
tADSPS
ADSP
tAH
tAS
A2
A1
Address
A3
tWH
tWS
GWE
CE0, CE2
CE1
tADVH
tADVS
ADV
OE
tDS tDH
Din
D(A2)
tOE
tCD
tLZC
Dout
DSEL
Read
Q(A1)
tHZOE
Q(A1)
Suspend
Read
Q(A1)
tOH
tLZOE
Q(A3)
Read
Q(A2)
Suspend
Write
D(A 2)
Read
Q(A3)
ADV
Burst
Read
Q(A 3Ý01)
Q(A3Ý01)
ADV
Burst
Read
Q(A 3Ý10)
Q(A3Ý10)
Q(A3Ý11)
ADV
Burst
Read
Q(A 3Ý11)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
2/10/05, v.1.1
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AS7C332MPFD18A
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCYC
tCL
tCH
CLK
tADSCS
tADSCH
ADSC
tAS
A1
ADDRESS
A5
A4
A3
A2
A7
A6
tWS
tAH
A8
A9
tWH
GWE
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
tLZOE
Q(A1)
Dout
tLZOE
tHZOE
Q(A2)
Q(A3)
Q(A8)
Q(A4)
D(A5)
READ
Q(A1)
2/10/05, v.1.1
READ
Q(A2)
READ
Q(A3)
READ
Q(A4)
Q(A9)
tDH
tDS
Din
tOH
D(A6)
D(A7)
WRITE WRITE WRITE
D(A6) D(A7)
D(A5)
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READ
Q(A8)
READ
Q(A9)
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Timing waveform of power down cycle
tCH
tCYC
tCL
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
tWH
tWS
GWE
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
Din
tLZOE
tHZOE
D(A2)
D(A2(Ý01))
tHZC
Dout
Q(A1)
tPUS
tPDS
ZZ Recovery Cycle
ZZ
Normal Operation Mode
ZZ Setup Cycle
tZZI
tRZZI
Isupply
ISB2
READ SUSPEND
Q(A1) READ
Q(A1)
2/10/05, v.1.1
Sleep
State
Alliance Semiconductor
READ SUSPEND CONQ(A2) WRITE TINUE
D(A2) WRITE
D(A2 Ý01)
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AC test conditions
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
• Input and output timing reference levels: 1.5V.
+3.0V
90%
10%
GND
90%
10%
Figure A: Input waveform
DOUT
Z0 = 50Ω
50Ω
VL = 1.5V
for 3.3V I/O;
30 pF* = V
DDQ/2
for 2.5V I/O
Figure B: Output load (A)
319Ω/1667Ω
DOUT
353Ω/1538Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load(B)
Notes
1
2
3
4
5
6
7
8
For test conditions, see “AC test conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
tCH is measured as high if above VIH, and tCL is measured as low if below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to GWE, BWE, and BW[a,b].
Chip select refers to CE0, CE1, and CE2.
2/10/05, v.1.1
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AS7C332MPFD18A
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Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
Hd
D
b
e
0.65 nominal
Hd
15.85
16.15
He
21.80
22.20
L
0.45
0.75
L1
He E
1.00 nominal
α
0°
7°
Dimensions in millimeters
c
L1
L
2/10/05, v.1.1
A1 A2
Alliance Semiconductor
α
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AS7C332MPFD18A
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Ordering information
Package & Width
TQFP x 18
200 MHz
AS7C332MPFD18A-200TQC
AS7C332MPFD18A-200TQI
166 MHz
AS7C332MPFD18A-166TQC
AS7C332MPFD18A-166TQI
133 MHz
AS7C332MPFD18A-133TQC
AS7C332MPFD18A-133TQI
Note:
Add suffix ‘N’ to the above part numbers for lead free parts (Ex AS7C332MPFD18A-200TQCN)
Part numbering guide
AS7C
33
2M
PF
D
18
A
–XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
11
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 2M = 2Meg
4. Pipelined Mode
5. Deselect: D = Double cycle deselect
6. Organization: 18 = x 18
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP
10. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
11. N = Lead Free Part
2/10/05, v.1.1
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AS7C332MPFD18A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C332MPFD18A
Document Version: v.1.1
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products
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