ACPL-P302/W302 0.4 Amp Output Current IGBT Gate Driver Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-P302/W302 consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. x High speed response. Applications x Isolated IGBT/Power MOSFET gate drive x AC and brushless DC motor drives x Industrial inverters x Ultra high CMR. x Bootstrappable supply current. x Available in Stretched SO-6 package x Package Clearance/Creepage at 8mm (ACPL-W302) x Safety Approval: UL1577 recognized with 3750 Vrms for 1 minute for ACPL-P302 and 5000 Vrms for 1 minute for ACPLW302. CSA Approved. IEC/EN/DIN EN 60747-5-2 Approved VIORM = 891 Vpeak for ACPL-P302 VIORM = 1140 Vpeak for ACPL-W302 x Inverter for home appliances Specifications x Induction cooker x 0.4 A maximum peak output current. x Switching Power Supplies (SPS) x 0.2 A minimum peak output current. Functional Diagram x 0.7 μs maximum propagation delay over temperature range. x ICC(max) = 3 mA maximum supply current. ANODE 1 6 VCC N.C. 2 5 VO CATHODE 3 4 VEE SHIELD x 10 kV/μs minimum common mode rejection (CMR) at VCM = 1000 V. x Wide VCC operating range: 10 V to 30 V over temperature range. x Wide operating temperature range: –40°C to 100°C. Truth Table LED VO OFF LOW ON HIGH Note: A 0.1 μF bypass apacitor must be connected between pins VCC and VEE. CAUTION: IT IS ADVISED THAT NORMAL STATIC PRECAUTIONS BE TAKEN IN HANDLING AND ASSEMBLY OF THIS COMPONENT TO PREVENT DAMAGE AND/OR DEGRADATION WHICH MAY BE INDUCED BY ESD. Ordering Information ACPL-P302 is UL Recognized with 3750 Vrms for 1 minute per UL1577. ACPL-W302 is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Package -000E ACPL-P302 ACPL-W302 -500E -060E Surface Mount Stretched SO-6 X X X -560E IEC/EN/DIN EN 60747-5-2 Stretched SO-6 X X 1000 per reel X X X X Quantity 100 per tube X -000E -060E UL 5000 Vrms / 1 minute rating X -560E -500E Tape & Reel X X 100 per tube X 1000 per reel X 100 per tube X 1000 per reel X X 100 per tube X X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-P302-560E to order product of Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/ DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: ACPL-P302-000E to order product of Stretched SO-6 Surface Mount package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. 2 Package Outline Drawings ACPL-P302 Stretched SO-6 Package 0.381±0.127 [0.015±0.005] +0.254 0 +0.010 0.180 -0.000 4.580 1.27 BSG [0.050] 10.7 [0.421] 1.27 [0.050] 7.62 [0.300] 6.81 [0.268] 0.45 [0.018] 2.16 [0.085] 3.180±0.127 [0.125±0.005] 1.590±0.127 [0.063±0.005] 45° 0.76 [0.030] 7° 7° 7° 7° 0.20±0.10 [0.008±0.004] 0.254±0.050 [0.010±0.002] 5° NOM. 1±0.250 [0.040±0.010] Floating Lead Protusions max. 0.25 [0.01] Dimensions in Millimeters [ Inches ] Lead Coplanarity= 0.1mm [0.004 Inches ] 9.7±0.250 [0.382±0.010] ACPL-W302 Stretched SO-6 Package 1.27 BSG [0.050] 0.381 ± 0.127 [0.015 ± 0.005] 1 0.760 [0.030] 12.650 [0.498] 6 2 5 3 4 7.62 [0.300] +0.127 6.807 0 +0.005 0.268 -0.000 0.45 [0.018] +0.254 0 +0.010 0.180 -0.000 4.580 7° 45° 1.270 [0.050] 1.590±0.127 [0.063±0.005] 1.905 [0.075] 3.180±0.127 0.125±0.005 7° 0.20±0.10 [0.008±0.004] 7° 0.750±0.250 [0.0295±0.010] 0.254±0.050 [0.010±0.002] 7° 35° NOM. 11.500±0.25 [0.453±0.010] Floating Lead protusion max. 0.25[0.01] Dimensions in millimeters [Inches] Lead Coplanarity=0.1mm [0.004 Inches] 3 Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-P302/W302 is approved by the following organizations: IEC/EN/DIN EN 60747-5-2 (Option 060 only) Approval under: IEC 60747-5-5:2007 CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. UL Approval under UL 1577 component recognition program up to VISO = 3750 VRMS for the ACPL-P302 and VISO = 5000 VRMS for the ACPL-W302, File E55361. Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060 only) Description Symbol ACPL-W302 ACPL-P302 Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage d 150 Vrms for rated mains voltage d 300 Vrms for rated mains voltage d 450 Vrms for rated mains voltage d 600 Vrms for rated mains voltage d 1000 Vrms I-IV I-IV I-IV I-IV I-III I-IV I-IV I-III I-III Climatic Classification 55/100/21 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 2 Units VIORM 1140 891 V peak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec Partial Discharge < 5 pC, VPR 2137 1670 V peak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and sample test, tm = 10 sec, Partial Discharge < 5 pC VPR 1824 1426 V peak VIOTM 8000 6000 V peak Safety Limiting Values (Maximum values allowed in the event of a failure) Case Temperature Input Current** Output Power ** TS IS,INPUT PS,OUTPUT 175 230 600 175 230 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS d109 d109 : Highest Allowable Overvoltage* (Transient Overvoltage, tini = 60 sec) * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and IS on ambient temperature. OUTPUT POWER – PS, INPUT CURRENT – IS Maximum Working Insulation Voltage 800 PS (mW) IS (mA) 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C 4 Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-P302 ACPL-W302 Units Conditions Minimum External Air Gap (External Clearance) L(101) 7.0 8.0 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 8.0 8.0 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Minimum Internal Tracking (Internal Creepage) NA NA mm Measured from input terminals to output terminals, along internal cavity. >175 >175 V DIN IEC 112/VDE 0303 Part 1 IIIa IIIa Tracking Resistance (Comparative Tracking Index) CTI Isolation Group Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature TS -55 125 °C Operating Temperature TA -40 100 °C Average Input Current IF(AVG) 25 mA Peak Transient Input Current (<1 μs pulse width, 300pps) IF(TRAN) 1.0 A Reverse Input Voltage VR 5 V “High” Peak Output Current IOH(PEAK) 0.4 A 2 “Low” Peak Output Current IOL(PEAK) 0.4 A 2 Supply Voltage VCC - VEE -0.5 35 V Output Voltage VO(PEAK) -0.5 VCC V 1 Output Power Dissipation PO 250 mW 3 Input Power Dissipation PI 45 mW 4 Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section Note Table 4.Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply VCC - VEE 10 30 V Input Current (ON) IF(ON) 7 12 mA Input Voltage (OFF) VF(OFF) - 3.6 0.8 V Operating Temperature TA - 40 100 °C 5 Table 5. Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. High Level Output Current IOH 0.15 Units Test Conditions A VO = VCC - 4 0.3 A VO = VCC - 10 A VO = VEE + 2.5 0.2 0.3 A VO = VEE + 10 4 2 VCC-4 VCC-1.8 V IO = -100 mA 1 6, 7 0.2 Low Level Output Current IOL Typ. Max. 0.15 Fig. Note 5 2 2 5 High Level Output Voltage VOH Low Level Output Voltage VOL 0.4 1 V IO = 100 mA 3 High Level Supply Current ICCH 0.7 3 mA IF = 10 mA 5, 6 15 Low Level Supply Current ICCL 1.2 3 mA IF = 0 mA 5, 6 15 Threshold Input Current Low to High IFLH 6 mA IO = 0 mA, VO > 5 V 7, 13 Threshold Input Voltage High to Low VFHL 0.8 V IO = 0 mA, VO > 5 V Input Forward Voltage VF 1.2 V IF = 10 mA Temperature Coefficient of Input Forward Voltage 'VF/'TA mV/°C IF = 10 mA V IR = 10 μA pF f = 1 MHz, VF = 0 V Input Reverse Breakdown Voltage BVR Input Capacitance CIN 1.5 1.8 -1.6 5 60 14 Table 6. Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level tPLH 0.1 0.2 0.7 μs 8, 9, 10, 11, 12, 15 14 Propagation Delay Time to Low Output Level tPHL 0.1 0.3 0.7 μs Rg = 75:, Cg = 1.5 nF, f = 10 kHz, Duty Cycle = 50%, IF = 7 mA, VCC = 30 V Propagation Delay Difference Between Any Two Parts or Channels PDD -0.5 0.5 μs Rise Time tR 50 ns Fall Time tF 50 ns Output High Level Common Mode Transient Immunity |CMH| 10 kV/μs Output Low Level Common Mode Transient Immunity |CML| 10 kV/μs 6 14 11 TA = 25°C, VCM = 1000 V 16 12 16 13 Table 7. Package Characteristics Parameter Symbol Input-Output Momentary Withstand Voltage VISO Min. ACPL-P302 3750 ACPL-W302 5000 Typ. Input-Output Resistance RI-O 1012 Input-Output Capacitance CI-O 0.6 Max. Units Test Conditions Vrms TA = 25°C, RH < 50% for 1 min. 8, 10 VI-O = 500 V 10 pF Fig. Note 9, 10 Freq=1 MHz Notes: 1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C. 2. Maximum pulse width = 10 Ps, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 0.2 A. See Application section for additional details on limiting IOL peak. 3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C. 4. Input power dissipation does not require derating. 5. Maximum pulse width = 50 Ps, maximum duty cycle = 0.5%. 6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 4500 Vrms for 1 second (leakage detection current limit II-O < 5 PA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 9. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000 Vrms for 1 second (leakage detection current limit II-O < 5 A). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 10. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 11. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions. 12. Common mode transient immunity in the high state is the maximum tolerable |dVCM/dt| of the common mode pulse VCM to assure that the output will remain in the high state (i.e. VO > 15.0 V). 13. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. VO < 1.0 V). 14. This load condition approximates the gate load of a 1200 V/20 A IGBT. 15. The power supply current increases when operating frequency and Qg of the driven IGBT increases. 7 -0.5 -1.0 -1.5 -2.0 -2.5 -50 -25 0 25 50 75 100 125 TA – TEMPERATURE – °C Figure 1. VOH vs. Temperature. (VOH-VCC) – OUTPUT HIGH VOLTAGE DROP – V (VOH-VCC) – HIGH OUTPUT VOLTAGE DROP – V 0 0 VOH -1 -2 -3 -4 -5 -6 0 0.2 0.6 0.4 IOH – OUTPUT HIGH CURRENT – A Figure 2. VOH vs. IOH. VOL – OUTPUT LOW VOLTAGE – V 0.44 0.43 0.42 0.41 0.40 0.39 -50 -25 0 25 50 75 100 125 TA – TEMPERATURE – °C Figure 3. VOL vs. Temperature. Figure 4. VOL vs. IOL. 1.2 1.2 1.0 0.8 0.6 0.4 ICCL ICCH 0.2 0 -50 -25 0 25 50 75 100 125 TA – TEMPERATURE – °C Figure 5. ICC vs. Temperature. 8 ICC – SUPPLY CURRENT – mA ICC – SUPPLY CURRENT – mA 1.4 1.0 0.8 0.6 0.4 ICCL ICCH 0.2 0 10 15 20 25 VCC – SUPPLY VOLTAGE – V Figure 6. ICC vs. VCC. 30 400 TP – PROPAGATION DELAY – ns IFLH – LOW TO HIGH CURRENT THRESHOLD – mA 3.5 3.0 2.5 2.0 1.5 -50 -25 0 25 50 100 TPLH TPHL TA – TEMPERATURE – °C TP – PROPAGATION DELAY – ns 200 100 6 9 12 15 400 300 200 100 TPLH TPHL 0 -50 18 IF – FORWARD LED CURRENT – mA Figure 9. Propagation Delay vs. IF. 0 25 50 100 125 75 Figure 10. Propagation Delay vs. Temperature. 400 TP – PROPAGATION DELAY – ns TP – PROPAGATION DELAY – ns -25 TA – TEMPERATURE – °C 400 350 TPLH TPHL 300 250 0 50 100 150 200 Rg – SERIES LOAD RESISTANCE – Ω Figure 11. Propagation Delay vs. Rg. 9 30 25 500 300 200 20 Figure 8. Propagation delay vs. VCC. 400 0 15 VCC – SUPPLY VOLTAGE – V Figure 7. IFLH vs. Temperature. TP – PROPAGATION DELAY – ns 200 0 10 100 125 75 300 300 200 100 TPLH TPHL 0 0 20 40 60 80 Cg – LOAD CAPACITANCE – nF Figure 12. Propagation Delay vs. Cg. 100 25 IF – FORWARD CURRENT – mA VO – OUTPUT VOLTAGE – V 35 30 25 20 15 10 5 0 -5 1 0 2 3 4 20 15 10 5 0 1.2 6 5 1.4 IF – FORWARD LED CURRENT – mA VF – FORWARD VOLTAGE – V Figure 13. Transfer characteristics. Figure 14. Input Current vs. Forward Voltage. IF IF = 7 to 16 mA 1 A 6 500 W + - 0.1 mF 2 VO 5 75 W 10 KHz 50% DUTY CYCLE 1.8 1.6 3 1 + - VCC = 15 to 30 V 6 0.1 mF B 5V + - 2 5 VO + VCC = 30V 1.5 nF 4 4 + - 3 VCM = 1000V IF tr VCM tf δV 90% δt = VCM Δt 50% VOUT 10% tPLH 0V Δt tPHL VO Figure 15. Propagation Delay Test Circuit and Waveforms. SWITCH AT A: IF = 10 mA VO SWITCH AT B: IF = 0 mA Figure 16. CMR Test Circuit and Waveforms. 10 VOH VOL Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the ACPL-P302/W302 has a very low maximum VOL specification of 1.0 V. Minimizing Rg and the lead inductance from the ACPL-P302/W302 to the IGBT gate and emitter (possibly by mounting the ACPL-P302/W302 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 17. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the ACPL-P302/ W302 input as this can result in unwanted coupling of transient signals into the input of ACPL-P302/W302 and degrade performance. (If the IGBT drain must be routed near the ACPL-P302/W302 input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the ACPL-P302/W302. Esw – ENERGY PER SWITCHING CYCLE – μJ Applications Information 4.0 Qg = 50 nC 3.5 Qg = 400 nC 2.5 2.0 1.5 1.0 0.5 0 40 60 80 100 Figure 18. Energy Dissipated in the ACPL-P302/W302 and for Each IGBT Switching Cycle. PT = P E + PO P E = I F u V F u DutyCycle Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 17 can be analyzed as a simple RC circuit with a voltage supplied by the ACPLP302/W302. V CC − V OL I OLPEAK = 20 0 Rg – GATE RESISTANCE – Ω Selecting the Gate Resistor (Rg) Rg ³ Qg = 100 nC Qg = 200 nC 3.0 24 − 1 0.4 = 57.5 Ω P O = P O(BIAS) + P O(SWITCHING) = I CC u V CC + E SW (R g ; Q g ) u f = (I CCBIAS + K ICC u Q g u f ) u VCC + E SW (R g ; Q g ) u f where KICC · Qg · f is the increase in ICC due to switching and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit in Figure 17 with IF (worst case) = 10 mA, Rg = 57.5 :, Max Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and TAMAX = 85°C: P E = 10 mA u 1.8V u 0.8 = 14 mW P O = (3 mA + (0.001 mA/nC u kHz) u 20 kHz u 100 nC) u 24V + The VOL value of 1 V in the previous equation is the VOL at the peak current of 0.4A. (See Figure 4). Step 2: Check the ACPL-P302/W302 power dissipation and increase Rg if necessary. The ACPL-P302/W302 total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO). 0.3 μJ u 20 kHz = 126 mW £ 250 mW ( P O(MAX) @85 °C) The value of 3 mA for ICC in the previous equation is the max. ICC over entire operating temperature range. Since PO for this case is less than PO(MAX), Rg = 57.5 : is alright for the power dissipation. +5 V 270Ω 1 ACPL-P302/W302 + HVDC 6 0.1 μF CONTROL INPUT 74XXX OPEN COLLECTOR 2 5 3 4 + - VCC = 24V Rg Q1 3-PHASE AC Q2 - HVDC Figure 17. Recommended LED Drive and Application Circuit for ACPL-P302/W302 11 Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 19. The ACPL-P302/W302 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 20. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 17), can achieve 10 kV/μs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. 1 CLEDP 6 2 3 5 4 CLEDN Figure 19. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. 1 CLEDP CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF d VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 21, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF) the LED will remain off and no common mode failure will occur. + VSAT - 3 2 VCC = 18V Rg CLEDN 4 SHIELD · THE ARROWS INDICATE THE DIRECTION · OF CURRENT FLOW DURING - dVCM / dt VCM Figure 21. Equivalent Circuit for Figure 15 During Common Mode Transient. The open collector drive circuit, shown in Figure 22, can not keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. The alternative drive circuit which like the recommended application circuit (Figure 17), does achieve ultra high CMR performance by shunting the LED in the off state. 1 +5 V CLEDP 6 5 6 SHIELD + - 5 2 CLED01 CLED02 CLEDN 6 0.1 mF ILEDP 3 CLEDN 3 2 CLEDP 1 +5 V + - LED Drive Circuit Considerations for Ultra High CMR Performance 5 ILEDN 4 SHIELD Q1 4 Figure 20. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. Figure 22. Not Recommended Open Collector Drive Circuit. +5 V CMR with the LED On (CMRH) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 7 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 10 kV/μs CMR. 1 CLEDP 6 2 3 5 CLEDN SHIELD 4 Figure 23. Recommended LED Drive Circuit for Ultra-High CMR Dead Time and Propagation Delay Specifications. 12 Dead Time and Propagation Delay Specifications The ACPL-P302/W302 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q2 conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 24. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be 500 ns over the operating temperature range of -40° to 100°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure 25. The maximum dead time for the ACPL-P302/ W302 is 1 μs (= 0.5 μs - (-0.5 μs)) over the operating temperature range of –40°C to 100°C. ILED1 VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 ILED1 VOUT1 Q2 OFF ILED2 Q1 ON tPHL MIN Q1 OFF tPHL MAX tPLH Q2 ON VOUT2 MIN Q2 OFF tPLH MAX (tPHL-tPLH) MAX ILED2 PDD* MAX tPHL MAX tPLH MIN PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 24. Minimum LED Skew for Zero Dead Time. MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX) = PDD* MAX – PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 25. Waveforms for Dead Time. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. 13 Thermal Model for ACPL-P302/W302 Streched-SO6 Package Optocoupler Definitions R11: Junction to Ambient Thermal Resistance of LED due to heating of LED Description This thermal model assumes that an 6-pin single-channel plastic package optocoupler is soldered into a 7.62 cm x 7.62 cm printed circuit board (PCB). The temperature at the LED and Detector junctions of the optocoupler can be calculated using the equations below. R12: Junction to Ambient Thermal Resistance of LED due to heating of Detector (Output IC) T1 = (R11 * P1 + R12 * P2) + Ta -- (1) R21: Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of LED. Jedec Specifications R11 R12, R21 R22 low K board 357 150, 166 228 high K board 249 76, 79 159 R22: Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of Detector (Output IC). P1: Power dissipation of LED (W). P2: Power dissipation of Detector / Output IC (W). T1: Junction temperature of LED (˚C). T2: Junction temperature of Detector (˚C). Ta: Ambient temperature. T2 = (R21 * P1 + R22 * P2) + Ta -- (2) Notes: 1. Maximum junction temperature for above parts: 125 °C. ΔT1: Temperature difference between LED junction and ambient (˚C). ΔT2: Temperature deference between Detector junction and ambient. Ambient Temperature: Junction to Ambient Thermal Resistances were measured approximately 1.25cm above optocoupler at ~23˚C in still air For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV02-0091EN AV02-0157EN - December 10, 2010