Intersil ISL6126IRZA Power sequencing controller Datasheet

Power Sequencing Controllers
ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128,
ISL6130
The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127,
ISL6128 and ISL6130 are integrated 4-channel
controlled-on/controlled-off power-supply sequencers with
supply monitoring, fault protection and a “sequence completed”
signal (RESET). For larger systems, more than four supplies can
be sequenced by simply connecting a wire between the
SYSRESET pins of cascaded ICs. The ISL6125 uses four
open-drain outputs to control the on/off sequencing of four
supplies. The other sequencers use a patented, micropower 7x
charge pump to drive four external low-cost NFET switch gates
above the supply rail by 5.3V. These ICs can be biased from 5V
down to 1.5V by any supply.
Features
• Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four
Power Supplies (0.7V to 5V)
• Operates From 1.5V to 5V Supply Voltage
• Supplies VDD +5.3V of Charge Pumped Gate Drive
• Adjustable Voltage Slew Rate for Each Rail
• Multiple Sequencers Can be Daisy-Chained to Sequence an
Infinite Number of Independent Supplies
• Glitch Immunity
• Undervoltage Lockout for Each Supply
• 1µA Sleep State (ISL6123, ISL6130)
• Active High (ISL6123, ISL6130) ENABLE or Low (ISL6124,
ISL6125, ISL6126, ISL6127, ISL6128) ENABLE Input
• Open Drain Version Available (ISL6125)
The 4-channel ISL6123 (ENABLE input), ISL6124 (ENABLE
input) and ISL6125 offer the designer 4-rail control when all
four rails must be in minimal compliance before turn-on and
during operation. The ISL6123 and ISL6130 have a low-power
standby mode when disabled, which is suitable for
battery-powered applications.
• Voltage-determined Sequence (ISL6126, ISL6130)
The ISL6125 operates like the ISL6124, but instead of
charge-pump-driven gate drive outputs, it has open-drain logic
outputs for direct interface to other circuitry.
Applications
In contrast, for the ISL6126 and ISL6130, each of the four
channels operates independently. Each GATE turns on once its
individually associated input voltage requirements are met.
• FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing
• Network Routers
• Telecommunications Systems
AIN
AOUT
BIN
BOUT
CIN
COUT
DIN
VDD
ENABLE
AIN
BIN
CIN
DIN
GATE A
GATE B
GATE C
DOUT
UVLO_A
UVLO_B
SYSRST
UVLO_C
UVLO_D
RESET
DLY_OFF_D
DLY_ON_D
DLY_OFF_C
DLY_ON_C
GROUND
DLY_OFF_B
For volume applications, other programmable options and
features are available. Contact Intersil sales support with your
needs.
• Graphics Cards
DLY_ON_B
Additional I/O is provided for indicating and driving the RESET
state in various configurations.
• Pb-free (RoHS-compliant)
GATE D
External resistors provide flexible voltage threshold
programming of monitored rail voltages. Delay and
sequencing are provided by external capacitors for ramp-up
and ramp-down.
• QFN Package
DLY_OFF_A
The ISL6128 has two groups of two channels, each with its
independent I/O. It is ideal for voltage sequencing into
redundant capability loads. All four inputs must be satisfied
before turn-on, but a single group fault is ignored by the other
group.
• Dual Channel Groupings (ISL6128)
DLY_ON_A
The ISL6127 is a pre-programmed A-B-C-D turn-on and D-C-B-A
turn-off sequenced IC. Once all inputs are in compliance and
ENABLE is asserted, sequencing begins. Each subsequent GATE
turns on after the previous one turns on.
• Pre-programmed Sequence Available (ISL6127)
FIGURE 1. TYPICAL ISL6123 APPLICATION
August 25, 2011
FN9005.11
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2001, 2003-2008, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ISL6123IRZA
61 23IRZ
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6124IRZA
61 24IRZ
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6125IRZA
61 25IRZ
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6126IRZA
61 26IRZ
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6127IRZA
61 27IRZ
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6128IRZA
61 28IRZ
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6130IRZA
61 30IRZ
-40 to +85
24 Ld 4x4 QFN
L24.4x4
ISL6123EVAL1Z
ISL6123 Evaluation Platform
ISL6125EVAL1Z
ISL6125 Evaluation Platform
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130. For
more information on MSL please see Tech Brief TB363.
AIN
AOUT
BIN
VDD
BOUT
CIN
COUT
DIN
BIAS
VDD+5V
LOCK OUT
Q-PUMP
1µA
DOUT
VDD
ENABLE
BIN
CIN
DIN
AIN
1.26V
DLY_OFF_D
DLY_ON_D
DLY_ON_C
DLY_ON_B
DLY_OFF_A
DLY_ON_A
DLY_OFF_B
RESET
DLY_OFF_C
UVLO_A
UVLO_B
UVLO_C
UVLO_D
SYSRST
GROUND
GATE A
GATE B
GATE C
GATE D
1µA
DLY_ONX
-1µA
1µA
DLY_OFFX
10ms
RISING DELAY
1.26V
GATEX
30µs
FIGURE 2. TYPICAL ISL6123 APPLICATION
USAGE
FILTER
UVLOX
RESET
LOGIC
0.633V
150ms
RISING DELAY
EN
SYSRST
FIGURE 3. ISL6123 BLOCK DIAGRAM (1/4)
2
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Configurations
ISL6127
(24 LD QFN)
TOP VIEW
1
18 DLY_OFF_A
GATE_A
2
17 UVLO_C
DLY_OFF_C
3
UVLO_A
NC
18 NC
GATE_A
2
17 UVLO_C
NC
3
16 NC
EPAD
(GND)
4
14 UVLO_D
GATE_B
5
14 UVLO_D
13 DLY_OFF_B
GATE_C
6
13 NC
9
10
11
12
7
8
2
17 UVLO_C
DLY_OFF_C
3
20
19
ENABLE_1
1
18 DLY_OFF_A
GATE_A
2
17 UVLO_C
DLY_OFF_C
3
16 DLY_ON_C
EPAD
(GND)
15 DLY_ON_D
5
14 UVLO_D
GATE_C
6
13 DLY_OFF_B
10
11
12
7
8
9
10
11
12
UVLO_B
GATE_B
13 DLY_OFF_B
ENABLE_2
14 UVLO_D
GND
4
RESET_2
DLY_OFF_D
DLY_ON_B
NC
21
GATE_D
NC
22
UVLO_B
9
23
NC
8
15 NC
24
GND
7
GATE_D
6
16 NC
EPAD
(GND)
NC
NC
19
UVLO_A
UVLO_A
20
DLY_ON_A
NC
21
NC
NC
22
GATE_A
GATE_C
12
VDD
VDD
23
18 DLY_OFF_A
5
11
RESET
RESET
24
1
GATE_B
10
ISL6128
(24 LD QFN)
TOP VIEW
ENABLE_1/
ENABLE_1
4
9
UVLO_B
8
ISL6126, ISL6130
(24 LD QFN)
TOP VIEW
DLY_OFF_D
15 NC
NC
NC
GATE_D
7
1
GATE_D
6
19
UVLO_B
GATE_C
20
NC
5
21
GND
GATE_B
15 DLY_ON_D
22
NC
4
23
DLY_ON_B
DLY_OFF_D
16 DLY_ON_C
EPAD
(GND)
24
ENABLE_1/
ENABLE_1
NC
19
NC
NC
20
GND
UVLO_A
21
SYSRST
DLY_ON_A
22
NC
SYSRST
23
VDD
VDD
24
ENABLE_1/
ENABLE_1
RESET
RESET
ISL6123, ISL6124, ISL6125
(24 LD QFN)
TOP VIEW
3
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Descriptions
PIN NUMBER
PIN
NAME
ISL6123, ISL6124,
ISL6125
ISL6126,
ISL6130
ISL6127
ISL6128
VDD
23
23
23
23
Chip Bias. Bias IC from nominal 1.5V to 5V.
GND
10
10
10
10
Bias Return. IC ground.
ENABLE_1/
ENABLE_1
1
1
1
1
ENABLE_2/
ENABLE_2
NC
NC
NC
11
Input to start on/off sequencing. Input to initiate start of programmed
sequencing of supplies on or off. Enable functionality disabled for 10ms after
UVLO is satisfied. ISL6123 and ISL6130 have ENABLE, and ISL6124,
ISL6125, ISL6126 and ISL6127 have ENABLE. Only ISL6128 has two ENABLE
inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and
ENABLE_2 is for (C, D).
RESET
24
24
24
24
RESET_2
NC
NC
NC
9
UVLO_A
20
20
20
20
UVLO_B
12
12
12
12
UVLO_C
17
17
17
17
UVLO_D
14
14
14
14
DLY_ON_A
21
-
-
21
DLY_ON_B
8
-
-
8
DLY_ON_C
16
-
-
16
DLY_ON_D
15
-
-
15
DLY_OFF_A
18
18
-
18
DLY_OFF_B
13
13
-
13
DLY_OFF_C
3
3
-
3
DLY_OFF_D
4
4
-
4
GATE_A
2
2
2
2
GATE_B
5
5
5
5
GATE_C
6
6
6
6
GATE_D
7
7
7
7
SYSRST
22
-
22
-
GND
EPAD
EPAD
EPAD
EPAD
Ground. Die Substrate
NC
9, 19
19, 22
No Connect
8, 9, 11, 3, 4, 8, 9,
11, 13,
15, 16,
19, 21, 22 15,16,18,
19, 21
4
DESCRIPTION
RESET Output. RESET provides low signal 150ms after all GATEs are fully
enhanced. Delay is for stabilization of output voltages. RESET asserts low
upon UVLO not being satisfied or ENABLE/ENABLE being deasserted. RESET
outputs are open-drain, N-channel FET and are guaranteed to be in correct
state for VDD down to 1V and are filtered to ignore fast transients on VDD and
UVLO_X.
RESET_2 only exists on ISL6128 for (C, D) group I/O.
Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout
referenced to an internal 0.633V reference. Filtered to ignore short (<30µs)
transients below programmed UVLO level.
Gate On Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-on using a capacitor to ground. Each capacitor charged with 1µA
10ms after turn-on initiated by ENABLE/ENABLE. Internal current source
provides delay to associated FET GATE turn-on.
Gate Off Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each
capacitor charged with 1µA internal current source to an internal reference
voltage, causing corresponding gate to be pulled down, thus turning off FET.
FET Gate Drive Output. Drives external FETs with 1µA current source to softstart ramp into load.
On ISL6125 only, these are open drain outputs that can be pulled up to a
maximum of VDD voltage.
System Reset I/O. As an input, allows for immediate and unconditional latch-off
of all GATE outputs when driven low. This input can also be used to initiate
programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input
signal on this pin being driven high to first GATE. As an output, when there is a UV
condition, this pin pulls low. If common to other SYSRST pins in a multiple IC
configuration, it causes immediate and unconditional latch-off of all other GATEs
on all other ISL612X sequencers.
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL612X and ISL6130 Variant Feature Matrix
NUMBER OF
NUMBER OF
UVLO INPUTS CHANNELS THAT
MONITORED TURN OFF WHEN
BY EACH
ONE UVLO
RESET
FAULTS
EN/EN
CMOS/
TTL
GATE DRIVE
OR OPEN
DRAIN
OUTPUTS
REQUIRED
CONDITIONS
FOR INITIAL
START-UP
ISL6123
EN
TTL
Gate Drive
4 UVLO
1 EN
4 UVLO
ISL6124
EN
CMOS
Gate Drive
4 UVLO
1 EN
ISL6125
EN
CMO
Open Drain
ISL6126
EN
CMOS
ISL6127
EN
ISL6128
ISL6130
PART
NAME
PRESET OR
ADJUSTABLE
SEQUENCE
NUMBER OF
UVLO AND
PAIRS OF I/O
4 Gates
Time Adjustable
On and Off
4 Monitors
with 1 I/O
Auto Restart,
Low Bias Current
Sleep
4 UVLO
4 Gates
Time Adjustable
On and Off
4 Monitors
with 1 I/O
Auto Restart
4 UVLO
1 EN
4 UVLO
4 Open Drain
Time Adjustable
On and Off
4 Monitors
with 1 I/O
Auto Restart, Open
Drain Sequenced
Outputs
Gate Drive
1 UVLO
1 EN
4 UVLO
1 Gate
Voltage
Determined ON
Time Adjustable
Off
4 Monitors
with 1 I/O
Gates Independent
On as UVLO Valid
CMOS
Gate Drive
4 UVLO
1 EN
4 UVLO
4 Gates
Preset
4 Monitors
with 1 I/O
Auto Restart
EN
CMOS
Gate Drive
4 UVLO
2 EN
2 UVLO
2 Gates
Preset
2 Monitors
with 2 I/O
Dual Redundant
Operation
EN
TTL
Gate Drive
1 UVLO
1 EN
4 UVLO
1 Gate
Voltage
Determined ON
Time Adjustable
Off
4 Monitors
with 1 I/O
Gates Independent
On as UVLO Valid
Low Bias Current
Sleep
5
FEATURES
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Absolute Maximum Ratings (Note 6)
Thermal Information
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V
ISL6125 LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
UVLO, ENABLE, ENABLE, SYSRST . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
RESET, DLY_ON, DLYOFF . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
24 Ld 4x4 QFN Package (Notes 4, 5) . . . . .
46
8
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.5V to +5.5V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
619
633
647
mV
UVLO
TJ = +25°C
Falling Undervoltage Lockout Threshold
VUVLOvth
Undervoltage Lockout Threshold Tempco
TCUVLOvth
40
µV/°C
Undervoltage Lockout Hysteresis
VUVLOhys
10
mV
Undervoltage Lockout Threshold Range
RUVLOvth
Max VUVLOvth- Min VUVLOvth
7
mV
Undervoltage Lockout Delay
TUVLOdel
ENABLE satisfied
10
ms
VDD, UVLO, ENABLE glitch filter
30
µs
Transient Filter Duration
tFIL
DELAY ON/OFF
Delay Charging Current
DLY_ichg
Delay Charging Current Range
DLY_ichg_r
Delay Charging Current Temperature
Coefficient
Delay Threshold Voltage
VDLY = 0V
TC_DLY_ichg
DLY_Vth
Delay Threshold Voltage Temperature
Coefficient
0.92
DLY_ichg(max) - DLY_ichg(min)
1.238
1
1.08
µA
0.08
µA
0.2
nA/°C
1.266
1.294
V
TC_DLY_Vth
0.2
mV/°C
ENABLE Threshold
VENh
1.2
V
ENABLE Threshold
VENh
0.5 VDD
V
ENABLE/ENABLE, RESET AND SYSRST I/O
ENABLE/ENABLE Hysteresis
VENh -VENl
Measured at VDD = 1.5V
0.2
V
ENABLE/ENABLE Lockout Delay
tdelEN_LO
UVLO satisfied
10
ms
ENABLE/ENABLE Input Capacitance
Cin_en
5
pF
RESET Pull-up Voltage
Vpu_rst
VDD
V
RESET Pull-Down Current
IRSTpd1
VDD = 1.5V, RST = 0.1V
5
mA
IRSTpd3
VDD = 3.3V, RST = 0.1V
13
mA
IRSTpd5
VDD = 5V, RST = 0.1V
17
mA
6
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Electrical Specifications
VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
RESET Delay after GATE High
TRSTdel
RESET Output Low
VRSTl
TEST CONDITIONS
MIN
(Note 7)
GATE = VDD+5V
TYP
MAX
(Note 7)
160
Measured at VDD = 5V with 5k
pull-up resistors
UNIT
ms
0.1
V
RESET Output Capacitance
COUT_RST
10
pF
SYSRST Pull-Up Voltage
Vpu_srst
VDD
V
SYSRST Pull-Down Current
Ipu_1.5
5
µA
VDD = 5V
100
µA
VDD = 1.5V, IOUT = 100µA
150
mV
10
pF
40
ns
Ipu_5
SYSRST Low Output Voltage
Vol_srst
SYSRST Output Capacitance
Cout_srst
SYSRST Low to GATE Turn-Off
tdelSYS_G
VDD = 1.5V
GATE = 80% of VDD + 5V
GATE
GATE Turn-On Current
IGATEon
GATE Turn-Off Current
IGATEoff_l
GATE Current Range
IGATE_range
GATE Turn-On/Off Current Temperature
Coefficient
TC_IGATE
GATE Pull-Down High Current
IGATEoff_h
GATE High Voltage
GATE Low Voltage
GATE = 0V
0.8
1.1
1.4
µA
GATE = VDD, Disabled
-1.4
-1.05
-0.8
µA
0.35
µA
Within IC IGATE max-min
GATE = VDD, UVLO = 0V
VGATEh
VDD < 2V, TJ = +25°C
VGATEh
VDD > 2V
VGATEl
Gate Low Voltage, VDD = 1V
VDD + 5V
0.2
nA/°C
88
mA
VDD + 4.9V
V
VDD + 5.3V
V
0
0.1
V
ISL6125 Open Drain
Open Drain On Resistance
VDD = 5V, EN = VDD
25
Ω
RDSON_3.3V
VDD = 3.3V, EN = VDD
32
Ω
RDSON_2.5V
VDD = 2.5V, EN = VDD
40
Ω
RDSON_5V
BIAS
IC Supply Current
IVDD_5V
ISL6123, ISL6130 Stand By IC Supply Current
VDD Power-on Reset
VDD = 5V
0.20
IVDD_3.3V
VDD = 3.3V
0.14
mA
IVDD_1.5V
VDD = 1.5V
0.10
mA
IVDD_sb
VDD = 5V, ENABLE = 0V
VDD_POR
0.5
mA
1
µA
1
V
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Descriptions and Operation
The ISL612X sequencer family consists of several 4-channel
voltage sequencing controllers in various functional and
personality configurations. All are designed for use in
multiple-voltage systems requiring power sequencing of
various supply voltages. Individual voltage rails are gated on
and off by external N-Channel MOSFETs, the gates of which
7
are driven by an internal charge pump to VDD + 5.3V (VQP) in
a user-programmed sequence.
With the 4-channel ISL6123, ENABLE must be asserted high,
and all four voltages to be sequenced must be above their
respective user-programmed undervoltage lockout (UVLO)
levels before programmed output turn-on sequencing can
begin. Sequencing and delay are determined by the choice of
external capacitor values on the DLY_ON and DLY_OFF pins.
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Once all four UVLO inputs and ENABLE are satisfied for 10ms,
the four DLY_ON capacitors are simultaneously charged with
1µA current sources to the DLY_Vth level of 1.27V. As each
DLY_ON pin reaches the DLY_Vth level, its associated GATE
turns on, with a 1µA source current to the VQP voltage of VDD
+ 5.3V. Thus, all four GATEs sequentially turn on. Once at
DLY_Vth, the DLY_ON pins discharge so they are ready when
next needed.
After the entire turn-on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay is started to ensure stability, after which the
RESET output is released to go high. After turn-on, if any input
falls below its UVLO point for longer than the glitch filter
period (~30µs), it is considered a fault. RESET and SYSRST
are pulled low, and all GATEs are simultaneously also pulled
low. In this mode, the GATEs are pulled low with 88mA.
Normal shutdown mode is entered when no UVLO is violated
and ENABLE is deasserted. When ENABLE is deasserted,
RESET is asserted and pulled low. Next, all four shutdown
ramp capacitors on the DLY_OFF pins are charged with a 1µA
source. When any ramp-capacitor reaches DLY_Vth, a latch is
set, and a current is sunk on the respective GATE pin to turn
off its external MOSFET. When the GATE voltage is
approximately 0.6V, the GATE is pulled down the rest of the
way at a higher current level. Each individual external FET is
thus turned off, which removes the voltages from the load in
the programmed sequence.
The ISL6123 and ISL6124 have the same functionality,
except for the ENABLE active polarity; the ISL6124 has an
ENABLE input. Additionally, the ISL6123 and ISL6130 also
have an ultra low-power sleep state when ENABLE is low.
The ISL6125 has the same personality as the ISL6124, but
instead of charged-pump-driven GATE outputs, it has
open-drain outputs that can be pulled up to a maximum of
VDD.
The ISL6126 and ISL6130 are different in that their on
sequence is not time determined but voltage determined.
Each of the four channels operates independently. Once the
IC is biased and any one of the UVLO inputs is greater than
the 0.63V internal reference, the ENABLE input is also
satisfied. The GATE for the associated UVLO input turns on.
In turn, the other UVLO inputs must be satisfied for the
associated GATEs to turn on. For a period of 150ms after all
GATEs are fully on (GATE voltage = VQP), RESET is released to
go high. The UVLO inputs can be driven by either a previously
turned-on output rail offering a voltage-determined sequence
or by logic signal inputs. Any subsequent UVLO level that is
less than its programmed level pulls the associated GATE and
RESET output low (if previously released) but does not
latch-off the other GATEs. Predetermined turn-off is
accomplished by deasserting ENABLE. This causes RESET to
latch low and all four GATE outputs to follow the programmed
turn-off sequence, similarly to the ISL6124.
The ISL6127 is a 4-channel sequencer pre-programmed for
A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and
ENABLE inputs are satisfied for ~10ms, the sequencing
starts. The next GATE in the sequence starts to ramp up once
the previous GATE has reached ~VQP-1V. After a period of
8
160ms after the last GATE is at VQP, the RESET output is
deasserted. If any UVLO is unsatisfied, RESET is pulled low,
SYSRST is pulled low, and all GATEs are simultaneously
turned off. When ENABLE is signaled high, the D GATE starts
to pull low. Once below 0.6V, the next GATE starts to pull low,
and so on, until all GATEs are at 0V. Unloaded, this turn-off
sequence completes in <1ms.
This variant offers a lower cost and size implementation
because the external delay capacitors are not used. Because
the delay capacitors are not used, this IC cannot delay the
start of subsequent GATEs. Thus, necessary stabilization or
system housekeeping need to be considered.
The ISL6128 is a 4-channel device that groups the four
channels into two groups of two channels each. Each group
of A, B and C, D, has its own ENABLE and RESET I/O pins. All
four UVLO and both ENABLEs must be satisfied for
sequencing to start. The A, B group turns on first, 10ms after
the second ENABLE is pulled low, with A then B turning on,
followed by C then D.
Once the preceding GATE = VQP, the next DLY_ON pin starts to
charge its capacitor; thus, all four GATEs turn on. Approximately
160ms after D GATE = VQP, the RESET output is released to go
high. Once any UVLO is unsatisfied, only the related group’s
RESET and two GATEs are pulled low. The related EN input must
be cycled for the faulted group to be turned on again.
Normal shutdown is invoked by signaling both ENABLE inputs
high, which causes the two related GATEs to shut down in
reverse order from turn-on. DLY_X capacitors adjust the delay
between GATES during turn-on and turn-off, but not the order.
During bias up, the RESET output is guaranteed to be in the
correct state, with VDD lower than 1V.
Upon power-up, the SYSRST pin follows VDD with a weak
internal pull-up. It is both an input and an output connection and
can provide two functions. As an input, if it is pulled low, all
GATEs are unconditionally shut off, and RESET pulls low
(Figure 8). This input can also be used as a no-wait enabling
input. If all inputs (ENABLE and UVLO) are satisfied, it does not
wait through the ~10ms enable delay to initiate DLY_ON
capacitor charging when released to go high. As an output, it is
useful when implementing multiple sequencers in a design
needing simultaneous shutdown, as with a kill switch across all
sequencers. Once any UVLO is unsatisfied longer than tFIL, the
related SYSRST pulls low. It also pulls low all other SYSRST
inputs that are on a common connection. By doing so, it
unconditionally shuts down all outputs across multiple
sequencers.
Except for the ISL6128 after a fault, restart of the turn-on
sequence is automatic, once all requirements are met. This
allows for no interaction between the sequencer and a controller
IC, if desired. The ENABLE and RESET I/O do allow for a higher
level of feedback and control, if desired. The ISL6128 requires
that the related ENABLE be cycled for restart of its associated
group GATEs. If no capacitors are connected between DLY_ON or
DLY_OFF pins and ground, then all such related GATEs start to
turn on immediately after the 10ms (TUVLOdel) ENABLE
stabilization timeout has expired. The GATEs start to turn off
immediately when ENABLE is asserted.
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
If some of the rails are sequenced together to reduce cost and
eliminate the effect of capacitor variance on the timing, a
common capacitor can be connected to two or more DLY_ON or
DLY_OFF pins. In this case, multiply the capacitor value by the
number of common DLY_X pins to obtain the desired timing.
TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD
DLY PIN CAPACITANCE
TIME(s)
Open
0.00006
100pF
0.00013
1000pF
0.0013
0.01µF
0.013
0.1µF
0.13
1µF
1.3
10µF
13
Table 1 shows the nominal time delay on the DLY_X pins for
various capacitor values, from the start of charging to the 1.27V
reference. This table does not include the 10ms of ENABLE
lockout delay during a start-up sequence, but it does represent
the time from the end of the ENABLE lockout delay to the start
of GATE transition. There is no ENABLE lockout delay for a
sequence-off, so this table illustrates the delay to GATE
transition from a disable signal.
NOTE: Nom. TDEL_SEQ = Capacitor (µF)*1.3MΩ.
Figure 4 shows the turn-on and Figure 5 shows the nominal
turn-off timing diagram of the ISL6123 and ISL6124.
The ISL6125 is similar to the ISL6124 except that, instead of
charge pumped GATE outputs, there are sequenced open-drain
outputs that can be pulled up to a maximum of VDD.
Delay and flexible sequencing possibilities include multiple series,
parallel, or adjustable capacitors that can be used to easily
fine-tune timing over that offered by standard value capacitors.
VUVLOVth
<tFIL
UVLO_A
VUVLOVth
UVLO_B
VUVLOVth
UVLO_C
VUVLOVth
tUVLOdel
UVLO_D
ENABLE (ISL6124)
VEN
ENABLE (ISL6123)
DLY_Vth
DLYON_B
DLY_Vth
DLYON_D
DLY_Vth
DLYON_A
DLY_Vth
DLYON_C
VQPUMP
VQPUMP
GATE_B
VQPUMP
GATE_D
VQPUMP
VQPUMP-1V
GATE_C
tRSTdel
GATE_A
RESET
FIGURE 4. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
9
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
l
UVLO_X>VUVLOVth
ENABLE (ISL6123)
VEN
ENABLE (ISL6124)
DLY_Vth
DLYOFF_A
DLY_Vth
DLYOFF_B
DLY_Vth
DLYOFF_C
DLY_Vth
DLYOFF_D
GATE_C
GATE_D
GATE_A
GATE_B
RESET
FIGURE 5. ISL6123, ISL6124 TURN-OFF TIMING DIAGRAM
Typical Performance Curves
1.04
634
DLY CURRENT SOURCE (µA)
633
UV THRESHOLD (mV)
VDD = 5V
632
631
630
VDD = 1.5V
629
628
1.03
1.02
1.01
1.00
VDD = 1.5V
0.99
DLY_OFF/ON
627
0.98
626
-40
0.97
-40
VDD = +5V
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 6. UVLO THRESHOLD VOLTAGE
10
80
100
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 7. DLY CHARGE CURRENT
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Curves (Continued)
GATE
5VOUT
3.3VOUT
SYSRST
2V/DIV
1µs/DIV
FIGURE 8. SYSRST LOW TO OUTPUT LATCH-OFF
Using the ISL6123EVAL1Z
Platform
The ISL6123EVAL1Z platform layout illustrates the small
implementation size for a typical 4-rail sequencing application.
The platform allows evaluation of the ISL6123, ISL6124,
ISL6126, ISL6127, ISL6128 and ISL6130. See Figure 17 for
schematic and photograph of evaluation platform and Table 2
for the component listing.
Significant current loading of the GATE or capacitive loading of
the DLY_ON and OFF pins will affect functionality and
performance.
The default configuration of the ISL6123EVAL1Z circuit is built
around the following design assumptions:
1. Using the ISL6123IR.
2. The four supplies being sequenced are 5V (IN_A), 3.3V
(IN_B), 2.5V (IN_D) and 1.5V (IN_C). The UVLO levels are
~80% of nominal voltages. Resistors are chosen such that
the total resistance of each divider is ~ 10k. Using standard
value resistors to approximate 80% of nominal voltage
supply = 0.63V on UVLO input.
3. The desired order turn-on sequence is 5V first, then 3.3V
about 12ms later, then the 2.5V supply about 19ms later,
and lastly, the 1.5V supply about 40ms later.
4. The desired turn-off sequence is first both 1.5V and 3.3V
supplies at the same time, then the 2.5V supply about
50ms later, and lastly, the 5V supply about 72ms after that.
LED off indicates sequence has completed and RESET has
released and pulled high.
The board is shipped with the ISL6123 installed and with each
of the other released variant types loose packed. As this
sequencer family has a common function pinout for most
variants, no major modifications to the board are necessary to
evaluate the other ICs. See Figure 18 for the ISL6125-specific
evaluation board and schematic.
11
All scope shots are taken from the ISL6123EVAL1Z board.
Figures 9 and 10 illustrate the desired turn-on and turn-off
sequences, respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values; sequences other than those illustrated can be
accomplished.
Figures 11 and 12 illustrate the timing relationships between the
EN input; the RESET, DLY and GATE outputs; and the VOUT voltage
for a single channel being turned on and off, respectively. RESET
is not shown in Figure 11 as it asserts 160ms after the last GATE
goes high.
All IC family variants share a similar function for DLY_X capacitor
charging and GATE and RESET operation. Figures 13 through 16
illustrate the principal feature and functional differences for each
of the ISL6125, ISL6126, ISL6127 and ISL6128 variants.
Figure 13 shows the ISL6125 open-drain outputs being
sequenced on and off, along with the RESET relationship, which is
similar to all other family variants.
Figure 14 illustrates the independent input feature of the
ISL6126 which, once EN is low, allows for each UVLO to be
individually satisfied and for its associated GATE to turn on. Only
when the last variable VIN is satisfied, as shown, does RESET
release, to signal all input voltages are valid.
Figure 15 shows the ISL6127 pre-programmed ABCD turn-on
and DCBA turn-off order of sequencing, with minimal
non-adjustable delay between each.
Figure 16 demonstrates the independence of the ISL6128, the
redundant 2-rail sequencer. It shows that either one of the two
groups can be turned off, and the ABCD order of restart with
capacitor programmable delay, once both EN inputs are pulled
low.
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Using the ISL6125EVAL1Z
Platform
The ISL6125EVAL1Z is the ISL6125-specific evaluation board
that allows evaluation of the ISL6125 and the ISL6130 with
their open-drain outputs (contact Intersil sales support with
your needs). The UVLO levels, sequence and delays are
programmed exactly like the other ISL612X ICs except that the
ISL6125 and ISL6130 have sequenced, open-drain outputs
rather than charge-pump-driven GATE outputs. See Figure 18
for the ISL6125EVAL1Z schematic and photograph and
Table 3 for the component listing.
Typical Performance Waveforms
5VOUT
5VOUT
RESET
ENABLE
3.3VOUT
3.3VOUT
2.5VOUT
2.5VOUT
1.5VOUT
1.5VOUT
ENABLE
1V/DIV
40ms/DIV
FIGURE 9. ISL6124 SEQUENCED TURN-ON
TdelENLO
GATE 2V/DIV
3.3VO 1V/DIV
DLY_Vth
1V/DIV
20ms/DIV
FIGURE 10. ISL6124 SEQUENCED TURN-OFF
GATE 2V/DIV
3.3VO 1V/DIV
DLY_Vth
RESET 2V/DIV
EN 2V/DIV
DLY_ON 1V/DIV
DLY_OFF 1V/DIV
EN 2V/DIV
10ms/DIV
FIGURE 11. ISL6123 SINGLE CHANNEL TURN-ON
12
4ms/DIV
FIGURE 12. ISL6123 SINGLE CHANNEL TURN-OFF
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Waveforms (Continued)
VIN_VAR
EN
RESET
STATIC EN/ALL OTHER VOUT
VOUT_VAR
LOGIC A -D
SEQUENCED
OUTPUTS
TRSTdel
RESET
100ms/DIV
FIGURE 13. ISL6125 LOGIC OUTPUTS SEQUENCED ON AND OFF
AND RESET RELATIONSHIP
A_VOUT
100ms/DIV
FIGURE 14. ISL6126 UVLO INPUT/OUTPUT INDEPENDENCE AND
RESET RELATIONSHIP
EN_1 5V/DIV
EN_2 5V/DIV
B_VOUT
C_VOUT
A_VOUT
D_VOUT
B_VOUT
C_VOUT
D_VOUT
FIGURE 15. ISL6127 PRE-PROGRAMMED ABCD TURN-ON AND
DCBA TURN-OFF
13
FIGURE 16. ISL6128 GROUP INDEPENDENT TURN-OFF AND DELAY
ADJUSTABLE PRE-PROGRAMMED TURN-ON
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
2.5V
3.3V
1.5V
+5V
C1
23
VDD
DLY_ON_B
DLY_ON_C
1
EN1
11
EN2
R1
7.68k
R2
6.98k
R4
4.99k
R6
8.45k
14
17
20
R3
3.01k
R5
4.99k
DLY_ON_D
DLY_ON_A
21 0.068µF
22
C7
UVLO_D DLY_OFF_C
3
UVLO_C DLY_OFF_B
13
0.047µF
C8
UVLO_B DLY_OFF_D
UVLO_A DLY_OFF_A
18 0.01µF
2
GATE_B
GATE_C
5
6
GATE_D
C6
0.01µF
C9
0.1µF
ISL6123IR
GATE_A
SYSRST
C4
0.1µF
C5
0.01µF
4
R11
1.47k
SYSRST
C2
16 0.01µF
C3
15
S1
12
R12
2.26k
EN_1
EN_2
1µF
8
78
2
Q1
1
5 6
4
7
19
NC
RESET2
25
EP
RESET1
GND
9
24
Q1
7 8
3
D2 DNP R10
2
R9 DNP
Q2
1
5 6
4
D1 750
10
Q2
3
RST2
RST
R9
10
R10
10 R13
10
R14
10
Z
FIGURE 17. ISL6123EVAL1Z SCHEMATIC AND PHOTOGRAPH
14
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
2.5V_(IND) 1.5V_(INC)
3.3V_(INB)
5.0V_(INA)
C1
23
1
ENABLE
VDD
ENABLE
DLY_ON_B
DLY_ON_D
DLY_ON_A
8.45k
R6
4.99k
R4
6.98k
R2
R1
7.68k
DLY_ON_C
12
14
17
20
U1
UVLO_B
DLY_OFF_C
UVLO_D
DLY_OFF_D
UVLO_C
DLY_OFF_B
UVLO_A
DLY_OFF_A
8
1µF
C2 0.01µF
15
C3 0.022µF
16
C4 0.068µF
21
C5 OPEN
3
C6 0.047µF
4
C7 OPEN
13
C8 0.01µF
18
C9 0.1µF
2
R8
10k
5
R9
10k
1.47k
R12
4.99k
R5
3.01k
R3
R11
2.26k
A
ISL6125 GATE_A
GATE_B
22
SYSRST
9
11
GATE_C
SYSRST
GATE_D
6
R10
10k
7
R13
10k
SEQ_A
SEQ_B
SEQ_C
SEQ_D
NC
NC
25
RESET
EP
GND
10
R7
24
D1
750
19
RESET
AGND
A
FIGURE 18. ISL6125EVAL1Z SCHEMATIC AND PHOTOGRAPH
15
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 2. ISL6123EVAL1Z BOARD COMPONENT LISTING
COMPONENT
DESIGNATOR
U1
COMPONENT FUNCTION
COMPONENT DESCRIPTION
ISL6123
Intersil, ISL6123, Four Supply Sequencer
Voltage Rail Switches
FDS6990S or equivalent, Dual N-Channel MOSFET
R6
5V to UVLO_A Resistor for Divider String
8.45kΩ 1%, 0402
R11
UVLO_A to GND Resistor for Divider String
1.47kΩ 1%, 0402
R1
3.3V to UVLO_B Resistor for Divider String
7.68kΩ 1%, 0402
R12
UVLO_B to GND Resistor for Divider String
2.26kΩ 1%, 0402
R2
2.5V to UVLO_D Resistor for Divider String
6.98kΩ 1%, 0402
R3
UVLO_D to GND Resistor for Divider String
3.01kΩ 1%, 0402
R4
1.5V to UVLO_C Resistor for Divider String
4.99kΩ 1%, 0402
R5
UVLO_D to GND Resistor for Divider String
4.99kΩ 1%, 0402
R9
RESET LED Current Limiting Resistor
750Ω 10%, 0402
C5
5V turn-on Delay Capacitor A (~10ms)
DNP, 0402
C9
5V turn-off Delay Capacitor A (~140ms)
0.1µF 10%, 6.3V, 0402
C2
3.3V turn-on Delay Capacitor B (~13ms)
0.01µF 10%, 6.3V, 0402
C8
3.3V turn-off Delay Capacitor B (~13ms)
0.01µF 10%, 6.3V, 0402
C3
2.5V turn-on Delay Capacitor D (~25ms)
0.022µF 10%, 6.3V, 0402
C7
2.5V turn-off Delay Capacitor D (0ms)
DNP, 0402
C4
1.5V turn-on Delay Capacitor C (~100ms)
0.068µF 10%, 6.3V, 0402
C6
1.5V turn-off Delay Capacitor C (~60ms)
0.047µF 10%, 6.3V, 0402
C1
Decoupling Capacitor
1µF, 0402
D1
RESET Indicating LED
0805, SMD LEDs Red
D2
RESET Indicating LED
DNP
R9
5V Load Resistor
10Ω 20%, 3W
R10
3.3V Load Resistor
10Ω 20%, 3W
R13
2.5V Load Resistor
10Ω 20%, 3W
R14
1.5V Load Resistor
10Ω 20%, 3W
Q1, Q2
Test Points Labeled as to Function
16
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 3. ISL6125EVAL1Z COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
COMPONENT DESCRIPTION
U1
ISL6125, Four Supply Sequencer
Intersil, ISL6125, Four Supply Sequencer with Open Drain Outputs
R6
5V to UVLO_A Resistor for Divider String
8.45kΩ 1%, 0402
R12
UVLO_A to GND Resistor for Divider String
1.47kΩ 1%, 0402
R1
3.3V to UVLO_B Resistor for Divider String
7.68kΩ 1%, 0402
R11
UVLO_B to GND Resistor for Divider String
2.26kΩ 1%, 0402
R2
2.5V to UVLO_D Resistor for Divider String
6.98kΩ 1%, 0402
R3
UVLO_D to GND Resistor for Divider String
3.01kΩ 1%, 0402
R4
1.5V to UVLO_C Resistor for Divider String
4.99kΩ 1%, 0402
R5
UVLO_D to GND Resistor for Divider String
4.99kΩ 1%, 0402
R9
RESET LED Current Limiting Resistor
750Ω 10%, 0805
C5
5V turn-on Delay Capacitor A
DNP, 0402
C9
5V turn-off Delay Capacitor A (135ms)
0.1µF 10%, 6.3V, 0402
C2
3.3V turn-on Delay Capacitor B (13.7ms)
0.01µF 10%, 6.3V, 0402
C8
3.3V turn-off Delay Capacitor B (13.7ms)
0.01µF 10%, 6.3V, 0402
C3
2.5V turn-on Delay Capacitor D (28ms)
0.022µF 10%, 6.3V, 0402
C7
2.5V turn-off Delay Capacitor D
DNP, 0402
C4
1.5V turn-on Delay Capacitor C (98ms)
0.068µF 10%, 6.3V, 0402
C6
1.5V turn-off Delay Capacitor C (59ms)
0.047µF 10%, 6.3V, 0402
C1
Decoupling Capacitor
0.1µF, 0805
D1
RESET1 Indicating LED
0805, SMD LED
R8
SEQ_OUTPUT_A Pull-Up Resistor
10kΩ, 0402
R9
SEQ_OUTPUT_B Pull-Up Resistor
10kΩ, 0402
R10
SEQ_OUTPUT_C Pull-Up Resistor
10kΩ, 0402
R13
SEQ_OUTPUT_D Pull-Up Resistor
10kΩ, 0402
Application Implementations
Multiple Sequencer Implementations
The ISL6123, ISL6124, ISL6125 and ISL6127 devices can be
configured to control sequencing of more than four voltages. A
particular configuration may be preferable to another, depending
on concerns. The fundamental questions to determine which
configuration is best suited for your applications are:
1. What level of voltage assurance is needed prior to sequencing
on, and can the voltage supplies be grouped into high and low
criticality?
2. Is there a critical maximum time window in which all supplies
must be present at load, or is there a first and a second group
preference, possibly with some work done in between the two
groups of voltages being present?
17
Three configurations are described and illustrated here.
In applications for which the integrity of critical voltages must be
assured prior to sequencing, additional monitoring of the critical
supplies is needed. If voltage compliance is critical for either
undervoltage or overvoltage, voltage supervisors can be used to
provide this additional assurance across multiple sequencers.
Figure 19 is a block diagram of a voltage-compliant,
high-assurance, low-risk configuration showing the ISL6131 or
ISL6132 supervisor and a mix of FET switched outputs and logic
output sequencers (ISL6124 and ISL6125 ICs).
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL6131 or ISL6132
MONITORING
ON ALL RAILS
VMON
PGOOD
OE
OE
LOW = RESET
LOW = RESET
UVLO
SYSRST
ISL6124
#N
UVLO
en
RESET
G
A
T
E
SYSRST
ISL6124
#N
UVLO
en
ENABLE
RESET
G
A
T
E
ENABLE
ENABLE
RESET
SYSRST
ENABLE
ISL6125
# N+1
POWER
SUPPLY
RESET
UVLO
L
O
G
I
C
RESET
SYSRST
ISL6125
# N+1
POWER
SUPPLY
RESET
UVLO
FIGURE 19. ISL612X AND ISL613X VOLTAGE COMPLIANT
SEQUENCING BLOCK DIAGRAM
If the mere presence of some voltage potential is adequate prior
to sequencing on, then a small number of standard logic AND
gates can be used to accomplish this. The block diagram in
Figure 20 illustrates this voltage presence configuration.
In either case, the sequencing is straightforward across multiple
sequencers, as all DLY_ON capacitors simultaneously start
charging ~10ms after the common ENABLE input signal is
delivered. This allows the choice of capacitors to be related to
each other and is no different than using a single sequencer.
When the common enabling signal is de-asserted, these
configurations execute the turn-off sequence across all
sequencers as programmed by the DLY_OFF capacitor values.
L
O
G
I
C
FIGURE 20. MULTIPLE ISL612X USING LOGIC GATES FOR
VOLTAGE PRESENCE DETECT
allows the sequenced turn-off of this configuration to ripple
through several banks as quickly as the user-programmed (by
DLY_OFF) sequence capacitors allow.
Again, with common bused SYSRTS pins, simultaneous
shutdown of all GATEs and LOGIC down upon an unsatisfied UVLO
input is assured, once all FETs or LOGIC outputs are on. If a GATE
drive option IC is used to drive both FETs and logic signals, then
care must be taken to ensure the charged pump GATE does not
overdrive and damage the logic input. A simple resistor divider
can be used to lower the GATE to a suitable voltage for the logic
input, as shown in Figure 21.
In both cases, with all the SYSRST pins bused together, once the
turn-on sequence is complete, simultaneous shutdown upon any
UVLO input failure is assured. SYSRST output momentarily pulls
low and turns off all GATE and LOGIC outputs.
Some applications may require or allow groups of supplies to be
brought up in sequence and for supplies within each group to be
sequenced. Figure 21 shows a configuration that allows the first
group of supplies to turn on before the second group starts. This
arrangement does not necessarily preclude adding the
assurance of all supplies prior to turn-on sequencing, as
previously shown. It does prevent the turn-on sequence from
completing, if there is one unsatisfied UVLO input in a group.
This configuration involves waiting through the TUVLOdel and
TRSTdel (total of ~160ms) for each sequencer IC in the chain
before the final RESET releases. Once ENABLE on the first
sequencer is de-asserted, all RESET outputs quickly pull low. This
18
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
OE
LOW = RESET
SYSRST
ISL6124
#N
UVLO
ENABLE
ENABLE
G
A
T
E
TO LOGIC
INPUT
RESET
ENABLE
SYSRST
FIGURE 22. OUTPUT VOLTAGE ON LOW TO HIGH TRACKING
ISL6125
# N+1
POWER
SUPPLY
RESET
UVLO
L
O
G
I
C
RESET
RESET
FIGURE 21. MULTIPLE ISL612X SERIAL CONFIGURATION
Voltage Tracking
In some applications, voltages may have to track each other as
they ramp up and down, whereas others may just need
sequencing. In these cases, tracking can be accomplished and
has been demonstrated over a wide range of load currents (1A to
10A) and load capacitances (10µF to 3300µF) with the ISL612X
family. Figure 22 and Figure 23 illustrate output voltage ramping
tracking performance. Note that differences are less than 0.5V.
With the relevant GATE pins tied together in a star pattern, so
that resistance between any two GATE pins is equivalent
(1k to 10k), GATE ramping voltage is shared. With the same or
similar enough FETs, this behavior is also observed.
FIGURE 23. OUTPUT VOLTAGE ON HIGH TO LOW TRACKING
It is suggested that this circuit implementation be prototyped
and evaluated for the particular expected loads prior to
committing to manufacturing build.
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FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Negative Voltage Sequencing
+V
The ISL612X family can use the charged pump GATE output to
drive FETs that would control and sequence negative voltages
down to a nominal -5V with minimal additional external circuitry.
Figure 24 shows simultaneous turn-on of the 5V bipolar supplies,
and then simultaneous turn-off of the +2.5V and both positive
supplies after the -5V. Figure 25 shows the minimal additional
external circuitry to accomplish this. The 5V zener diode is used
to level-shift the GATE drive down by 5V to prevent premature
turn-on when GATE = 0V. Once GATE drive voltage > Vz, then FET
Vgs > 5V, ensuring full turn-on once GATE gets to VDD + 5.3V.
Turn-on and turn-off ramp rates can be adjusted with the FET
gate series resistor value. The -V rail is sequenced normally via
the DLY_X capacitor value, although adjustments in prototyping
should be factored in to fine-tune for actual circuit requirements.
+BIAS
R1
VMON
R2
R3
(1k)
R5
(10k)
ISL6131
OR
ISL6536A PGOOD R4
(15K)
-BIAS
Q1 Si1300DL
OR EQUIV.
R6
-V
TO UVLO OF
ISL612X FOR
-V CONTROL AND
SEQUENCING
R1 and R2 define -V UVLO level.
R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up.
R4 and R5 provide Q1 gate bias between 0V and +V
to 0V (resistor values suitable for -V = -5V and +V = +3.3V).
FIGURE 26. HIGH ACCURACY -V LOCK OUT
Figures 26 and 27 illustrate a high-accuracy -V detection circuit
using the ISL6131 and a low-cost, low-accuracy -V detection
circuit, respectively.
+V
R1
TO UVLO OF ISL612X FOR CONTROL
AND SEQUENCING OF -V
R2
-V
Choose R1 and R2 values to drive UVLO
high when -V is sufficiently present.
FIGURE 27. LOW ACCURACY -V PRESENCE DETECTION
Application Considerations
Timing Error Sources
In any system there are variance contributors. For the ISL612x
family, timing errors are mainly contributed by three sources.
Capacitor Timing Mismatch Error
FIGURE 24. ±VOLTAGE SEQUENCING
-VOUT
-VIN
R1
ISL612X GATE
Obviously, the absolute capacitor value is an error source; thus,
lower-percentage tolerance capacitors help to reduce this error
source. Figure 28 illustrates a difference of 0.57ms between two
DLY_X outputs ramping to DLY_X threshold voltage. These 5%
capacitors were from a common source. In applications where
two or more GATEs or LOGIC outputs must have concurrent
transitions, it is recommended that a common GATE drive be
used to eliminate this timing error.
ADDITIONAL 2 COMPONENTS
NECESSARY FOR -V CONTROL
AND SEQUENCING.
D1
D1 necessary to prevent premature turn-on. R1 is used to hold
FET Vgs = 0V until D1 Vz is overcome. R1 value can be changed to
adjust -V ramp rates. Choose an R1 value between 4MW and 10MW
initially, and fine-tune resistor value for the particular need.
FIGURE 25. -VOLTAGE FET DRIVE CIRCUIT
FIGURE 28. CAPACITOR TIMING MISMATCH
20
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
DLY_X Threshold Voltage and Charging
Current Mismatch
The two other error sources come from the IC itself and are found
across the four DLY_X outputs. These errors are the DLY_X
threshold voltage (DLY_Vth) variance when the GATE_X charging
and discharging current latches are set, and the DLY_X charging
current (DLY_ichg) variances to determine the time to next
sequencing event. Both of these parameters are bounded by
specification. Figure 29 shows that, with a common capacitor,
the typical error contributed by these factors is insignificant,
since both DLY_X traces overlay each other.
FIGURE 29. DLY_VTH AND DLY_ICHG TIMING MISMATCH
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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21
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
5/24/2011
FN9005.11
- On page 1, Features: added "ENABLE" to Active High information for ISL6123 and ISL6130.
- On page 2, Ordering Information table: updated evaluation board; changed ISL612XSEQEVAL1Z to
ISL6123EVAL1Z. Removed obsolete parts: ISL6123IR, ISL6124IR, ISL6125IR, ISL6126IR, ISL6127IR,
ISL6128IR.
- On page 4, Pin Descriptions: changed Description for ENABLE/ENABLE pins from “ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127 and ISL6130 have ENABLE.” to “ISL6123 and ISL6130 have ENABLE, and ISL6124, ISL6125,
ISL6126 and ISL6127 have ENABLE.”
- On page 6, Thermal Information: changed theta-ja from 48 to 46; changed theta-jc from 9 to 8.
- On page 6, Electrical Specifications: added "ISL6125 Open Drain" specs for "Open Drain On Resistance".
- On page 11: changed heading "Using the ISL612XSEQEVAL1Z Platform" to "Using the ISL6123EVAL1Z
Platform" and edited this section to reflect attributes of revised evaluation board.
- On page 14: replaced Figure 16, "EVAL BOARD CHANNEL 1 SCHEMATIC AND ISL612XSEQEVAL1Z
PHOTOGRAPH" with "ISL6123EVAL1Z SCHEMATIC AND PHOTOGRAPH"
- On page 16: replaced Table 2, "ISL612XSEQEVAL1Z BOARD CHANNEL 1 COMPONENT LISTING" with
"ISL6123EVAL1Z BOARD COMPONENT LISTING"
10/15/2008
FN9005.10
Corrected pinout information in table and diagram.
2/27/2008
FN9005.9
- Updated evaluation boards discussion to indicate Pb-free versions throughout document.
- Clarified pinouts and pin description tables.
- Added Pb-free reflow link to Thermal Information.
2/5/2007
FN9005.8
Added ISL6130 to datasheet.
10/12/2006
FN9005.7
Made corrections and clarifications to discussions of evaluation board.
3/9/2006
FN9005.6
Clarified block diagram and applications text.
12/2/2005
FN9005.5
- Clarified text of SYSRST functional description.
- Added bias and several SYSRST# and RST# typical parameters numbers.
- Cleared up tracking scope shot mismatch.
6/10/2005
FN9005.4
Improved ESD to 2.5kV.
8/18/2004
FN9005.3
Added Pb-free options.
1/14/2004
FN9005.2
Minor edits
10/3/2003
FN9005.1
Minor edits
7/15/2003
FN9005.0
New document
Products
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Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information pages
on intersil.com: ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130.
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff.
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22
FN9005.11
August 25, 2011
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Package Outline Drawing
L24.4x4
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X 2.5
4.00
A
20X 0.50
B
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
19
1
4.00
18
2 . 10 ± 0 . 15
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 10 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
23
FN9005.11
August 25, 2011