AD ADA4500-2ARMZ-R7 10 mhz, 14.5 nv/â hz, rail-to-rail i/o, zero input crossover distortion amplifier Datasheet

FEATURES
PIN CONFIGURATION
Power supply rejection ratio (PSRR): 98 dB minimum
Common-mode rejection ratio (CMRR): 95 dB minimum
Offset voltage: 120 µV maximum
Single-supply operation: 2.7 V to 5.5 V
Dual-supply operation: ±1.35 V to ±2.75 V
Wide bandwidth: 10 MHz
Rail-to-rail input and output
Low noise
2 µV p-p from 0.1 Hz to 10 Hz
14.5 nV/√Hz at 1 kHz
Very low input bias current: 2 pA maximum
OUT A 1
8 V+
–IN A 2
ADA4500-2
7 OUT B
+IN A 3
TOP VIEW
(Not to Scale)
6 –IN B
V– 4
5 +IN B
10617-001
Data Sheet
10 MHz, 14.5 nV/√Hz, Rail-to-Rail I/O,
Zero Input Crossover Distortion Amplifier
ADA4500-2
Figure 1. 8-Lead MSOP Pin Configuration
For more information on the pin connections, see the Pin
Configurations and Function Descriptions section
100
ADA4500-2
80 VSY = 5.0V
60
40
Pressure and position sensors
Remote security
Medical monitors
Process controls
Hazard detectors
Photodiode applications
20
VOS (µV)
APPLICATIONS
0
–20
–40
–60
0
1
2
3
4
VCM (V)
5
10617-004
–80
–100
Figure 2. The ADA4500-2 Eliminates Crossover Distortion
Across its Full Supply Range
GENERAL DESCRIPTION
The ADA4500-2 is a dual 10 MHz, 14.5 nV/√Hz, low power
amplifier featuring rail-to-rail input and output swings while
operating from a 2.7 V to 5.5 V single power supply. Compatible
with industry-standard nominal voltages of +3.0 V, +3.3 V,
+5.0 V, and ±2.5 V.
Employing a novel zero-crossover distortion circuit topology, this
amplifier offers high linearity over the full, rail-to-rail input
common-mode range, with excellent power supply rejection ratio
(PSRR) and common-mode rejection ratio (CMRR) performance
without the crossover distortion seen with the traditional
complementary rail-to-rail input stage. The resulting op amp
also has excellent precision, wide bandwidth, and very low
bias current.
Rev. A
This combination of features makes the ADA4500-2 an ideal choice
for precision sensor applications because it minimizes errors due to
power supply variation and maintains high CMRR over the full
input voltage range. The ADA4500-2 is also an excellent amplifier
for driving analog-to-digital converters (ADCs) because the output
does not distort with the common-mode voltage, which enables
the ADC to use its full input voltage range, maximizing the
dynamic range of the conversion subsystem.
Many applications such as sensors, handheld instrumentation,
precision signal conditioning, and patient monitors can benefit
from the features of the ADA4500-2.
The ADA4500-2 is specified for the extended industrial temperature
range (−40°C to +125°C) and available in the standard 8-lead
MSOP and 8-lead LFCSP packages.
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ADA4500-2* Product Page Quick Links
Last Content Update: 11/01/2016
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Data Sheet
• ADA4500-2: 10 MHz, 14.5 nV/√Hz, Rail-to-Rail I/O, Zero
Input Crossover Distortion Amplifier Data Sheet
Technical Articles
• MS-2066: Low Noise Signal Conditioning for SensorBased Circuits
Tutorials
• MT-035: Op Amp Inputs, Outputs, Single-Supply, and Railto-Rail Issues
• MT-053: Op Amp Distortion: HD, THD, THD + N, IMD,
SFDR, MTPR
• MT-095: EMI, RFI, and Shielding Concepts
Tools and Simulations
Design Resources
• Analog Filter Wizard
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• ADA4500 SPICE Macro Model
•
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•
•
Evaluation Kits
• EVAL-OPAMP-2 Evaluation Board
Documentation
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• CN0348
• CN0370
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ADA4500-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 19
Applications ....................................................................................... 1
Rail-to-Rail Output .................................................................... 19
Pin Configuration ............................................................................. 1
Rail-to-Rail Input (RRI) ............................................................ 19
General Description ......................................................................... 1
Zero Cross-Over Distortion ..................................................... 19
Revision History ............................................................................... 2
Overload Recovery ..................................................................... 20
Specifications..................................................................................... 3
Power-On Current Profile ......................................................... 21
VSY = 2.7 V Electrical Characteristics ........................................ 3
Applications Information .............................................................. 22
VSY = 5.0 V Electrical Characteristics ........................................ 5
Resistance and Capacitance Sensor Circuit ............................ 22
Absolute Maximum Ratings ............................................................ 7
Adaptive Single-Ended-to-Differential Signal Converter..... 22
Thermal Resistance ...................................................................... 7
Outline Dimensions ....................................................................... 24
ESD Caution .................................................................................. 7
Ordering Guide .......................................................................... 24
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
REVISION HISTORY
10/12–Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 24
10/12–Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADA4500-2
SPECIFICATIONS
VSY = 2.7 V ELECTRICAL CHARACTERISTICS
VSY = 2.7 V, VCM = VSY/2, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Conditions
Min
Typ
VOS
Offset Voltage Drift
Input Bias Current
TCVOS
IB
Input Offset Current
IOS
−40°C < TA < +125°C
−40°C < TA < +125°C
0.8
0.3
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Capacitance
Common Mode
Differential
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity Gain Crossover
−3 dB Bandwidth
Phase Margin
Settling Time to 0.1%
IVR
CMRR
AVO
CINCM
CINDM
RIN
VOH
VOL
ISC
ZOUT
PSRR
ISY
SR
GBP
UGC
−3 dB
ΦM
ts
0.3
−40°C < TA < +125°C
−40°C < TA < +125°C
VCM = V− to V+
−40°C < TA < +125°C
VCM = [(V−) − 0.2 V] to [(V+) + 0.2 V]
−40°C < TA < +125°C
RL = 2 kΩ, [(V−) + 0.05 V] < VOUT < [(V+) − 0.05 V]
−40°C < TA < +125°C
RL = 10 kΩ, [(V−) + 0.05 V] < VOUT < [(V+) − 0.05 V]
−40°C < TA < +125°C
V−
95
90
90
80
100
100
105
105
Common mode and differential mode
RL = 10 kΩ to V−
−40°C < TA < +125°C
RL = 2 kΩ to V−
−40°C < TA < +125°C
RL = 10 kΩ to V+
−40°C < TA < +125°C
RL = 2 kΩ to V+
−40°C < TA < +125°C
Sourcing, VOUT shorted to V−
Sinking, VOUT shorted to V+
f = 10 MHz, AV = 1
2.685
2.68
2.65
2.65
VSY = 2.7 V to 5.5 V
−40°C to +125°C
IO = 0 mA
−40°C < TA < +125°C
98
94
RL = 10 kΩ, CL = 30 pF, AV = +1, VIN = VSY
RL = 10 kΩ, CL = 30 pF, AV = −1, VIN = VSY
VIN = 5 mV p-p, RL = 10 kΩ, AV = +100
VIN = 5 mV p-p, RL = 10 kΩ, AV = +1
VIN = 5 mV p-p, RL = 10 kΩ, AV = −1
VIN = 5 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 2 V p-p, RL = 10 kΩ, CL = 10 pF, AV = −1
Rev. A | Page 3 of 24
Max
Unit
120
700
5.5
1
170
1
20
V+
µV
µV
µV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
dB
dB
dB
dB
110
110
110
120
5
1.7
400
pF
pF
GΩ
2.695
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
2.68
3
13
5
10
20
25
26
−48
70
119
1.5
5.5
8.7
10.1
10.3
18.4
52
1
1.65
1.7
dB
dB
mA
mA
V/µs
V/µs
MHz
MHz
MHz
Degrees
µs
ADA4500-2
Parameter
NOISE PERFORMANCE
Total Harmonic Distortion + Noise
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
Data Sheet
Symbol
Test Conditions/Conditions
THD+N
G = 1, f = 10 Hz to 20 kHz, VIN = 0.7 V rms at 1 kHz
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
Rev. A | Page 4 of 24
Min
Typ
0.0006
0.001
3
14.5
<0.5
Max
Unit
%
%
µV p-p
nV/√Hz
fA/√Hz
Data Sheet
ADA4500-2
VSY = 5.0 V ELECTRICAL CHARACTERISTICS
VSY = 5.0 V, VCM = VSY/2, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
Typ
VOS
Offset Voltage Drift
Input Bias Current
TCVOS
IB
Input Offset Current
IOS
−40°C < TA < +125°C
−40°C < TA < +125°C
0.9
0.7
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Capacitance
Common Mode
Differential
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity Gain Crossover
−3 dB Bandwidth
Phase Margin
Settling Time to 0.1%
IVR
CMRR
AVO
CINCM
CINDM
RIN
VOH
VOL
ISC
ZOUT
PSRR
ISY
SR
GBP
UGC
−3 dB
ΦM
ts
0.3
−40°C < TA < +125°C
−40°C < TA < +125°C
VCM = V− to V+
−40°C < TA < +125°C
VCM = [(V−) − 0.2 V] to [(V+) + 0.2 V]
−40°C < TA < +125°C
RL = 2 kΩ, [(V−) + 0.05 V] < VOUT < [(V+) − 0.05 V]
−40°C < TA < +125°C
RL = 10 kΩ, [(V−) + 0.05 V] < VOUT < [(V+) − 0.05 V]
−40°C < TA < +125°C
V−
95
95
95
84
105
80
110
110
Common mode and differential mode
RL = 10 kΩ to V−
−40°C < TA < +125°C
RL = 2 kΩ to V−
−40°C < TA < +125°C
RL = 10 kΩ to V+
−40°C < TA < +125°C
RL = 2 kΩ to V+
−40°C < TA < +125°C
Sourcing, VOUT shorted to V−
Sinking, VOUT shorted to V+
f = 10 MHz, AV = +1
4.975
4.97
4.95
4.95
VSY = 2.7 V to 5.5 V
−40°C to +125°C
IO = 0 mA
−40°C < TA < +125°C
98
94
RL = 10 kΩ, CL = 30 pF, AV = +1, VIN = VSY
RL = 10 kΩ, CL = 30 pF, AV = −1, VIN = VSY
VIN = 5 mV p-p, RL = 10 kΩ, AV = +100
VIN = 5 mV p-p, RL = 10 kΩ, AV = +1
VIN = 5 mV p-p, RL = 10 kΩ, AV = −1
VIN = 5 mV p-p, RL = 10 kΩ, CL = 20 pF, AV = +1
VIN = 4 V p-p, RL = 10 kΩ, CL = 10 pF, AV = −1
Rev. A | Page 5 of 24
Max
Unit
120
700
5.5
2
190
3
20
V+
µV
µV
µV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
dB
dB
dB
dB
115
115
110
120
5
1.7
400
pF
pF
GΩ
4.99
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
4.97
7
24
15
20
40
50
75
−75
60
119
1.55
5.5
8.7
10
10.5
19.2
57
1
1.75
1.8
dB
dB
mA
mA
V/µs
V/µs
MHz
MHz
MHz
Degrees
µs
ADA4500-2
Parameter
NOISE PERFORMANCE
Total Harmonic Distortion + Noise
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
Data Sheet
Symbol
Test Conditions/Comments
THD+N
G = 1, f = 20 Hz to 20 kHz, VIN = 1.4 V rms at 1 kHz
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
Rev. A | Page 6 of 24
Min
Typ
0.0004
0.0008
2
14.5
<0.5
Max
Unit
%
%
µV p-p
nV/√Hz
fA/√Hz
Data Sheet
ADA4500-2
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
1
Rating
6V
(V−) − 0.2 V to (V+) + 0.2 V
(V−) − 0.2 V to (V+) + 0.2 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Differential input voltage is limited to 5.6 V or the supply voltage + 0.6 V,
whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead MSOP (RM-8)1
8-Lead LFCSP (CP-8-12)2, 3
1
θJA
142
85
θJC
45
2
Unit
°C/W
°C/W
Thermal numbers were simulated on a 4-layer JEDEC printed circuit board (PCB).
Thermals numbers were simulated on a 4 layer JEDEC PCB with the exposed
pad soldered to the PCB.
3
θJC was simulated at the exposed pad on the bottom of the package.
2
ESD CAUTION
Rev. A | Page 7 of 24
ADA4500-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT A 1
–IN A 2
ADA4500-2
7 OUT B
+IN A 3
TOP VIEW
(Not to Scale)
6 –IN B
7 OUT B
+IN A 3
TOP VIEW
(Not to Scale)
6 –IN B
V– 4
5 +IN B
10617-400
V– 4
ADA4500-2
8 V+
5 +IN B
NOTES
1. CONNECT THE EXPOSED PAD TO V–
OR LEAVE IT UNCONNECTED.
Figure 4. 8-Lead LFCSP Pin Configuration
Figure 3. 8-Lead MSOP Pin Configuration
Table 5. 8-Lead MSOP and 8-Lead LFCSP Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
EPAD
10617-200
OUT A 1
8 V+
–IN A 2
Description
Output, Channel A.
Inverting Input, Channel A.
Noninverting Input, Channel A.
Negative Supply Voltage.
Noninverting Input, Channel B.
Inverting Input, Channel B.
Output, Channel B.
Positive Supply Voltage.
For the LFCSP package only, connect the exposed pad to V− or leave it unconnected.
Rev. A | Page 8 of 24
Data Sheet
ADA4500-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
100
ADA4500-2
90 VSY = 5.0V
VCM = VSY/2
80
80
70
70
60
50
40
30
60
50
40
30
20
20
10
10
0
–120 –100 –80 –60 –40 –20
0
20
40
60
80
100 120
VOS (µV)
0
–120 –100 –80 –60 –40 –20
Figure 5. Input Offset Voltage Distribution, VSY = 2.7 V
40
60
80
100 120
35
ADA4500-2
VSY = 2.7V
VCM = VSY/2
–40°C ≤ TA ≤ +125°C
30
ADA4500-2
VSY = 5.0V
VCM = VSY/2
–40°C ≤ TA ≤ +125°C
30
25
20
15
20
15
10
10
5
5
1.25
2.50
3.75
5.00
6.25
7.50
8.75
TCVOS (µV/°C)
0
0
1.25
2.50
Figure 6. Input Offset Voltage Drift Distribution, VSY = 2.7 V
5.00
6.25
7.50
8.75
Figure 9. Input Offset Voltage Drift Distribution, VSY = 5.0 V
100
100
ADA4500-2
80 VSY = 5.0V
60
60
40
40
20
20
VOS (µV)
ADA4500-2
80 VSY = 2.7V
0
–20
0
–20
–40
–40
–60
–60
–80
–80
0.3
0.8
1.3
VCM (V)
1.8
2.3
2.8
–100
–0.2
10617-007
–100
–0.2
3.75
TCVOS (µV/°C)
Figure 7. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 2.7 V
0.8
1.8
2.8
VCM (V)
3.8
4.8
10617-004
0
10617-006
0
10617-003
NUMBER OF UNITS
25
NUMBER OF UNITS
20
Figure 8. Input Offset Voltage Distribution, VSY = 5.0 V
35
VOS (µV)
0
VOS (µV)
10617-005
NUMBER OF UNITS
ADA4500-2
90 VSY = 2.7V
VCM = VSY/2
10617-002
NUMBER OF UNITS
100
Figure 10. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 5.0 V
Rev. A | Page 9 of 24
ADA4500-2
Data Sheet
TA = 25°C, unless otherwise noted.
100
100
ADA4500-2
VSY = 2.7V
80 VCM = VSY/2
ADA4500-2
VSY = 5.0V
80 VCM = VSY/2
IB+
60
40
IB (pA)
IB (pA)
60
IB–
20
40
20
IB+
0
0
IB–
–25
0
25
50
75
125
100
150
TEMPERATURE (°C)
–40
–50
10617-008
–40
–50
25
50
75
100
125
150
Figure 14. Input Bias Current (IB) vs. Temperature, VSY = 5.0 V
100
100
ADA4500-2
VSY = 2.7V
ADA4500-2
VSY = 5.0V
80
60
60
40
40
20
20
0
0
–20
–20
–40
0
0.5
1.0
1.5
2.0
2.5
3.0
VCM (V)
–40
Figure 12. Input Bias Current (IB) vs. Common-Mode Voltage (VCM), VSY = 2.7 V
0
2
1
3
4
5
VCM (V)
10617-009
IB (pA)
80
10617-012
Figure 15. Input Bias Current (IB) vs. Common-Mode Voltage (VCM), VSY = 5.0 V
10k
10k
ADA4500-2
VSY = 5.0V
SOURCING OUTPUT CURRENT
OUTPUT (VOH) TO SUPPLY (mV)
ADA4500-2
VSY = 2.7V
SOURCING OUTPUT CURRENT
1k
100
10
+125°C
+25°C
1
1k
100
+125°C
10
+25°C
1
–40°C
–40°C
0.01
0.1
1
LOAD CURRENT (mA)
10
100
0.1
0.001
10617-010
0.1
0.001
Figure 13. Output Voltage (VOH) to Supply Rail vs. Load Current, VSY = 2.7 V
0.01
0.1
1
LOAD CURRENT (mA)
10
100
10617-013
IB (pA)
0
TEMPERATURE (°C)
Figure 11. Input Bias Current (IB) vs. Temperature, VSY = 2.7 V
OUTPUT (VOH) TO SUPPLY (mV)
–25
10617-011
–20
–20
Figure 16. Output Voltage (VOH) to Supply Rail vs. Load Current, VSY = 5.0 V
Rev. A | Page 10 of 24
Data Sheet
ADA4500-2
TA = 25°C, unless otherwise noted.
10k
10k
1k
+25°C
100
+125°C
10
–40°C
1
0.1
0.001
0.1
0.01
1
10
100
LOAD CURRENT (mA)
Figure 17. Output Voltage (VOL) to Supply Rail vs. Temperature, VSY = 2.7 V
1k
100
+125°C
10
+25°C
0.1
0.001
0.1
0.01
10
1
100
LOAD CURRENT (mA)
Figure 20. Output Voltage (VOL) to Supply Rail vs. Load Current, VSY = 5.0 V
50
50
ADA4500-2
VSY = 5.0V
OUTPUT (VOH) TO SUPPLY (mV)
ADA4500-2
VSY = 2.7V
OUTPUT (VOH) TO SUPPLY (mV)
–40°C
1
10617-017
OUTPUT (VOL) TO SUPPLY (mV)
ADA4500-2
VSY = 5.0V
SINKING OUTPUT CURRENT
10617-014
OUTPUT (VOL) TO SUPPLY (mV)
ADA4500-2
VSY = 2.7V
SINKING OUTPUT CURRENT
40
30
RL = 2kΩ
20
10
40
RL = 2kΩ
30
20
RL = 10kΩ
10
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
0
–50
10617-015
0
–50
Figure 18. Output Voltage (VOH) to Supply Rail vs. Temperature, VSY = 2.7 V
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 21. Output Voltage (VOH) to Supply Rail vs. Temperature, VSY = 5.0 V
50
20
ADA4500-2
VSY = 5.0V
OUTPUT (VOL) TO SUPPLY (mV)
ADA4500-2
VSY = 2.7V
15
RL = 2kΩ
10
5
40
30
RL = 2kΩ
20
10
RL = 10kΩ
RL = 10kΩ
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
0
–50
10617-016
0
–50
Figure 19. Output Voltage (VOL) to Supply Rail vs. Temperature, VSY = 2.7 V
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
10617-019
OUTPUT (VOL) TO SUPPLY (mV)
–25
10617-018
RL = 10kΩ
Figure 22. Output Voltage (VOL) to Supply Rail vs. Temperature, VSY = 5.0 V
Rev. A | Page 11 of 24
ADA4500-2
Data Sheet
TA = 25°C, unless otherwise noted.
2.0
SUPPLY CURRENT PER AMP (mA)
1.50
1.25
+85°C
1.00
+125°C
+25°C
0.75
–40°C
0.50
0.25
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
VSY = ±1.35V
1.4
1.2
1.0
–50
0
25
50
75
100
150
PHASE
150
100
ADA4500-2
–50
RL = 10kΩ
CL = 20pF
VSY = 2.7V
VCM = VSY/2
–100
100
1k
–50
10k
100k
1M
10M
FREQUENCY (Hz)
1k
10k
100k
1M
10M
–100
100M
FREQUENCY (Hz)
Figure 27. Open-Loop Gain and Phase vs. Frequency, VSY = 5.0 V
60
ADA4500-2
VSY = 2.7V
50 VCM = VSY/2
ADA4500-2
VSY = 5.0V
50 V
CM = VSY/2
CLOSED-LOOP GAIN (dB)
AV = +100
30
AV = +10
20
10
AV = +1
0
–10
AV = +100
40
30
AV = +10
20
10
AV = +1
0
–10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
10617-022
CLOSED-LOOP GAIN (dB)
–50
RL = 10kΩ
CL = 20pF
VSY = 5.0V
VCM = VSY/2
–100
100
60
–20
10
0
0
Figure 24. Open-Loop Gain and Phase vs. Frequency, VSY = 2.7 V
40
50
GAIN
–50
–100
100M
150
100
50
GAIN (dB)
0
0
10617-021
GAIN (dB)
GAIN
PHASE
100
PHASE (Degrees)
50
50
150
Figure 26. Supply Current per Amp vs. Temperature
ADA4500-2
100
125
TEMPERATURE (°C)
Figure 23. Supply Current per Amp vs. Supply Voltage
150
–25
10617-024
1.0
VSY = ±2.5V
1.6
PHASE (Degrees)
0.5
1.8
Figure 25. Closed Loop Gain vs. Frequency, VSY = 2.7 V
–20
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 28. Closed-Loop Gain vs. Frequency, VSY = 5.0 V
Rev. A | Page 12 of 24
100M
10617-025
0
ADA4500-2
10617-023
ADA4500-2
10617-020
SUPPLY CURRENT PER AMP (mA)
1.75
Data Sheet
ADA4500-2
TA = 25°C, unless otherwise noted.
160
140
140
120
120
100
CMRR (dB)
80
60
80
60
40
20
ADA4500-2
VSY = 2.7V
VCM = VSY/2
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
ADA4500-2
VSY = 5.0V
VCM = VSY/2
0
100
ADA4500-2
VSY = 2.7V
VCM = VSY/2
100
100
80
80
60
40
20
20
0
0
10k
100k
1M
10M
100M
FREQUENCY (Hz)
PSRR+
PSRR–
–20
100
10617-026
1k
ADA4500-2
VSY = 5.0V
VCM = VSY/2
1k
10k
100k
1M
10M
100M
Figure 33. PSRR vs. Frequency, VSY = 5.0 V
1k
1k
ADA4500-2
VSY = 2.7V
VCM = VSY/2
100
10
1
0.1 A = +10
V
AV = +100
1
0.1
AV = +1
0.01
0.01
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
0.001
100
10617-027
0.001
100
ADA4500-2
VSY = 5.0V
VCM = VSY/2
10
AV = +100
ZOUT (Ω)
ZOUT (Ω)
100M
FREQUENCY (Hz)
Figure 30. PSRR vs. Frequency, VSY = 2.7 V
100
10M
60
40
–20
100
1M
120
PSRR (dB)
PSRR (dB)
120
100k
Figure 32. CMRR vs. Frequency, VSY = 5.0 V
140
PSRR+
PSRR–
10k
FREQUENCY (Hz)
Figure 29. CMRR vs. Frequency, VSY = 2.7 V
140
1k
10617-029
0
100
10617-100
20
10617-101
40
Figure 31. Closed Loop Output Impedance (ZOUT) vs. Frequency, VSY = 2.7 V
AV = +1
AV = +10
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
10617-030
CMRR (dB)
100
Figure 34. Closed Loop Output Impedance (ZOUT) vs. Frequency, VSY = 5.0 V
Rev. A | Page 13 of 24
ADA4500-2
Data Sheet
VOLTAGE (1V/DIV)
TIME (400ns/DIV)
TIME (200ns/DIV)
Figure 38. Large Signal Transient Response, VSY = 5.0 V
VOLTAGE (50mV/DIV)
VOLTAGE (50mV/DIV)
Figure 35. Large Signal Transient Response, VSY = 2.7 V
ADA4500-2
VSY = 5.0V
VCM = VSY/2
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 100pF
10617-032
ADA4500-2
VSY = 2.7V
VCM = VSY/2
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 100pF
TIME (200ns/DIV)
TIME (200ns/DIV)
Figure 36. Small Signal Transient Response, VSY = 2.7 V
Figure 39. Small Signal Transient Response, VSY = 5.0 V
80
80
ADA4500-2
VSY = 2.7V
VCM = VSY/2
VIN = 100mV p-p
AV = +1
RL = 10kΩ
60
ADA4500-2
VSY = 5.0V
VCM = VSY/2
VIN = 100mV p-p
AV = +1
RL = 10kΩ
70
60
OVERSHOOT (%)
70
OVERSHOOT (%)
10617-031
ADA4500-2
VSY = 5.0V
VCM = VSY/2
VIN = 4V p-p
AV = +1
RL = 10kΩ
CL = 100pF
10617-028
ADA4500-2
VSY = 2.7V
VCM = VSY/2
VIN = 2V p-p
AV = +1
RL = 10kΩ
CL = 100pF
10617-035
VOLTAGE (0.5V/DIV)
TA = 25°C, unless otherwise noted.
50
40
OS–
30
OS+
20
50
40
30
OS+
20
OS–
0
1
10
LOAD CAPACITANCE (pF)
100
Figure 37. Small Signal Overshoot vs. Load Capacitance, VSY = 2.7 V
0
1
10
LOAD CAPACITANCE (pF)
100
10617-036
10
10617-033
10
Figure 40. Small Signal Overshoot vs. Load Capacitance, VSY = 5.0 V
Rev. A | Page 14 of 24
Data Sheet
ADA4500-2
0
–0.05
INPUT
0
–0.1
1.0
0.5
0
OUTPUT
–0.5
TIME (2µs/DIV)
1
0
OUTPUT
–1
TIME (2µs/DIV)
Figure 41. Positive Overload Recovery, VSY = ±1.35 V
Figure 43. Positive Overload Recovery, VSY = ±2.5 V
INPUT VOLTAGE (V)
0.10
0.05
INPUT
0
–0.05
0.2
0.1
INPUT
0
–0.1
TIME (2µs/DIV)
0
ADA4500-2
–1
VSY = ±2.5V
VIN = 100mV p-p
AV = –100
–2
RL = 10kΩ
CL = 100pF
–3
TIME (2µs/DIV)
Figure 44. Negative Overload Recovery, VSY = ±2.5 V
Figure 42. Negative Overload Recovery, VSY = ±1.35 V
Rev. A | Page 15 of 24
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0
ADA4500-2
–0.5
VSY = ±1.35V
VIN = 50mV p-p
AV = –100
–1.0
RL = 10kΩ
CL = 100pF
–1.5
OUTPUT
10617-041
1
0.5
OUTPUT
10617-038
INPUT VOLTAGE (V)
ADA4500-2
VSY = ±2.5V
VIN = 100mV p-p
3
AV = –100
RL = 10kΩ
CL = 100pF
2
–0.2
1.5
OUTPUT VOLTAGE (V)
ADA4500-2
VSY = ±1.35V
VIN = 50mV p-p
AV = –100
RL = 10kΩ
CL = 100pF
–0.10
0.1
OUTPUT VOLTAGE (V)
INPUT
10617-037
INPUT VOLTAGE (V)
0.05
10617-034
INPUT VOLTAGE (V)
TA = 25°C, unless otherwise noted.
ADA4500-2
Data Sheet
TA = 25°C, unless otherwise noted.
INPUT
ADA4500-2
VSY = 2.7V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
DUT AV = –1
INPUT VOLTAGE (2V/DIV)
ERROR BAND
POST GAIN = 20
+20mV
0
ADA4500-2
VSY = 5.0V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
DUT AV = –1
ERROR BAND
POST GAIN = 20
+40mV
0
OUTPUT
OUTPUT
–20mV
TIME (400ns/DIV)
TIME (400ns/DIV)
Figure 45. Positive Settling Time to 0.1%, VSY = 2.7 V
Figure 47. Positive Settling Time to 0.1%, VSY = 5.0 V
INPUT VOLTAGE (2V/DIV)
ADA4500-2
VSY = 2.7V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
DUT AV = –1
INPUT
ERROR BAND
POST GAIN = 20
+20mV
0
ADA4500-2
VSY = 5.0V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
DUT AV = –1
INPUT
ERROR BAND
POST GAIN = 20
+40mV
0
OUTPUT
OUTPUT
–20mV
TIME (400ns/DIV)
–40mV
10617-040
INPUT VOLTAGE (1V/DIV)
10617-042
10617-039
–40mV
Figure 46. Negative Settling Time to 0.1%, VSY = 2.7 V
TIME (400ns/DIV)
Figure 48. Negative Settling Time to 0.1%, VSY = 5.0 V
Rev. A | Page 16 of 24
10617-043
INPUT VOLTAGE (1V/DIV)
INPUT
Data Sheet
ADA4500-2
TA = 25°C, unless otherwise noted.
1k
100
10
1k
100k
10k
1M
10M
FREQUENCY (Hz)
10
1
10
VOLTAGE NOISE DENSITY (nV/ Hz)
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1M
10M
ADA4500-2
VSY = 5.0V
VCM = VSY/2
10
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 50. Voltage Noise Density vs. Frequency, VSY = 2.7 V
(10 Hz to 100 MHz)
Figure 53. Voltage Noise Density vs. Frequency, VSY = 5.0 V
(10 Hz to 100 MHz)
10617-045
INPUT REFERRED VOLTAGE (500nV/DIV)
ADA4500-2
VSY = 2.7V, AV = +100
VCM = VSY/2
TIME (1s/DIV)
100k
100
10617-300
10
INPUT REFERRED VOLTAGE (500nV/DIV)
VOLTAGE NOISE DENSITY (nV/ Hz)
1k
100
100
10k
Figure 52. Voltage Noise Density vs. Frequency, VSY = 5.0 V
(10 Hz to 10 MHz)
ADA4500-2
VSY = 2.7V
VCM = VSY/2
1
10
1k
FREQUENCY (Hz)
Figure 49. Voltage Noise Density vs. Frequency, VSY = 2.7 V
(10 Hz to 10 MHz)
1k
100
ADA4500-2
VSY = 5.0V
AV = +100
VCM = VSY/2
TIME (1s/DIV)
Figure 51. 0.1 to 10 Hz Noise, VSY = 2.7 V
Figure 54. 0.1 to 10 Hz Noise, VSY = 5.0 V
Rev. A | Page 17 of 24
10617-301
100
100
10617-048
1
10
ADA4500-2
VSY = 5.0V
VCM = VSY/2
10617-047
VOLTAGE NOISE DENSITY (nV/ Hz)
ADA4500-2
VSY = 2.7V
VCM = VSY/2
10617-044
VOLTAGE NOISE DENSITY (nV/ Hz)
1k
ADA4500-2
Data Sheet
TA = 25°C, unless otherwise noted.
100
100
ADA4500-2
VSY = 2.7V
VCM = VSY/2
AV = +1
80kHz LOW-PASS FILTER
RL = 10kΩ
10
1
THD + NOISE (%)
0.1
0.01
0.1
0.01
0.001
0.01
1
0.1
10
100
VIN (V rms)
0.0001
0.001
10617-046
0.0001
0.001
10
100
Figure 57. THD + Noise vs. Amplitude, VSY = 5.0 V
1
1
ADA4500-2
VSY = 2.7V
AV = +1
80kHz LOW-PASS FILTER
RL = 10kΩ
VIN = 0.7V rms
0.1
THD + NOISE (%)
THD + NOISE (%)
1
0.1
VIN (V rms)
Figure 55. THD + Noise vs. Amplitude, VSY = 2.7 V
0.1
0.01
10617-049
0.001
1
0.01
0.01
0.001
100
1k
10k
FREQUENCY (Hz)
100k
10617-050
0.001
0.0001
10
ADA4500-2
VSY = 5.0V
AV = +1
80kHz LOW-PASS FILTER
RL = 10kΩ
VIN = 1.4V rms
0.0001
10
Figure 56. THD + Noise vs. Frequency, VSY = 2.7 V
100
1k
10k
FREQUENCY (Hz)
Figure 58. THD + Noise vs. Frequency, VSY = 5.0 V
Rev. A | Page 18 of 24
100k
10617-051
THD + NOISE (%)
10
ADA4500-2
VSY = 5.0V
VCM = VSY/2
AV = +1
80kHz LOW-PASS FILTER
RL = 10kΩ
Data Sheet
ADA4500-2
THEORY OF OPERATION
RAIL-TO-RAIL OUTPUT
VDD
When processing a signal through an op amp to a load, it is often
desirable to have the output of the op amp swing as close to the
voltage supply rails as possible. For example, when an op amp is
driving an ADC and both the op amp and ADC are using the
same supply rail voltages, the op amp must drive as close to the
V+ and V− rails as possible so that all codes in the ADC are
usable. A non-rail-to-rail output can require as much as 1.5 V
or more between the output and the rails, thus limiting the
input dynamic range to the ADC, resulting in less precision
(number of codes) in the converted signal.
M9
M3 M4
M11
M10
BIAS5
M12
BIAS4
BIAS2
VIN+
–AV
VIN–
VSS
OUT
VDD
BIAS1
M8
M7
BIAS3
M1 M2
M5
M6
10617-103
The ADA4500-2 can drive its output to within a few millivolts
of the supply rails (see the output voltage high and output voltage
low specifications in Table 1 and Table 2). The rail-to-rail output
maximizes the dynamic range of the output, increasing the range
and precision, and often saving the cost, board space, and added
error of the additional gain stages.
VSS
Figure 59. Typical PMOS-NMOS Rail-to-Rail Input Structure
300
VSY = 5V
TA = 25°C
250
200
RAIL-TO-RAIL INPUT (RRI)
150
ZERO CROSS-OVER DISTORTION
A typical rail-to-rail input stage uses two differential pairs (see
Figure 59). One differential pair amplifies the input signal when
the common-mode voltage is on the high end, and the other
pair amplifies the input signal when the common-mode voltage
is on the low end. This classic dual-differential pair topology
does have a potential drawback. If the signal level moves through
the range where one input stage turns off and the other input
stage turns on, noticeable distortion occurs. Figure 60 shows the
distortion in a typical plot of VOS (voltage difference between the
inverting and the noninverting input) vs. VCM (input voltage).
100
50
VOS (µV)
0
–50
–100
–150
–200
–250
–300
0
0.5
1.0
1.5
2.0
2.5
3.0
VCM (V)
3.5
4.0
4.5
5.0
10617-060
Using a CMOS nonrail-to-rail input stage (that is, a single
differential pair) limits the input voltage to approximately one gatesource voltage (VGS) away from one of the supply lines. Because
VGS for normal operation is commonly more than 1 V, a single
differential pair, input stage op amp greatly restricts the allowable
input voltage. This can be quite limiting with low supply voltages
supplies. To solve this problem, RRI stages are designed to allow
the input signal to range to the supply voltages (see the input
voltage range specifications in Table 1 and Table 2). In the case
of the ADA4500-2, the inputs continue to operate 200 mV beyond
the supply rails (see Figure 7 and Figure 10).
Figure 60. Typical Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM)
Response in a Dual Differential Pair Input Stage Op Amp (Powered by a 5 V
Supply; Results of Approximately 100 Units per Graph Are Displayed)
This distortion in the offset error forces the designer to live with
the bump in the common-mode error or devise impractical ways
to avoid the crossover distortion areas, thereby narrowing the
common-mode dynamic range of the op amp.
Rev. A | Page 19 of 24
ADA4500-2
Data Sheet
The ADA4500-2 solves the crossover distortion problem by using
an on-chip charge pump in its input structure to power the input
differential pair (see Figure 61). The charge pump creates a
supply voltage higher than the voltage of the supply, allowing
the input stage to handle a wide range of input signal voltages
without using a second differential pair. With this solution, the
input voltage can vary from one supply voltage to the other with
no distortion, thereby restoring the full common-mode dynamic
range of the op amp.
Figure 62 shows the elimination of the crossover distortion in
the ADA4500-2. This solution improves the CMRR performance
tremendously. For example, if the input varies from rail to rail
on a 5 V supply rail, using a part with a CMRR of 70 dB minimum,
an input-referred error of 1581 µV is introduced. The ADA4500-2,
with its high CMRR of 90 dB minimum (over its full operating
temperature) reduces distortion to a maximum error of 158 µV
with a 5 V supply. The ADA4500-2 eliminates crossover distortion
without unnecessary circuitry complexity and increased cost.
VCP
300
ADA4500-2
240 VSY = 5.0V
BIAS6
CHARGE
PUMP
180
VDD
120
VDD
VIN+
VOS (µV)
BIAS5
VIN–
BIAS4
M1 M2
60
0
–60
–120
–AV
–180
OUT
BIAS3
–300
0
1
2
3
4
5
VCM (V)
VSS
Figure 62. Charge Pump Design Eliminates Crossover Distortion
10617-102
VSS
OVERLOAD RECOVERY
Figure 61. ADA4500-2 Input Structure
Some charge pumps are designed to run in an open-loop
configuration. Disadvantages of this design include: a large ripple
voltage on the output, no output regulation, slow start-up, and a
large power-supply current ripple. The charge pump in this op
amp uses a feedback network that includes a controllable clock
driver and a differential amplifier. This topology results in a low
ripple voltage; a regulated output that is robust to line, load, and
process variations; a fast power-on startup; and lower ripple on
the power supply current.1 The charge pump ripple does not
show up on an oscilloscope; however, it can be seen at a high
frequency on a spectrum analyzer. The charge pump clock speed
adjusts between 3.5 MHz (when the supply voltage is 2.7 V) to
5 MHz (at VSY = 5 V). The noise and distortion are limited only by
the input signal and the thermal or flicker noise.
1
10617-108
–240
When the output is driven to one of the supply rails, the
ADA4500-2 is in an overload condition. The ADA4500-2 recovers
quickly from the overload condition. Typical op amp recovery
times can be in the tens of microseconds. The ADA4500-2 typically
recovers from an overload condition in 1 µs from the time the
overload condition is removed until the output is active again.
This is important in, for example, a feedback control system. The
fast overload recovery of the ADA4500-2 greatly reduces loop
delay and increases the response time of the control loop (see
Figure 41 to Figure 44).
Oto, D.H.; Dham, V.K.; Gudger, K.H.; Reitsma, M.J.; Gongwer, G.S.; Hu, Y.W.; Olund, J.F.; Jones, H.S.; Nieh, S.T.K.; "High-Voltage Regulation and Process
Considerations for High-Density 5 V-Only E2PROM's," IEEE Journal of Solid-State Circuits, Vol. SC-18, No.5, pp.532-538, October 1983.
Rev. A | Page 20 of 24
Data Sheet
ADA4500-2
POWER-ON CURRENT PROFILE
55
45
40
3
35
30
25
2
20
15
1
10
60
5
55
4
0
0
0
50
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
40
3
35
30
25
2
20
15
1
SUPPLY CURRENT (mA)
TIME (µs)
45
10
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
TIME (µs)
10617-107
5
0
10617-106
5
SUPPLY CURRENT (mA)
50
4
SUPPLY VOLTAGE (V)
The ADA4500-2 powers up with a smooth current profile, with
no supply current overshoot (see Figure 63). When powering up
a system, spikes in the power-up current are undesirable (see
Figure 64). The overshoot requires a designer to source a large
enough power supply (such as a voltage regulator) to supply the
peak current, even though a heavier supply is not necessary once
the system is powered up. If multiple amplifiers are pulling a
spike in current, the system can go into a current limit state and
not power up. This is all avoided with the smooth power up of
the ADA4500-2.
SUPPLY VOLTAGE (V)
60
5
Figure 64. ISY and VSY vs. Time with a Power-Up Spike
For systems that are frequently switching off and on, the powerup overshoot results in excess power use. As the amplifier switches
off and on, the power consumed by the large spike is repeated
on each power-up, increasing the total power consumption by
magnitudes. As an example, if a battery-powered sensor system
periodically powers up the sensor and signal path, takes a reading,
and shuts down until the next reading, the ADA4500-2 enables
much longer battery life because there is no excess charge being
consumed at each power-up.
Figure 63. ISY and VSY vs. Time for ADA4500-2 with No Spike
Rev. A | Page 21 of 24
ADA4500-2
Data Sheet
APPLICATIONS INFORMATION
RESISTANCE AND CAPACITANCE SENSOR CIRCUIT
The application shown in Figure 65 generates a square-wave
output in which the period is proportional to the value of RX
and CX by Equation 1. By fixing the CX and measuring the
period of the output signal, RX can be determined. Fixing RX
allows for the measurement of CX.
Period = 4.80 × RX × CX
Three key challenges are encountered often when designing a
single-ended-to-differential signal converter circuit with a
single supply:
•
(1)
U1A takes advantage of the high input impedance and large railto-rail input dynamic range of the ADA4500-2 to measure a
wide range of resistances (RX).
•
U1B is used as a comparator; with the noninverting input
swinging between (1/12) × VPOS and (11/12) × VPOS, and the
output swinging from rail to rail. Because the accuracy of the
circuit depends on the propagation time through the amplifers,
the fast recovery of U1B from the output overload conditions
makes it ideal for this application.
VPOS
•
VPOS
U1A
VPOS
ADA4500-2
R3
100kΩ
Cx
R2
100kΩ
U1B
ADA4500-2
R1
10kΩ
OUTPUT
The Solution
10617-104
Rx
When the supply is limited to a single voltage, the input
signal level to the circuit is generally limited to operate
from ground to the supply voltage (VSY). This limitation
on the input dynamic range can require attenuation and/or
level-shifting of the source signal before it even gets to the
single-ended-to-differential signal converter. This results in
reduced signal-to-noise ratio (SNR) and additional error.
The dc part of the input signal, on which the ac signal rides, is
generally not known during system operation. For example, if
multiple input signals from varying sources are multiplexed
into the single-ended-to-differential signal converter circuit,
each one could have a different dc level. Accommodating
multiple dc input levels means that the system design must
compromise the maximum allowed peak voltage of the ac
part of the input so that it does not clip against the rails.
The system processor does not know what the dc level is of the
original signal so it cannot make adjustments accordingly.
Figure 65. A Resistance/Capacitance Sensor
ADAPTIVE SINGLE-ENDED-TO-DIFFERENTIAL
SIGNAL CONVERTER
The Challenge
When designing a signal path in systems that have a single voltage
supply, the biggest challenge is how to represent the full range of
an input signal that may have positive, zero, and negative values.
By including zero in the output, the output signal must go
completely to ground, which single-supply amplifiers cannot do.
Converting the single-ended input signal to a differential signal
(through a single-ended-to-differential signal converter circuit)
allows zero to be represented as the positive and negative outputs
being equal, requiring neither amplifier to go to ground.
There are other benefits of the single-ended-to-differential signal
conversion, such as doubling the amplitude of the signal for
better signal-to-noise ratio, rejecting common-mode noise, and
driving the input of a high precision differential ADC.
In addition to converting to a differential signal, the circuit must set
the common-mode dc level of its output to a level that gives the ac
signal maximum swing at the load (like the input to an ADC).
These challenges are solved with the adaptive single-ended to
differential converter shown in Figure 66. This circuit operates
off a single supply from 2.7 V to 5.5 V, it automatically adjusts the
dc common mode of the output to a desired level, and it provides
the ability to measure the dc component of the input signal. This
circuit uses two voltage sources: a positive supply rail (VSY) and
a reference voltage (VREF). U1A buffers the input signal, while
U1B integrates that signal and feeds the integrated (dc) voltage
back to U1A to center the output signal on VREF. Resistors R10
and R11 are set to equal the impedance of the resistors R8 and R9
for a matched ac response and for balancing the effects of the
bias current.
The input frequency can range from 10 Hz to 1 MHz. Peak-to-peak
amplitude of the input signal can be as large as VSY − 100 mV.
The dc common mode (VCM) of the input signal can be as high
as +1.5 × VSY and −0.5 × VSY; therefore, a system with a +5 V supply
voltage can take a common mode from as high as +7.5 V and as
low as −2.5 V with a signal amplitude of 5 V p-p. The wide range of
VCM above and below ground, along with a signal amplitude as
large as the supply, eliminates the need to reduce the amplitude
of the input signal and sacrifice SNR. When measuring both the
ac and the dc parts of the signal, a capacitor cannot be in the signal
path. Figure 66 shows examples of the voltage ranges of the singleended-to-differential signal converter circuit.
Rev. A | Page 22 of 24
Data Sheet
ADA4500-2
The dc common-mode part of the input signal (VDC) was measured
using the voltage applied at REF and the voltage measured at the
feedback (FB) output using Equation 2. With VCM of the input
signal known to the system, it can respond appropriately to, for
example, a situation when the common mode is getting too close to
the rails.
Besides converting the ac signal from single-ended to differential,
this circuit separates the ac and dc part of the input signal and
automatically adjusts the common-mode dc level of the output
signal to the same voltage as VREF. The output signal is then a
differential version of the input signal with its common-mode
voltage set to an optimal value (such as, ½ the full-scale input
range to the ADC). The noninverted ac part of the signal is
output at OUTP, and the inverted ac signal is output at OUTN.
The differential output signal (OUTP to OUTN) is centered on
the voltage applied to REF. In this design, R3 and R4 set REF to
½VPOS for maximum signal peak-to-peak swing; however, these
resistors can be eliminated, and the REF input can be driven
from an external source, such as a reference or the output of a
digital-to-analog converter (DAC).
VDC = (2 × FB) − (REF)
(2)
C2
10pF
R11
5kΩ
R2
2kΩ
INPUT
R1A
1kΩ
R1B
1kΩ
VSY
VSY
R10
5kΩ
C1
100pF
U1A
ADA4500-2
C7
1µF
C6
1µF
VSY
U1B
OUTN
U2A
ADA4500-2
R9
5kΩ
R8
5kΩ
VSY
OUTP
U2B
R6
10kΩ
R5
10kΩ
VSY
R4
100kΩ
C5
0.01µF
C3
1µF
R3
100kΩ
REF
FB
INPUT
VCM
OUTP
VREF
VPP
OUTPUT
VPP
OUTN
VCM_MAX = 1.5 × VSY
VCM_MIN = –0.5 × VSY
VPP_MAX = VSY – 0.1V
EXAMPLES (VSY = 5V)
+10V
+7.5V
OUTP
+5V
+5V
OR
+2.5V
VPP
0V
OUTN
10617-105
0V
–2.5V
–5V
Figure 66. Single-Ended-to-Differential Conversion Circuit Separates the AC and DC Part of the Signal
Rev. A | Page 23 of 24
ADA4500-2
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
1.70
1.60 SQ
1.50
EXPOSED
PAD
BOTTOM VIEW
0.80
0.75
0.70
SEATING
PLANE
1
4
TOP VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.30
0.25
0.20
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
07-06-2011-A
0.50
0.40
0.30
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 67. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very, Very Thin, Dual Lead
(CP-8-12)
Dimensions shown in millimeters
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
0.80
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 68. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADA4500-2ACPZ-R7
ADA4500-2ACPZ-RL
ADA4500-2ARMZ
ADA4500-2ARMZ-R7
ADA4500-2ARMZ-RL
1
Temperature
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10617-0-10/12(A)
Rev. A | Page 24 of 24
Package Option
CP-8-12
CP-8-12
RM-8
RM-8
RM-8
Branding
A2Z
A2Z
A2Z
A2Z
A2Z