P-Channel JFET Switch CORPORATION J174 – J177 / SST174 – SST177 FEATURES • Low Insertion Loss • No Offset or Error Generated By Closed Switch Resistive - Purely - High Isolation Resistance From Driver • Short Sample and Hold Aperture Time • Fast Switching APPLICATIONS Switches • Analog • Choppers • Commutators ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise specified) Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . . 30V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC Operating Temperature Range . . . . . . . . . . . -55oC to +135oC Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . . 300oC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350mW Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/ oC NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION ORDERING INFORMATION Part SOT-23 G TO-92 D S S D G 5508 PRODUCT MARKING (SOT-23) SST174 P04 SST175 P05 SST176 P06 SST177 P07 Package Temperature Range J174-J177 Plastic TO-92 -55oC to +135oC SST174-SST177 Plastic SOT-23 -55oC to +135oC For Sorted Chips in Carriers see 2N5114 series. CORPORATION ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified) J174 SYMBOL PARAMETER J175 J176 J177 UNITS TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX IGSS Gate Reverse Current (Note 1) VGS(off) Gate Source Cutoff Voltage 1 5 10 1 3 6 1 1 4 1 0.8 nA 2.25 VDS = 0, VGS = 20V VDS = -15V, ID = -10nA V BVGSS Gate Source Breakdown Voltage 30 30 IDSS Drain Saturation Current (Note 2) -20 -135 -7 ID(off) Drain Cutoff Current (Note 1) -1 rDS(on) Drain-Source ON Resistance 85 Cdg(off) Drain-Gate OFF Capacitance 5.5 Csg(off) Source-Gate OFF Capacitance 5.5 5.5 5.5 5.5 Cdg(on) + Csg(on) Drain-Gate Plus Source Gate ON Capacitance 32 32 32 32 VDS = VGS = 0 td(on) Turn On Delay Time 2 5 15 20 tr Rise Time 5 10 20 25 td(off) Turn Off Delay Time 5 10 15 20 tf Fall Time 10 20 20 25 Switching Time Test Conditions (Note 3) J174 J175 J176 VDD -10V -6V -6V VGS(off) 12V 8V 3V RL 560Ω 12kΩ 5.6kΩ VGS(on) 0V 0V 0V 30 30 -2 -35 -1.5 -20 mA VDS = -15V, VGS = 0 -1 -1 -1 nA VDS = -15V, VGS = 10V 125 250 300 Ω VGS = 0, VDS = -0.1V -70 5.5 5.5 VDS = 0, IG = 1µA 5.5 VDS = 0, VGS = 10V o NOTES: 1. Approximately doubles for every 10 C increase in TA. 2. Pulse test duration -300µs; duty cycle ≤3%. 3. For design reference only, not 100% tested. f = 1MHz (Note 3) pF ns J177 -6V 3V 10kΩ 0V