Current Output/Serial Input, 16-/14-Bit DACs AD5543/AD5553 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 16-bit resolution AD5543 14-bit resolution AD5553 ±1 LSB DNL ±1 LSB INL Low noise: 12 nV/√Hz Low power: IDD = 10 µA 0.5 µs settling time 4Q multiplying reference input 2 mA full-scale current ± 20%, with VREF = 10 V Built-in RFB facilitates voltage conversion 3-wire interface Ultracompact 8-lead MSOP and 8-lead SOIC packages AD5543/AD5553 VREF 16 OR 14 CLK GND 02917-001 16-BIT/14-BIT SHIFT REGISTER SDI Figure 1. 1.0 0.8 0.6 INL (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 65,536 CODE 02917-002 61,440 57,344 53,248 49,152 45,056 40,960 36,864 32,768 28,672 24,575 20,480 16,384 8152 12,288 0 –1.0 4096 –0.8 The applied external reference, VREF, determines the full-scale output current. An internal feedback resistor (RFB) facilitates the R-2R and temperature tracking for voltage conversion when combined with an external op amp. Figure 2. Integral Nonlinearity A serial-data interface offers high speed, 3-wire microcontrollercompatible inputs using serial data in (SDI), clock (CLK), and chip select (CS). 2 0 –2 –4 GAIN (dB) The AD5543/AD5553 are packaged in ultracompact (3 mm × 4.7 mm) 8-lead MSOP and 8-lead SOIC packages. DAC REGISTER CONTROL LOGIC CS Automatic test equipment Instrumentation Digitally controlled calibration Industrial control PLCs The AD5543/AD5553 are precision 16-/14-bit, low power, current output, small form factor digital-to-analog converters (DACs). They are designed to operate from a single 5 V supply with a ±10 V multiplying reference. IOUT DAC 16 OR 14 APPLICATIONS GENERAL DESCRIPTION RFB VDD –6 –8 –10 –14 10k 100k 1M 10M FREQUENCY (Hz) 100M 02917-025 –12 Figure 3. Reference Multiplying Bandwidth Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved. AD5543/AD5553 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 11 Applications ....................................................................................... 1 Stability ........................................................................................ 11 General Description ......................................................................... 1 Positive Voltage Output ............................................................. 11 Functional Block Diagram .............................................................. 1 Bipolar Output ............................................................................ 11 Revision History ............................................................................... 2 Programmable Current Source ................................................ 12 Specifications..................................................................................... 3 Reference Selection .................................................................... 12 Timing Diagrams.......................................................................... 4 Amplifier Selection .................................................................... 12 Absolute Maximum Ratings............................................................ 5 Evaluation Board ............................................................................ 14 ESD Caution .................................................................................. 5 System Development Platform ................................................. 14 Pin Configuration and Function Descriptions ............................. 6 AD5543/AD5553 to SPORT Interface .................................... 14 Typical Performance Characteristics ............................................. 7 Waveform Generator ................................................................. 14 Circuit Operation ............................................................................. 9 Operating the Evaluation Board .............................................. 14 DAC Section .................................................................................. 9 Bill of Materials ........................................................................... 18 Serial Data Interface ....................................................................... 10 Outline Dimensions ....................................................................... 19 ESD Protection Circuits............................................................. 10 Ordering Guide .......................................................................... 20 PCB Layout and Power Supply Bypassing .............................. 10 REVISION HISTORY 1/12—Rev. E to Rev. F Added Figure 15, Renumbered Sequentially ................................ 8 Change to Table 9 ........................................................................... 13 Changes to Figure 27 ...................................................................... 15 Changes to Figure 28 ...................................................................... 16 Replaced Figure 29, Figure 30, and Figure 31 ............................. 17 2/11—Rev. D to Rev. E Added Evaluation Board Section ................................................. 14 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 4/10—Rev. C to Rev. D Changes to Figure 3 .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Moved Timing Diagrams Section .................................................. 4 Moved Table 4 ................................................................................... 6 Delete Figure 13; Renumbered Sequentially ................................. 8 Changes to Figure 14 ........................................................................ 8 Changes to Figure 18 ........................................................................ 9 Moved Table 5 and Table 6 ............................................................ 10 Added Reference Selection Section and Amplifier Selection Section .............................................................................................. 12 Added Table 7, Table 8, and Table 9; Renumbered Sequentially.............................................................. 13 10/09—Rev. B to Rev. C Updated Outline Dimensions..................................................... 14 Changes to Ordering Guide .......................................................... 15 7/09—Rev. A to Rev. B Updated Format .................................................................. Universal Change to Features Section ..............................................................1 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 2/03—Rev. 0 to Rev. A Changes to Ordering Guide .............................................................3 12/02—Revision 0: Initial Version Rev. F | Page 2 of 20 Data Sheet AD5543/AD5553 SPECIFICATIONS VDD = 5 V ± 10%, VSS = 0 V, IOUT = virtual GND, GND = 0 V, VREF = 10 V, TA = full operating temperature range, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE 1 Resolution Symbol Condition 5 V ± 10% Unit N 1 LSB = VREF/216 = 153 µV when VREF = 10 V (AD5543) 1 LSB = VREF/214 = 610 µV when VREF = 10 V (AD5553) Grade: AD5553C Grade: AD5543C Grade: AD5543B Monotonic Data = 0x0000, TA = 25°C Data = 0x0000, TA = TA maximum Data = 0xFFFF 16 14 ±1 ±1 ±2 ±1 10 20 ±1/±4 1 Bits Bits LSB max LSB max LSB max LSB max nA max nA max mV typ/max ppm/°C typ −15/+15 5 5 V min/max kΩ typ 3 pF typ 2 mA typ 200 pF typ 0.8 2.4 10 10 V max V min µA max pF max 50 10 10 0 10 5 10 MHz ns min ns min ns min ns min ns min ns min 4.5/5.5 10 0.055 0.006 V min/max µA max mW max %/% max Relative Accuracy INL Differential Nonlinearity Output Leakage Current DNL IOUT Full-Scale Gain Error Full-Scale Temperature Coefficient 2 REFERENCE INPUT VREF Range Input Resistance Input Capacitance2 ANALOG OUTPUT Output Current GFSE TCVFS Output Capacitance2 LOGIC INPUTS AND OUTPUT Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance2 INTERFACE TIMING2, 4 Clock Input Frequency Clock Width High Clock Width Low CS to Clock Setup Clock to CS Hold Data Setup Data Hold SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity COUT VREF RREF CREF IOUT Data = 0xFFFF for AD5543 Data = 0x3FFF for AD5553 Code dependent VIL VIH IIL CIL See Figure 4 and Figure 5 fCLK tCH tCL tCSS tCSH tDS tDH VDD RANGE IDD PDISS PSS Logic inputs = 0 V Logic inputs = 0 V ΔVDD = ±5% Rev. F | Page 3 of 20 AD5543/AD5553 Data Sheet Parameter AC CHARACTERISTICS4 Output Voltage Settling Time Reference Multiplying Bandwidth DAC Glitch Impulse Feedthrough Error Digital Feedthrough Total Harmonic Distortion Output Spot Noise Voltage Symbol Condition 5 V ± 10% Unit tS To ±0.1% of full scale, Data = 0x0000 to 0xFFFF to 0x0000 for AD5543 Data = 0x0000 to 0x3FFF to 0x0000 for AD5553 VREF = 100 mV rms, data = 0xFFFF VREF = 0 V, data = 0x7FFF to 0x8000 for AD5543 Data = 0x0000, VREF = 100 mV rms, same channel CS = 1 and fCLK = 1 MHz VREF = 5 V p-p, data = 0xFFFF, f = 1 kHz f = 1 kHz, BW = 1 Hz 0.5 µs typ 6.6 7 −83 7 −103 12 MHz typ nV-sec dB nV-sec dB typ nV/√Hz BW Q VOUT/VREF Q THD eN All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is tied to the amplifier output. The +IN op amp is grounded, and the DAC IOUT is tied to the −IN op amp. Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and are not subject to production testing. 3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used. 4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 1 TIMING DIAGRAMS SDI D15 D14 D13 D12 D11 D10 D9 D8 D1 D0 CLK tDS tDH tCH tCL tCSS tCSH 02917-016 CS Figure 4. AD5543 Timing Diagram SDI D13 D12 D11 D10 D9 D8 D7 D6 D1 D0 CLK tDS tDH tCH tCL tCSS tCSH 02917-017 CS Figure 5. AD5553 Timing Diagram Rev. F | Page 4 of 20 Data Sheet AD5543/AD5553 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD to GND VREF to GND Logic Inputs to GND V(IOUT) to GND Input Current to Any Pin Except Supplies Package Power Dissipation Thermal Resistance, θJA 8-Lead Surface Mount (MSOP) 8-Lead Surface Mount (SOIC) Maximum Junction Temperature (TJ Max) Operating Temperature Range Model B and Model C Storage Temperature Range Lead Temperature R-8, RM-8 (Vapor Phase, 60 sec) R-8, RM-8 (Infrared, 15 sec) Rating −0.3 V to +8 V −18 V to +18 V −0.3 V to +8 V −0.3 V to VDD + 0.3 V ±50 mA (TJ Max − TA )/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 150°C/W 100°C/W 150°C −40°C to +85°C −65°C to +150°C 215°C 220°C Rev. F | Page 5 of 20 AD5543/AD5553 Data Sheet CLK 1 AD5543/ AD5553 SDI 2 RFB 3 VREF 4 TOP VIEW (Not to Scale) 8 CS 7 VDD 6 GND 5 IOUT 02917-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic CLK SDI RFB VREF IOUT 6 7 8 GND VDD CS Description Clock Input. Positive-edge triggered, clocks data into shift register. Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored. Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output. DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for voltage output. Analog and Digital Ground. Positive Power Supply Input. Specified range of operation at 5 V ± 10%. Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge. See Table 4 for operation. Table 4. Control-Logic Truth Table CLK X ↑+ 1 X1 X1 1 CS H L H ↑+1 Serial Shift Register Function No effect Shift register data advanced one bit No effect Shift register data transferred to DAC register ↑+ = positive logic transition; X = don't care. Rev. F | Page 6 of 20 DAC Register Latched Latched Latched New data loaded from serial register Data Sheet AD5543/AD5553 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 DNL (LSB) 1.0 0 –0.2 0 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE (Decimal) –1.0 0 2048 Figure 7. AD5543 Integral Nonlinearity Error 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) 02917-008 –0.2 02917-005 INL (LSB) TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. AD5553 Differential Nonlinearity Error 1.5 1.0 VREF = 2.5V TA = 25°C 0.8 1.0 0.2 0 –0.2 –0.4 –0.6 0.5 INL 0 DNL –0.5 –1.0 GE –0.8 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE (Decimal) –1.5 02917-006 –1.0 2 4 Figure 8. AD5543 Differential Nonlinearity Error 10 Figure 11. Linearity Error vs. VDD 5 1.0 VDD = 5V TA = 25°C 0.8 4 SUPPLY CURRENT IDD (mA) 0.6 0.4 0.2 0 –0.2 –0.4 3 2 1 –0.6 –0.8 –1.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) 02917-007 INL (LSB) 6 8 SUPPLY VOLTAGE VDD (V) 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 LOGIC INPUT VOLTAGE VIH (V) Figure 12. Supply Current vs. Logic Input Voltage Figure 9. AD5553 Integral Nonlinearity Error Rev. F | Page 7 of 20 5.0 02917-010 DNL (LSB) 0.4 02917-009 LINEARITY ERROR (LSB) 0.6 AD5543/AD5553 Data Sheet 3.0 SUPPLY CURRENT (mA) 2.5 A2 –5V 5V 2V DLY 67.72µs 2.0 0x5555 1.5 0x8000 1.0 0xFFFF 0x0000 100k 100M 1M 10M CLOCK FREQUENCY (Hz) 136ns Figure 16. Settling Time Figure 13. AD5543 Supply Current vs. Clock Frequency –3.65 90 VDD = 5V ± 10% VREF = 10V 80 –3.70 70 –3.75 60 –3.80 VOUT (V) PSRR (dB) 02917-014 0 10k 02917-011 0.5 50 40 –3.85 –3.90 30 –3.95 20 100 10k 1k FREQUENCY (Hz) 100k 1M –4.05 –20 02917-012 0 10 0 –40 –60 –80 –100 –120 –140 10 15 20 FREQUENCY (kHz) 25 02917-200 POWER SPECTRUM (dB) –20 5 10 20 30 Figure 17. Midscale Transition and Digital Feedthrough 20 0 0 TIME (ns) Figure 14. Power Supply Rejection Ratio (PSRR) vs. Frequency –160 –10 Figure 15. AD5543/AD5553 Analog THD Rev. F | Page 8 of 20 40 02917-026 –4.00 10 Data Sheet AD5543/AD5553 CIRCUIT OPERATION Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity. DAC SECTION VDD The DAC architecture uses a current steering R-2R ladder design. Figure 18 shows the typical equivalent DAC structure. The DAC contains a matching feedback resistor for use with an external op amp (see Figure 19). With RFB and IOUT terminals connected to the op amp output and inverting node, respectively, a precision voltage output is achieved as VOUT = −VREF × D/65,536 (AD5543) (1) VOUT = −VREF × D/16,384 (AD5553) (2) Note that the output voltage polarity is the opposite of the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal logic to drive the on and off states of the DAC switches. VDD R R R RFB VREF 2R 2R 2R R S2 5kΩ S1 IOUT DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY; SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED. 02917-018 GND R2 VREF VREF R1 C1 RFB VDD AD5543/ AD5553 IOUT1 A1 GND VOUT = 0 TO –VREF SYNC SCLK SDIN AGND µCONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (4pF TO 6pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. 02917-019 The AD5543/AD5553 contain 16-/14-bit current output, DACs, serial input registers, and DAC registers. Both converters use a 3-wire serial data interface. Figure 19. Voltage Output Configuration These DACs are also designed to accommodate ac reference input signals. The AD5543 accommodates input reference voltages in the range of −12 V to +12 V. The reference voltage inputs exhibit a constant nominal input resistance value of 5 kΩ ± 30%. The DAC output (IOUT) is code dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the AD5543 on the inverting input node of the amplifier. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. To maintain good analog performance, power supply bypassing of 0.01 µF to 0.1 µF ceramic or chip capacitors, in parallel with a 1 µF tantalum capacitor, is recommended. Due to degradation of PSRR in frequency, users must avoid using switching power supplies. Figure 18. Equivalent R-2R DAC Circuit Rev. F | Page 9 of 20 AD5543/AD5553 Data Sheet SERIAL DATA INTERFACE VDD The AD5543/AD5553 use a 3-wire (CS, SDI, CLK) serial data interface. New serial data is clocked into the serial input register in a 16-bit data-word format for the AD5543. The MSB is loaded first. Table 5 defines the 16 data-word bits. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK, subject to the data setup-and-hold time requirements that are specified in the interface timing specifications. Only the last 16 bits clocked into the serial register are interrogated when the CS pin is strobed to transfer the serial register data to the DAC register. Because most microcontrollers output serial data in 8bit bytes, two data bytes can be written to the AD5543/AD5553. After loading the serial register, the rising edge of CS transfers the serial register data to the DAC register; during this strobe, the CLK should not be toggled. For the AD5553, with 16-bit clock cycles, the two LSBs are ignored. DIGITAL INPUTS 02917-020 5kΩ DGND Figure 20. Equivalent ESD Protection Circuits PCB LAYOUT AND POWER SUPPLY BYPASSING It is a good practice to employ compact, minimum lead length PCB layout design. The leads to the input should be as short as possible to minimize IR drop and stray inductance. It is also essential to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. ESD PROTECTION CIRCUITS All logic input pins contain back-biased ESD protection Zener diodes that are connected to ground (DGND) and VDD, as shown in Figure 20. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. Table 5. AD5543 Serial Input Register Data Format; Data Loaded MSB-First Format B15 (MSB) D15 B14 D14 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 (LSB) D0 Table 6. AD5553 Serial Input Register Data Format; Data Loaded MSB-First Format B13 (MSB)1 D13 1 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 (LSB) D0 A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered are transferred to the DAC register when CS returns to logic high. Rev. F | Page 10 of 20 Data Sheet AD5543/AD5553 APPLICATIONS INFORMATION STABILITY BIPOLAR OUTPUT VDD RFB VDD IOUT VREF VO AD8628 GND AD5543/AD5553 02917-021 VREF The AD5543/AD5553 are inherently 2-quadrant multiplying DACs. That is, they can easily be set up for unipolar output operation. The full-scale output polarity is the inverse of the reference input voltage. C1 U2 Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible to each other, and proper PCB layout technique must be employed. Because every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. An optional compensation capacitor, C1, can be added for stability, as shown in Figure 21. C1 should be found empirically, but 20 pF is generally adequate for the compensation. POSITIVE VOLTAGE OUTPUT To achieve the positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the tolerance errors of the resistors. To generate a negative reference, the reference can be level-shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and −2.5 V, respectively (see Figure 22). In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing, which is easily accomplished by using an additional U4 external amplifier configured as a summing amplifier (see Figure 23). In this circuit, the second amplifier, U4, provides a gain of 2 that increases the output span magnitude to 5 V. Biasing the external amplifier with a 2.5 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = −2.5 V) to midscale (VOUT = 0 V) to full-scale (VOUT = +2.5 V). VOUT = (D/32,768 − 1) × VREF (AD5543) (3) VOUT = (D/16,384 − 1) × VREF (AD5553) (4) For the AD5543, the resistance tolerance becomes the dominant error of which users should be aware. R1 C2 U4 +5V +5V ADR03 +5V ADR03 +5V VOUT VIN +5V V+ 1/2AD8620 V– VDD U3 U1 VDD VOUT VIN VREF GND GND 5kΩ ± 0.01% R3 RFB C1 VREF AD5553 ONLY C1 RFB IOUT 1/2AD8620 1/2AD8628 GND –5V AD5543/AD5553 U2 0V < VO < +2.5V Figure 22. Positive Voltage Output Configuration Rev. F | Page 11 of 20 VO –5V –2.5V < VO < +2.5V U2 Figure 23. 4-Quadrant Multiplying Application Circuit VO –2.5V V+ 1/2AD8620 V– IOUT U3 U1 GND 02917-022 U4 R2 10kΩ ± 0.01% 10kΩ ± 0.01% 02917-023 U1 AD5543/AD5553 Data Sheet PROGRAMMABLE CURRENT SOURCE REFERENCE SELECTION Figure 24 shows a versatile V-I conversion circuit using an improved Howland current pump. In addition to the precision current conversion it provides, this circuit enables a bidirectional current flow and high voltage compliance. This circuit can be used in 4 mA to 20 mA current transmitters with up to 500 Ω of load. In Figure 24, it can be shown that if the resistor network is matched, the load current is When selecting a reference for use with the AD55xx series of current output DACs, pay attention to the output voltage, temperature coefficient specification of the reference. Choosing a precision reference with a low output temperature coefficient minimizes error sources. Table 7 lists some of the references available from Analog Devices, Inc., that are suitable for use with this range of current output DACs. IL = (R2 + R3)/ R1 R3 × V REF × D (5) R3 in theory can be made small to achieve the current needed within the U3 output current driving capability. This circuit is versatile such that AD8510 can deliver ±20 mA in both directions and the voltage compliance approaches 15 V, which is limited mainly by the supply voltages of U3. However, users must pay attention to the compensation. Without C1, it can be shown that the output impedance becomes ZO = R1' R3(R1 + R2 ) (6) R1(R2' + R3' ) − R1' (R2 + R3 ) If the resistors are perfectly matched, ZO is infinite, which is desirable, and behaves as an ideal current source. On the other hand, if they are not matched, ZO can be either positive or negative. Negative can cause oscillation. As a result, C1 is needed to prevent the oscillation. For critical applications, C1 could be found empirically but typically falls in the range of a few picofarads (pF). VDD U1 VDD VREF VREF GND AD8628 R1' R2' 150kΩ 15kΩ C1 10pF AD5543/AD5553 U2 VDD V+ U3 R3' 50Ω The input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor, RFB. Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error at the voltage output of the circuit. Analog Devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in Table 8 and Table 9. AD8510 V– The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. Because of the code-dependent output resistance of the DAC, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. Provided that the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, minimize capacitance at the VREF node (the voltage output node in this application) of the DAC. This is done by using low input capacitance buffer amplifiers and careful board design. RFB IOUT AMPLIFIER SELECTION R3 50Ω VSS VL R1 150kΩ R2 15kΩ IL 02917-024 LOAD Figure 24. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance Capabilities Rev. F | Page 12 of 20 Data Sheet AD5543/AD5553 Table 7. Suitable Analog Devices Precision References Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR420 ADR421 ADR423 ADR425 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5.0 5.0 2.5 2.5 3.0 3.0 2.048 2.50 3.00 5.00 2.500 5.000 2.5 5.0 Maximum Temperature Drift (ppm/°C) 3 9 3 9 3 9 3 9 3 3 3 3 3 3 9 9 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.1 0.1 0.1 0.1 0.05 0.04 0.04 0.04 0.04 0.04 0.16 0.10 ISS (mA) 1 1 1 1 1 1 1 1 0.5 0.5 0.5 0.5 0.8 0.8 0.12 0.12 Output Noise (μV p-p) 20 20 10 10 6 6 10 10 1.75 1.75 2 3.4 3.5 8 5 8 Package(s) SOIC-8 TSOT-5, SC70-5 SOIC-8 TSOT-5, SC70-5 SOIC-8 TSOT-5, SC70-5 SOIC-8 TSOT-5, SC70-5 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 TSOT-5 TSOT-5 Table 8. Suitable Analog Devices Precision Op Amps Part No. OP97 OP1177 AD8675 AD8671 ADA4004-1 AD8603 AD8607 AD8605 AD8615 AD8616 Supply Voltage (V) ±2 to ±20 ±2.5 to ±15 ±5 to ±18 ±5 to ±15 ±5 to ±15 1.8 to 5 1.8 to 5 2.7 to 5 2.7 to 5 2.7 to 5 VOS Maximum (μV) 25 60 75 75 125 50 50 65 65 65 IB Maximum (nA) 0.1 2 2 12 90 0.001 0.001 0.001 0.001 0.001 0.1 Hz to 10 Hz Noise (μV p-p) 0.5 0.4 0.1 0.077 0.1 2.3 2.3 2.3 2.4 2.4 Supply Current (μA) 600 500 2300 3000 2000 40 40 1000 2000 2000 Package(s) SOIC-8 , PDIP-8 MSOP-8, SOIC-8 MSOP-8, SOIC-8 MSOP-8, SOIC-8 SOIC-8, SOT-23-5 TSOT-5 MSOP-8, SOIC-8 WLCSP-5, SOT-23-5 TSOT-5 MSOP-8, SOIC-8 Table 9. Suitable Analog Devices High Speed Op Amps Part No. AD8065 AD8066 AD8021 AD8038 ADA4899-1 AD8057 AD8058 AD8061 AD8062 AD9631 Supply Voltage (V) 5 to 24 5 to 24 5 to 24 3 to 12 5 to 12 3 to 12 3 to 12 2.7 to 8 2.7 to 8 ±3 to ±6 BW @ ACL (MHz) 145 145 490 350 600 325 325 320 320 320 Slew Rate (V/μs) 180 180 120 425 310 1000 850 650 650 1300 Rev. F | Page 13 of 20 VOS (Max) (μV) 1500 1500 1000 3000 35 5000 5000 6000 6000 10,000 IB (Max) (nA) 0.006 0.006 10,500 750 100 500 500 350 350 7000 Package(s) SOIC-8, SOT-23-5 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, SC70-5 LFCSP-8, SOIC-8 SOT-23-5, SOIC-8 SOIC-8, MSOP-8 SOT-23-5, SOIC-8 SOIC-8, MSOP-8 SOIC-8, PDIP-8 AD5543/AD5553 Data Sheet EVALUATION BOARD SPORT_TFS CS SPORT_TSCLK SCLK SPORT_DTO SDIN SYSTEM DEVELOPMENT PLATFORM 02917-124 The EVAL-AD5543/EVAL-AD5553 is used in conjunction with an SDP1Z system development platform board available from Analog Devices, which is purchased separately from the evaluation board. The USB-to-SPI communication to the AD5543 is completed using this Blackfin-based development board. The software offers a waveform generator. The system development platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this device, see the system development platform web page. WAVEFORM GENERATOR AD5543/AD5553 TO SPORT INTERFACE OPERATING THE EVALUATION BOARD The Analog Devices SDP has one SPORT serial port. The SPORT interface is used to control the AD5543/AD5553, allowing clock frequencies up to 30 MHz. The evaluation board requires ±12 V and +5 V supplies. The +12 V VDD and VSS are used to power the output amplifier, while the +5 V is used to power the DAC (VDD1). AD5543/AD5553 ADSP-BF527 Figure 25. AD5543/AD5553 to SPORT Interface 02917-125 The evaluation board software offers a waveform generator to show every change introduced and transmitted to the output. Figure 26. Evaluation Board Software—Waveform Generator Rev. F | Page 14 of 20 Rev. F | Page 15 of 20 Figure 27. Schematic of AD5543/AD5553 Evaluation Board C8 10uF + 4 U2 ADR435 C9 5 TRIM 0.1uF GND VOUT 8 /CS 2 2 /CS SDIN + VIN SDIN J1-3 J1-4 J1-5 1 SCLK DGND SCLK VDD VSS VDD J1-2 6 CS C1 AGND 0.1uF C10 AGND 6 LK1 VREF IOUT RFB C2 AD5543_53 SDIN SCLK U1 7 VDD DVDD 4 5 3 0.1uF 10uF OP AMP + REFERENCE SUPPLY DAC + VIN FOR SDP + J1-1 J3 U3 + DIS 8 - VDD 3 2 VREF C3 5.6pF VSS C6 V- 4 OP V+ 7 C5 C4 C7 + 10uF 6 0.1uF 10uF 0.1uF + DVDD VOUT J4 VOUT Data Sheet AD5543/AD5553 02917-126 AD5543/AD5553 Data Sheet BMODE1: PULL UP WITH A 10k RESISTOR TO SET SDP TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD J2 VIN: USE THIS PIN TO POWER THE SDP REQUIRES 4-7V 200mA RESET_IN BMODE1 UART_TX UART_RX GND GND NC NC SDP NC NC STANDARD NC NC CONNECTOR NC NC NC NC GND GND NC NC NC NC TMR_D TMR_C * TIMERS TMR_B TMR_A GPIO7 GPIO6 GND GND GENERAL GPIO5 GPIO4 INPUT/OUTPUT GPIO3 GPIO2 GPIO1 GPIO0 SCL_0 SCL_1 I2C SDA_0 SDA_1 GND GND SPI_CLK SPI_SEL1/SPI_SS SPI_MISO SPI_SEL_C SPI SPI_MOSI SPI_SEL_B SPI_SEL_A GND GND SPORT_INT SPORT_TSCLK SPORT_DT3 * * SPORT_DT0 SPORT_DT2 SPORT SPORT_TFS SPORT_DT1 SPORT_RFS SPORT_DR1 SPORT_DR0 SPORT_DR2 * SPORT_RSCLK SPORT_DR3 * GND GND PAR_CLK PAR_FS1 PAR_FS2 PAR_FS3 PAR_A0 PAR_A1 PAR_A2 PAR_A3 GND GND PAR_INT PAR_CS PAR_WR PAR_RD PAR_D0 PAR_D1 PARALLEL PAR_D2 PAR_D3 PORT PAR_D4 PAR_D5 GND GND PAR_D6 PAR_D7 PAR_D8 PAR_D9 PAR_D10 PAR_D11 PAR_D12 PAR_D13 GND PAR_D14 PAR_D15 GND * * PAR_D16 PAR_D17 * PAR_D18 PAR_D19 * * PAR_D20 PAR_D21 * * PAR_D22 PAR_D23 * GND GND VIO(+3.3V) USB_VBUS GND GND GND GND NC NC *NC ON BLACKFIN SDP NC VIN 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 BOARD ID EEPROM (24LC64) MUST BE ON I2C BUS 0, ADDRESS IS AT USER DISCRETION 3.3V_BF U4 1 2 A0 3 A1 4 A2 VSS 24LC64 STATUS START MAIN I2C BUS (CONNECTED TO BLACKFIN TWI - PULL UP RESISTORS NOT REQUIRED) I2C BUS 1 IS COMMON ACROSS BOTH CONNECTORS ON SDP - PULL UP RESISTORS REQUIRED (CONNECTED TO BLACKFIN GPIO - USE I2C_0 FIRST) Figure 28. Schematic of SDP Interface Rev. F | Page 16 of 20 8 VCC 7 WP 6 SCL 5 SDA SCLK SDIN /CS 3.3V_BF VIO: USE TO SET IO VOLTAGE MAX DRAW 20mA 02917-127 USB_VBUS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AD5543/AD5553 02917-128 Data Sheet 02917-129 Figure 29. Silkscreen—Component Side View (Top Layer) 02917-130 Figure 30 Component Side Artwork Figure 31. Solder Side Artwork Rev. F | Page 17 of 20 AD5543/AD5553 Data Sheet BILL OF MATERIALS Table 10. Name CS AGND C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 GL1 J1 J2 J3 J4 SCLK SDIN U1 U2 U3 U4 USB_VBUS VOUT VREF X1 X2 Part Description Testpoint Testpoint Capacitor+ Capacitor Capacitor Capacitor+ Capacitor Capacitor+ Capacitor Capacitor+ Capacitor Capacitor Capacitor Capacitor Ground link CON\POWER5 SDP-STANDARD-CONN SMB SMB Testpoint Testpoint AD5543/AD5553 ADR435 AD8038 24LC64 Testpoint Testpoint Testpoint MTHOLE-3MM MTHOLE-3MM Value 10 µF 0.1 µF 5.6 pF 10 µF 0.1 µF 10 µF 0.1 µF 10 µF 0.1 µF 0.1 µF 10 µF 0.1 µF PCB Decal Testpoint Testpoint RTAJ_A C0603 C0603 RTAJ_B C0603 RTAJ_B C0603 RTAJ_B C0603 C0603 C0805 C0603 Component link CON\POWER5 CON-120/FX8-120S-SV SMB SMB Testpoint Testpoint SO8NB SO8NB SO8NB MSO8 Testpoint Testpoint Testpoint MTHOLE-3MM MTHOLE-3MM Rev. F | Page 18 of 20 Part Description Red testpoint Black testpoint 10 V SMD tantalum capacitor 50 V X7R ceramic capacitor Multilayer ceramic capacitor 16 V tantalum capacitor 50 V X7R ceramic capacitor 16 V tantalum capacitor 50 V X7R ceramic capacitor 16 V tantalum capacitor 50 V X7R ceramic capacitor 50 V X7R ceramic capacitor 10 V 10 µF ceramic capacitor 10% X5R 0805 50 V X7R ceramic capacitor Copper short 5-pin terminal block 120-way connector, 0.6 mm pitch, receptacle Straight PCB mount SMB jack—50 Ω Straight PCB mount SMB jack—50 Ω Red testpoint Red testpoint Digital-to-analog converter 5 V reference Single op amp 8-pin 64K I2C serial EEPROM MSOP8 Black testpoint Red testpoint Red testpoint 3 mm NPTH hole 3 mm NPTH hole Data Sheet AD5543/AD5553 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.80 0.55 0.40 0.23 0.09 6° 0° 0.40 0.25 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 32. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 19 of 20 012407-A 8 4.00 (0.1574) 3.80 (0.1497) AD5543/AD5553 Data Sheet ORDERING GUIDE Model 1, 2 AD5543CRMZ AD5543CRMZ-REEL7 AD5543BR AD5543BRZ AD5543BRM AD5543BRM-REEL7 AD5543BRMZ AD5543BRMZ-REEL7 AD5553CRM AD5553CRM-REEL7 AD5553CRMZ AD5553CRMZ-REEL7 EVAL-AD5543SDZ 1 2 INL (LSB) ±1 ±1 ±2 ±2 ±2 ±2 ±2 ±2 ±1 ±1 ±1 ±1 RES (LSB) 16 16 16 16 16 16 16 16 14 14 14 14 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C The AD5543 contains 1040 transistors. The die size measures 55 mil × 73 mil or 4,015 sq. mil. Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked. ©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02917-0-1/12(F) Rev. F | Page 20 of 20 Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board Package Option RM-8 RM-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding DEV DEV DXB DXB DXB# DXB# DUC DUC DUC# DUC#