Burr-Brown OPA2889IDGST Dual, low-power, wideband, voltage feedback operational amplifier with disable Datasheet

 OPA2889
OP
A2
889
OP
A28
89
SBOS373 – JUNE 2007
Dual, Low-Power, Wideband, Voltage-Feedback
OPERATIONAL AMPLIFIER with Disable
FEATURES
•
•
•
•
•
•
•
FLEXIBLE SUPPLY RANGE:
+2.6V to +12V Single Supply
±1.3V to ±6V Dual Supplies
UNITY-GAIN STABLE
WIDEBAND ±5V OPERATION: 60MHz
(G = +2V/V)
OUTPUT VOLTAGE SWING: ±4V
HIGH SLEW RATE: 250V/μs
LOW QUIESCENT CURRENT: 460μA/ch
LOW DISABLE CURRENT: 18μA/ch
APPLICATIONS
•
•
•
•
•
•
•
50W
500pF
200W
RELATED
OPERATIONAL AMPLIFIER
PRODUCTS
+5V
+6V
ADS8472
Vi
0V ® 4V
1/2
OPA2889
16W
-6V
200W
750W
.01mF
16-Bit
1MSPS
SAR ADC
750W
+6V
375W
The OPA2889 represents a major step forward in
unity-gain stable, voltage-feedback op amps. A new
internal architecture provides slew rate and
full-power bandwidth previously found only in
wideband, current-feedback op amps. These
capabilities give exceptional full-power bandwidth.
Using a dual ±5V supply, the OPA2889 can deliver a
±4V output swing with over 40mA drive current and
60MHz bandwidth. This combination of features
makes the OPA2889 an ideal RGB line driver or
single-supply analog-to-digital converter (ADC) input
driver or low power twisted pair line receiver.
The low 460μA/ch supply current of the OPA2889 is
precisely trimmed at +25°C. System power may be
reduced further using the optional disable control pin.
Leaving this disable pin open, or holding it HIGH,
operates the OPA2889 normally. If pulled LOW, the
OPA2889 supply current drops to less than 20μA/ch
while the output goes into a high-impedance state.
VIDEO LINE DRIVING
xDSL LINE RECEIVERS
HIGH-SPEED IMAGING CHANNELS
ADC BUFFERS
PORTABLE INSTRUMENTS
TRANSIMPEDANCE AMPLIFIERS
ACTIVE FILTERS
1kW
DESCRIPTION
1/2
OPA2889
SINGLES
DUALS
Low-Power Voltage-Feedback
with Disable
TRIPLES
OPA890
OPA2890
Voltage-Feedback Amplifier
with Disable (1800V/μs)
OPA690
OPA2690
OPA3690
Current-Feedback Amplifier
with Disable (2100V/μs)
OPA691
OPA2691
OPA3691
Fixed Gain
OPA692
OPA3692
16W
VREF/2
-6V
500kHz LP
Pole
Low Power, DC-Coupled, Single-to-Differential
Driver for ≤100kHz Inputs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
OPA2889
www.ti.com
SBOS373 – JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA2889
SO-8
D
–40°C to +85°C
OP2889
OPA2889
MSOP-10
DGS
–40°C to +85°C
BZY
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA2889ID
Rail, 75
OPA2889IDR
Tape and Reel, 2500
OPA2889IDGST
Tape and Reel, 250
OPA2889IDGSR
Tape and Reel, 2500
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).
OPA2889
UNIT
±6.5
V
Power supply
Internal power dissipation
See Thermal Characteristics
±VS
V
–40 to +125
°C
Lead temperature (soldering, 10s)
+260
°C
Maximum junction temperature (TJ)
+150
°C
Maximum junction temperature (TJ), continuous operation
+140
C
Human body model (HBM)
2000
V
Charge device model (CDM)
1000
V
Machine model (MM)
150
V
Input voltage range
Storage temperature range
ESD Rating:
PIN ASSIGNMENTS
Top View
2
SO-8
Out A
1
-In A
2
+In A
3
-VS
4
A
B
8
+VS
7
Out B
6
-In B
5
+In B
Top View
MSOP-10
+In A
1
10
-In A
DIS A
2
9
Out A
-VS
3
8
+VS
DIS B
4
7
Out B
+In B
5
6
-In B
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SBOS373 – JUNE 2007
ELECTRICAL CHARACTERISTICS: VS = 5V
At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted.
OPA2889ID, IDGS
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
60
40
36
32
G = +10V/V, VO = 100mVPP
8
6
5
G > +20V/V
75
60
50
G = +2V/V, VO = 100mVPP
14
CONDITIONS
+25°C
G = +1V/V, VO = 100mVPP, RF = 0Ω
115
G = +2V/V, VO = 100mVPP
MIN/
MAX
TEST
LEVEL (1)
MHz
typ
C
MHz
min
B
4.5
MHz
min
B
45
MHz
min
B
MHz
typ
C
UNITS
AC PERFORMANCE
Small-Signal Bandwidth
Gain Bandwidth Product
Bandwidth for 0.1dB Flatness
Peaking at a Gain of +1V/V
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Settling Time to 0.02%
VO < 100mVPP , RF =0 Ω
1
dB
typ
C
G = +2V/V, VO = 2VPP
70
MHz
typ
C
G = +2V/V, VO = 2V Step
250
V/μs
min
B
0.2V Step
6
ns
typ
C
G = +1V/V, VO = 2V Step
36
ns
typ
C
25
ns
typ
C
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
175
160
150
G = +2V/V, f = 1MHz, VO = 2VPP
RL = 200Ω
–75
–65
–62
–60
dBc
max
B
RL ≥ 500Ω
–80
–73
–68
–65
dBc
max
B
RL = 200Ω
–80
–74
–70
–68
dBc
max
B
RL ≥ 500Ω
–82
–80
–75
–72
dBc
max
B
Input Voltage Noise
f > 100kHz
8.4
10
11.5
12
nV/√Hz
max
B
Input Current Noise
f > 100kHz
0.7
1
1.2
1.4
pA/√Hz
max
B
Differential Gain
G = +2V/V, VO = 1.4VPP, RL = 150Ω
0.06
%
typ
C
Differential Phase
G = +2V/V, VO = 1.4VPP, RL = 150Ω
0.04
°
typ
C
f = 5MHz, Input-referred
–85
dB
typ
C
Channel-to-Channel Crosstalk
DC PERFORMANCE (4)
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Input Bias Current Drift
Input Offset Current
Average Input Offset Current
Drift
VO = 0V, RL = 100Ω
66
60
58
57
dB
min
A
VCM = 0V
±1.5
5
5.9
6.3
mV
max
A
20
20
μV/°C
max
B
840
880
nA
max
A
2
2
nA/°C
max
B
225
235
nA
max
A
0.5
0.5
nA/°C
max
B
VCM = 0V
VCM = 0V
±150
±750
VCM = 0V
VCM = 0V
±50
200
VCM = 0V
INPUT
Common-Mode Input Range
(CMIR) (5)
Common-Mode Rejection Ratio
(CMRR)
VCM = 0V, Input-referred
±3.9
±3.8
3.7
3.6
V
min
A
70
60
59
58
dB
min
A
Input Impedance
(1)
(2)
(3)
(4)
(5)
Differential
VCM = 0V
3.5 || 0.5
MΩ || pF
typ
C
Common-Mode
VCM = 0V
170 || 0.8
MΩ || pF
typ
C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C tested specifications.
Junction temperature = ambient at low temperature limit; junction temperature = ambient +4°C at high temperature limit for over
temperature specifications.
Current is considered positive out-of-node. VCM is the input common-mode voltage.
Tested < 3dB below minimum specified CMRR at ±CMIR limits
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SBOS373 – JUNE 2007
ELECTRICAL CHARACTERISTICS: VS = 5V (continued)
At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted.
OPA2889ID, IDGS
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
CONDITIONS
+25°C
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
UNITS
MIN/
MAX
TEST
LEVEL (1)
OUTPUT
Output Voltage Swing
Output Current, Sourcing, Sinking
Peak Output Current
Closed-Loop Output Impedance
DISABLE (MSOP-10 ONLY)
Power-Down Supply Current (+VS)
No load
±4.0
±3.9
3.8
3.7
V
min
A
RL = 100Ω
±3.3
±3.0
2.95
2.85
V
min
A
±28
25
22
VO = 0V
±40
mA
min
A
Output shorted to ground
±60
mA
typ
C
G = +2V/V, f = 100kHz
0.04
Ω
typ
C
μA
max
A
μs
typ
C
Disable LOW
VDIS = 0, Both channels
36
VIN = 1VDC
70
Enable Time
VIN = 1VDC
200
ns
typ
C
Off Isolation
G = +2V/V, f = 5MHz
70
dB
typ
C
4
pF
typ
C
Disable Time
Output Capacitance in Disable
50
53
55
Enable Voltage
3.3
3.4
3.5
3.55
V
min
A
Disable Voltage
1.2
1.0
0.9
0.85
V
max
A
15
25
30
35
μA
max
A
V
typ
C
V
typ
C
Control Pin Input Bias Current (VDIS)
VDIS = 0V, Each channel
POWER SUPPLY
±5
Specified Operating Voltage
Minimum Operating Voltage
1.3
Maximum Operating Voltage
±6.0
6.0
6.0
V
max
A
Maximum Quiescent Current
VS = ±5V, Both channels
0.92
1
1.05
1.1
mA
max
A
Minimum Quiescent Current
VS = ±5V, Both channels
0.92
0.8
0.75
0.7
mA
min
A
+VS = 4.5V to 5.5V
64
62
61
60
dB
min
A
–VS = -4.5V to -5.5V
74
72
71
70
dB
min
A
–40 to +85
°C
typ
C
C
Power-Supply Rejection (+PSRR)
Ratio
(–PSRR)
THERMAL CHARACTERISTICS
Specified Operating Range
D and DGS Packages
Thermal Resistance, θJA
4
Junction-to-ambient
D
SO-8
100
°C/W
typ
DGS
MSOP-10
135
°C/W
typ
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OPA2889
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SBOS373 – JUNE 2007
ELECTRICAL CHARACTERISTICS: VS = +5V
At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted.
OPA2889ID, IDGS
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
+25°C (2)
0°C to
+70°C (3)
–40°C to
+85°C (3)
50
30
26
22
G = +10V/V, VO = 100mVPP
7
5.5
4.5
G > +20V/V
70
55
45
G = +2V/V, VO = 100mVPP
14
CONDITIONS
+25°C
G = +1V/V, VO = 100mVPP, RF = 0Ω
100
G = +2V/V, VO = 100mVPP
MIN/
MAX
TEST
LEVEL (1)
MHz
typ
C
MHz
min
B
4
MHz
min
B
40
MHz
min
B
MHz
typ
C
UNITS
AC PERFORMANCE
Small-Signal Bandwidth
Gain Bandwidth Product
Bandwidth for 0.1dB Flatness
Peaking at a Gain of +1V/V
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Settling Time to 0.02%
VO < 100mVPP , RF =0 Ω
1
dB
typ
C
G = +2V/V, VO = 2VPP
60
MHz
typ
C
G = +2V/V, VO = 2V Step
200
V/μs
min
B
0.2V Step
6.5
ns
typ
C
G = +1V/V, VO = 2V Step
38
ns
typ
C
27
ns
typ
C
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
125
110
100
G = +2V/V, f = 1MHz, VO = 2VPP
RL = 200Ω
–71
–61
–58
–56
dBc
max
B
RL ≥ 500Ω
–76
–69
–64
–61
dBc
max
B
RL = 200Ω
–76
–70
–66
–64
dBc
max
B
RL ≥ 500Ω
–76
–74
–69
–66
dBc
max
B
Input Voltage Noise
f > 100kHz
8.5
10.5
12
12.5
nV/√Hz
max
B
Input Current Noise
f > 100kHz
0.7
1
1.1
1.2
pA/√Hz
max
B
Differential Gain
G = +2V/V, VO = 1.4VPP, RL = 150Ω
0.06
%
typ
C
Differential Phase
G = +2V/V, VO = 1.4VPP, RL = 150Ω
0.04
°
typ
C
f = 5MHz, Input-referred
–85
dB
typ
C
Channel-to-Channel Crosstalk
DC PERFORMANCE (4)
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Input Bias Current Drift
Input Offset Current
Average Input Offset Current
Drift
VO = 0V, RL = 100Ω
64
58
56
55
dB
min
A
VCM = 0V
±1.5
5
5.9
6.3
mV
max
A
20
20
μV/°C
max
B
890
930
nA
max
A
2
2
nA/°C
max
B
275
285
nA
max
A
0.5
0.5
nA/°C
max
B
VCM = 0V
VCM = 0V
±150
±800
VCM = 0V
VCM = 0V
±50
250
VCM = 0V
INPUT
Most Positive Input Voltage
4
3.9
3.8
3.75
V
min
A
Least Positive Input Voltage
1
1.1
1.2
1.25
V
max
A
VCM = 0V, Input-referred
68
58
57
56
dB
min
A
Differential
VCM = 0V
3.5 || 0.5
MΩ || pF
typ
C
Common-Mode
VCM = 0V
170 || 0.8
MΩ || pF
typ
C
Common-Mode Rejection Ratio
(CMRR)
Input Impedance
(1)
(2)
(3)
(4)
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Junction temperature = ambient for +25°C tested specifications.
Junction temperature = ambient at low temperature limit; junction temperature = ambient +4°C at high temperature limit for over
temperature specifications.
Current is considered positive out-of-node. VCM is the input common-mode voltage.
Submit Documentation Feedback
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OPA2889
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SBOS373 – JUNE 2007
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25C, RF = 750Ω, G = +2V/V, and RL = 100Ω, unless otherwise noted.
OPA2889ID, IDGS
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
+25°C
+25°C (2)
0°C to
+70°C (3)
No load
4
3.9
RL = 100Ω
3.85
3.7
CONDITIONS
–40°C to
+85°C (3)
UNITS
MIN/
MAX
TEST
LEVEL (1)
3.8
3.7
V
min
A
3.6
3.55
V
min
A
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Output Current, Sourcing, Sinking
Peak Output Current
Closed-Loop Output Impedance
DISABLE (MSOP-10 ONLY)
Power-Down Supply Current (+VS)
No Load
1
1.1
1.2
1.3
V
max
A
RL = 100Ω
1.15
1.3
1.4
1.45
V
max
A
VO = 0V
±35
±24
21
18
mA
min
A
Output shorted to ground
±50
mA
typ
C
G = +2V/V, f = 100kHz
0.04
Ω
typ
C
μA
max
A
μs
typ
C
Disable LOW
VDIS = 0, both channels
36
VIN = 1VDC
70
Enable Time
VIN = 1VDC
200
ns
typ
C
Off Isolation
G = +2V/V, f = 5MHz
70
dB
typ
C
4
pF
typ
C
Disable Time
Output Capacitance in Disable
50
53
55
Enable Voltage
3.3
3.4
3.5
3.55
V
min
A
Disable Voltage
1.2
1.0
0.9
0.85
V
max
A
15
25
30
35
μA
max
A
V
typ
C
V
typ
C
Control Pin Input Bias Current (VDIS)
VDIS = 0V, Each channel
POWER SUPPLY
Specified Operating Voltage
+5
Minimum Operating Voltage
+2.6
Maximum Operating Voltage
+12
+12
+12
V
max
A
Maximum Quiescent Current
VS = +5V, Both channels
0.85
0.95
1.0
1.05
mA
max
A
Minimum Quiescent Current
VS = +5V, Both channels
0.85
0.75
0.7
0.65
mA
min
A
+VS = 4.5V to 5.5V
60
dB
typ
C
–40 to +85
°C
typ
C
Power-Supply Rejection (+PSRR)
Ratio
THERMAL CHARACTERISTICS
Specified Operating Range
D and DGS Packages
Thermal Resistance, θJA
6
Junction-to-ambient
D
SO-8
100
°C/W
typ
C
DGS
MSOP-10
135
°C/W
typ
C
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SBOS373 – JUNE 2007
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 100Ω, unless otherwise noted. See Figure 50.
SMALL-SIGNAL FREQUENCY RESPONSE
3
G = +1V/V
R F = 0W
0
VO = 1VPP
6
-3
3
G = +10V/V
Gain (dB)
Normalized Gain (dB)
LARGE-SIGNAL FREQUENCY RESPONSE
9
-6
-9
G = +5V/V
VO = 0.5VPP
0
VO = 2VPP
-3
-12
VO = 4VPP
-6
-15
G = +2V/V
VO = 0.1VPP
-18
100k
-9
10M
1M
100M
RL = 100W
G = +2V/V
10
1
300M
Figure 1.
LARGE-SIGNAL PULSE RESPONSE
1.5
VO = 200mVPP
G = +2V/V
VO = 2VPP
G = +2V/V
1.0
Output Voltage (V)
Output Voltage (mV)
100
50
0
-50
-100
0.5
0
-0.5
-1.0
-150
-1.5
Time (10ns/div)
Time (10ns/div)
Figure 3.
Figure 4.
VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE
-dP
0.45
0.40
0.40
0.35
0.35
0.30
+dP
0.25
0.30
-dG
0.25
0.20
0.20
0.15
0.15
+dG
0.10
0.10
0.05
0.05
0
0
3
2
Video Loads
-40
4
Input-Referred
-50
Crosstalk (dB)
Differential Gain (%)
0.45
CHANNEL-TO-CHANNEL CROSSTALK
0.50
Differential Phase (°)
0.50
1
200
Figure 2.
SMALL-SIGNAL PULSE RESPONSE
150
100
Frequency (MHz)
Frequency (Hz)
-60
-70
-80
-90
1M
10M
100M
1G
Frequency (Hz)
Figure 5.
Figure 6.
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SBOS373 – JUNE 2007
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 2VPP
f = 1MHz
G = +2V/V
-70
1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
-70
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-65
-75
2nd Harmonic
-80
3rd Harmonic
-85
VO = 2VPP
RL = 200W
G = +2V/V
-72
-74
-76
2nd Harmonic
-78
-80
3rd Harmonic
-82
-90
-84
100
1k
Load Resistance (W)
5
6
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
-70
2nd Harmonic
-90
3rd Harmonic
12
RL = 200W
f = 1MHz
G = +2V/V
-60
-65
-70
-75
2nd Harmonic
-80
3rd Harmonic
-90
-110
0.1
1
0.1
10
Output Voltage Swing (VPP)
Figure 9.
Figure 10.
HARMONIC DISTORTION vs INVERTING GAIN
-60
Harmonic Distortion (dBc)
VO = 2VPP
RL = 200W
f = 1MHz
-70
10
1
Frequency (MHz)
HARMONIC DISTORTION vs NONINVERTING GAIN
-65
Harmonic Distortion (dBc)
11
-85
-100
2nd Harmonic
-75
3rd Harmonic
-80
-85
VO = 2VPP
RL = 200W
f = 1MHz
-65
-70
2nd Harmonic
3rd Harmonic
-75
-80
-85
-90
1
Gain (V/V)
10
1
Figure 11.
8
10
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-55
VO = 2VPP
RL = 200W
G = +2V/V
-80
9
Figure 8.
HARMONIC DISTORTION vs FREQUENCY
-50
8
Supply Voltage (V)
Figure 7.
-40
7
Gain (-V/V)
Figure 12.
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LOW-FREQUENCY INVERTING HARMONIC DISTORTION
-40
RL = 500W
VO = 2VPP
G = -1V/V
-90
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
5MHz
-50
Spurious Point (dBc)
Harmonic Distortion (dBc)
-85
-95
-100
2nd Harmonic
-105
-110
3rd Harmonic
-115
-60
-70
1MHz
-80
500kHz
-90
-120
Load Power at Matched 50W Load
-100
10k
1k
100k
1M
-8
-6
-4
0
-2
2
Single-Tone Load Power (dBm)
Figure 13.
Figure 14.
RECOMMENDED RS vs CAPACITIVE LOAD
8
FREQUENCY RESPONSE vs CAPACITIVE LOAD
100
9
Gain to Capacitive Load (dB)
VIN
RS (W)
6
4
Frequency (Hz)
10
1
1/2
OPA2889
6
RS
VOUT
CL
1kW
(1)
750W
3
NOTE: (1) 1kW is optional.
750W
0
-3
CL = 10pF
-6
CL = 22pF
CL = 47pF
-9
CL = 100pF
-12
-15
10
1
100
1000
0
20
40
60
80
100
120
140
160
180
Frequency (MHz)
Capacitive Load (pF)
Figure 15.
Figure 16.
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
INPUT VOLTAGE AND CURRENT NOISE
80
100
-PSRR
+PSRR
60
Voltage Noise (nV/ÖHz)
Current Noise (pA/ÖHz)
CMRR and PSRR (dB)
70
CMRR
50
40
30
20
Input Voltage Noise (8.4nV/ÖHz)
10
1
Input Current Noise (0.7pA/ÖHz)
10
0
0.1
1k
10k
100k
1M
10M
100M
100
Frequency (Hz)
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 17.
Figure 18.
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SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
0.85
Output Current, Sourcing
40
0.80
Output Current, Sinking
0.75
30
0.70
25
0.65
20
-25
0
25
50
75
100
180
2.0
1.5
108
Input Offset Current (IOS)
1.0
72
36
0
125
-50
-25
Ambient Temperature (°C)
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 19.
Figure 20.
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
NONINVERTING OVERDRIVE RECOVERY
6
8
4
6
2
4
-2
3
2
1
0
-1
Output Voltage (1V/div)
0
Output Voltage (V)
VDIS (2V/div)
144
Input Offset
Voltage (VOS)
0.5
0.60
-50
2.5
4
RL = 100W
G = +2V/V
3
2
Output Voltage
Left Scale
2
1
0
0
Input Voltage
Right Scale
-2
-1
-4
-2
-6
-3
-8
Input Voltage (V)
35
Input Offset Voltage (mV)
0.90
45
216
Input Bias Current (IB)
0.95
Quiescent Current (IQ)
50
Output Current (mA)
3.0
Supply Current (mA)
55
TYPICAL DC DRIFT OVER TEMPERATURE
1.00
Input Bias and Offset Current (nA)
60
-4
Time (10ns/div)
Time (5ns/div)
Figure 21.
Figure 22.
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
OPEN-LOOP GAIN AND PHASE
100
120
0
1/2
OPA2889
100
ZO
750W
1
750W
0.1
0.01
80
-30
60
-90
40
-120
20
-150
0
-180
-20
0.001
1k
10k
100k
1M
Frequency (Hz)
10M
100M
-210
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 23.
10
-60
Open-Loop Gain
Figure 24.
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1G
Open-Loop Phase (°)
374W
10
Open-Loop Gain (dB)
Output Impedance (W)
Open-Loop Phase
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DISABLE FEEDTHROUGH
-70
COMMON-MODE AND DIFFERENTIAL INPUT IMPEDANCE
1G
Input-Referred
Common-Mode Input
-75
100M
Input Impedance (W)
Feedthrough (dB)
-80
-85
-90
-95
-100
-105
10M
1M
Differential Input
100k
10k
-110
-115
1
10
100
1k
100
1k
10k
100k
Frequency (MHz)
Frequency (Hz)
Figure 25.
Figure 26.
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10M
100M
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TYPICAL CHARACTERISTICS: VS = ±5V, Differential
At TA = +25°C, Differential Gain = +2V/V, and RL = 200Ω, unless otherwise noted. See Figure 52 and Figure 53.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
3
9
GD = +1V/V
GD = +2V/V
-3
-6
GD = +5V/V
-9
GD = +10V/V
-12
-15
-18
6
Normalized Gain (dB)
Normalized Gain (dB)
0
0
14VPP
-3
-6
RF = 750W
RL = 200W
See Figure 53
-9
10
1
3
100
RL = 200W
GD = +2V/V
See Figure 53
0
200
5VPP and
8VPP
20
40
Frequency (MHz)
60
Figure 27.
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
3rd Harmonic
2nd Harmonic
-85
-95
VO = 4VPP
RL = 200W
GD = +2V/V
-40
-80
-90
-50
-80
2nd Harmonic
-90
-100
-110
1k
See Figure 53
0.1
Load Resistance (W)
1
Frequency (MHz)
Figure 29.
Figure 30.
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-70
3rd Harmonic
-75
-80
-90
See Figure 53
0.1
RL_DIFF = 1kW
GD = -1V/V
VO = 4VPP
-80
-100
-110
-120
2nd Harmonic
See Figure 52
-140
1
Output Voltage (VPP)
10
1
10
100
Frequency (kHz)
Figure 31.
12
3rd Harmonic
-90
-130
2nd Harmonic
10
DIFFERENTIAL DISTORTION vs FREQUENCY
-70
RL = 200W
f = 1MHz
GD = +2V/V
-85
3rd Harmonic
-70
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
-65
140
-60
See Figure 53
100
-60
120
DIFFERENTIAL DISTORTION vs FREQUENCY
-30
VO = 4VPP
f = 1MHZ
GD = +2V/V
100
Figure 28.
-70
-75
80
Frequency (MHz)
Figure 32.
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 100Ω, unless otherwise noted. See Figure 51.
NONINVERTING SMALL-SIGNAL FREQUENCY
RESPONSE
3
NONINVERTING LARGE-SIGNAL FREQUENCY
RESPONSE
9
G = +1V/V, RF = 0W
VO = 1VPP
6
-3
3
Gain (dB)
Normalized Gain (dB)
0
-6
G = +2V/V
-9
G = +5V/V
VO = 2VPP
-3
-12
VO = 3VPP
G = +10V/V
-6
-15
VO = 0.1VPP
-18
100k
VO = 0.5VPP
0
-9
10M
1M
100M 200M
RL = 100W
G = +2V/V
10
1
Frequency (Hz)
Figure 33.
LARGE-SIGNAL PULSE RESPONSE
4.0
VO = 0.2VPP
G = +2V/V
Large Signal Output Voltage (V)
Small Signal Output Voltage (V)
2.60
2.55
2.50
2.45
2.40
2.35
VO = 2VPP
G = +2V/V
3.5
3.0
2.5
2.0
1.5
1.0
Time (10ns/div)
Time (10ns/div)
Figure 35.
Figure 36.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
100
9
Gain to Capacitive Load (dB)
RS (W)
200
Figure 34.
SMALL-SIGNAL PULSE RESPONSE
2.65
100
Frequency (MHz)
10
6
CL = 10pF
3
CL = 100pF
CL = 47pF
-3
-6
VIN
-9
1/2
OPA2889
RS
VOUT
CL
1kW
(1)
750W
-12
1
CL = 22pF
0
NOTE: (1) 1kW is optional.
750W
-15
1
10
100
1000
0
Capacitive Load (pF)
20
40
60
80
100
120
140
Frequency (MHz)
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 100Ω, unless otherwise noted. See Figure 51.
HARMONIC DISTORTION vs LOAD RESISTANCE
5.5
4.0
4.5
3.5
3.5
3.0
Output Voltage
Left Scale
2.5
2.5
Input Voltage
Right Scale
1.5
2.0
0.5
1.5
-0.5
1.0
-1.5
-65
Harmonic Distortion (dBc)
4.5
Input Voltage (V)
Output Voltage (V)
NONINVERTING OVERDRIVE RECOVERY
6.5
0.5
VO = 2VPP
f = 1MHz
G = +2V/V
-70
2nd Harmonic
-75
3rd Harmonic
-80
-85
100
Time (10ns/div)
Figure 39.
Figure 40.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-60
VO = 2VPP
RL = 200W to VS/2
G = +2V/V
3rd Harmonic
-50
-60
2nd Harmonic
-70
-80
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-30
-40
-90
0.1
-70
2nd Harmonic
-75
3rd Harmonic
-80
-85
10
1
0.1
10
1
Frequency (MHz)
Output Voltage Swing (VPP)
Figure 41.
Figure 42.
HARMONIC DISTORTION vs NONINVERTING GAIN
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-60
-30
-65
-40
Load Power of Matched 50W Load
5MHz
Spurious Point (dBc)
Harmonic Distortion (dBc)
RL = 200W to VS/2
f = 1MHz
G = +2V/V
-65
-90
-100
2nd Harmonic
-70
3rd Harmonic
-75
-80
-85
-50
-60
-70
1MHz
-80
500kHz
-90
-90
-100
0.1
14
1k
Load Resistance (W)
10
-8
-7
-6
-5
-4
-3
-2
-1
Gain (V/V)
Single-Tone Load Power (dBm)
Figure 43.
Figure 44.
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TYPICAL CHARACTERISTICS: VS = +5V, Differential
At TA = +25°C, Differential Gain = +2V/V, and RL = 200Ω, unless otherwise noted. See Figure 52.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
9
6
0
6
GD = +2V/V
-3
GD = +5V/V
-6
-9
GD = +10V/V
-12
VO = 4VPP
0
-3
-9
10
1
3
-6
RF = 750W
RL = 200W
-15
100
0
200
10
20
30
40
Figure 45.
70
80
90
100 110
DIFFERENTIAL DISTORTION vs FREQUENCY
-30
VO = 4VPP
f = 1MHz
GD = +2V/V
RL = 200W
VO = 4VPP
GD = +2V/V
Harmonic Distortion (dBc)
-40
-70
3rd Harmonic
-75
-80
-50
3rd Harmonic
-60
-70
-80
2nd Harmonic
-90
-100
2nd Harmonic
-110
-85
100
0.1
1k
Load Resistance (W)
1
10
Frequency (MHz)
Figure 47.
Figure 48.
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
-60
-65
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
60
Figure 46.
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
-65
50
Frequency (MHz)
Frequency (MHz)
-60
RF = 750W
RL = 200W
GD = +2V/V
VO = 1VPP
GD = +1V/V
RF = 0W
Normalized Gain (dB)
Normalized Gain (dB)
3
-70
RL = 400W
f = 1MHz
GD = +2V/V
3rd Harmonic
-75
-80
-85
2nd Harmonic
-90
-95
-100
0.1
1
10
Output Voltage (VPP)
Figure 49.
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APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
+5V
+VS
0.1mF
The OPA2889 provides an exceptional combination
of high output power capability in a dual, wideband,
unity-gain stable, voltage-feedback op amp using a
new high slew rate input stage. Typical differential
input stages used for voltage-feedback op amps are
designed to steer a fixed-bias current to the
compensation capacitor, setting a limit to the
achievable slew rate. The OPA2889 uses a new
input stage that places the transconductance
element between two input buffers, using the output
currents as the forward signal. As the error voltage
increases across the two inputs, an increasing
current is delivered to the compensation capacitor.
This configuration provides high slew rate (250V/μs)
while consuming very low quiescent current
(460μA/ch). This exceptional full-power performance
comes at the price of a slightly higher input noise
voltage than alternative architectures. The 8.4nV/√Hz
input voltage noise for the OPA2889 is exceptionally
low for this type of input stage.
Figure 50 shows the dc-coupled, gain of +2V/V, dual
power-supply circuit configuration used as the basis
of the ±5V Electrical Characteristics and ±5V Typical
Chararacteristics. This illustration is for one channel;
the other channel is connected similarly. For test
purposes, the input impedance is set to 50Ω with a
resistor to ground and the output impedance is set to
100Ω. Voltage swings reported in the Electrical
Characteristics are taken directly at the input and
output pins, while output powers (dBm) are at the
matched 50Ω load. For the circuit of Figure 50, the
total effective load will be 100Ω || 1.5kΩ. The disable
control line (MSOP-10 package only) is typically left
open for normal amplifier operation. Two optional
components are included in Figure 50. An additional
resistor (350Ω) is included in series with the
noninverting input. Combined with the 25Ω dc source
resistance looking back towards the signal generator,
this resistor gives an input bias current cancelling
resistance that matches the 375Ω source resistance
seen at the inverting input (see the DC Accuracy and
Offset Control section). In addition to the usual
power-supply decoupling capacitors to ground, a
0.1μF capacitor is included between the two
power-supply pins. In practical printed circuit board
(PCB) layouts, this optional-added capacitor typically
improves the 2nd-harmonic distortion performance
by 3dB to 6dB.
16
50W Source
VI
6.8mF
+
350W
DIS
VD
50W
VO
1/2
OPA2889
0.1mF
50W
50W Load
RF
750W
RG
750W
+
6.8mF
0.1mF
-VS
-5V
Figure 50. DC-Coupled, G = +2, Bipolar Supply,
Specification and Test Circuit
Figure 51 illustrates the ac-coupled, gain of +2V/V,
single-supply circuit configuration used as the basis
of the +5V Electrical Characteristics and +5V Typical
Chararacteristics. Though not a rail-to-rail design, the
OPA2889 requires minimal input and output voltage
headroom compared to other very wideband
voltage-feedback op amps. It delivers a 2.8VPP
output swing on a single +5V supply with > 50MHz
bandwidth. The key requirement of broadband
single-supply operation is to maintain input and
output signal swings within the usable voltage ranges
at both the input and the output. The circuit of
Figure 51 establishes an input midpoint bias using a
simple resistive divider from the +5V supply (two
698Ω resistors). Separate bias networks would be
required at each input. The input signal is then
ac-coupled into the midpoint voltage bias. The input
voltage can swing to within 1.1V of either supply pin,
giving a 2VPP input signal range centered between
the supply pins. The input impedance matching
resistor (59Ω) used for testing is adjusted to give a
50Ω input load when the parallel combination of the
biasing divider network is included.
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DIFFERENTIAL OPERATION
+5V
+VS
0.1mF
+
Figure 52 shows the inverting input differential
configuration used as the basis for the ±5V and +5V
Typical Characteristics. This circuit offers a
combination of excellent distortion with low quiescent
current.
6.8mF
698W
0.1mF
50W
DIS
VD
VI
698W
59W
1/2
OPA2889
VO
200W
VS/2
RF
750W
The other possibility is using the OPA2889 in a
differential configuration as shown in Figure 53. This
figure illustrates the differential noninverting input
configuration which has the advantage of showing a
high input impedance to any prior stage.
+5V
GD =
RG
750W
RF
RG
1/2
OPA2889
0.1mF
Figure 51. DC-Coupled, G = +2, Single-Supply,
Specification and Test Circuit
Again, an additional resistor (50Ω in this case) is
included directly in series with the noninverting input.
This minimum recommended value provides part of
the dc source resistance matching for the
noninverting input bias current. It is also used to form
a simple parasitic pole to roll off the frequency
response at very high frequencies ( > 500MHz) using
the input parasitic capacitance. The gain resistor
(RG) is ac-coupled, giving the circuit a dc gain of +1,
which puts the input dc bias voltage (2.5V) on the
output as well. The output voltage can swing to
within 1V of either supply pin while delivering >
40mA output current.
VIN
RG
RF
RG
RF
RL
VOUT
1/2
OPA2889
-5V
Figure 52. Differential Inverting Specification and
Test Circuit
+5V
GD = 1 +
2RF
RG
1/2
OPA2889
RF
VIN
RG
RL
RF
1/2
OPA2889
-5V
Figure 53. Differential Noninverting Specification
and Test Circuit
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HIGH-PERFORMANCE DAC
TRANSIMPEDANCE AMPLIFIER
WIDEBAND VIDEO MULTIPLEXING
One common application for video speed amplifiers
that include a disable pin is to wire multiple amplifier
outputs together, then select one of several possible
video inputs to source onto a single line. This simple
wired-OR video multiplexer can be easily
implemented using the OP2889IDGS (MSOP-10
package only), as shown in Figure 55.
High-frequency DDS Digital-to-Analog Converters
(DACs) require a low distortion output amplifier to
retain their SFDR performance into real-world loads.
Figure 54 shows a single-ended output drive
implementation. The diagram shows the signal
output current(s) connected into the virtual ground
summing junction(s) of the OPA2889, which is set up
as a transimpedance stage or I-V converter. If the
DAC requires that its outputs terminate to a
compliance voltage other than ground for operation,
the appropriate voltage level may be applied to the
noninverting input of the OPA2889. The dc gain for
this circuit is equal to RF. At high frequencies, the
DAC output capacitance (CD in Figure 54) produces
a zero in the noise gain for the OPA2889 that may
cause peaking in the closed-loop frequency
response. CF is added across RF to compensate for
this noise gain peaking. To achieve a flat
transimpedance frequency response, the pole in
each feedback network should be set to:
1
=
2pRFCF
50W
1/2
OPA2889
High-Speed
DAC
RF1
CF1
IO
CD1
RF2
CF2
-IO
GBP
4pRFCD
VO = IO RF
CD2
1/2
OPA2889
(1)
-VO = -IO RF
which gives a cutoff frequency f–3dB of approximately:
f-3dB =
50W
GBP
2pRFCD
GBP ® Gain Bandwidth
Product (Hz) for the OPA2889
(2)
Figure 54. DAC Transimpedance Amplifier
+5V
2kW
VDIS
+5V
146W
1/2
OPA2889
Video 1
75W
340W
DISA
402W
-5V
82.5W
75W Cable
340W
402W
RG-59
75W Load
+5V
82.5W
146W
1/2
OPA2889
DISB
Video 2
75W
2kW
-5V
Figure 55. 2-Channel Video Multiplexer (SO-14 package only)
18
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Typically, channel switching is performed either on
sync or retrace time in the video signal. The two
inputs are approximately equal at this point. The
make-before-break disable characteristic of the
OPA2889 ensures that there is always one amplifier
controlling the line when using a wired-OR circuit like
that shown in Figure 55. Because both inputs may
be on for a short period during the transition between
channels, the outputs are combined through the
output impedance matching resistors (82.5Ω in this
case). When one channel is disabled, its feedback
network forms part of the output impedance and
slightly attenuates the signal in getting out onto the
cable. The gain and output matching resistor are
slightly increased to get a signal gain of +1V/V at the
matched load and provide a 75Ω output impedance
to the cable. The video multiplexer connection (see
Figure 55) also ensures that the maximum
differential voltage across the inputs of the
unselected channel does not exceed the rated ±1.2V
maximum for standard video signal levels.
See the Disable Operation section for the turn-on
and turn-off switching glitches using a 0V input for a
single channel is typically less than ±50mV. Where
two outputs are switched (see Figure 55), the output
line is always under the control of one amplifier or
the other as a result of the make-before-break
disable timing. In this case, the switching glitches for
two 0V inputs drops to < 20mV.
HIGH-SPEED DELAY CIRCUIT
The OPA2889 makes an ideal amplifier for a variety
of active filter designs. Figure 56 illustrates a circuit
that uses the two amplifiers within the dual OPA2889
to design a 2-stage analog delay circuit. For
simplicity, the circuit uses a dual-supply (±5V)
operation, but it can also be modified to operate on a
signal supply. The input to the first filter stage is
driven by the OPA890 as a gain of +2V/V to isolate
the signal input from the filter network.
Each of the two filter stages is a 1st-order filter with a
voltage gain of +1V/V. The delay time through one
filter is given by Equation 3.
tGR0 = 2RC
(3)
For a more accurate analysis of the circuit, consider
the group delay for the amplifiers. For example, in
the case of the OPA2889, the group delay in the
bandwidth from 1MHz to 100MHz is approximately
1.0ns. To account for this delay, modify the transfer
function, which now comes out to be:
tGR = 2 (2RC + TD)
(4)
with TD = (1/360) × (dφ/df) = delay of the op amp
itself. The values of resistors RF and RG should be
equal and low to avoid parasitic effects. If the
all-pass filter is designed for very low delay times,
include parasitic board capacitances to calculate the
correct delay time. Simulating this application using
the PSPICE model of the OPA2889 allows this
design to be tuned to the desired performance.
C
VIN
OPA890
1/2
OPA2889
C
1/2
OPA2889
R
750W
750W
VOUT
R
RG
402W
RF
402W
RG
402W
RF
402W
Figure 56. 2-Stage, All-Pass Network
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A very versatile application for a dual operational
amplifier is the differential amplifier configuration
shown in Figure 57. With both amplifiers of the
OPA2889 connected for noninverting operation, the
circuit provides a high input impedance whereas the
gain can easily be set by just one resistor, RG. When
operated in low gains, the output swing may be
limited as a result of the common-mode input swing
limits of the amplifier itself. An interesting
modification of this circuit is to place a capacitor in
series with RG. Now the dc gain for each side is
reduced to +1V/V, whereas the ac gain still follows
the standard transfer function of G = 1 + 2RF/RG.
This might be advantageous for applications
processing only a frequency band that excludes dc
or very low frequencies. An input dc voltage resulting
from input bias currents is not amplified by the ac
gain and can be kept low. This circuit can be used as
a differential line receiver, driver, or as an interface
to a differential input ADC.
1/2
OPA2889
50W
-3
-6
-9
-12
10k
100k
1M
10M
Frequency (Hz)
LOW POWER, DC-COUPLED,
SINGLE-TO-DIFFERENTIAL DRIVER FOR
≤100kHz INPUT
VDIFF = 1 +
RF
750W
1/2
OPA2889
2RF
RG
VI - (-VI)
RO
-VI
Figure 57. High-Speed Differential Receiver
SINGLE-SUPPLY MFB DIFFERENTIAL
ACTIVE FILTER: 2MHz BUTTERWORTH
CONFIGURATION
The active filter circuit illustrated in Figure 59 can be
easily implemented using the OPA2889. In this
configuration, each amplifier of the OPA2889
operates as an integrator. For this reason, this type
of application is also called an infinite gain filter
implementation. A Butterworth filter can be
implemented using the following component ratios:
1
fO =
2´p´R´C
R1 = R2 = 0.65 ´ R
R3 = 0.375 ´ R
C1 = C
C2 = 2 ´ C
20
0
RO
RF
750W
RG
3
Figure 58. Multiple Feedback Filter Frequency
Response
50W
VI
The frequency response for a 2MHz Butterworth filter
is shown in Figure 58. One advantage for using this
type of filter is the independent setting of ωo and Q.
Q can be easily adjusted by changing the R3A, B
resistors without affecting ωo.
Gain (dB)
DIFFERENTIAL RECEIVER/DRIVER
In systems where the input is differential (see
front-page figure), the OPA2889 can be used in the
inverting configuration with an additional dc bias
applied to its positive input so as to keep the input to
the ADS8472 within its rated operating voltage
range. The dc bias can be derived from the
REF3220 or the REF3240 reference voltage ICs.
The input configuration shown on the front page of
the data sheet is capable of delivering better than
100dB SNR and –100dBc THD at an input frequency
of 200kHz. In case band-pass filters are used to filter
the input, care should be taken to ensure that the
signal swing at the input of the band-pass filter is
small, so as to minimize the distortion introduced by
the filter. In such cases, the gain of the circuit shown
on the front page of the data sheet can be increased
to keep the input to the ADS8472 large in order to
keep the SNR of the system high. Note that the gain
of the system from the positive input to the output of
the OPA2889 in such a configuration is a function of
the ac signal gain. A resistor divider can be used to
scale the output of the REF3220 or REF3240 to
reduce the voltage at the dc input to OPA2889 to
keep the voltage at the input of the converter within
its rated operating range.
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+12V
6kW
50W
VCM
1/2
OPA2889
1000pF
6kW
C1A
129pF
R3A
232W
R1A
402W
R2A
402W
C2
257pF
VIN
R2B
402W
R1B
402W
R3B
232W
50W
VOUT
C1B
129pF
1/2
OPA2889
VCM
Figure 59. Single-Supply, MFB Active Filter, 2MHz LP Butterworth
DESIGN-IN TOOLS
MACROMODELS
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA2889 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user’s guide. The summary
information for these fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING NUMBER
LITERATURE
NUMBER
OPA2889ID
SO-8
DEM-OPA-SO-2A
SBOU003A
OPA2889IDGS
MSOP-10
DEM-OPA-MSOP-2B
SBOU040
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
principle is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the OPA2889 is available through
the Texas Instruments web page (www.ti.com). This
model does a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. It does not do as well in
predicting the harmonic distortion or dG/dP
characteristics. This model does not attempt to
distinguish between the package types in their
small-signal ac performance.
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA2889 product folder.
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OPERATING RECOMMENDATIONS
OPTIMIZING RESISTOR VALUES
Because the OPA2889 is a unity-gain stable,
voltage-feedback op amp, a wide range of resistor
values may be used for the feedback and gain
setting resistors. The primary limits on these values
are set by dynamic range (noise and distortion) and
parasitic capacitance considerations. For a
noninverting unity-gain follower application, the
feedback connection should be made with a direct
short. Usually, the feedback resistor value should be
between 200Ω and 1.5kΩ. Below 200Ω, the
feedback network presents additional output loading
which can degrade the harmonic distortion
performance of the OPA2889. Above 1.5kΩ, the
typical parasitic capacitance (approximately 0.2pF)
across the feedback resistor can cause unintentional
band-limiting in the amplifier response.
A good rule of thumb is to target the parallel
combination of RF and RG (see Figure 50) to be less
than approximately 400Ω. The combined impedance
RF || RG interacts with the inverting input
capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward
response. Assuming a 2pF total parasitic on the
inverting node, holding RF || RG < 400Ω keeps this
pole above 160MHz. By itself, this constraint implies
that the feedback resistor RF can increase to several
kΩ at high gains. This increase in resistor size is
acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out
of the frequency range of interest.
BANDWIDTH vs GAIN: NONINVERTING
OPERATION
Voltage-feedback op amps exhibit decreasing
closed-loop bandwidth as the signal gain increases.
In theory, this relationship is described by the Gain
Bandwidth Product (GBP) shown in the Electrical
Characteristics. Ideally, dividing GBP by the
noninverting signal gain (also called the Noise Gain,
or NG) predicts the closed-loop bandwidth. In
practice, this principle only holds true when the
phase margin approaches 90°, as it does in high
gain configurations. At low gains (increased
feedback factors), most amplifiers exhibit a more
complex response with lower phase margin. The
OPA2889 is compensated to give a slightly peaked
response in a noninverting gain of 2V/V (see
Figure 50). This compensation results in a typical
gain of +2V/V bandwidth of 60MHz, far exceeding
that predicted by dividing the 75MHz GBP by 2.
Increasing the gain causes the phase margin to
approach 90° and the bandwidth to more closely
22
approach the predicted value of (GBP/NG). At a gain
of +10, the 8MHz bandwidth shown in the Electrical
Characteristics agrees closely with that predicted
using the simple formula and the typical GBP of
75MHz.
The frequency response in a gain of +2V/V may be
modified to achieve exceptional flatness simply by
increasing the noise gain to 2.5V/V. One way to
modify the response without affecting the +2V/V
signal gain, is to add a 750Ω resistor across the two
inputs, as shown in the circuit of Figure 50. A similar
technique may be used to reduce peaking in
unity-gain (voltage follower) applications. For
example, by using a 750Ω feedback resistor along
with a 750Ω resistor across the two op amp inputs,
the voltage follower response is similar to the gain of
+2V/V response of Figure 51. Reducing the value of
the resistor across the op amp inputs further limits
the frequency response due to increased noise gain.
The OPA2889 exhibits minimal bandwidth reduction
going to single-supply (+5V) operation as compared
with ±5V. This behavior occurs because the internal
bias control circuitry retains nearly constant
quiescent current as the total supply voltage between
the supply pins is changed.
INVERTING AMPLIFIER OPERATION
The OPA2889 is a general-purpose, wideband,
voltage-feedback op amp; therefore, all of the
familiar op amp application circuits are available to
the designer. Inverting operation is one of the more
common
requirements
and
offers
several
performance benefits. See Figure 60 for a typical
inverting configuration where the I/O impedances
and signal gain from Figure 50 are retained in an
inverting circuit configuration.
In the inverting configuration, three key design
considerations must be noted. The first is that the
gain resistor (RG) becomes part of the signal channel
input impedance. If input impedance matching is
desired (which is beneficial whenever the signal is
coupled through a cable, twisted-pair, long PCB
trace, or other transmission line conductor), RG may
be set equal to the required termination value and RF
adjusted to give the desired gain. This consideration
is the simplest approach and results in optimum
bandwidth and noise performance. However, at low
inverting gains, the resultant feedback resistor value
can present a significant load to the amplifier output.
For an inverting gain of –2V/V, setting RG to 50Ω for
input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This approach
has the interesting advantage that the noise gain
becomes equal to 2V/V for a 50Ω source
impedance—the same as the noninverting circuits
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considered in Figure 60 The amplifier output,
however, now sees the 100Ω feedback resistor in
parallel with the external load. In general, the
feedback resistor should be limited to the 200Ω to
1.5kΩ range. In this case, it is preferable to increase
both the RF and RG values (see Figure 60), and then
achieve the input matching impedance with a third
resistor (RM) to ground. The total input impedance
becomes the parallel combination of RG and RM.
+5V
+
0.1mF
6.8mF
0.1mF
RB
261W
50W
Source
VO
1/2
OPA2889
RG
375W
RO
50W
50W Load
VO
= -2
VI
RF
750W
VI
RM
57.6W
0.1mF
+
6.8mF
-5V
Figure 60. Gain of –2V/V Example Circuit
The second major consideration, touched on in the
previous paragraph, is that the signal source
impedance becomes part of the noise gain equation
and influences the bandwidth. For the example in
Figure 60, the RM value combined in parallel with the
external 50Ω source impedance yields an effective
driving impedance of 50Ω || 57.6Ω = 26.7Ω. This
impedance is added in series with RG for calculating
the noise gain (NG). The resulting NG is 2.86V/V for
Figure 60, as opposed to only 2V/V if RM could be
eliminated as discussed above. Therefore, the
bandwidth is slightly lower for the gain of –2V/V
circuit of Figure 60 than for the gain of +2V/V circuit
of Figure 50.
The third important consideration in inverting
amplifier design is setting the bias current
cancellation resistor on the noninverting input (RB). If
this resistor is set equal to the total dc resistance
looking out of the inverting node, the output dc error,
as a result of the input bias currents, is reduced to
(Input Offset Current) × RF. If the 50Ω source
impedance is dc-coupled in Figure 60, the total
resistance to ground on the inverting input is 402Ω.
Combining this resistance in parallel with the
feedback resistor gives the RB = 261Ω used in this
example. To reduce the additional high-frequency
noise introduced by this resistor, it is sometimes
bypassed with a capacitor. As long as RB < 350Ω,
the capacitor is not required because the total noise
contribution of all other terms will be less than that of
the op amp input noise voltage. As a minimum, the
OPA2889 requires an RB value of 50Ω to damp out
parasitic-induced peaking—a direct short to ground
on the noninverting input runs the risk of a very
high-frequency instability in the input stage.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance that
may be recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier such as
the OPA2889 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the open-loop output resistance of the
amplifier is considered, this capacitive load
introduces an additional pole in the signal path that
can decrease the phase margin. Several external
solutions to this problem have been suggested.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series-isolation resistor between the
amplifier output and the capacitive load. This solution
does not eliminate the pole from the loop response,
but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the
phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The 5 Typical Chararacteristics show the
recommended RS versus capacitive load (see
Figure 15 and Figure 16) and the resulting frequency
response at the load. Parasitic capacitive loads
greater than 2pF can begin to degrade the
performance of the OPA2889. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the OPA2889 output pin (see the Board Layout
Guidelines section).
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DISTORTION PERFORMANCE
The OPA2889 provides good distortion performance
into a 200Ω load on ±5V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads and/or operating on a
single +5V supply. Generally, until the fundamental
signal reaches very high frequency or power levels,
the 2nd-harmonic dominates the distortion with a
negligible 3rd-harmonic component. Focusing then
on the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total
load includes the feedback network; in the
noninverting configuration (see Figure 50), this total
is the sum of RF + RG, while in the inverting
configuration it is just RF. Also, providing an
additional supply-decoupling capacitor (0.1μF)
between the supply pins (for bipolar operation)
improves the 2nd-order distortion slightly (3dB to
6dB).
Operating
differentially
also
lowers
2nd-harmonic distortion terms (see the plot on the
front page).
In most op amps, increasing the output voltage
swing increases harmonic distortion directly. The
output stage used in the OPA2889 actually holds the
difference between fundamental power and the 2ndand 3rd-harmonic powers relatively constant with
increasing output power until very large output
swings are required ( > 4VPP). This result also shows
up in the 2-tone, 3rd-order intermodulation spurious
(IM3) response curves. The 3rd-order spurious levels
are extremely low at low output power levels. The
output stage continues to hold them low even as the
fundamental power reaches very high levels. As the
Typical
Characteristics
show,
the
spurious
intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not
decrease significantly. For two tones centered at
1MHz, with 4dBm/tone into a matched 50Ω load (that
is, 1VPP for each tone at the load, which requires
4VPP for the overall 2-tone envelope at the output
pin), the Typical Characteristics show –73dBc
difference between the test tone powers and the
3rd-order intermodulation spurious powers. This
performance is exceptional for an amplifier with only
4.6mW of internal power dissipation.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback
op amps usually achieve the slew rate at the
expense of a higher input noise voltage. However,
the 8.4nV/√Hz input voltage noise for the OPA2889
is much lower than that of comparable amplifiers.
The input-referred voltage noise, and the two
input-referred current noise terms, combine to give
low output noise under a wide variety of operating
24
conditions. Figure 61 shows the op amp noise
analysis model with all the noise terms included. In
this model, all noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
ENI
1/2
OPA2889
RS
EO
IBN
ERS
RF
Ö4kTRS
Ö4kTRF
RG
4kT
RG
IBI
4kT = 1.6E - 20J
at +290°K
Figure 61. Op Amp Noise Analysis Model
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 5 shows the
general form for the output noise voltage using the
terms shown in Figure 61.
EO =
[E
2
2
NI
2
2
+ (IBNRS) + 4kTRS ]NG + (IBIRF) + 4kTRFNG
(5)
Dividing this expression by the noise gain (NG = (1 +
RF/RG)) gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 6.
EN =
2
NI
E
2
+ (IBNRS) + 4kTRS +
(
IBIRF
NG
)2 +
4kTRF
NG
(6)
Evaluating these two equations for the OPA2889
circuit and component values (see Figure 50) gives a
total output spot noise voltage of 18.2nV/√Hz and a
total equivalent input spot noise voltage of
9.1nV/√Hz. This total includes the noise added by
the bias current cancellation resistor (350Ω) on the
noninverting input. This total input-referred spot
noise voltage is slightly higher than the 8nV/√Hz
specification for the op amp voltage noise alone.
This result is the case as long as the impedances
appearing at each op amp input are limited to the
previously recommend maximum value of 400Ω.
Keeping both (RF || RG) and the noninverting input
source impedance less than 400Ω satisfies both
noise
and
frequency
response
flatness
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considerations. Because the resistor-induced noise is
relatively negligible, additional capacitive decoupling
across the bias current cancellation resistor (RB) for
the inverting op amp configuration of Figure 60 is not
required.
+5V
Power-supply
decoupling not shown.
0.1mF
250W
1/2
OPA2889
VO
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband
voltage-feedback op amp allows good output dc
accuracy in a wide variety of applications. The
power-supply current trim for the OPA2889 gives
even tighter control than comparable amplifiers.
Although the high-speed input stage does require
relatively low 0.75μA input bias current, the close
matching between them may be used to reduce the
output dc error caused by this current. The total
output offset voltage may be reduced by matching
the dc source resistances appearing at the two
inputs. This matching reduces the output dc error
resulting from the input bias currents to the offset
current times the feedback resistor. Evaluating the
configuration of Figure 50, and using worst-case
+25°C input offset voltage and current specifications,
gives a worst-case output offset voltage equal to:
±(NG ´ VOS(MAX)) ± (RF ´ IOS(MAX))
= ±(2 ´ 5mV) ± (750W ´ 0.75mA)
= ±10.6mV with -(NG = noninverting signal gain)
A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques eventually
reduce to adding a dc current through the feedback
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal
path frequency response. If the signal path is
intended to be noninverting, the offset control is best
applied as an inverting summing signal to avoid
interaction with the signal source. If the signal path is
intended to be inverting, applying the offset control to
the noninverting input may be considered. However,
the dc offset voltage on the summing junction sets
up a dc current back into the source that must be
considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain
and frequency response flatness. For a dc-coupled
inverting amplifier, Figure 62 shows one example of
an offset adjustment technique that has minimal
impact on the signal frequency response. In this
case, the dc offsetting current is brought into the
inverting input node through resistor values that are
much larger than the signal path resistors. This
technique ensures that the adjustment circuit has
minimal effect on the loop gain and thus, the
frequency response.
-5V
RG
375W
+5V
5kW
RF
750W
VI
20kW
±200mV Output Adjustment
10kW
0.1mF
VO
5kW
VI
=-
RF
RG
= -2
-5V
Figure 62. DC-Coupled, Inverting Gain of –2V/V,
with Offset Adjustment
DISABLE OPERATION (MSOP-10 Package
Only)
The OPA2889IDGS provides an optional disable
feature that can be used either to reduce system
power or to implement a simple channel multiplexing
operation. If the DIS control pin is left unconnected,
the OPA2889IDGS operates normally. To disable,
the control pin must be asserted LOW. Figure 63
shows a simplified internal circuit for the disable
control feature.
+VS
100kW
Q1
150kW
VDIS
4MW
IS
Control
-VS
Figure 63. Simplified Disable Control Circuit
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In normal operation, base current to Q1 is provided
through the 4MΩ resistor, while the emitter current
through the 100kΩ resistor sets up a voltage drop
that is inadequate to turn on the two diodes in the Q1
emitter. As VDIS is pulled LOW, additional current is
pulled through the 100kΩ resistor, eventually turning
on those two diodes (≈18μA). At this point, any
further current pulled out of VDIS goes through those
diodes holding the emitter-base voltage of Q1 at
approximately 0V. This current shuts off the collector
current out of Q1, turning the amplifier off. The
supply currents in the disable mode are only those
required to operate the circuit of Figure 63.
Additional circuitry ensures that turn-on time occurs
faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a
high-impedance state. If the OPA2889 is operating at
a gain of +1V/V, the device shows a very high
impedance at the output and exceptional signal
isolation. If operating at a gain greater than +1V/V,
the total feedback network resistance (RF + RG)
appears as the impedance looking back into the
output, but the circuit still shows very high forward
and reverse isolation. If configured as an inverting
amplifier, the input and output are connected through
the feedback network resistance (RF + RG) and the
isolation will be very poor as a result.
THERMAL ANALYSIS
Maximum desired junction temperature sets the
maximum allowed internal power dissipation as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by TA +
PD • θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load; for a grounded resistive load, PDL is
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, PDL = VS2/(4 ×
RL), where RL includes feedback network loading.
Note that it is the power in the output stage and not
into the load that determines internal power
dissipation.
As a worst-case example, compute the maximum TJ
using an OPA2889ID (SO-8 package) in the circuit of
Figure 50 operating at the maximum specified
ambient temperature of +85°C and with both outputs
driving a grounded 75Ω load to +2.5V.
2
PD = 10V ´ 2.5mA + 2[5 /(4 ´ (75W || 1.5kW))] = 200mW
Maximum TJ = +85°C + (200mW ´ 125°C/W) = +110°C
This absolute worst-case condition does not exceed
the specified maximum junction temperature. Actual
PDL is normally less than that considered here.
Carefully consider maximum TJ in your application.
26
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BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the OPA2889 requires
careful attention to board layout parasitics and
external component types. Recommendations that
optimize performance include:
a) Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the
power-supply pins to high-frequency 0.1μF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor (0.1μF) across the two power
supplies
(for
bipolar
operation)
improves
2nd-harmonic distortion performance. Larger (2.2μF
to 6.8μF) decoupling capacitors, effective at lower
frequencies, should also be used on the main supply
pins. These capacitors may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the printed
circuit board (PCB).
c) Careful selection and placement of external
components preserves the high-frequency
performance of the OPA2889. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal
film or carbon composition axially-leaded resistors
can also provide good high-frequency performance.
Again, keep the leads and PCB traces as short as
possible. Never use wirewound type resistors in a
high-frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series
output resistor, if any, as close as possible to the
output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Even with a low
parasitic capacitance shunting the external resistors,
excessively high resistor values can create
significant time constants that can degrade
performance. Good axial metal film or surface-mount
resistors have approximately 0.2pF in shunt with the
resistor. For resistor values > 1.5kΩ, this parasitic
capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep
resistor values as low as possible consistent with
load driving considerations. The 750Ω feedback
used in the Electrical Characteristics is a good
starting point for design. Note that a 0Ω feedback
resistor is suggested for the unity-gain follower
application.
d) Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the plots of Figure 15 and Figure 16.
Low parasitic capacitive loads (< 3pF) may not need
an RS because the OPA2889 is nominally
compensated to operate with a 2pF parasitic load.
Higher parasitic capacitive loads without an RS are
allowed as the signal gain increases (increasing the
unloaded phase margin; see Figure 24). If a long
trace is required, and the 6dB signal loss intrinsic to
a doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher
impedance environment improves distortion as
shown in the distortion versus load plots. With a
characteristic board trace impedance defined (based
on board material and trace dimensions), a matching
series resistor into the trace from the output of the
OPA2889 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and the
input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance.
e) Socketing a high-speed part like the OPA2889
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the socket
can create an extremely troublesome parasitic
network that can make it almost impossible to
achieve a smooth, stable frequency response. Best
results are obtained by soldering the OPA2889 onto
the board.
Submit Documentation Feedback
27
OPA2889
www.ti.com
SBOS373 – JUNE 2007
INPUT AND ESD PROTECTION
+VCC
The OPA2889 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD
protection diodes to the power supplies, as shown in
Figure 64.
External
Pin
-VCC
Figure 64. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA2889), current-limiting
series resistors should be added into the two inputs.
Keep these resistor values as low as possible since
high values degrade both noise performance and
frequency response.
28
Internal
Circuitry
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA2889ID
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2889IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2889IDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2889IDGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2889IDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2889IDGSTG4
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2889IDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2889IDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
4-Jul-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2889IDGSR
DGS
10
MLA
330
12
5.2
3.3
1.6
12
12
Q1
OPA2889IDGST
DGS
10
MLA
178
12
5.3
3.4
1.4
8
12
Q1
OPA2889IDR
D
8
MLA
330
12
6.4
5.2
2.1
8
12
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
OPA2889IDGSR
DGS
10
MLA
346.0
346.0
29.0
OPA2889IDGST
DGS
10
MLA
0.0
0.0
0.0
OPA2889IDR
D
8
MLA
346.0
346.0
29.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2007
Pack Materials-Page 3
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