Intersil ISL8484IU Ultra low on-resistance, 1.65v to 4.5v, single supply, dual spdt analog switch Datasheet

ISL8484
®
Data Sheet
June 14, 2007
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Dual SPDT Analog Switch
The Intersil ISL8484 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+4.5V supply. Targeted applications include battery powered
equipment that benefit from low rON (0.23Ω) and fast
switching speeds (tON = 20ns, tOFF = 15ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 10µA max of I+
current.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL8484 is offered in small form factor packages, alleviating
board space limitations.
The ISL8484 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally closed (NC) switches. This configuration can be
used as a dual 2-to-1 multiplexer. The ISL8484 is pin
compatible with the MAX4684 and MAX4685.
FN6128.3
Features
• Pin Compatible Replacement for the MAX4684 and
MAX4685
• ON-Resistance (rON )
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.23Ω
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.27Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45Ω
• rON Matching Between Channels. . . . . . . . . . . . . . . . . 0.03Ω
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.03Ω
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD). . . . . . . . . . . . . . . . <0.3μW
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
• Guaranteed Break-before-Make
• 1.8V Logic Compatible (+3V supply)
• Low I+ Current when VinH is not at the V+ Rail
• Available in 10 Ld 3x3 TDFN and 10 Ld MSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
TABLE 1. FEATURES AT A GLANCE
ISL8484
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
Number of Switches
2
SW
SPDT or 2-to-1 MUX
4.3V rON
0.23Ω
4.3V tON/tOFF
20ns/15ns
3V rON
0.27Ω
3V tON/tOFF
25ns/20ns
1.8V rON
0.45Ω
1.8V tON/tOFF
65ns/50ns
Packages
10 Ld 3x3 Thin DFN, 10 Ld MSOP
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8484
Pinout
Truth Table
(Note 1)
ISL8484
(10 LD TDFN, MSOP)
TOP VIEW
LOGIC
PIN NC1 and NC2
PIN NO1 and NO2
0
ON
OFF
1
OFF
ON
10 NO2
V+ 1
NOTE:
9 COM2
NO1 2
Pin Descriptions
8 IN2
COM1 3
IN1 4
7 NC2
NC1 5
6 GND
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
PIN
V+
NOTE:
1. Switches Shown for Logic “0” Input.
FUNCTION
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ISL8484IR
484
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL8484IR-T
484
-40 to +85
10 Ld 3x3 TDFN Tape and Reel
L10.3x3A
ISL8484IU
8484
-40 to +85
10 Ld MSOP
M10.118
ISL8484IU-T
8484
-40 to +85
10 Ld MSOP Tape and Reel
M10.118
ISL8484IRZ (Note)
484Z
-40 to +85
10 Ld 3x3 TDFN (Pb-free)
L10.3x3A
ISL8484IRZ-T (Note)
484Z
-40 to +85
10 Ld 3x3 TDFN Tape and Reel (Pb-free)
L10.3x3A
ISL8484IUZ (Note)
8484Z
-40 to +85
10 Ld MSOP (Pb-free)
M10.118
ISL8484IUZ-T (Note)
8484Z
-40 to +85
10 Ld MSOP Tape and Reel (Pb-free)
M10.118
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6128.3
June 14, 2007
ISL8484
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) +0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) +0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical)
θJA (°C/W)
10 Ld 3x3 TDFN Package (Note 3) . . . . . . . . . . . . .
90
10 Ld MSOP Package (Note 4) . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 5, 7),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 6)
Full
0
TYP
MAX
(NOTE 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
rON Matching Between Channels,
ΔrON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max rON , (Note 10)
rON Flatness, rFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 8)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or Floating
V+
V
25
0.23
0.4
Ω
Full
0.26
0.6
Ω
25
0.03
Ω
Full
0.04
Ω
25
0.03
Ω
Full
0.04
Ω
25
-100
100
nA
Full
-195
195
nA
25
-100
100
nA
Full
-195
195
nA
30
ns
35
ns
25
ns
30
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 9)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 9)
25
Full
25
15
Full
Break-Before-Make Time Delay, td
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF,
(See Figure 3, Note 9)
Full
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
OFF Isolation
Crosstalk (Channel-to-Channel)
3
20
2
4
ns
25
128
pC
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
68
dB
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-95
dB
FN6128.3
June 14, 2007
ISL8484
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 5, 7),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 6)
TYP
MAX
(NOTE 6) UNITS
25
0.003
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
115
pF
COM ON Capacitance, CCOM(ON)
25
224
pF
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
POWER SUPPLY CHARACTERISTICS
Full
4.5
V
25
0.1
μA
Full
1
μA
25
12
μA
Input Voltage Low, VINL
Full
0.5
V
Input Voltage High, VINH
Full
1.4
Full
-0.5
Power Supply Range
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
1.65
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+, (Note 9)
V
μA
0.5
NOTES:
5. VIN = input voltage to perform proper function.
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
9. Guaranteed but not tested.
10. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 11, 13),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 12)
Full
0
TYP
MAX
(NOTE 12) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
ON-Resistance, rON
rON Matching Between Channels,
ΔrON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON , (Note 16)
rON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 14)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
25
V+
V
0.4
Ω
0.6
Ω
0.03
0.06
Ω
0.06
Ω
0.03
0.15
Ω
0.15
Ω
0.29
Full
25
Full
25
Full
25
1.1
nA
Full
25
nA
25
1.7
nA
Full
48
nA
25
25
DYNAMIC CHARACTERISTICS
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 15)
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 15)
Turn-OFF Time, tOFF
4
Full
25
Full
20
35
ns
40
ns
30
ns
35
ns
FN6128.3
June 14, 2007
ISL8484
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 11, 13),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 12)
TYP
MAX
(NOTE 12) UNITS
2
6
ns
Break-Before-Make Time Delay, td
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 3, Note 15)
Full
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
95
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
68
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-95
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
0.003
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
115
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
224
pF
25
0.014
μA
Full
0.52
μA
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
Input Voltage High, VINH
25
1.4
Full
-0.5
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+ (Note 15)
0.5
V
V
μA
0.5
NOTES:
11. VIN = input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
13. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
14. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
15. Guaranteed but not tested.
16. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 17, 19),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 18)
Full
0
TYP
MAX
(NOTE 18)
UNITS
V+
V
0.8
Ω
0.85
Ω
80
ns
90
ns
70
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to
V+, (See Figure 5)
ON-Resistance, rON
25
0.5
Full
DYNAMIC CHARACTERISTICS
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 20)
Turn-ON Time, tON
25
Full
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω,
CL = 35pF, (See Figure 1, Note 20)
Break-Before-Make Time Delay, td
V+ = 2.0V, VNO or VNC = 1.0V, RL = 50Ω,
CL = 35pF, (See Figure 3, Note 20)
Full
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
5
65
25
50
Full
80
2
ns
9
ns
25
49
pC
25
68
dB
FN6128.3
June 14, 2007
ISL8484
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 17, 19),
Unless Otherwise Specified (Continued)
TEMP
(°C)
TEST CONDITIONS
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
MIN
(NOTE 18)
TYP
MAX
(NOTE 18)
UNITS
25
-95
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
115
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
224
pF
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
Input Voltage High, VINH
25
1.0
Full
-0.5
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 20)
0.4
V
V
μA
0.5
NOTES:
17. VIN = input voltage to perform proper function.
18. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
19. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
20. Guaranteed but not tested.
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
tr < 5ns
tf < 5ns
50%
C
0V
tOFF
SWITCH
V
INPUT NO
VOUT
NO OR NC
COM
IN
VOUT
90%
SWITCH
OUTPUT
SWITCH
INPUT
90%
LOGIC
INPUT
GND
RL
50Ω
CL
35pF
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------R L + r ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
6
FN6128.3
June 14, 2007
ISL8484
Test Circuits and Waveforms (Continued)
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
COM
NO OR NC
ΔVOUT
VG
GND
IN
CL
V+
ON
ON
LOGIC
INPUT
LOGIC
INPUT
OFF
0V
Q = ΔVOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
V+
LOGIC
INPUT
C
NO
VNX
VOUT
COM
NC
0V
RL
50Ω
IN
SWITCH
OUTPUT
VOUT
90%
CL
35pF
GND
LOGIC
INPUT
0V
tD
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
C
V+
C
SIGNAL
GENERATOR
rON = V1/100mA
NO OR NC
NO OR NC
IN
0V OR V+
VNX
100mA
IN
V1
0V OR V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
7
Repeat test for all switches.
FIGURE 5. rON TEST CIRCUIT
FN6128.3
June 14, 2007
ISL8484
Test Circuits and Waveforms (Continued)
V+
V+
C
C
SIGNAL
GENERATOR
NO OR NC
COM
NO OR NC
50Ω
IN
IN1
0V OR V+
IMPEDANCE
ANALYZER
0V or V+
COM
NC or NO
COM
ANALYZER
GND
N.C.
GND
RL
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
.
V+
The ISL8484 is a bidirectional, dual single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single 1.65V to 4.5V supply with low on-resistance
(0.23Ω) and high speed operation (tON = 20ns, tOFF = 15ns).
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.65V), low power consumption (4.5μW max), low leakage
currents (110nA max), and the tiny DFN and MSOP
packages. The ultra low ON-resistance and rON flatness
provide very low insertion loss and distortion to applications
that require signal reproduction.
OPTIONAL
PROTECTION
RESISTOR
C
100Ω
NO
COM
NC
IN
GND
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the ISL8484 IC (see Figure 8).
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from the
V+ power supply to ground. This will result in a significant
amount of current flow in the IC which can potentially create a
latch-up state or permanently damage the IC. The external V+
resistor limits the current during this over-stress situation and
has been found to prevent latch-up or destructive damage for
many over voltage transient events.
Under normal operation the sub-microamp IDD current of the
IC produces an insignificant voltage drop across the 100Ω
series resistor resulting in no impact to switch operation or
performance.
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (See
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 9). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch, so two small signal
8
FN6128.3
June 14, 2007
ISL8484
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 9). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation. The ISL8484 has been
designed to minimize the supply current whenever the digital
input voltage is not driven to the supply rails (0V to V+). For
example driving the device with 2.85V logic (0V to 2.85V)
while operating with a 4.2V supply the device draws only
8μA of current (see Figure 15 for VIN = 2.85V).
High-Frequency Performance
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNO OR NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8484 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL8484 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the “Electrical Specifications” tables, beginning on page 3,
and “Typical Performance Curves”, beginning on page 10,
for details.
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
In 50Ω systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 120MHz (See
Figure 20). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 21 details the high off Isolation and crosstalk rejection
provided by this part. At 100kHz, off Isolation is about 68dB
in 50Ω systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (See Figure 17). At 2.7V
the VIL level is about 0.53V. This is still above the 1.8V
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
9
FN6128.3
June 14, 2007
ISL8484
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
0.27
3.0
ICOM = 100mA
ICOM = 100mA
0.26
2.5
0.25
2.0
V+ = 2.7V
0.23
rON (Ω)
rON (Ω)
0.24
V+ = 3V
0.22
V+ = 1.1V
1.5
1.0
0.21
V+ = 1.5V
0.20
V+ = 3.6V
0.5
V+ = 4.3V
0.19
V+ = 1.62V
0
0.18
0
1
2
VCOM (V)
3
4
0
5
0.5
1.0
1.5
2.0
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.32
0.28
V+ = 4.3V
ICOM = 100mA
0.26
V+ = 2.7V
ICOM = 100mA
0.30
+85°C
0.28
0.24
+85°C
0.22
rON (Ω)
rON (Ω)
V+ = 1.8V
0.2
0.26
+25°C
0.24
+25°C
0.22
0.18
-40°C
0.16
0.14
0.20
-40°C
0
1
2
3
4
VCOM (V)
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
10
5
0.18
0
0.5
1.0
1.5
2.0
2.5
3.0
VCOM (V)
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN6128.3
June 14, 2007
ISL8484
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
0.50
200
V+ = 1.8V
ICOM = 100mA
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
0.45
+85°C
150
i+ (µA)
rON (Ω)
0.40
0.35
100
0.30
+25°C
50
-40°C
0.25
0.20
0
0
0.5
1
1.5
2
1
2
VCOM (V)
3
4
5
VIN1-2 (V)
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 15. VLOGIC vs SUPPLY VOLTAGE
150
1.1
1.0
100
0.9
VINH AND VINL (V)
VINH
Q (pC)
50
V+ = 4.3V
V+ = 1.8V
0
V+ = 3V
0.8
0.7
VINL
0.6
0.5
-50
0.4
-100
0
1
2
3
4
VCOM (V)
FIGURE 16. CHARGE INJECTION vs SWITCH VOLTAGE
11
5
0.3
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V+ (V)
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6128.3
June 14, 2007
ISL8484
200
200
150
150
100
tOFF (ns)
tON (ns)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
+85°C
+25°C
100
+85°C
+25°C
-40°C
50
50
0
1.0
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
0
1.0
4.5
FIGURE 18. TURN-ON TIME vs SUPPLY VOLTAGE
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
-10
V+ = 3V
10
V+ = 3V
-20
20
-30
30
-40
40
-50
50
GAIN
0
PHASE
20
40
60
80
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1M
100
10M
100M
FREQUENCY (Hz)
FIGURE 20. FREQUENCY RESPONSE
12
600M
CROSSTALK (dB)
-20
-60
60
ISOLATION
-70
70
-80
80
OFF ISOLATION (dB)
0
4.5
FIGURE 19. TURN-OFF TIME vs SUPPLY VOLTAGE
PHASE (°)
NORMALIZED GAIN (dB)
-40°C
CROSSTALK
-90
90
-100
100
-110
1k
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 21. CROSSTALK AND OFF ISOLATION
FN6128.3
June 14, 2007
ISL8484
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
100
50
V+ = 4.5V
V+ = 4.5V
VCOM = 03V
0
50
0
iOFF (nA)
iON (nA)
+25°C
+25°C
-50
+85°C
-100
-50
+85°C
-150
-100
0
1
2
3
VCOM/NX (V)
4
FIGURE 22. ON LEAKAGE vs SWITCH VOLTAGE
5
0
1
2
3
4
5
VNX (V)
FIGURE 23. OFF LEAKAGE vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (DFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
13
FN6128.3
June 14, 2007
ISL8484
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
E
A3
6
INDEX
AREA
TOP VIEW
B
//
A
C
SEATING
PLANE
0.08 C
b
0.20
0.25
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
A3
SIDE VIEW
D2
(DATUM B)
0.10 C
0.20 REF
7
8
N
10
2
Nd
5
3
Rev. 3 3/06
D2/2
NOTES:
6
INDEX
AREA
1
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
8
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
14
FN6128.3
June 14, 2007
ISL8484
Mini Small Outline Plastic Packages
(MSOP)
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
N
SYMBOL
E1
E
-B-
INDEX
AREA
0.20 (0.008)
1 2
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
4X θ
A2
A1
b
-H-
0.10 (0.004)
L
L1
SEATING
PLANE
C
-Ae
D
0.20 (0.008)
C
C
MILLIMETERS
MAX
MIN
MAX
A
0.037
0.043
0.94
1.10
-
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
L1
0.037 REF
0.95 REF
-
N
10
10
7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
-
θ
5o
15o
5o
15o
-
α
0o
6o
0o
6o
Rev. 0 12/02
a
SIDE VIEW
CL
E1
0.20 (0.008)
NOTES
A1
e
SEATING
PLANE -C-
MIN
C D
-B-
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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15
FN6128.3
June 14, 2007