19-4145; Rev 3; 12/08 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Features The MAX16016/MAX16020/MAX16021 supervisory circuits monitor power supplies, provide battery-backup control, and chip-enable (CE) gating to write protect memory in microprocessor (µP)-based systems. These low-power devices improve system reliability by providing several supervisory functions in a small, single integrated solution. o System Monitoring for 5V, 3.3V, 3V, 2.5V, or 1.8V Power-Supply Voltages o 1.53V to 5.5V Operating Voltage Range o Low 1.2µA Supply Current (0.25µA in BatteryBackup Mode) o 145ms (min) Reset Timeout Period o Battery Freshness Seal o On-Board Gating of CE Signals, 1.5ns Propagation Delay (MAX16020/MAX16021) o Debounced Manual Reset Input o Watchdog Timer, 1.2s (typ) Timeout o Power-Fail Comparator and Low-Line Indicator for Monitoring Voltages Down to 0.6V o Battery-On, Battery-OK, and Battery Test Indicators o Small 10-Pin TDFN or 16-Pin TQFN Packages o UL®-Certified to Conform to IEC 60950-1 The MAX16016/MAX16020/MAX16021 perform four basic system functions: 1) Provide a µP reset output during VCC supply powerup, power-down, and brownout conditions. 2) Control VCC to battery-backup switching internally to maintain data or low-power operation for memories, real-time clocks (RTCs), and other digital logic when the main power is removed. 3) Provide memory write protection through internal chip-enable gating during brownout. 4) Provide a combination of additional supervisory functions listed in the Features section. The MAX16016/MAX16020/MAX16021 operate from a 1.53V to 5.5V supply voltage and offer fixed reset thresholds for monitoring 5V, 3.3V, 3V, 2.5V, and 1.8V systems. Each device is available with either a pushpull or open-drain reset output. The MAX16016/MAX16020/MAX16021 are available in small TDFN/TQFN packages and are fully specified for an operating temperature range of -40°C to +85°C. Applications Main/Backup Power for RTCs, CMOS Memories Ordering Information PART MAX16016_TB_+T PIN-PACKAGE 10 TDFN-EP* The first placeholder “_” designates all output options. Letter “L” indicates push-pull outputs and letter “P” indicates opendrain outputs. The last placeholder “_” designates the reset threshold (see Table 1). T = Tape and reel. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Ordering Information continued at end of data sheet. Selector Guide located at end of data sheet. Pin Configurations Industrial Control CEIN CEOUT OUT TOP VIEW Set-Top Boxes VCC GPS Systems TEMP RANGE -40°C to +85°C Point-of-Sale Equipment 16 15 14 13 Portable/Battery Equipment BATT 1 MR 2 PFI 3 WDI 4 + 12 RESET 11 GND 10 PFO 9 WDO MAX16020 *EP = EXPOSED PAD. UL is a registered trademark of Underwriters Laboratories, Inc. 5 6 7 8 LL BATT_TEST BATTOK BATTON *EP TQFN Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX16016/MAX16020/MAX16021 General Description MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating ABSOLUTE MAXIMUM RATINGS VCC, BATT, OUT, BATT_TEST to GND.....................-0.3V to +6V RESET, RESET, PFO, BATTOK, WDO, BATTON, BATT_TEST, LL, (all open-drain) to GND .....................-0.3V to +6V RESET, RESET, BATTOK, WDO, BATTON, LL (all push-pull) to GND......................-0.3V to (VOUT + 0.3V) WDI, PFI to GND.......................................-0.3V to (VOUT + 0.3V) CEIN, CEOUT to GND ..............................-0.3V to (VOUT + 0.3V) MR to GND .................................................-0.3V to (VCC + 0.3V) Input Current VCC Peak Current.................................................................1A VCC Continuous Current ...............................................250mA BATT Peak Current .......................................................500mA BATT Continuous Current ...............................................70mA Output Current OUT Short Circuit to GND Duration ....................................10s RESET, RESET, BATTON ....................................................20mA Continuous Power Dissipation (TA = +70°C) 10-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW 16-Pin TQFN (derate 25mW/°C above +70°C) ..........2000mW Thermal Resistance (Note 1) For 10-Pin TDFN θJA ................................................................................41°C/W For 16-Pin TQFN θJA ................................................................................40°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Operating Voltage Range (Note 3) Supply Current Supply Current in Battery-Backup Mode SYMBOL VCC, VBATT ICC IBATT CONDITIONS VCC or VBATT > VTH VCC > VTH 5.5 V 1.2 2 1.9 3 VCC = 3.6V 2.3 3.5 VCC = 5.5V 3.4 5 0.25 0.5 VCC = 0V VCC falling, VCC < VTH, VCC - VBATT BATT Standby Current VCC > VBATT + 0.2V BATT Freshness Leakage Current VBATT = 5.5V 2 UNITS VCC = 2.8V BATT Switchover Threshold Voltage Output Voltage in Battery-Backup Mode MAX VCC = 1.62V VCC rising, VCC - VBATT RON TYP 0 VCC Switchover Threshold Voltage VCC to OUT On-Resistance MIN V 0 mV +10 nA 20 nA VCC = 4.75V, IOUT = 150mA 1.4 4.5 VCC = 3.15V, IOUT = 65mA 1.7 4.5 VCC = 2.35V, IOUT = 25mA 2.1 5.0 VCC = 1.91V, IOUT = 10mA 2.6 5.5 VBATT - 0.1 VBATT = 2.5V, IOUT = 20mA VBATT - 0.15 VOUT µA 0.1 x VCC -10 VBATT = 4.5V, IOUT = 20mA µA Ω V _______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RESET OUTPUT (RESET, RESET) Reset Threshold VTH VCC Falling to Reset Delay tRD Reset Timeout Period tRP RESET Output Low Voltage RESET Output High Voltage (Push-Pull Output) VOL VOH RESET Output Leakage Current (Open-Drain Output) RESET Output Low Voltage RESET Output High Voltage (Push-Pull Output) VOL VOH RESET Output Leakage Current (Open-Drain Output) (see Table 1) VCC falling at 10V/ms V 20 145 215 µs 285 VCC ≥ 3.3V, ISINK = 3.2mA, RESET asserted 0.3 VCC ≥ 1.6V, ISINK = 1mA, RESET asserted 0.3 VCC ≥ 1.2V, ISINK = 100µA, RESET asserted 0.3 VCC = 1.1 x VTH, ISOURCE = 100µA, RESET deasserted VOUT - 0.3 V V VRESET = 5.5V, RESET deasserted 1 VCC ≥ 3.3V, ISINK = 3.2mA, RESET deasserted 0.3 µA V VCC ≥ 1.8V, ISINK = 1.0mA, RESET deasserted VCC = 0.9 x VTH, ISOURCE = 100µA, RESET asserted ms 0.3 VOUT - 0.3 V VRESET = 5.5V, RESET asserted 1 µA POWER-FAIL COMPARATOR PFI, Input Threshold PFI, Hysteresis VPFT VIN falling, 1.6V ≤ VCC ≤ 5.5V 0.572 VPFT-HYS PFI Input Current VOL PFO Output Voltage High (Push-Pull Output) VOH 0.611 30 VCC = 5.5V PFO Output Low Voltage 0.590 -1 +1 VCC ≥ 1.6V, ISINK = 1mA, output asserted 0.3 VCC ≥ 1.2V, ISINK = 100µA, output asserted 0.3 VCC = 1.1 x VTH, ISOURCE = 100µA, output asserted PFO, Leakage Current (Open-Drain Output) VPFO = 5.5V, output deasserted PFO, Delay Time VPFT + 100mV to VPFT - 100mV V mV VOUT - 0.3 µA V V 1 20 µA µs MANUAL RESET (MR) Input Low Voltage VIL Input High Voltage VIH 0.3 x VCC 0.7 x VCC Pullup Resistance Glitch Immunity MR to Reset Delay 20 VCC = 3.3V V V 30 kΩ 100 ns 120 ns _______________________________________________________________________________________ 3 MAX16016/MAX16020/MAX16021 ELECTRICAL CHARACTERISTICS (continued) MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 1.235 1.64 UNITS WATCHDOG TIMER (WDI, WDO) Watchdog Timeout Period tWD 0.83 Minimum WDI Input Pulse Width tWDI 320 WDI Input Low Voltage VIL (Note 6) WDI Input High Voltage VIH (Note 6) WDI Input Current (Note 7) VWDI = 0 or 5.5V, time average WDO Output Low Voltage VOL VCC = 1.1 x VTH, ISINK = 1mA, WDO asserted WDO Output High Voltage (Push-Pull Output) VOH VCC = 1.1 x VTH, ISOURCE = 100µA, WDO deasserted WDO Leakage Current (Open-Drain Output) s ns 0.3 x VCC 0.7 x VCC V V -1 +1 µA 0.3 V VOUT - 0.3 V VWDO = 5.5V, WDO deasserted 1 µA BATTERY-ON INDICATOR (BATTON) Output Low Voltage VOL BATTON Leakage Current BATTON Output High Voltage Output Short-Circuit Current (Note 4) ISINK = 3.2mA, VBATT = 2.1V VBATTON = 5.5V VOH VCC = 0.9 x VTH, ISOURCE = 100µA, BATTON asserted 0.3 V 1 µA VOUT - 0.3 Sink current, VCC = 5V V 60 mA CE GATING (CEIN, CEOUT) CEIN Leakage Current Reset asserted, VCC = 0.9 x VTH or 0V +1 µA CEIN to CEOUT Resistance Reset not asserted (Note 5) 8 50 Ω CEOUT Short-Circuit Current Reset asserted, CEOUT = 0, VCC = 0.9 x VTH 0.75 2 mA CEIN to CEOUT Propagation Delay 50Ω source, CLOAD = 50pF, VCC = 4.75V 1.5 7 ns VCC = 5V, VCC ≥ VBATT, ISOURCE = 100µA Output High Voltage VCC = 0V, VBATT ≥ 2.2V ISOURCE = 1µA Reset to CEOUT Delay 4 -1 0.8 x VCC V VBATT 0.1 12 _______________________________________________________________________________________ µs Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOW LINE (LL) Low Line to Reset Threshold Voltage VCC falling VCC Falling to LL Delay VCC falling at 10V/ms LL Output Low Voltage VOL LL Output High Voltage (PushPull Output) VOH (see Table 2) 20 µs VCC ≥ 1.6V, ISINK = 1mA, LL asserted 0.3 VCC ≥ 1.2V, ISINK = 100µA, LL asserted 0.3 VCC = 0.9 x VTH_LL, ISOURCE = 100µA, LL deasserted V VOUT 0.3 V VLL = 5.5V, LL deasserted Output Leakage Current mV 1 µA 2.673 V 0.3 V BATTERY-OK INDICATOR (BATTOK, BATT_TEST) BATTOK Threshold Inferred internally from BATT BATTOK Output Voltage Low VOL VCC = 1.1 x VTH, ISINK = 1mA, reset asserted BATTOK Output High Voltage VOH VCC = 1.1 x VTH, ISOURCE = 100µA, BATTOK asserted 2.508 2.6 VOUT 0.3 V BATTOK Output Leakage Current VBATTOK = 5.5V, deasserted 1 µA BATT_TEST Output Low Voltage VCC = 1.1 x VTH, ISINK = 1mA 0.3 V Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: All devices are 100% production tested at TA = +25°C and TA = +85°C. Limits to -40°C are guaranteed by design. VBATT can be 0V anytime, or VCC can go down to 0V if VBATT is active (except at startup). Use external current-limit resistor to limit current to 20mA (max). CEIN/CEOUT resistance is tested with VCC = 5V and VCEIN = 0V or 5V. WDI is internally serviced within the watchdog period if WDI is left unconnected. The WDI input current is specified as the average input current when the WDI input is driven high or low. The WDI input is designed for a three-stated output device with a 10µA maximum leakage current and capable of driving a maximum capacitive load of 200pF. The three-state device must be able to source and sink at least 200µA when active. Table 1b. Reset Threshold Ranges (MAX16020/MAX16021) Table 1a. Reset Threshold Ranges (MAX16016) SUFFIX RESET THRESHOLD RANGES (V) MIN TYP SUFFIX MAX RESET THRESHOLD RANGES (V) MIN TYP MAX L 4.508 4.63 4.906 L 4.520 4.684 4.852 M 4.264 4.38 4.635 M 4.275 4.428 4.585 T 2.991 3.08 3.239 T 3.010 3.100 3.190 S 2.845 2.93 3.080 S 2.862 2.946 3.034 R 2.549 2.63 2.755 R 2.568 2.640 2.716 2.425 Z 2.260 2.323 2.390 Z 2.243 2.32 Y 2.117 2.19 2.288 Y 2.133 2.192 2.255 W 1.603 1.67 1.733 W 1.616 1.661 1.710 V 1.514 1.575 1.639 V 1.528 1.571 1.618 _______________________________________________________________________________________ 5 MAX16016/MAX16020/MAX16021 ELECTRICAL CHARACTERISTICS (continued) Table 2. Low-Line Threshold Ranges LOW-LINE THRESHOLD RANGES (V) SUFFIX MIN TYP MAX L 4.627 4.806 4.955 M 4.378 4.543 4.683 T 3.075 2.922 3.181 S 3.023 3.274 3.111 R 2.620 2.409 2.787 Z 2.309 2.383 2.450 Y 2.180 2.246 2.311 W 1.653 1.704 1.752 V 1.563 1.612 1.657 Typical Operating Characteristics (VCC = 5V, VBATT = 0V, TA = +25°C, unless otherwise noted.) BATT SUPPLY CURRENT vs. SUPPLY VOLTAGE VCC SUPPLY CURRENT vs. TEMPERATURE (IOUT = 0) MAX16020PTEZ+ 4 0.7 MAX16016 toc02 6 MAX16016 toc01 5 MAX16020PTEZ+ 5 MAX16016 toc03 VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX16020PTEZ+ VBATT = 2.5V 0.6 0.5 IBATT (µA) 3 ICC (µA) 3 2 2 1 0.1 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 5.5 -15 10 35 60 TEMPERATURE (°C) SUPPLY VOLTAGE (V) BATTERY SUPPLY CURRENT vs. TEMPERATURE (VCC = 0V) BATT STANDBY CURRENT vs. TEMPERATURE VCC TO OUT ON-RESISTANCE vs. SUPPLY VOLTAGE 0.4 0.3 0.2 0.1 5 VCC = 3.2V VBATT = 3.0V 4 3 2 1 0 -1 -2 -3 10 35 TEMPERATURE (°C) 6 60 85 3.0 IOUT = 25mA 2.5 2.0 1.5 IOUT = 10mA 1.0 0 -5 -15 MAX16020PTEZ+ 3.5 0.5 -4 0 4.0 VCC TO OUT ON-RESISTANCE (Ω) VBATT = +3.0V MAX16016 toc05 MAX16016 toc04 0.5 -40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 85 SUPPLY VOLTAGE (V) BATT STANDBY CURRENT (nA) 1.5 0.3 0.2 1 0 0.4 MAX16016 toc06 ICC (µA) 4 IBATT (µA) MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating -40 -15 10 35 TEMPERATURE (°C) 60 85 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 4.5 5.0 5.5 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating 3 2 1 VBATT = 2.5V VBATT = 3V 4 3 2 1 RESET OUTPUT VOLTAGE LOW vs. SINK CURRENT 0.5 MAX16016 toc09 4 5 MAX16016 toc08 VCC TO OUT ON-RESISTANCE (Ω) VCC = +3.15V, IOUT = 65mA BATT TO OUT ON-RESISTANCE (Ω) MAX16016 toc07 5 BATT TO OUT ON-RESISTANCE vs. TEMPERATURE (VCC = 0V, IOUT = 20mA) RESET OUTPUT VOLTAGE LOW (V) VCC TO OUT ON-RESISTANCE vs. TEMPERATURE 0.4 0.3 VCC = 3.3V 0.2 VCC = 5V 0.1 VBATT = 4.5V 0 -15 10 35 60 -40 -15 10 35 60 0 85 6 8 10 12 14 16 18 20 MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE RESET TIMEOUT PERIOD vs. TEMPERATURE 0.999 0.998 0.997 0.996 0.996 400 350 300 250 RESET OCCURS ABOVE THE CURVE 200 150 100 210 10 35 60 206 204 202 200 198 196 194 192 50 85 MAX16020PTEZ+ 208 190 0 -15 MAX16016 toc12 MAX16020PTEZ+ 450 RESET TIMEOUT PERIOD (ms) 1.000 MAXIMUM TRANSIENT DURATION (µs) MAX16016 toc10 1.001 500 MAX16016 toc11 NORMALIZED RESET THRESHOLD vs. TEMPERATURE 1.002 0 50 -40 100 150 200 250 300 350 400 -15 10 35 60 TEMPERATURE (°C) RESET THRESHOLD OVERDRIVE (mV) TEMPERATURE (°C) WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE PFI THRESHOLD vs. TEMPERATURE NORMALIZED LL THRESHOLD vs. TEMPERATURE PFI THRESHOLD (V) 1.2 0.63 1.1 1.0 0.9 0.8 0.62 0.61 0.60 0.59 0.58 0.7 0.57 0.6 0.56 0.5 VPFI- 10 35 TEMPERATURE (°C) 60 85 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 0.55 -15 1.005 85 MAX16016 toc15 1.3 VPFI+ 0.64 NORMALIZED LL THRESHOLD 1.4 MAX16016 toc14 0.65 MAX16016 toc13 1.5 -40 4 SINK CURRENT (mA) 1.003 -40 2 TEMPERATURE (°C) 1.004 NORMALIZED RESET THRESHOLD 85 TEMPERATURE (°C) 1.005 WATCHDOG TIMEOUT PERIOD (s) 0 0 -40 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX16016/MAX16020/MAX16021 Typical Operating Characteristics (continued) (VCC = 5V, VBATT = 0V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = 5V, VBATT = 0V, TA = +25°C, unless otherwise noted.) BATTON OUTPUT VOLTAGE LOW vs. SINK CURRENT VCC SUPPLY CURRENT vs. WDI FREQUENCY 60 50 ICC (µA) 0.3 VCC = 3.3V 0.2 40 30 VCC = 5V 20 0.1 10 0 2 4 6 10 12 14 16 18 20 8 0 10 SINK CURRENT (mA) 0.3 VCC = 3.3V 0.2 VCC = 5V 0.1 100 1000 0 4 6 8 10 12 14 16 18 20 MR FALLING TO RESET DELAY MAX16016 toc20 MAX16016 toc19 0.5 2 SINK CURRENT (mA) WDI FREQUENCY (kHz) BATTOK OUTPUT VOLTAGE LOW vs. SINK CURRENT BATTOK OUTPUT VOLTAGE LOW (V) 0.4 0 0 0 0.5 MAX16016 toc18 0.4 MAX16016 toc17 70 MAX16016 toc16 0.5 BATTON OUTPUT VOLTAGE LOW (V) WDO OUTPUT VOLTAGE LOW vs. SINK CURRENT WDO OUTPUT VOLTAGE LOW (V) 0.4 MR 5V/div VCC = 3.3V 0.3 0.2 VCC = 5V RESET 5V/div 0.1 0 0 2 4 6 8 10 12 14 16 18 20 200ns/div SINK CURRENT (mA) CHIP-ENABLE GATING LOCKING OUT SIGNAL DURING RESET CONDITION RESET PROPAGATION DELAY vs. THRESHOLD OVERDRIVE MAX16020PTEZ+ 60 MAX16016 toc21 MAX16016 toc22 70 PROPAGATION DELAY (µs) MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating RESET 5V/div 50 CEIN 5V/div 40 30 CEOUT 5V/div 20 10 0 0 50 100 150 200 250 300 350 400 10µs/div THRESHOLD OVERDRIVE (mV) 8 _______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating PIN NAME 1 VCC Supply Voltage Input. Bypass VCC to GND with a 0.1µF capacitor. FUNCTION 2 BATT Backup Battery Input. If VCC falls below its reset threshold, and if VBATT > VCC, OUT connects to BATT. If VCC rises above 1.01 x VBATT, OUT connects to VCC. Bypass BATT to GND with a 0.1µF capacitor. 3 MR Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low for the duration of reset timeout period after MR transitions from low to high. Connect MR to OUT or leave unconnected if not used. MR is internally connected to OUT through a 30kΩ pullup resistor. 4 PFI Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI threshold. The PFI input is referenced to an internal VPFT threshold. A VPFT-HYS internal hysteresis provides noise immunity. The power-fail comparator is powered from OUT. 5 WDI Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout period (tWD), the internal watchdog timer runs out and a reset pulse is triggered for the reset timeout period. The internal watchdog clears when reset asserts or whenever WDI sees a rising or falling edge. To disable the watchdog feature, leave WDI unconnected or three-state the driver connected to WDI. 6 BATTON 7 PFO Active-Low Power-Fail Comparator Output. PFO goes low when VPFI falls below the internal VPFT threshold and goes high when VPFI rises above VPFT + VPFT-HYS hysteresis. 8 GND Ground 9 RESET Active-Low Reset Output. RESET asserts when VCC falls below the reset threshold or MR is pulled low. RESET remains low for the duration of the reset timeout period after VCC rises above the reset threshold and MR goes high. RESET also asserts low when the internal watchdog timer runs out. 10 OUT Switched Output. OUT is connected to VCC when the reset output is not asserted or when VCC is greater than VBATT. OUT connects to BATT when RESET is asserted and VBATT is greater than VCC. Bypass OUT to GND with a 0.1µF (min) capacitor. Active-High Battery-On Output. BATTON goes high when in battery-backup mode. _______________________________________________________________________________________ 9 MAX16016/MAX16020/MAX16021 Pin Description—MAX16016 MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Pin Description—MAX16020/MAX16021 PIN MAX16020 MAX16021 1 FUNCTION BATT Backup Battery Input. If VCC falls below its reset threshold, and if VBATT > VCC, OUT connects to BATT. If VCC rises above 1.01 x VBATT, OUT connects to VCC. Bypass BATT to GND with a 0.1µF capacitor. 2 2 MR Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low for the duration of reset timeout period after MR transitions from low to high. Connect MR to OUT or leave unconnected if not used. MR is internally connected to OUT through a 30kΩ pullup resistor. 3 3 PFI Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI threshold. The PFI input is referenced to an internal threshold VPFT, VPFT-HYS internal hysteresis provides noise immunity. The power-fail comparator is powered from OUT. WDI Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout period (tWD), the internal watchdog timer runs out and asserts WDO. The internal watchdog clears when reset asserts or whenever WDI sees a rising or falling edge. To disable the watchdog feature, leave WDI unconnected or three-state the driver connected to WDI. LL Active-Low Low-Line Output. LL goes low when VCC falls to 2.5% above the reset threshold (Table 2). LL provides an early warning of VCC failure before reset asserts. Use this output to generate a nonmaskable interrupt (NMI) to initiate an orderly shutdown routine when VCC is falling. 4 10 1 NAME 4 5 5 6 — — 6 RESET 7 7 BATTOK Battery-OK Output. BATTOK goes low when the battery voltage falls below the BATTOK threshold (BATTOK is low when in battery-backup mode). 8 8 BATTON Active-High Battery-On Output. BATTON goes high when in battery-backup mode. Open-Drain Battery-Test Output. Pulses low for 1.3s every 24 hours during the battery BATT_TEST voltage test. If VBATT < 2.6V, BATTOK deasserts low. See Figure 6 for providing additional load during the battery test. Active-High Reset Output. RESET asserts when VCC falls below the reset threshold or when MR asserts and stays asserted for the reset timeout period after VCC rises above the reset threshold and MR deasserts. ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating PIN MAX16020 MAX16021 NAME FUNCTION 9 9 WDO Active-Low Watchdog Output. WDO asserts when WDI remains high or low longer than the watchdog timeout period. WDO returns high on the next WDI transition or when a reset is asserted. 10 10 PFO Active-Low Power-Fail Comparator Output. PFO goes low when VPFI falls below the internal 0.6V VPFT threshold and goes high when VPFI rises above VPFT + VPFT-HYS hysteresis. 11 11 GND Ground 12 12 RESET Active-Low Reset Output. RESET asserts when VCC falls below the reset threshold or MR is pulled low. RESET remains low for the duration of the reset timeout period after VCC rises above the reset threshold and MR goes high. 13 13 OUT Switched Output. OUT is connected to VCC when the reset output is not asserted or when VCC is greater than VBATT. OUT connects to BATT when RESET is asserted and VBATT is greater than VCC. Bypass OUT to GND with a 0.1µF (min) capacitor. 14 14 CEOUT Active-Low Chip-Enable Output. CEOUT goes low only when CEIN is low and reset is not asserted. If CEIN is low when reset is asserted, CEOUT stays low for 12µs (typ) or until CEIN goes high, whichever occurs first. 15 15 CEIN Chip-Enable Input. The input to CE gating circuitry. Connect to GND or OUT if not used. 16 16 VCC Supply Voltage Input. Bypass VCC to GND with a 0.1µF capacitor. — — EP Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to aid heat dissipation. Do not use EP as the only ground connection for the device. ______________________________________________________________________________________ 11 MAX16016/MAX16020/MAX16021 Pin Description—MAX16020/MAX16021 (continued) Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Functional Diagrams BATT BATTERY FRESHNESS SEAL OUT VCC BATTON MR RESET DELAY RESET OUT REF PFO PFI CLEAR WATCHDOG TRANSITION DETECTOR WDI WATCHDOG TIMER MAX16016 100nA 25kΩ GND 12 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating BATT BATTERY TEST CIRCUIT BATTERY FRESHNESS SEAL BATT_TEST (MAX16020 ONLY) DISABLE OUT VCC LATCH BATTOK MR BATTON RESET OUT DELAY RESET (RESET) (MAX16021 ONLY) LL REF OUT PF1 PFO WATCHDOG TRANSITION DETECTOR WDI CLEAR CE OUTPUT CONTROL WDO WATCHDOG TIMER 25kΩ CEIN CEOUT 100nA MAX16020 MAX16021 GND ______________________________________________________________________________________ 13 MAX16016/MAX16020/MAX16021 Functional Diagrams (continued) MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Detailed Description The Typical Application Circuit shows a typical connection using the MAX16020. OUT powers the static random-access memory (SRAM). If VCC is greater than the reset threshold (VTH), or if VCC is lower than VTH, but higher than VBATT, VCC connects to OUT. If VCC is lower than VTH and VCC is less than VBATT, BATT connects to OUT (see the Functional Diagrams). In battery-backup mode, an internal MOSFET connects the backup battery to OUT. The on-resistance of the MOSFET is a function of backup-battery voltage and temperature. Backup-Battery Switchover In a brownout or power failure, it may be necessary to preserve the contents of the RAM. With a backup battery installed at BATT, the MAX16016/MAX16020/MAX16021 automatically switch the RAM to the backup power when VCC falls. The MAX16016/MAX16020/MAX16021 have a BATTON output that goes high when in battery-backup mode. These devices require two conditions before switching to battery-backup mode: 1) VCC must be below the reset threshold. 2) VCC must be below VBATT. Table 3 lists the status of the inputs and outputs in battery-backup mode. The device does not power up if the only voltage source is on BATT. OUT only powers up from VCC at startup. CE Signal Gating The MAX16020/MAX16021 provide internal gating of CE signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure or Table 3. Input and Output Status in Battery-Backup Mode PIN STATUS VCC Disconnected from OUT OUT Connected to BATT BATT Connected to OUT. Current drawn from the battery is less than 0.55µA (at VBATT = 3V, excluding IOUT) when VCC = 0V. RESET/RESET Asserted BATTON, WDO High state (push-pull), high impedance (open-drain) BATTOK, LL CEIN CEOUT PFO 14 Low state Disconnected from CEOUT brownout. During normal operation, the CE gate is enabled and passes all CE transitions. When the reset output asserts, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. CEOUT is pulled up to OUT through an internal current source. The 1.5ns propagation delay from CEIN to CEOUT allows the devices to be used with most µPs and high-speed DSPs. During normal operation (reset not asserted), CEIN is connected to CEOUT through a low on-resistance transmission gate. If CEIN is high when a reset asserts, CEOUT remains high regardless of any subsequent transition on CEIN during the reset event. If CEIN is low when reset asserts, CEOUT is held low for 12µs to allow completion of the read/write operation. After the 12µs delay expires, CEOUT goes high and stays high regardless of any subsequent transitions on CEIN during the reset event. When CEOUT is disconnected from CEIN, CEOUT is actively pulled up to OUT. The propagation delay through the CE circuitry depends on both the source impedance of the drive to CEIN and the capacitive loading at CEOUT. Minimize the capacitive load at CEOUT to minimize the propagation delay, and use a low output-impedance driver. Low-Line Output (LL) The low-line comparator monitors VCC with a threshold voltage typically 2.5% higher than the reset threshold (see Table 2). LL asserts prior to a reset condition during a brownout condition. On power-up, LL deasserts after the reset output. LL can be used to provide a nonmaskable interrupt (NMI) to the µP when the voltage begins to fall to initiate an orderly software shutdown routine. Manual Reset Input Many µP-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. For the MAX16016/MAX16020/ MAX16021, a logic-low on MR asserts RESET/RESET. RESET/RESET remains asserted while MR is low. When MR goes high RESET/RESET deasserts after a minimum of 145ms (tRP). MR has an internal 30kΩ pullup resistor to VCC. MR can be driven with TTL/CMOS logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from a long cable or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. Pulled up to VOUT Not affected ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Watchdog Input The watchdog monitors µP activity through the input WDI. If the µP becomes inactive, either the reset output is asserted in pulses (MAX16016) or the watchdog output goes low (MAX16020/MAX16021). To use the watchdog function, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and RESET asserts for the reset timeout period (MAX16016) or WDO goes low (MAX16020/MAX16021). The internal watchdog timer clears whenever the reset output asserts or the WDI sees a rising or falling edge within the watchdog timeout period. The WDI input is designed for a threestated output device with a 10µA maximum leakage current and the capability of driving a maximum capacitive load of 200pF. The three-state device must be able to source and sink at least 200µA when active. Disable the watchdog timer by leaving WDI unconnected or by three-stating the driver connected to WDI. The watchdog timer periodically attempts to pulse WDI to the opposite logic-level through a 25kΩ resistor for 40µs to determine whether WDI is either unconnected or latched to a logic state. The watchdog function is also disabled when in battery-backup mode. Watchdog Output WDO remains high if there is a transition or pulse at WDI during the watchdog-timeout period. WDO goes low if no transition occurs at WDI during the watchdog timeout period and remains low until the next transition at WDI or when a reset is asserted. Connect WDO to MR to generate a system reset on every watchdog fault. When a tWD watchdog fault occurs in this mode, WDO goes low, which pulls MR low, causing a reset pulse to be issued. As soon as the reset output is asserted, the watchdog timer clears and WDO returns high. With WDO connected to MR, a continuous high or low on WDI causes 145ms (min) reset pulses to be issued every 1.235s. Battery Testing Function/BATTOK Indicator (MAX16020/MAX16021) The MAX16020/MAX16021 feature a battery testing function that works in conjunction with the BATTOK output. The battery voltage is tested for 1.235s after VCC is applied and once every 24 hours thereafter. During this test, an internal 100kΩ resistor is connected from BATT to ground and the battery is monitored to ensure that the battery voltage is above 2.6V. If the battery voltage is below 2.6V, the BATTOK output deasserts low to indicate a weak battery condition. The MAX16020 has a BATT_TEST output that pulses high during the battery voltage test. Connect a resistor and FET as shown in Figure 6 to provide an additional load during the battery test. In battery-backup mode, the battery testing function is disabled and BATTOK goes low. Battery Freshness Seal Mode The MAX16016/MAX16020/MAX16021 battery freshness seal disconnects the backup battery from internal circuitry and OUT until VCC is applied. This ensures the backup battery connected to BATT is fresh when the final product is used for the first time. The internal freshness seal latch prevents BATT from powering OUT until VCC has come up for the first time, setting the latch. When VCC subsequently turns off, BATT begins to power OUT. tWD tWD WDI WDO Figure 1. Watchdog Timing (MAX16016/MAX16020) ______________________________________________________________________________________ 15 MAX16016/MAX16020/MAX16021 Watchdog Timer MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Power-Fail Comparator To reenable the freshness seal: 1) Connect a battery to BATT. 2) Bring VCC to 0V. 3) Drive MR higher than VBATT + 1.2V for at least 3µs. 4) Pull OUT to 0V. Reset Output A µP’s reset input starts the µP in a known state. The µP supervisory circuits assert a reset to prevent codeexecution errors during power-up, power-down, and brownout conditions. Reset output is guaranteed to be a logic-low or logic-high depending on the device chosen. RESET or RESET asserts when VCC is below the reset threshold and remains asserted for at least 145ms (tRP) after VCC rises above the reset threshold. RESET or RESET also asserts when MR is low. The MAX16016 watchdog function causes RESET to assert in pulses following a watchdog timeout. The reset output is available in both push-pull and open-drain configurations. The MAX16016/MAX16020/MAX16021 offer an undervoltage comparator that the output PFO goes low when the voltage at PFI falls below its VPFT threshold. Common uses for the power-fail comparator include monitoring the power supply (such as a battery) before any voltage regulation to provide an early power-fail warning, so software can conduct an orderly system shutdown. The power-fail comparator has a typical input hysteresis of VPFT-HYS and is powered from OUT, making it independent of the reset circuit. Connect the PFI input to GND if not used. Applications Information Monitoring an Additional Supply The MAX16016/MAX16020/MAX16021 µP supervisors can monitor either positive or negative supplies using a resistive voltage-divider to PFI. PFO can be used to generate an interrupt to the µP or to trigger a reset (Figures 2 and 3). To monitor a negative supply, connect the top of the resistive divider to VCC. Connect the bottom of the resistive divider to the negative voltage to be monitored. 5V V1 0.1µF VCC VCC R1 PFI RESET PFI R2 R1 0.1µF V2 µP MAX16016L MAX16020L MAX16021L PFO RESET MAX16016 MAX16020 MAX16021 R2 V- PFO MR GND GND VTRIP = VPFT ADDITIONAL SUPPLY RESET VOLTAGE R1+R2 V2(RESET) = VPFT x R2 (—) R2 (5 - VPFT) — R1 VTRIP IS NEGATIVE +5V PFO 0 VTRIP Figure 2. Monitoring an Additional Supply by Connecting PFO to MR 16 Figure 3. Monitoring a Negative Supply ______________________________________________________________________________________ 0V V- Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Battery-On Indicator (Push-Pull Version) BATTON goes high when in battery-backup mode. Use BATTON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher current applications (Figure 5). Operation Without a Backup Power Source The MAX16016/MAX16020/MAX16021 provide a battery-backup function. If a backup power source is not used, connect BATT to GND and OUT to VCC. +5V VCC VIN 0.1µF 1µF 0.1µF R1 VCC VCC BATTON PFI R2 BATT C1* R3 PFO MAX16016L MAX16020L MAX16021L OUT CEOUT MAX16020L CEIN MR TO µP CE ADDRESS DECODE CMOS RAM A0–A15 µP RESET GND RESET *OPTIONAL R1+R2 (—) R2 R1 R1 ) x (– + – + 1) V = (V + V R2 R3 V -V V V = R1 x (— + —) + V R2 R3 VTRIP = VPFT x H PFT GND PFT-HYS PFT CC PFT L Figure 5. BATTON Driving an External Pass Transistor PFT WHERE VPFT IS THE POWER-FAIL THRESHOLD VOLTAGE +5V PFO 0 VL VTRIP VH VIN Figure 4. Adding Hysteresis to the Power-Fail Comparator ______________________________________________________________________________________ 17 MAX16016/MAX16020/MAX16021 Adding Hysteresis to PFI The power-fail comparators have a typical input hysteresis of VPFT-HYS. This is sufficient for most applications where a power-supply line is being monitored through an external voltage-divider (see the Monitoring an Additional Supply section). Figure 4 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 so that PFI sees VPFT when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. R3 is typically an order of magnitude greater than R1 or R2. R3 should be larger than 50kΩ to prevent it from loading down PFO. Capacitor C1 adds additional noise rejection. MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Replacing the Backup Battery When VCC is above VTH, the backup power source can be removed without danger of triggering a reset pulse. The device does not enter battery-backup mode when VCC stays above the reset threshold voltage. BATT Negative-Going VCC Transients VCC RLOAD MAX16020L BATT_TEST The MAX16016/MAX16020/MAX16021 are relatively immune to short duration, negative going VCC transients. Resetting the µP when VCC experiences only small glitches is usually not desirable. A 0.1µF bypass capacitor mounted close to VCC provides additional transient immunity. Figure 6. Adjustable BATT_TEST Load 18 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating 10 9 8 7 6 BATT 1 MR 2 PFI 3 WDI 4 VCC CEIN CEOUT OUT BATTON PFO GND OUT RESET TOP VIEW 16 15 14 13 + *EP 11 GND 10 PFO 9 WDO 5 6 7 8 BATTOK BATTON WDI TDFN *EP RESET 5 LL 4 PFI BATT 3 MR VCC + 2 RESET MAX16021 MAX16016 1 12 TQFN Typical Application Circuit 3.3V 0.1µF SECONDARY DC VOLTAGE 0.1µF VCC R1 VCC PFI R2 RESET RST LL NMI WDI I/O WDO I/O µP A0–A15 MAX16020L OUT 0.1µF (MIN) PFO RAM MR CEOUT BATT GND CEIN CE RTC ADDRESS DECODE 0.1µF ______________________________________________________________________________________ 19 MAX16016/MAX16020/MAX16021 Pin Configurations (continued) MAX16016/MAX16020/MAX16021 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Selector Guide ALL LOGIC OUTPUTS (EXCEPT BATT_TEST) MR POWER-FAIL COMPARATOR MAX16016LTB_ Push-pull √ √ WDI √ — — — MAX16016PTB_ Open-drain √ √ WDI √ — — — MAX16020LTE_ Push-pull √ √ WDI/WDO √ √ BATTOK/ BATT_TEST √ MAX16020PTE_ Open-drain √ √ WDI/WDO √ √ BATTOK/ BATT_TEST √ MAX16021LTE_ Push-pull √ √ WDI/WDO √ √ BATTOK/ RESET √ MAX16021PTE_ Open-drain √ √ WDI/WDO √ √ BATTOK/ RESET √ PART WATCHDOG BATTON TIMER Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE MAX16020_TE_+T -40°C to +85°C 16 TQFN-EP* MAX16021_TE_+T -40°C to +85°C 16 TQFN-EP* The first placeholder “_” designates all output options. Letter “L” indicates push-pull outputs and letter “P” indicates opendrain outputs. The last placeholder “_” designates the reset threshold (see Table 1). T = Tape and reel. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. 20 LOWBATTOK/ LINE BATT_TEST/ OUTPUT RESET CHIPENABLE Chip Information PROCESS: BiCMOS Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 TDFN T1033-1 21-0137 16 TQFN T1644-4 21-0139 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating REVISION NUMBER REVISION DATE 0 5/08 Initial release 1 7/08 Released the MAX16016. Updated Ordering Information, Electrical Characteristics, Tables 1 and 2, Pin Description, and Detailed Description. 2 10/08 Released the MAX16021. 12/08 Updated Electrical Characteristics, Pin Description, Table 3, and the PowerFail Comparator section. 3 DESCRIPTION PAGES CHANGED — 1, 3, 4, 5, 9, 10, 12, 13, 15, 16, 19, 20 20 3, 9, 10, 11, 14, 16 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX16016/MAX16020/MAX16021 Revision History