3.3 VOLT CMOS SyncBiFIFOTM 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 • FEATURES • • • • • • • • • • Memory storage capacity: IDT72V3652 – 2,048 x 36 x 2 IDT72V3662 – 4,096 x 36 x 2 IDT72V3672 – 8,192 x 36 x 2 Supports clock frequencies up to 100MHz Fast access times of 6.5ns Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in opposite directions Mailbox bypass register for each FIFO Programmable Almost-Full and Almost-Empty flags Microprocessor Interface Control Logic FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB • • • • IDT72V3652 IDT72V3662 IDT72V3672 Select IDT Standard timing (using EFA, EFB, FFA and FFB flags functions) or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions) Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving 120-pin Thin Quad Flatpack (TQFP) Pin and functionally compatible versions of the 5V operating IDT723652/723662/723672 Pin compatible to the lower density parts, IDT72V3622/72V3632/ 72V3642 Industrial temperature range (–40°°C to +85°°C) is available DESCRIPTION The IDT72V3652/72V3662/72V3672 are pin and functionally compatible versions of the IDT723652/723662/723672, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, highspeed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which support clock frequencies up to 100MHz and have read access times as fast FUNCTIONAL BLOCK DIAGRAM MBF1 Port-A Control Logic RST1 FIFO1, Mail1 Reset Logic RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 Input Register CLKA CSA W/RA ENA MBA Write Pointer 36 FFA/IRA AFA 36 Read Pointer EFB/ORB AEB Status Flag Logic FIFO 1 FS0 FS1 A0 - A35 Output Register Mail 1 Register Programmable Flag Offset Registers Timing Mode FWFT B0 - B35 13 EFA/ORA AEA Status Flag Logic Read Pointer Output Register 36 FFB/IRB AFB 36 Write Pointer RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 Input Register FIFO 2 Mail 2 Register FIFO2, Mail2 Reset Logic RST2 Port-B Control Logic CLKB CSB W/RB ENB MBB 4660 drw01 MBF2 IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE NOVEMBER 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4660/3 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT pin during FIFO operation determines the mode in use. Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/ IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the DESCRIPTION (CONTINUED) as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 NC NC VCC CLKB ENB W/RB CSB GND FFB/IRB EFB/ORB AFB AEB VCC MBF1 MBB RST2 FS1 GND FS0 RST1 MBA MBF2 AEA AFA VCC EFA/ORA FFA/IRA CSA W/RA ENA CLKA GND NC PIN CONFIGURATION 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC *Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner. NOTES: 1. NC – no internal connection 2. Uses Yamaichi socket IC51-1324-828 PQFP(2) (PQ132-1, order code: PQF) TOP VIEW 2 NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 FWFT A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC 4660 drw02 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE threshold can be set at 8, 16 or 64 locations from the empty boundary and the AFA and AFB threshold can be set at 8, 16 or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Reset. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V3652/72V3662/72V3672 are characterized for operation from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by special order. They are fabricated using IDT’s high speed, submicron CMOS technology. memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFA and AFB indicate when the FIFO contains more than a selected number of words. FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are two-stage synchronized to the port clock that reads data from its array. Programmable offsets for AEA, AEB, AFA and AFB are loaded by using Port A. Three default offset settings are also provided. The AEA and AEB 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 GND CLKA ENA W/RA CSA FFA/IRA EFA/ORA VCC AFA AEA MBF2 MBA RST1 FS0 GND FS1 RST2 MBB MBF1 VCC AEB AFB EFB/ORB FFB/IRB GND CSB W/RB ENB CLKB VCC PIN CONFIGURATION (CONTINUED) 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 B10 B11 A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 FWFT A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 TQFP (PN120-1, order code: PF) TOP VIEW 3 4660 drw03 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS Symbol Name I/O Description A0-A35 Port A Data I/0 AEA Port A AlmostEmpty Flag O (Port A) Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2. AEB Port B AlmostEmpty Flag O (Port B) Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1. AFA Port A AlmostFull Flag O (Port A) Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1. AFB Port B AlmostFull Flag O (Port B) Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2. B0 - B35 Port B Data I/O CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0- B35 outputs are in the high-impedance state when CSB is HIGH. EFA/ORA Port A Empty/ Output Ready Flag O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. EFB/ORB Port B Empty/ Output Ready Flag O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on B0-B35 outputs, available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. FFA/IRA Port A Full/ Input Ready Flag O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA. FFB/IRB Port B Full/ Input Ready Flag O This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB. FWFT First Word Fall Through Mode I This pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static throughout device operation. FS1, FS0 Flag Offset Selects I A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the AlmostEmpty and Almost-Full offsets for both FIFOs. 36-bit bidirectional data port for side A. 36-bit bidirectional data port for side B. 4 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O Description MBA Port A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2 output register data for output. MBB Port B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a LOW level selects FIFO1 output register data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset. MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset. RST1 FIFO1 Reset I To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM. RST2 FIFO2 Reset I To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM. W/RA Port A Write/ Read Select I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH. W/RB Port B Write/ Read Select I A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW. 5 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)(1) Symbol VCC (2) Rating Supply Voltage Range Commercial Unit –0.5 to +4.6 V VI Input Voltage Range –0.5 to VCC+0.5 V VO(2) Output Voltage Range –0.5 to VCC+0.5 V IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA IOUT Continuous Output Current (VO = 0 to VCC) ±50 mA ICC Continuous Current Through VCC or GND ±400 mA TSTG Storage Temperature Range –65 to 150 °C NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS Symbol (1) Parameter Min. Typ. Max. Unit Supply Voltage for 10ns 3.15 3.3 3.45 V VCC Supply Voltage for 15ns 3.0 3.3 3.6 V VIH High-Level Input Voltage 2 — VCC+0.5 V VCC VIL Low-Level Input Voltage — — 0.8 V IOH High-Level Output Current — — –4 mA IOL Low-Level Output Current — — 8 mA TA Operating Temperature 0 — 70 °C NOTE: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol Parameter Test Conditions IDT72V3652 IDT72V3662 IDT72V3672 Commercial tCLK = 10, 15 ns(2) Min. Typ.(1) Max. 2.4 VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V ILI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±10 µA Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±10 µA ICC2 Standby Current (with CLKA & CLKB running) VCC = 3.6V, VI = VCC –0.2V or 0V — — 5 mA ICC3(3) Standby Current (no clocks running) VCC = 3.6V, VI = VCC –0.2V or 0V — — 1 mA ILO (3) CIN (4) COUT(4) — — Unit V Input Capacitance VI = 0, f = 1 MHz — 4 — pF Output Capacitance VO = 0, f = 1 MHZ — 8 — pF NOTES: 1. All typical values are at VCC = 3.3V, TA = 25°C. 2. Commercial-10ns speed grade only: Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant. 3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS). 4. Characterized values, not currently tested. 6 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3652/72V3662/72V3672 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x ICC(f) + Σ(CL x VCC2 X fo) N where: N = number of outputs = 36 CL = output capacitance load fo = switching frequency of an output 100 90 VCC = 3.6V 80 70 VCC = 3.0V VCC = 3.3V fdata = 1/2 fS 60 TA = 25°C CL = 0 pF 40 30 ICC(f) Supply Current mA 50 20 10 0 0 10 20 30 40 50 60 70 80 fS Clock Frequency MHz Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) 7 90 100 4660 drw03a IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant) Symbol IDT72V3652L10(1) IDT72V3662L10(1) IDT72V3672L10(1) Min. Max. Parameter IDT72V3652L15 IDT72V3662L15 IDT72V3672L15 Min. Max. Unit fS Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns tCLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns tCLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 3 — 4 — ns tENS1 Setup Time, CSA and W/RA, before CLKA↑; CSB, and W/RB before CLKB↑ 4 — 4.5 — ns tENS2 Setup Time, ENA and MBA, before CLKA↑; ENB, and MBB before CLKB↑ 3 — 4.5 — ns tRSTS Setup Time, RST1 or RST2 LOW before CLKA↑ or CLKB↑(2) 5 — 5 — ns tFSS Setup Time, FS0 and FS1 before RST1 and RST2 HIGH 7.5 — 7.5 — ns tFWS Setup Time, FWFT before CLKA↑ 0 — 0 — ns tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑ 0.5 — 1 — ns tRSTH Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑(2) 4 — 4 — ns tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — ns tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB 7.5 — 7.5 — ns tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 12 — 12 — ns NOTES: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested. 8 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF (For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant) Symbol IDT72V3652L10(1) IDT72V3662L10(1) IDT72V3672L10(1) Min. Max. Parameter IDT72V3652L15 IDT72V3662L15 IDT72V3672L15 Min. Max. Unit tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 6.5 2 10 ns tPIR Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to FFB/IRB 2 6.5 2 8 ns tPOR Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB/ORB 1 6.5 1 8 ns tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1 6.5 1 8 ns tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 1 6.5 1 8 ns tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH 0 6.5 0 8 ns tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3) 2 8 2 10 ns tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid 2 6.5 2 10 ns tPRF Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH 1 10 1 15 ns tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH to B0-B35 Active 2 6 2 10 ns tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or W/RB LOW to B0-B35 at high-impedance 1 6 1 8 ns NOTES: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°. 2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 9 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SIGNAL DESCRIPTION RESET After power up, a Master Reset operation must be performed by providing a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO memories of the IDT72V3652/72V3662/72V3672 are reset separately by taking their Reset (RST1, RST2) inputs LOW for at least four port-A Clock (CLKA) and four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready flag (ORA, ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the Almost-Full flag (AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a FIFO is reset, its Input Ready flag is set HIGH after two clock cycles to begin normal operation. A LOW-to-HIGH transition on a FIFO Reset (RST1, RST2) input latches the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and Almost-Empty offset programming method. (For details see Table 1, Flag Programming, and the Programming the Almost-Empty and Almost-Full Flags section). The relevant FIFO Reset timing diagram can be found in Figure 2. FIRST WORD FALL THROUGH (FWFT) After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: IDT Standard mode or First Word Fall Through (FWFT) mode. Once the Reset (RST1, RST2) input is HIGH, a HIGH on the FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode uses the Empty Flag function (EFA, EFB) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function (FFA, FFB) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. Once the Reset (RST1, RST2) input is HIGH, a LOW on the FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Following Reset, the level applied to the FWFT input to choose the desired timing mode must remain static throughout FIFO operation. Refer to Figure 2 (Reset) for a First Word Fall Through select timing diagram. ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING Four registers in these devices are used to hold the offset values for the Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (AEB) Offset register is labeled X1 and the port A Almost-Empty flag (AEA) Offset register is labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1 and the port B Almost-Full flag (AFB) Offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1). FS0 and FS1 function the same way in both IDT Standard and FWFT modes. — PRESET VALUES To load the FIFO's Almost-Empty flag and Almost-Full flag Offset registers with one of the three preset values listed in Table 1, at least one of the flag select inputs must be HIGH during the LOW-to-HIGH transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 Reset (RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset value loading timing diagram, see Figure 2. — PARALLEL LOAD FROM PORT A To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH transition of the Reset inputs. It is important to note that once parallel programming has been selected during a Master Reset by holding both FS0 & FS1 LOW, these inputs must remain LOW during all subsequent FIFO operation. They can only be toggled HIGH when future Master Resets are performed and other programming methods are desired. After this reset is complete, the first four writes to FIFO1 do not store data in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2. TABLE 1 — FLAG PROGRAMMING FS1 FS0 RST1 RST2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2) H H ↑ X 64 X H H X ↑ X 64 H L ↑ X 16 X H L X ↑ X 16 L H ↑ X 8 X L H X ↑ X 8 L ↑ ↑ Parallel programming via Port A(3) Parallel programming via Port A(3) L NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. 3. If parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation. 10 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE outputs are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3) . FIFO reads and writes on port B are independent of any concurrent port A operation. Write and Read cycle timing diagrams for Port B can be found in Figure 5 and 6. The setup and hold time constraints to the port Clocks for the port Chip Selects and Write/Read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. When operating the FIFO in FWFT mode and the Output Ready flag is LOW, the next word written is automatically sent to the FIFO’s output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the output registers only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in IDT Standard mode, the first word will cause the Empty Flag to change state on the second LOW-to-HIGH transition of the Read Clock. The data word will not be automatically sent to the output register. Instead, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. The port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9A0) for the IDT72V3652, IDT72V3662, or IDT72V3672, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers ranges from 1 to 2,044 for the IDT72V3652; 1 to 4,092 for the IDT72V3662; and 1 to 8,188 for the IDT72V3672. After all the offset registers are programmed from port A, the port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation. See Figure 3 for relevant offset register parallel programming timing diagram. FIFO WRITE/READ OPERATION The state of the port A data (A0-A35) outputs is controlled by port A Chip Select (CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and writes on port A are independent of any concurrent port B operation. Write and Read cycle timing diagrams for Port A can be found in Figure 4 and 7. The port B control signals are identical to those of port A with the exception that the port B Write/Read select (W/RB) is the inverse of the port A Write/Read select (W/RA). The state of the port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35 TABLE 2 — PORT A ENABLE FUNCTION TABLE CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O Port Function H X X X X High-Impedance None L H L X X Input None L H H L ↑ Input FIFO1 write L H H H ↑ Input Mail1 write L L L L X Output None L L H L ↑ Output FIFO2 read L L L H X Output None L L H H ↑ Output Mail2 read (set MBF2 HIGH) TABLE 3 — PORT B ENABLE FUNCTION TABLE CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O Port Function H X X X X High-Impedance None L L L X X Input None L L H L ↑ Input FIFO2 write L L H H ↑ Input Mail2 write L H L L X Output None L H H L ↑ Output FIFO1 read L H L H X Output None L H H H ↑ Output Mail1 read (set MBF1 HIGH) 11 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/ ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB) These are dual purpose flags. In the FWFT mode, the Output Ready (ORA, ORB) function is selected. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. In the IDT Standard mode, the Empty Flag (EFA, EFB) function is selected. When the Empty Flag is HIGH, data is available in the FIFO’s RAM for reading to the output register. When the Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT and IDT Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. In FWFT mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FlFO output register and three cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. In IDT Standard mode, from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW TABLE 4 — FIFO1 FLAG OPERATION (IDT STANDARD AND FWFT MODES) Synchronized to CLKB Number of Words in FIFO(1,2) Synchronized to CLKA IDT72V3652(3) IDT72V3662(3) IDT72V3672(3) EFB/ORB AEB AFA FFA/IRA 0 0 0 L L H H 1 to X1 1 to X1 1 to X1 H L H H (X1+1) to [2,048-(Y1+1)] (X1+1) to [4,096-(Y1+1)] (X1+1) to [8,192-(Y1+1)] H H H H (2,048-Y1) to 2,047 (4,096-Y1) to 4,095 (8,192-Y1) to 8,191 H H L H 2,048 4,096 8,192 H H L L NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from port A. 4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode. TABLE 5 — FIFO2 FLAG OPERATION (IDT STANDARD AND FWFT MODES) Synchronized to CLKA Number of Words in FIFO(1,2) IDT72V3652(3) IDT72V3662(3) IDT72V3672(3) Synchronized to CLKB EFA/ORA AEA AFB FFB/IRB 0 0 0 L L H H 1 to X2 1 to X2 1 to X2 H L H H (X2+1) to [2,048-(Y2+1)] (X2+1) to [4,096-(Y2+1)] (X2+1) to [8,192-(Y2+1)] H H H H (2,048-Y2) to 2,047 (4,096-Y2) to 4,095 (8,192-Y2) to 8,191 H H L H 2,048 4,096 8,192 H H L L NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from port A. 4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode. 12 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE if a word in memory is the next data to be sent to the FlFO output register and two cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then can data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 8 through 11 for EFA/ORA and EFB/ORB timing diagrams). if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. (See Figures 16 and 17). ALMOST-FULL FLAGS (AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FlFO reset or programmed from port A (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Full flag is LOW when the number of words in its FIFO is greater than or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT72V3652, IDT72V3662, or IDT72V3672 respectively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [2,048-(Y+1)], [4,096-(Y+1)], or [8,192-(Y+1)] for the IDT72V3652, IDT72V3662, or IDT72V3672 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [2,048/4,096/8,192(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second LOWto-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle (see Figures 18 and 19). FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB) This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB) function is selected. In IDT Standard mode, the Full Flag (FFA and FFB) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. The Full/Input Ready flag of a FlFO is synchronized to the port clock that writes data to its array. For both FWFT and IDT Standard modes, each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls a Full/Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FlFO memory status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input Ready flag HIGH. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 12 through 15 for FFA/IRA and FFB/IRB timing diagrams). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The Mailbox select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A Write is selected by CSA, W/RA, and ENA and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port B Write is selected by CSB, W/RB, and ENB and with MBB HIGH. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port Mailbox select input is LOW and from the mail register when the port mailbox select input is HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port B Read is selected by CSB, W/RB, and ENB and with MBB HIGH. The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. For mail register and Mail Register Flag timing diagrams, see Figure 20 and 21. ALMOST-EMPTY FLAGS ( AEA , AEB ) The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset or programmed from port A (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock are required after a FIFO write for its Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchronization cycle 13 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKA tRSTH CLKB tRSTS tFSS tFSH RST1 tFWS FWFT 0,1 FS1,FS0 tPIR tPIR FFA/IRA tPOR EFB/ORB tPRF AEB tPRF AFA tPRF MBF1 4660 drw04 NOTES: 1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value. 2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW. Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes) CLKA 4 tFSS 1 2 RST1, RST2 tFSH FS1,FS0 0,0 tPIR FFA/IRA tENS2 (1) tENH tSKEW1 ENA tDS tDH A0 - A35 AFA Offset (Y1) AEB Offset (X1) CLKB AFB Offset (Y2) AEA Offset (X2) First Word to FIFO1 1 2 tPIR FFB/IRB 4660 drw05 NOTES: 1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown. 2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles. Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes) 14 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKL tCLKH CLKA FFA/IRA HIGH tENS1 tENH CSA tENS1 tENH tENS2 tENH tENS2 tENH W/RA MBA tENS2 tENH tENS2 tENH ENA tDS tDH W1(1) A0 - A35 W2 (1) No Operation 4660 drw06 NOTE: 1. Written to FIFO1. Figure 4. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes) tCLK tCLKH tCLKL CLKB FFB/IRB HIGH CSB tENS1 tENS1 tENH tENH W/RB tENS2 tENH MBB tENS2 tENH tENS2 tENH tENS2 tENH ENB B0 - B35 tDS W1(1) tDH W2(1) No Operation 4660 drw07 NOTE: 1. Written to FIFO2. Figure 5. Port B Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes) 15 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB EFB/ORB HIGH CSB W/RB tENS2 MBB tENH tENS2 tENH tENS2 tENH ENB tMDV tA tEN B0-B35 tA W1(1) Previous Data (IDT Standard Mode) OR tMDV tEN B0-B35 tA tDIS W2 (1) tDIS tA W1(1) (FWFT Mode) No Operation W2(1) W3 (1) 4660 drw08 NOTE: 1. Read From FIFO1. Figure 6. Port B Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes) tCLK tCLKH tCLKL CLKA EFA/ORA HIGH CSA W/RA tENS2 MBA tENH tENS2 tENH tENH tENS2 ENA A0-A35 tEN (Standard Mode) OR A0-A35 (FWFT Mode) tEN tMDV tA tA Previous Data tMDV No Operation tDIS tA tA W2 (1) W1 (1) tDIS W2 (1) W1(1) W3 (1) 4660 drw09 NOTE: 1. Read From FIFO2. Figure 7. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes) 16 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA CSA LOW WRA HIGH tENS2 tENH tENS2 tENH MBA ENA IRA HIGH tDH tDS A0 - A35 W1 tSKEW1 CLKB (1) tCLKH 1 tCLK tCLKL 2 3 tPOR ORB FIFO1Empty CSB LOW W/RB HIGH MBB LOW tPOR tENS2 tENH ENB tA B0 -B35 Old Data in FIFO1 Output Register W1 4660 drw10 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB cycle later than shown. Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode) 17 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA CSA LOW WRA HIGH tENS2 tENH tENS2 tENH tDS tDH MBA ENA FFA HIGH A0-A35 W1 (1) tSKEW1 CLKB tCLK tCLKH tCLKL 1 2 tPOR EFB FIFO1 Empty CSB LOW W/RB HIGH MBB LOW tENS2 tPOR tENH ENB tA W1 B0-B35 4660 drw11 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown. Figure 9. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode) 18 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB CSB LOW W/RB LOW tENS2 tENH tENS2 tENH MBB ENB IRB HIGH tDS B0 - B35 tDH W1 (1) tSKEW1 CLKA tCLKH 1 tCLK tCLKL 2 3 tPOR tPOR ORA FIFO2 Empty CSA LOW W/RA LOW MBA LOW tENS2 tENH ENA tA A0 -A35 Old Data in FIFO2 Output Register W1 4660 drw12 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA cycle later than shown. Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode) 19 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKL tCLKH CLKB CSB LOW W/RB LOW tENS2 tENH tENS2 tENH tDS tDH MBB ENB FFB HIGH W1 B0-B35 (1) tSKEW1 CLKA tCLK tCLKH tCLKL 1 2 tPOR EFA FIFO2 Empty CSA LOW W/RA LOW MBA LOW tENS2 tPOR tENH ENA tA A0-A35 W1 4660 drw13 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. Figure 11. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode) 20 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB CSB LOW W/RB MBB HIGH LOW tENS2 tENH ENB ORB B0 -B35 HIGH tA Previous Word in FIFO1 Output Register tSKEW1 Next Word From FIFO1 (1) tCLKH tCLK 1 CLKA tCLKL 2 tPIR tPIR IRA FIFO1 Full CSA LOW W/RA HIGH tENS2 tENH tENS2 tENH MBA ENA tDS tDH Write A0 - A35 To FIFO1 4660 drw14 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown. Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode) 21 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 tCLKH tCLK COMMERCIAL TEMPERATURE RANGE tCLKL CLKB CSB LOW W/RB MBB HIGH LOW tENS2 tENH ENB EFB B0-B35 HIGH tA Previous Word in FIFO1 Output Register tSKEW1 CLKA Next Word From FIFO1 (1) tCLKH 1 tCLK tCLKL 2 tPIR tPIR FFA FIFO1 Full CSA LOW W/RA HIGH tENS2 tENH tENS2 tENH MBA ENA tDS A0-A35 tDH Write To FIFO1 4660 drw15 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown. Figure 13. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode) 22 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 tCLKH tCLK COMMERCIAL TEMPERATURE RANGE tCLKL CLKA CSA LOW W/RA LOW MBA LOW tENS2 tENH ENA ORA A0 -A35 HIGH tA Previous Word in FIFO2 Output Register tSKEW1(1) CLKB Next Word From FIFO2 tCLKH 1 tCLK tCLKL 2 tPIR IRB FIFO2 FULL CSB LOW tPIR W/RB LOW tENS2 tENH tENS2 tENH MBB ENB tDS B0 - B35 tDH Write To FIFO2 4660 drw16 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown. Figure 14. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode) 23 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKA CSA LOW W/RA MBA LOW LOW tENS2 tENH ENA EFA A0-A35 HIGH tA Previous Word in FIFO2 Output Register Next Word From FIFO2 tSKEW1(1) CLKB tCLKH 1 tCLK tCLKL 2 tPIR tPIR FFB FIFO2 Full CSB LOW W/RB LOW tENS2 tENH tENS2 tENH MBB ENB tDS B0-B35 tDH Write To FIFO2 4660 drw17 NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown. Figure 15. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode) CLKA tENS2 tENH ENA tSKEW2 (1) 1 CLKB 2 tPAE tPAE AEB X1 Words in FIFO1 (X1+1) Words in FIFO1 tENS2 tENH ENB 4660 drw18 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. Figure 16. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes) 24 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB tENS2 tENH ENB tSKEW2 (1) 1 CLKA 2 tPAE tPAE AEA (X2+1) Words in FIFO2 X2 Words in FIFO2 tENS2 tENH ENA 4660 drw19 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. Figure 17. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes) tSKEW2 (1) 1 CLKA tENS2 2 tENH ENA tPAF AFA tPAF (D-Y1) Words in FIFO1 [D-(Y1+1)] Words in FIFO1 CLKB tENS2 tENH ENB 4660 drw20 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 2,048 for the IDT72V3652, 4,096 for the IDT72V3662, 8,192 for the IDT72V3672. Figure 18. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes) 25 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tSKEW2 (1) 1 CLKB tENS2 2 tENH ENB tPAF AFB tPAF (D-Y2) Words in FIFO2 [D-(Y2+1)] Words in FIFO2 CLKA tENS2 tENH ENA 4660 drw21 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown. 2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 2,048 for the IDT72V3652, 4,096 for the IDT72V3662, 8,192 for the IDT72V3672. Figure 19. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes) CLKA tENS1 tENH tENS1 tENH tENS2 tENH tENS2 tENH CSA W/RA MBA ENA tDS W1 A0 - A35 tDH CLKB tPMF tPMF MBF1 CSB W/RB MBB tENS2 tENH ENB tEN B0 - B35 tMDV tPMR tDIS W1 (Remains valid in Mail1 Register after read) FIFO1 Output Register 4660 drw22 Figure 20. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes) 26 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 CLKB tENS1 tENH tENS1 tENH tENS2 tENH tENS2 tENH COMMERCIAL TEMPERATURE RANGE CSB W/RB MBB ENB tDS W1 B0 - B35 tDH CLKA tPMF tPMF MBF2 CSA W/RA MBA tENS2 tENH ENA tEN A0 - A35 tMDV tPMR FIFO2 Output Register tDIS W1 (Remains valid in Mail 2 Register after read) 4660 drw23 Figure 21. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes) 27 IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION 3.3V 330 Ω From Output Under Test 30 pF 510 Ω (1) PROPAGATION DELAY LOAD CIRCUIT 3V Timing Input 1.5V GND tS 3V High-Level Input 1.5V th 3V 1.5V 1.5V GND tW 3V Data, Enable Input 1.5V Low-Level Input GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5V 1.5V GND VOLTAGE WAVEFORMS PULSE DURATIONS 3V Output Enable 1.5V tPLZ 1.5V tPZL GND ≈ 3V Input 1.5V Low-Level Output VOL tPZH VOH High-Level tPHZ Output 1.5V 3V 1.5V 1.5V tPD tPD GND VOH In-Phase Output 1.5V 1.5V ≈ OV VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTE: 1. Includes probe and jig capacitance. Figure 22. Load Circuit and Voltage Waveforms 28 VOL 4660 drw24 ORDERING INFORMATION IDT XXXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range BLANK Commercial (0°C to +70°C) PF PQF Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) 10 15 Commercial Only L Low Power 72V3652 72V3662 72V3672 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 Clock Cycle Time (tCLK) Speed in Nanoseconds 3.3V SyncBiFIFO 3.3V SyncBiFIFO 3.3V SyncBiFIFO 4660 drw 25 NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 06/12/2000 09/25/2000 12/21/2000 03/21/2001 11/03/2003 pgs. pgs. pg. pgs. pg. 1,7 and 11. 6, 8, 9 and 29. 11. 6 and 7. 1. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 29 for TECH SUPPORT: 408-330-1753 e-mail: [email protected]