PD - 91326D
IRL2505S/L
Logic-Level Gate Drive
l Advanced Process Technology
l Surface Mount (IRL2505S)
l Low-profile through-hole (IRL2505L)
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
Description
HEXFET® Power MOSFET
l
D
VDSS = 55V
RDS(on) = 0.008Ω
G
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL2505L) is available for lowprofile applications.
ID = 104A
S
D 2 P ak
T O -26 2
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
104
Units
74
360
3.8
200
1.3
±16
500
54
20
5.0
-55 to + 175
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
Max.
Units
–––
–––
0.75
40
°C/W
5/12/98
IRL2505S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
–––
–––
–––
–––
1.0
59
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
V(BR)DSS
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = 250µA
0.035 ––– V/°C Reference to 25°C, ID = 1mA
––– 0.008
VGS = 10V, ID = 54A
––– 0.010 Ω
VGS = 5.0V, ID = 54A
––– 0.013
VGS = 4.0V, ID = 45A
––– 2.0
V
VDS = VGS, ID = 250µA
––– –––
S
VDS = 25V, ID = 54A
––– 25
VDS = 55V, VGS = 0V
µA
––– 250
VDS = 44V, VGS = 0V, TJ = 150°C
––– 100
VGS = 16V
nA
––– -100
VGS = -16V
––– 130
ID = 54A
––– 25
nC
VDS = 44V
––– 67
VGS = 5.0V, See Fig. 6 and 13
12 –––
VDD = 28V
160 –––
ID = 54A
ns
43 –––
RG = 1.3Ω, VGS = 5.0V
84 –––
RD = 0.50Ω, See Fig. 10
Between lead,
7.5 –––
nH
and center of die contact
5000 –––
VGS = 0V
1100 –––
pF
VDS = 25V
390 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 240µH
RG = 25Ω, IAS = 54A. (See Figure 12)
ISD ≤ 54A, di/dt ≤ 230A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 104
showing the
A
G
integral reverse
––– ––– 360
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 54A, VGS = 0V
––– 140 210
ns
TJ = 25°C, IF = 54A
––– 650 970
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Uses IRL2505 data and test conditions
Caculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the
package refer to Design Tip # 93-4
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
IRL2505S/L
1000
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
ID , Drain-to-Source Current (A )
ID , D rain-to-S ource C urrent (A )
TOP
100
10
2 .5 V
2 0µ s P U LS E W ID T H
T J = 2 5°C
1
0.1
1
10
100
2 .5 V
10
2 0µ s P U LS E W ID TH
T J = 1 75 °C
1
A
100
0.1
1
V D S , D rain-to-S ource V oltage (V )
Fig 2. Typical Output Characteristics
3.0
R D S (on) , D ra in-to -S o urc e O n R e s is ta nc e
(N o rm alize d)
I D , D ra in -to-S ourc e C urrent (A)
1000
T J = 25 °C
T J = 1 75 °C
10
V DS= 25V
2 0 µ s P U LS E W ID TH
1
2.5
3.5
4.5
5.5
6.5
A
100
V D S , D rain-to-S ource V oltage (V )
Fig 1. Typical Output Characteristics
100
10
7.5
V G S , G ate-to -Sou rce Voltage (V)
Fig 3. Typical Transfer Characteristics
A
I D = 90 A
2.5
2.0
1.5
1.0
0.5
V G S = 1 0V
0.0
-60
-40 -20
0
20
40
60
80
A
100 120 140 160 180
T J , J unc tion T em perature (°C )
Fig 4. Normalized On-Resistance
Vs. Temperature
IRL2505S/L
V GS
C is s
C rs s
C o ss
C , Capacitance (pF)
8000
=
=
=
=
15
0V ,
f = 1M H z
C g s + C g d , Cd s S H O R T E D
C gd
C d s + C gd
V G S , G a te-to-S ou rc e V o ltag e (V )
10000
C iss
C oss
2000
C rss
0
10
9
6
3
FO R TE S T CIR C U IT
S E E FIG U R E 1 3
0
A
1
V D S = 44 V
V D S = 28 V
12
6000
4000
I D = 5 4A
100
0
V D S , D rain-to-S ourc e V oltage (V )
80
120
160
A
200
Q G , T otal G ate C harge (nC )
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
O P E R A T IO N IN T H IS A R E A L IM ITE D
B Y R D S (o n )
10µs
I D , D rain Current (A )
I S D , R everse Drain C urrent (A )
40
100
T J = 17 5°C
T J = 2 5°C
100
100µ s
1m s
10
10m s
V G S = 0V
10
0.4
0.8
1.2
1.6
2.0
2.4
V S D , S ourc e-to-D rain V oltage (V )
Fig 7. Typical Source-Drain Diode
Forward Voltage
A
2.8
T C = 25 °C
T J = 17 5°C
S ing le P u lse
1
1
A
10
V D S , D rain-to-S ource V oltage (V )
Fig 8. Maximum Safe Operating Area
100
IRL2505S/L
120
LIMITED BY PACKAGE
VGS
I D , Drain Current (A)
100
D.U.T.
RG
+
-V DD
80
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60
Fig 10a. Switching Time Test Circuit
40
VDS
90%
20
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
10%
VGS
td(on)
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
P DM
0.05
t1
0.02
0.01
0.01
0.00001
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1
IRL2505S/L
VDS
D.U.T.
RG
+
V
- DD
IAS
10 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
VDD
E A S , S ingle P ulse A valanche E nergy (m J)
1200
L
ID
22 A
3 8A
54 A
TO P
1000
B O TTO M
800
600
400
200
0
V D D = 25 V
25
A
50
75
100
125
150
175
S tarting T J , J unc tion T em perature (°C )
VDS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS
QGD
D.U.T.
VGS
VG
3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
+
V
- DS
IRL2505S/L
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
Period
-
V DD
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
ISD
*
IRL2505S/L
D2Pak Package Outline
1 0.54 (.4 15)
1 0.29 (.4 05)
1.4 0 (.055 )
M AX.
-A-
1.3 2 (.05 2)
1.2 2 (.04 8)
2
1.7 8 (.07 0)
1.2 7 (.05 0)
1
1 0.16 (.4 00 )
RE F.
-B -
4.69 (.1 85)
4.20 (.1 65)
6.47 (.2 55 )
6.18 (.2 43 )
3
15 .4 9 (.6 10)
14 .7 3 (.5 80)
2.7 9 (.110 )
2.2 9 (.090 )
2.61 (.1 03 )
2.32 (.0 91 )
5 .28 (.20 8)
4 .78 (.18 8)
3X
1.40 (.0 55)
1.14 (.0 45)
5 .08 (.20 0)
0.5 5 (.022 )
0.4 6 (.018 )
0 .93 (.03 7 )
3X
0 .69 (.02 7 )
0 .25 (.01 0 )
M
8.8 9 (.3 50 )
R E F.
1.3 9 (.0 5 5)
1.1 4 (.0 4 5)
B A M
M IN IM U M R E CO M M E ND E D F O O TP R IN T
1 1.43 (.4 50 )
NO TE S:
1 D IM EN S IO N S A FTER SO L D ER D IP.
2 D IM EN S IO N IN G & TO LE RA N C IN G PE R A N S I Y1 4.5M , 198 2.
3 C O N TRO L LIN G D IM EN SIO N : IN C H .
4 H E ATSINK & L EA D D IM EN S IO N S D O N O T IN C LU D E B UR R S.
LE A D A SS IG N M E N TS
1 - G A TE
2 - D R AIN
3 - S O U RC E
8.89 (.3 50 )
17 .78 (.70 0)
3 .8 1 (.15 0)
2 .08 (.08 2)
2X
Part Marking Information
D2Pak
IN TE R N A TIO N A L
R E C T IF IE R
LO G O
A S S E M B LY
LO T C O D E
A
PART NUM BER
F530S
9 24 6
9B
1M
DATE CODE
(Y YW W )
YY = Y E A R
W W = W EEK
2.5 4 (.100 )
2X
IRL2505S/L
Package Outline
TO-262 Outline
Part Marking Information
TO-262
IRL2505S/L
Tape & Reel Information
D2Pak
TR R
1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
4 .1 0 (.1 6 1 )
3 .9 0 (.1 5 3 )
F E E D D IRE CTIO N 1 .8 5 (.0 7 3 )
1 .6 5 (.0 6 5 )
1 .60 (.06 3)
1 .50 (.05 9)
1 1 .6 0 (.4 5 7 )
1 1 .4 0 (.4 4 9 )
0 .3 68 (.0 1 4 5 )
0 .3 42 (.0 1 3 5 )
1 5 .4 2 (.6 0 9 )
1 5 .2 2 (.6 0 1 )
2 4 .3 0 (.9 5 7 )
2 3 .9 0 (.9 4 1 )
TR L
10 .9 0 (.42 9)
10 .7 0 (.42 1)
1 .75 (.06 9 )
1 .25 (.04 9 )
4 .7 2 (.1 3 6)
4 .5 2 (.1 7 8)
16 .10 (.63 4 )
15 .90 (.62 6 )
F E E D D IRE C TIO N
13.50 (.532 )
12.80 (.504 )
2 7.4 0 (1.079)
2 3.9 0 (.9 41)
4
33 0.00
(1 4.1 73)
MA X.
NO TES :
1. C O M F O R M S TO E IA -4 18.
2. C O N TR O LLIN G D IM E N S IO N : M ILL IM ET ER .
3. D IM E N S IO N ME A S U R E D @ H U B .
4. IN C LU D E S F LA N G E D IS TO R T IO N @ O U T E R E D G E .
60.00 (2.3 62)
MIN .
26 .40 (1.03 9)
24 .40 (.961 )
3
3 0.40 (1.1 97)
MAX.
4
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/
Data and specifications subject to change without notice.
5/98