ISSI IS24C32A-2PLI 64k-bit/32k-bit 2-wire serial cmos eeprom Datasheet

IS24C32A/B
IS24C64A/B
ISSI
64K-bit/32K-bit
2-WIRE SERIAL CMOS EEPROM
®
APRIL 2006
FEATURES
DESCRIPTION
• Two-Wire Serial Interface, I2CTM Compatible
–Bi-directional data transfer protocol
• Wide Voltage Operation
–Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1MHz (5.0V) Compatible
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Hardware Data Protection
–IS24C32A/64A: WP protects entire array
–IS24C32B/64B: WP protects top quarter of
array
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max.@ 2.5V
• Organization:
–IS24C32A/B: 4Kx8 (128 pages of 32 bytes)
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)
• 32 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Automotive and Industrial temperature ranges
• 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, and 8-pin
MSOP packages
• Lead-free Available
The IS24C32A/B and IS24C64A/B are electrically
erasable PROM devices that use the standard 2wire interface for communications. The IS24C32A/B
and IS24C64A/B contain a memory array of 32Kbits (4K x 8) and 64K-bits (8K x 8), respectively.
Each device is organized into 32 byte pages for
page write mode.
This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution.
The devices are available in 8-pin PDIP, 8-pin
SOIC, 8-pin TSSOP, and 8-pin MSOP packages.
The IS24C32A/32B/64A/64B (IS24CXX) maintains
compatibility with the popular 2-wire bus protocol,
so it is easy to use in applications implementing
this bus type. The simple bus consists of the
Serial Clock wire (SCL) and the Serial Data wire
(SDA). Using the bus, a Master device such as a
microcontroller is usually connected to one or
more Slave devices such as this device. The bit
stream over the SDA line includes a series of
bytes, which identifies a particular Slave device,
an instruction, an address within that Slave device,
and a series of data, if appropriate. The IS24CXX
has a Write Protect pin (WP) to allow blocking of
any write instruction transmitted over the bus.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
1
IS24C32A/B
IS24C64A/B
ISSI
®
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
8
SDA
5
SCL
6
WP
7
CONTROL
LOGIC
X
DECODER
Vcc
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
GND
4
EEPROM
ARRAY
WORD ADDRESS
COUNTER
Y
DECODER
ACK
Clock
DI/O
>
nMOS
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
DATA
REGISTER
PIN CONFIGURATION
8-Pin DIP, SOIC, TSSOP, and MSOP
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire-Ored with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
WP
WP is the Write Protect pin. The input level determines if all,
partial, or none of the array is protected from modifications.
Write Protection
Array Addresses Protected
WP
A0, A1, A2
GND or floating
The A0, A1 and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
with the 24C16. When pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus
system. When the pins are not hardwired, the default values
of A0, A1, and A2 are zero.
Vcc
2
IS24C32A/64A
IS24C32B
IS24C64B
None
None
None
Entire Array
C00h
-FFFh
1800h
-1FFFh
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
ISSI
®
DEVICE OPERATION
Stop Condition
IS24CXX features serial communication and supports a bidirectional 2-wire bus transmission protocol called I2CTM.
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by a
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24CXX is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a
Start or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24CXX contains a reset function in case the 2wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24CXX will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
signal if a no write operation is initiated; or c) Following any
internal write operation.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when SCL
is High. The EEPROM monitors the SDA and SCL lines and
will not respond until the Start condition is met.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
3
IS24C32A/B
IS24C64A/B
ISSI
DEVICE ADDRESSING
WRITE OPERATION
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave
device (Fig. 5) address is 8 bits.
Byte Write
The four most significant bits of the Slave address are fixed
as 1010 for the IS24CXX.
The next three bits of the Slave address are A0, A1, and
A2, and are used in comparison with the hard-wired input
values on the A0, A1, and A2 pins. Up to eight IS24CXX
units may share the 2-wire bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C64A) will respond with ACK on the SDA line. The
Slave will pull down the SDA on the ninth clock cycle,
signaling that it received the eight bits of data. The selected
EEPROM then prepares for a Read or Write operation by
monitoring the bus.
®
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the two byte address that is to
be written into the address pointer of the IS24CXX. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The IS24CXX acknowledges once more
and the Master generates the Stop condition, at which time
the device begins its internal programming cycle. While
this internal cycle is in progress, the device will not respond
to any request from the Master device.
Page Write
The IS24CXX is capable of 32-byte Page-Write operation. A
Page-Write is initiated in the same manner as a Byte Write,
but instead of terminating the internal Write cycle after the
first data word is transferred, the Master device can transmit
up to 31 more bytes. After the receipt of each data word, the
EEPROM responds immediately with an ACK on SDA line,
and the five lower order data word address bits are internally
incremented by one, while the higher order bits of the data
word address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the
first byte of that page. If the Master device should transmit
more than 32 bytes prior to issuing the Stop condition, the
address counter will “roll over,” and the previously written data
will be overwritten. Once all 32 bytes are received and the
Stop condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data is
written to the IS24CXX in a single Write cycle. All inputs are
disabled until completion of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24CXX initiates the internal Write cycle. ACK polling can
be initiated immediately. This involves issuing the Start
condition followed by the Slave address for a Write operation.
If the EEPROM is still busy with the Write operation, no ACK
will be returned. If the IS24CXX has completed the Write
operation, an ACK will be returned and the host can then
proceed with the next Read or Write operation.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
ISSI
®
READ OPERATION
Random Address Read
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
is set to “1”. There are three Read operation options: current
address read, random address read and sequential read.
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read.
After the IS24CXX acknowledges the byte address, the
Master device resends the Start condition and the Slave
address, this time with the R/W bit set to one. The
EEPROM then responds with its ACK and sends the data
requested. The Master device does not send an ACK but
will generate a Stop condition. (Refer to Figure 9. Random
Address Read Diagram.)
Current Address Read
The IS24CXX contains an internal address counter which
maintains the address of the last byte accessed, incremented
by one. For example, if the previous operation is either a
Read or Write operation addressed to the address location
n, the internal address counter would increment to address
location n+1. When the EEPROM receives the Slave
Addressing Byte with a Read operation (R/W bit set to “1”),
it will respond an ACK and transmit the 8-bit data byte stored
at address location n+1. The Master should not acknowledge
the transfer but should generate a Stop condition so the
IS24CXX discontinues transmission. If 'n' is the last byte
of the memory, the data from location '0' will be transmitted.
(Refer to Figure 8. Current Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the IS24CXX
sends the initial byte sequence, the Master device now
responds with an ACK indicating it requires additional data
from the IS24CXX. The EEPROM continues to output data
for each ACK received. The Master device terminates the
sequential Read operation by pulling SDA High (no ACK)
indicating the last data word to be read, followed by a Stop
condition.
The data output is sequential, with the data from address
n followed by the data from address n+1, n+2 ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundary of 8191 for IS24C64A/B or 4095 for IS24C32A/B
(depending on the device) is reached, the address counter
“rolls over” to address 0, and the device continues to output
data. (Refer to Figure 10. Sequential Read Diagram).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
5
IS24C32A/B
IS24C64A/B
ISSI
®
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS24CXX
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
tAA
Data Output
from
Receiver
tAA
ACK
STOP
Condition
SCL
START
Condition
Figure 3. START and STOP Conditions
SDA
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
ISSI
®
Figure 4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5. Slave Address
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Figure 6. Byte Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E
Word Address
Word Address
A
A
A
C * * * #
C
C
K
K
K
L
M
S
* = Don't care bits
S
B
B
# = Don't care bit for 24C32A/B
R/W
S
T
O
P
Data
A
C
K
Figure 7. Page Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E
Word Address (n) Word Address (n)
A
A
A
C
C * * * #
C
K
K
K
L
S
B
R/W
Data (n+1)
A
C
K
Data (n+31)
A
C
K
A
C
K
* = Don't care bits
# = Don't care bit for 24C32A/B
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
Data (n)
S
T
O
P
7
IS24C32A/B
IS24C64A/B
ISSI
®
Figure 8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
SDA
Bus
Activity
S
T
O
P
Data
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Address Read
S
T
A
R
T
Device
Address
W
R
I
T
E
SDA
Bus
Activity
Word
Address (n)
A
C * * * #
K
M
S
B
S
T
A
R
T
Word
Address (n)
A
C
K
Device
Address
R
E
A
D
Data n
A
C
K
A
C
K
L
S
B
R/W
S
T
O
P
N
O
* = Don't care bits
# = Don't care bit for 24C32A/B
A
C
K
DUMMY WRITE
Figure 10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
Data Byte n+2
A
C
K
S
T
O
P
Data Byte n+X
A
C
K
N
O
R/W
8
A
C
K
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VS
VP
TBIAS
TSTG
IOUT
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
–0.5 to +6.5
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE (IS24C64A/B-2 and IS24C32A/B-2)
Range
Industrial
Ambient Temperature
–40°C to +85°C
VCC
1.8V to 5.5V
Note: ISSI offers Industrial grade for Commerical applications (0oC to +70oC).
OPERATING RANGE (IS24C64A/B-3 and IS24C32A/B-3)
Range
Automotive
Ambient Temperature
–40°C to +125°C
VCC
2.5V to 5.5V
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
9
IS24C32A/B
IS24C64A/B
ISSI
®
AC WAVEFORMS
Figure 11. Bus Timing
tR
tF
tHIGH
tLOW
tSU:STO
SCL
tSU:STA
tBUF
tHD:DAT
tHD:STA
tSU:DAT
SDAIN
tAA
tDH
SDAOUT
tSU:WP
tHD:WP
WP
Figure 12. Write Cycle Timing
SCL
SDA
8th BIT
ACK
tWR
WORD n
STOP
Condition
10
START
Condition
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
ISSI
®
DC ELECTRICAL CHARACTERISTICS Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOL1
Output Low Voltage
VCC = 1.8V, IOL = 0.15 mA
—
0.2
V
VOL2
Output Low Voltage
VCC = 2.5V, IOL = 3 mA
—
0.4
V
VIH
Input High Voltage
VIL
Input Low Voltage
ILI
Input Leakage Current
ILO
Output Leakage Current
VCC X 0.7 VCC + 0.5
VIN = VCC max.
V
–1.0
VCC X 0.3
V
—
3
µA
—
3
µA
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
ICC1
Vcc Operating Current
Read at 400 KHz (Vcc = 5V)
—
2.0
mA
ICC2
Vcc Operating Current
Write at 400 KHz (Vcc = 5V)
—
3.0
mA
ISB1
Standby Current
Vcc = 1.8V
—
1
µA
ISB2
Standby Current
Vcc = 2.5V
—
2
µA
ISB3
Standby Current
Vcc = 5.0V
—
6
µA
AC ELECTRICAL CHARACTERISTICS Industrial (TA = -40oC to +85oC)
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V(1)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fSCL
SCL Clock Frequency
0
100
0
400
0
1000
KHz
T
Noise Suppression Time(1)
—
100
—
50
—
50
ns
tLow
Clock Low Period
4.7
—
1.2
—
0.6
—
µs
tHigh
Clock High Period
tBUF
Bus Free Time Before New Transmission(1)
tSU:STA
4
—
0.6
—
0.4
—
µs
4.7
—
1.2
—
0.5
—
µs
Start Condition Setup Time
4
—
0.6
—
0.25
—
µs
tSU:STO
Stop Condition Setup Time
4
—
0.6
—
0.25
—
µs
tHD:STA
Start Condition Hold Time
4
—
0.6
—
0.25
—
µs
tHD:STO
Stop Condition Hold Time
4
—
0.6
—
0.25
—
µs
tSU:DAT
Data In Setup Time
100
—
100
—
100
—
ns
tHD:DAT
Data In Hold Time
0
—
0
—
0
—
ns
tSU:WP
WP pin Setup Time
4
—
0.6
—
0.6
—
µs
tHD:WP
WP pin Hold Time
4.7
—
1.2
—
1.2
—
µs
tDH
Data Out Hold Time
(SCL Low to SDA Data Out Change)
100
—
50
—
50
—
ns
tAA
Clock to Output
(SCL Low to SDA Data Out Valid)
100
3500
50
900
50
400
ns
tR
SCL and SDA Rise Time(1)
—
1000
—
300
—
300
ns
tF
SCL and SDA Fall Time(1)
—
300
—
300
—
100
ns
tWR
Write Cycle Time
—
5
—
5
—
5
ms
Note: 1. These parameters are characterized but not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
11
IS24C32A/B
IS24C64A/B
ISSI
®
AC ELECTRICAL CHARACTERISTICS Automotive (TA = -40oC to +125oC)
2.5V ≤ Vcc < 4.5V
Symbol Parameter
Min.
Max.
4.5V ≤ Vcc ≤ 5.5V(1)
Min.
Max.
Unit
fSCL
SCL Clock Frequency
0
400
0
1000
KHz
T
Noise Suppression Time(1)
—
50
—
50
ns
tLow
Clock Low Period
1.2
—
0.6
—
µs
tHigh
Clock High Period
0.6
—
0.4
—
µs
Transmission(1)
tBUF
Bus Free Time Before New
1.2
—
0.5
—
µs
tSU:STA
Start Condition Setup Time
0.6
—
0.25
—
µs
tSU:STO
Stop Condition Setup Time
0.6
—
0.25
—
µs
tHD:STA
Start Condition Hold Time
0.6
—
0.25
—
µs
tHD:STO
Stop Condition Hold Time
0.6
—
0.25
—
µs
tSU:DAT
Data In Setup Time
100
—
100
—
ns
tHD:DAT
Data In Hold Time
0
—
0
—
ns
tSU:WP
WP pin Setup Time
0.6
—
0.6
—
µs
tHD:WP
WP pin Hold Time
1.2
—
1.2
—
µs
tDH
Data Out Hold Time (SCL Low to SDA Data Out Change)
50
—
50
—
ns
tAA
Clock to Output (SCL Low to SDA Data Out Valid)
50
900
50
550
ns
—
300
—
300
ns
—
300
—
100
ns
—
10
—
5
ms
tR
SCL and SDA Rise
tF
SCL and SDA Fall
tWR
Write Cycle Time
Time(1)
Time(1)
Note:
1. These parameters are characterized but not 100% tested.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
ISSI
®
ORDERING INFORMATION
Industrial Range: -40°C to +85°C, Lead-free
Voltage
Range
Part Number
Package
1.8V
to 5.5V
IS24C32A-2PLI
IS24C32A-2GLI
IS24C32A-2ZLI
IS24C32A-2SLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
MSOP
1.8V
to 5.5V
IS24C32B-2PLI
IS24C32B-2GLI
IS24C32B-2ZLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C64A-2PLI
IS24C64A-2GLI
IS24C64A-2ZLI
IS24C64A-2SLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
MSOP
1.8V
to 5.5V
IS24C64B-2PLI
IS24C64B-2GLI
IS24C64B-2ZLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage
Range
Part Number
Package
1.8V
to 5.5V
IS24C32A-2PI
IS24C32A-2GI
IS24C32A-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C32B-2PI
IS24C32B-2GI
IS24C32B-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C64A-2PI
IS24C64A-2GI
IS24C64A-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C64B-2PI
IS24C64B-2GI
IS24C64B-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
13
PACKAGING
ISSI
INFORMATION
PlasticMSOP
Package Code: S
N
E1
E
1
D
SEATING PLANE
A
A1
e
L
α
C
B
Ref. Std.
No. Leads
Plastic MSOP (S)
JEDEC MO 187
8 (120 mil)
Inches
Symbol Min Max
A
0.038 0.043
A1
0.002 0.006
B
0.010 0.016
C
0.005 0.009
D
0.114 0.122
E
0.193 BSC
E1
0.114 0.122
e
0.0256BSC
L
— 0.022
α
—
7°
Millimeters
Min Max
0.97 1.10
0.05 0.15
0.25 0.40
0.13 0.23
2.90 3.10
4.90BSC
2.90 3.10
0.65BSC
—
0.55
—
7°
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 02/01/02
®
ISSI
PACKAGING INFORMATION
®
300-mil Plastic DIP
Package Code: N,P
N
E1
1
D
S
S
SEATING PLANE
B1
E
A
L
C
A1
FOR
32-PIN ONLY
e
MILLIMETERS
Sym.
Min.
INCHES
Max.
Min.
Max.
4.57
9.53
8.26
0.145
0.015
0.014
0.045
0.032
0.008
0.359
0.300
0.180
E
3.68
0.38
0.36
1.14
0.81
0.20
9.12
7.62
E1
6.20
6.60
0.244
0.260
eA
e
8.13
9.65
0.320
0.380
L
3.18
—
0.125
—
S
0.64
0.762
0.025
0.030
N0.
Leads
A
A1
B
B1
B2
C
D
B2
B
eA
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should
be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004
inches at the seating plane.
8
—
0.56
1.52
1.17
0.33
2.54 BSC
—
0.022
0.060
0.046
0.013
0.375
0.325
0.100 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/14/03
ISSI
PACKAGING INFORMATION
150-mil Plastic SOP
Package Code: G, GR
®
N
E
H
1
D
SEATING PLANE
A
A1
e
L
α
C
B
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
150-mil Plastic SOP (G, GR)
Min
Max
Min
Max
Inches
mm
8
8
—
0.068
—
1.73
0.004
0.009
0.1
0.23
0.013
0.020
0.33
0.51
0.007
0.010
0.18
0.25
0.189
0.197
4.8
5
0.150
0.157
3.81
3.99
0.228
0.245
5.79
6.22
0.050 BSC
1.27 BSC
0.020
0.035
0.51
0.89
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the
seating plane.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
10/03/01
2
ISSI
PACKAGING INFORMATION
Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)
N
E1
1
E
α
N/2
A1
D
A2
A
L
C
e
B
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
8
Millimeters
Inches
Symbol Min Max
Min Max
A
—
1.20
— 0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.032 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.004 0.008
D
2.90 3.10
0.114 0.122
E1
4.30 4.50
0.169 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
α
—
8°
—
8°
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
14
Millimeters
Inches
Symbol Min Max
Min
Max
A
—
1.20
—
0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.031 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.0035 0.008
D
4.90 5.10
0.193 0.201
E1
4.30 4.50
0.170 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.0177 0.0295
α
—
8°
—
8°
SSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev B 02/01/02
®