ON NCL30186BDR2G Analog/digital dimmable power factor corrected quasi-resonant primary Datasheet

NCL30186
Analog/Digital Dimmable
Power Factor Corrected
Quasi-Resonant Primary
Side Current-Mode
Controller for LED Lighting
The NCL30186 is a controller targeting isolated and non−isolated
“smart−dimmable” constant−current LED drivers. Designed to
support flyback, buck−boost, and SEPIC topologies, its proprietary
current− control algorithm provides near−unity power factor and tightly
regulates a constant LED current from the primary side, thus
eliminating the need for a secondary−side feedback circuitry or an
optocoupler.
Housed in the SOIC10 which has the same body size as a standard
SOIC8, the NCL30186 is specifically intended for very compact
space−efficient designs. The device is highly integrated with a
minimum number of external components. A robust suite of safety
protections is built in to simplify the design. To ensure reliable
operation at elevated temperatures, a user configurable current
foldback circuit is also provided. In addition, it supports analog and
PWM dimming with a dedicated dimming input intended to control
the average LED current.
Pin−to−pin compatible to the NCL30086, the NCL30186 provides
the same benefits with in addition, an increased resolution of the
digital current−control algorithm for a 75% reduction in the LED
current quantization ripple.
•
SOIC−10
CASE 751BQ
MARKING DIAGRAM
L30186x
ALYW
G
L30186x = Specific Device Code
x = A, B, C, D
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
PIN CONNECTIONS
DIM
Features
•
•
•
•
•
•
•
•
•
•
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1
NC
ZCD
VCC
Quasi−resonant Peak Current−mode Control Operation
DRV
VS
Valley Lockout Optimizes Efficiency over the Line/Load Range
COMP
GND
Constant Current Control with Primary Side Feedback
SD
CS
Tight LED Constant Current Regulation of ±2% Typical
(Top View)
Power Factor Correction
Analog or PWM dimming
ORDERING INFORMATION
Line Feedforward for Enhanced Regulation Accuracy
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
Low Start−up Current (10 mA typ.)
Wide Vcc Range
♦ User programmable NTC Based Thermal Foldback
300 mA / 500 mA Totem Pole Driver with 12 V Gate
♦ Thermal Shutdown
Clamp
•
−40
to 125°C Operating Junction Temperature
Robust Protection Features
• Pb−Free, Halide−Free Product
♦ Brown−Out Detection
♦ OVP on VCC
• Four Versions: NCL30186A, B, C and D (See Table 1)
♦ Programmable Over Voltage / LED Open Circuit
Typical Applications
Protection
• Integral LED Bulbs
♦ Cycle−by−cycle Peak Current Limit
♦ Winding Short Circuit Protection
• LED Light Engines
♦ Secondary Diode Short Protection
• LED Driver Power Supplies
♦ Output Short Circuit Protection
• Smart LED Lighting Applications
♦ Current Sense (CS) Short Detection
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 1
1
Publication Order Number:
NCL30186/D
NCL30186
.
Aux
.
.
NCL30186
VDIM
1
10
2
9
3
8
4
7
5
6
Rsense
Figure 1. Typical Application Schematic in a Flyback Converter
.
Aux
.
VDIM NCL30186
1
10
2
9
3
8
4
7
5
6
Rsense
Figure 2. Typical Application Schematic in a Buck−Boost Converter
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2
NCL30186
Table 1. FOUR NCL30186 VERSIONS
Part Number
Protection Mode
Current Regulation
Reference Voltage
(VREF)
Recommended for (*):
Isolated converters.
Non−isolated converters with
NCL30186A
Latching−off
250 mV
V out v Ǹ2 @ (V in,rms) LL
Isolated converters.
Non−isolated converters with
NCL30186B
Auto−recovery
250 mV
V out v Ǹ2 @ (V in,rms) LL
Non−isolated converters with
NCL30186C
Latching−off
200 mV
V out u Ǹ2 @ (V in,rms) LL
Non−isolated converters with
NCL30186D
Auto−recovery
200 mV
V out u Ǹ2 @ (V in,rms) LL
*(Vin,rms)LL designates the lowest line rms voltage. Refer to ANDxxxx/D for more details.
(http://www.onsemi.com/pub_link/Collateral/ANDxxxx−D.PDF).
Table 2. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
DIM
Analog / PWM Dimming
This pin is used for analog or PWM dimming control. An analog signal that can be
varied between VDIM0 and VDIM100 or a PWM signal can be used to adjust the
LED current.
2
ZCD
Zero Crossing Detection
Connected to the auxiliary winding, this pin detects the core reset event.
3
VS
Input Voltage Sensing
4
COMP
Filtering Capacitor
5
SD
Thermal Foldback and
Shutdown
6
CS
Current Sense
7
GND
−
8
DRV
Driver Output
The driver’s output to an external MOSFET
9
VCC
IC Supply Pin
This pin is the positive supply of the IC. The circuit starts to operate when VCC
exceeds 18 V and turns off when VCC goes below 8.8 V (typical values). After
start−up, the operating range is 9.4 V up to 26 V (VCC (OVP ) minimum level).
10
NC
−
This pin monitors the input voltage rail for:
Power Factor Correction
Valley lockout
Brownout Detection
This pin receives a filtering capacitor for power factor correction. Typical values
ranges from 1 − 4.7 mF.
Connecting an NTC to this pin allows the user to program thermal current foldback threshold and slope. A Zener diode can also be used to pull−up the pin and
stop the controller for adjustable OVP protection.
This pin monitors the primary peak current.
Controller ground pin.
−
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3
NCL30186
Internal Circuit Architecture
Enable
Over Voltage Protection
(Auto−recovery or Latched)
Aux_SCP
OFF
Thermal
Foldback
VCC Management
Latch
Internal
Thermal
Shutdown
V TF
VCC
UVLO
Fault
Management
Over Temp. Protection
(Auto−recovery or Latched)
SD
V REF
V DD
STOP
VCC_max
VCC Over Voltage
Protection
WOD_SCP
BO_NOK
DRV
FF_mode
V VS
VCC
ZCD
Zero Crossing Detection Logic
(ZCD Blanking, Time−Out, ...)
FF_mode
Aux_SCP
Clamp
Circuit
Valley Selection
Frequency Foldback
Aux. Winding Short Circuit Prot.
DRV
S
Q
CS_ok
Q
V VS
Line
feed−forward
STOP
VVS
R
DIM_disable
V REFX
GND
CS
Power Factor and
Constant−Current
Control
Leading
Edge
Blanking
CS_reset
Ipkmax
DIM_disable
Maximum
on time
STOP
t on,max
COMP
Ipkmax
Max. Peak
Current
Limit
VVS
BO_NOK
VS
Brown−Out
CS_ok
CS Short
Protection
UVLO
V REF
t on,max
DIM_disable
V
Winding and
Output diode
Short Circuit
Protection
WOD_SCP
REFX
DIM
Dimming
control
VTF
Figure 3. Internal Circuit Architecture
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NCL30186
Table 3. MAXIMUM RATINGS TABLE(S)
Symbol
Rating
VCC(MAX)
ICC(MAX)
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
VDRV(MAX)
IDRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
Value
Unit
−0.3 to 30
Internally limited
V
mA
−0.3, VDRV (Note 1)
−300, +500
V
mA
−0.3, 5.5 (Notes 2 and 5)
−2, +5
V
mA
VMAX
IMAX
Maximum voltage on low power pins (except DRV and VCC pins)
Current range for low power pins (except DRV and VCC pins)
RθJ−A
Thermal Resistance Junction−to−Air
180
°C/W
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (Note 3)
3.5
kV
ESD Capability, MM model (Note 3)
250
V
2
kV
TJ(MAX)
ESD Capability, CDM model (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can
be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA.
5. Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range.
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Test Condition
Symbol
Min
Typ
Max
VCC rising
VCC rising
VCC falling
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
16.0
8.2
8
4
18.0
8.8
−
5
20.0
9.4
−
6
VCC Over Voltage Protection Threshold
VCC(OVP)
25.5
26.8
28.5
V
VCC(off) noise filter
VCC(reset) noise filter
tVCC(off)
tVCC(reset)
−
−
5
20
−
−
ms
Startup current
ICC(start)
−
13
30
mA
Startup current in fault mode
ICC(Fault)
58
75
mA
Description
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset
Supply Current
Device Disabled/Fault
Device Enabled/No output load on DRV pin
Device Switching
V
mA
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF, Fsw = 65 kHz
ICC1
ICC2
ICC3
0.8
–
−
1.0
2.6
3.0
1.2
4.0
4.5
Maximum Internal current limit
VILIM
0.95
1.00
1.05
V
Leading Edge Blanking Duration for VILIM
tLEB
240
300
360
ns
Propagation delay from current detection to gate
off−state
tILIM
−
100
150
ns
CURRENT SENSE
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30186
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
Maximum on−time
ton(MAX)
26
36
46
ms
Threshold for immediate fault protection activation
VCS(stop)
1.35
1.50
1.65
V
Leading Edge Blanking Duration for VCS(stop)
tBCS
−
150
−
ns
Current source for CS to GND short detection
ICS(short)
400
500
600
mA
VCS(low)
30
65
100
mV
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
−
−
13
30
−
−
Drive current capability
DRV Sink (Note 6)
DRV Source (Note 6)
ISNK
ISRC
−
−
500
300
−
−
CURRENT SENSE
Current sense threshold for CS to GND short detection
VCS rising
GATE DRIVE
W
mA
Rise Time (10% to 90%)
CDRV = 470 pF
tr
–
40
−
ns
Fall Time (90% to 10%)
CDRV = 470 pF
tf
–
30
−
ns
DRV Low Voltage
VCC = VCC(off)+0.2 V
CDRV = 470 pF, RDRV = 33 kW
VDRV(low)
8
–
−
V
DRV High Voltage
VCC = VCC(MAX)
CDRV = 470 pF, RDRV = 33 kW
VDRV(high)
10
12
14
V
Upper ZCD threshold voltage
VZCD rising
VZCD(rising)
−
90
150
mV
Lower ZCD threshold voltage
VZCD falling
VZCD(falling)
35
55
−
mV
ZERO VOLTAGE DETECTION CIRCUIT
ZCD hysteresis
VZCD(HYS)
15
−
−
mV
VZCD falling
TDEM
−
100
300
ns
Blanking delay after on−time
VREFX > 30% VREF
TZCD(blank1)
1.12
1.50
1.88
ms
Blanking delay at light load
VREFX < 25% VREF
TZCD(blank2)
0.56
0.75
0.94
ms
TTIMO
5.0
6.5
8.0
ms
RZCD(PD)
−
200
−
kW
Propagation Delay from valley detection to DRV
high
Timeout after last DEMAG transition
Pulling−down resistor
VZCD = VZCD(falling)
CONSTANT CURRENT AND POWER FACTOR CONTROL
Reference Voltage at TJ = 25°C
A and B versions
C and D versions
VREF
245
195
250
200
255
205
mV
Reference Voltage TJ = 25°C to 100°C
A and B versions
C and D versions
VREF
242.5
192.5
250.0
200.0
257.5
207.5
mV
Reference Voltage TJ = −40°C to 125°C
A and B versions
C and D versions
VREF
240
190
250
200
260
210
mV
VCS falling
VCS(low)
20
50
100
mV
Vratio
−
4
−
−
GEA
40
50
60
mS
Current sense lower threshold
Vcontrol to current setpoint division ratio
Error amplifier gain
VREFX = VREF
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30186
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VREFX = VREF (no dimming)
VREFX = 25%* VREF
IEA
±60
±240
mA
COMP pin grounded
IEA_STUP
140
mA
CONSTANT CURRENT AND POWER FACTOR CONTROL
Error amplifier current capability
COMP Pin Start−up Current Source
LINE FEED FORWARD
VVS to ICS(offset) conversion ratio
Line feed−forward current on CS pin
DRV high, VVS = 2 V
Offset current maximum value
KLFF
18
20
22
mS
IFF
35
40
45
mA
Ioffset(MAX)
80
100
120
mA
VALLEY LOCKOUT SECTION
Threshold for high− line range (HL) detection
VVS rising
VHL
2.28
2.40
2.52
V
Threshold for low−line range (LL) detection
VVS falling
VLL
2.18
2.30
2.42
V
tHL(blank)
15
25
35
ms
tFF1LL
1.4
2.0
2.6
ms
40
−
ms
−
ms
Blanking time for line range detection
FREQUENCY FOLDBACK
Minimum additional dead time in frequency foldback mode
Additional dead time
VREFX = 5% VREF
tFF2HL
−
Additional dead time
VREFX = 0% VREF
tFF3HL
90
FSW = 65 kHz
TSHDN
130
150
170
°C
Thermal Shutdown Hysteresis
TSHDN(HYS)
−
50
–
°C
Threshold voltage for output short circuit or aux.
winding short circuit detection
VZCD(short)
0.8
1.0
1.2
V
tOVLD
70
90
110
ms
Auto−recovery timer duration
trecovery
3
4
5
s
SD pin Clamp series resistor
RSD(clamp)
FAULT PROTECTION
Thermal Shutdown (Note 6)
Short circuit detection Timer
Clamped voltage
VZCD < VZCD(short)
1.6
kW
SD pin open
VSD(clamp)
1.13
1.35
1.57
V
VSD rising
VOVP
2.35
2.50
2.65
V
Delay before OVP or OTP confirmation
TSD(delay)
22.5
30.0
37.5
ms
Reference current for direct connection of an NTC
(Note 8)
IOTP(REF)
80
85
90
mA
SD pin detection level for OVP
Fault detection level for OTP (Note 7)
VSD falling
VOTP(off)
0.47
0.50
0.53
V
SD pin level for operation recovery after an OTP
detection
VSD rising
VOTP(on)
0.66
0.70
0.74
V
OTP blanking time when circuit starts operating
(Note 8)
tOTP(start)
250
370
ms
SD pin voltage where thermal fold−back starts
(VREF is decreased)
VTF(start)
0.94
1.00
1.06
V
SD pin voltage at which thermal fold−back stops
(VREF is clamped to VREF50)
VTF(stop)
0.64
0.69
0.74
V
RTF(start)
10.8
11.7
12.6
kW
VTF(start) over IOTP(REF) ratio (Note 7)
TJ = +25°C to +125°C
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30186
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VTF(stop) over IOTP(REF) ratio (Note 7)
TJ = +25°C to +125°C
RTF(stop)
7.4
8.1
8.8
kW
VOTP(off) over IOTP(REF) ratio (Note 7)
TJ = +25°C to +125°C
ROTP(off)
5.4
5.9
6.4
kW
VOTP(on) over IOTP(REF) ratio (Note 7)
TJ = +25°C to +125°C
ROTP(on)
7.5
8.1
8.7
kW
VREFX @ VSD = 600 mV (as percentage of VREF)
SD pin falling (no OTP
detection)
VREF(50)
40
50
60
%
Brown−Out ON level (IC start pulsing)
VS rising
VBO(on)
0.95
1.00
1.05
V
Brown−Out OFF level (IC shuts down)
VS falling
VBO(off)
0.85
0.90
0.95
V
FAULT PROTECTION
BROWN−OUT
ms
BO comparators delay
tBO(delay)
Brown−Out blanking time
tBO(blank)
15
25
35
ms
VS = VBO(on)
IBO(bias)
50
250
450
nA
DIM pin voltage for zero output current
(OFF voltage)
VDIM falling
VDIM0
0.66
0.70
0.74
V
DIM pin voltage for maximum output current
(VREFX = VREF)
TJ = −40°C to +125°C
TJ = +25°C to +85°C (NCL30186D only)
TJ = +25°C (NCL30186D only)
VDIM rising
VDIM100
VS pin Pulling−down Current
30
DIMMING SECTION
DIM pin voltage for 50% output current
(VREFX = 50% VREF)
Output Current Internal Reference (VREFX) @
VDIM = 0.8225 V) (NCL30186D only)
TJ = +25°C to +50°C
VDIM rising or falling
VDIM50
VDIM = 0.8225 V
VREF7
V
−
2.32
2.335
2.45
2.45
2.450
2.60
2.57
2.555
1.35
1.57
1.75
mV
9.4
Dimming range
VDIM(range)
Dimming pin pull−up current source
IDIM(pullup)
V
14
18.6
1.75
7.5
9.6
V
12
mA
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30186
TYPICAL CHARACTERISTICS
20.0
9.4
9.3
19.5
9.2
9.1
18.5
VCC(off) (V)
VCC(on) (V)
19.0
18.0
17.5
17.0
−25
0
25
50
75
100
125
150
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. VCC Start−up Threshold vs.
Temperature
Figure 5. VCC Minimum Operating Voltage vs.
Temperature
11.5
6.0
11.0
5.8
5.6
VCC(reset) (V)
5.4
10.0
9.5
9.0
5.2
5.0
4.8
4.6
8.5
4.4
8.0
7.5
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
10.5
VCC(hys) (V)
8.7
8.6
8.5
8.4
8.3
8.2
−50
16.5
16.0
−50
9.0
8.9
8.8
−25
0
25
50
75
100
125
4.2
4.0
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Hysteresis (VCC(on) − VCC(off)) vs.
Temperature
Figure 7. VCC(reset) vs. Temperature
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NCL30186
TYPICAL CHARACTERISTICS
40
28.0
27.8
35
30
27.2
27.0
ICC(start) (mA)
VCC(ovp) (V)
27.6
27.4
26.8
26.6
26.4
25
20
15
10
26.2
26.0
25.8
25.6
−50
5
−25
0
25
50
75
100
125
0
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. VCC Over Voltage Protection
Threshold vs. Temperature
Figure 9. Start−up Current vs. Temperature
2.0
150
1.8
125
ICC1 (mA)
ICC(sfault) (mA)
1.6
100
75
50
1.4
1.2
1.0
0.8
25
0.6
−25
0
25
50
75
100
125
0.4
−50
150
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Start−up Current in Fault Mode vs.
Temperature
Figure 11. ICC1 vs. Temperature
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
−50
125 150
5.0
4.5
4.0
ICC3 (mA)
ICC2 (mA)
0
−50
3.5
3.0
2.5
2.0
1.5
−25
0
25
50
75
100
125
150
1.0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. ICC2 vs. Temperature
Figure 13. ICC3 vs. Temperature
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10
125 150
NCL30186
1.05
400
1.04
380
360
1.02
340
1.01
320
TLEB (ns)
1.03
1.00
0.99
280
260
0.97
240
0.96
0.95
−50
220
−25
0
25
50
75
100
125
200
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 14. Maximum Internal Current Limit vs.
Temperature
Figure 15. Leading Edge Blanking vs.
Temperature
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
−50
50
48
46
44
42
40
38
36
34
−25
0
25
50
75
100
125
32
30
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Current Limit Propagation Delay vs.
Temperature
Figure 17. Maximum On−time vs. Temperature
1.60
220
210
1.58
200
190
1.56
1.54
1.52
TBCS (ns)
VCS(stop) (V)
300
0.98
TON(max) (ms)
TILIM (ns)
VILIM (V)
TYPICAL CHARACTERISTICS
1.50
1.48
1.46
1.44
1.42
1.40
1.38
−50
−25
0
25
50
75
100
125
150
180
170
160
150
140
130
120
110
100
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. VCS(stop) vs. Temperature
Figure 19. Leading Edge Blanking Duration for
VCS(stop) vs. Temperature
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11
NCL30186
TYPICAL CHARACTERISTICS
600
100
580
90
560
80
VCS(low) (mV)
ICS(short) (mA)
540
520
500
480
460
−25
0
25
50
75
100
125
20
−50
150
25
50
75
100
125 150
Figure 20. ICS(short) vs. Temperature
Figure 21. VCS(low), VCS Rising vs.
Temperature
14
12
RSRC (W)
RSNK (W)
0
TJ, JUNCTION TEMPERATURE (°C)
16
10
8
6
4
−25
0
25
50
75
100
125
150
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 22. Sink Gate Drive Resistance vs.
Temperature
Figure 23. Source Gate Drive Resistance vs.
Temperature
50
45
45
40
40
35
35
30
30
tF (ns)
50
25
25
20
20
15
15
10
10
5
0
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
18
tr (ns)
50
30
20
2
0
−50
60
40
440
420
400
−50
70
−25
0
25
50
75
100
125
150
5
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 24. Gate Drive Rise Time vs.
Temperature
Figure 25. Gate Drive Fall Time
(CDRV = 470 pF) vs. Temperature
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12
125 150
NCL30186
TYPICAL CHARACTERISTICS
9.8
15.0
9.6
14.5
14.0
VDRV(high) (V)
VDRV(low) (V)
9.4
9.2
9.0
8.8
12.0
11.0
8.4
8.2
−50
−25
0
25
50
75
100
125
10.5
10.0
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 26. DRV Low Voltage vs. Temperature
Figure 27. DRV High Voltage vs. Temperature
150
80
140
130
75
120
110
65
VZCD(falling) (mV)
70
100
90
80
70
60
55
50
45
60
50
40
40
30
−50
35
30
−50
−25
0
25
50
75
100
125
150
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 28. Upper ZCD Threshold Voltage vs.
Temperature
Figure 29. Lower ZCD Threshold vs.
Temperature
50
2.0
45
1.9
40
1.8
35
1.7
30
25
20
15
10
5
0
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
tZCD(blank1) (ms)
VZCD(rising) (mV)
13.0
12.5
11.5
8.6
VZCD(HYS) (mV)
13.5
1.6
1.5
1.4
1.3
1.2
−25
0
25
50
75
100
125
150
1.1
1.0
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 30. ZCD Hysteresis vs. Temperature
Figure 31. ZCD Blanking Delay vs.
Temperature
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13
NCL30186
TYPICAL CHARACTERISTICS
7.8
256
255
254
253
7.6
7.4
252
VREF (mV)
TTIMO (ms)
7.2
7.0
6.8
6.6
6.4
246
−25
0
25
50
75
100
125
245
244
−50
150
25
50
75
100
125 150
Figure 32. ZCD Time−out vs. Temperature
Figure 33. Reference Voltage vs. Temperature
(A and B versions)
110
60
58
90
56
54
70
GEA (mS)
VCS(low) (mV)
0
TJ, JUNCTION TEMPERATURE (°C)
100
60
50
52
50
48
40
30
46
20
10
−50
44
−25
0
25
50
75
100
125
42
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 34. Current Sense Lower Threshold
(VCS Falling) vs. Temperature
Figure 35. Error Amplifier Trans−conductance
Gain vs. Temperature
44
21.5
43
21.0
42
20.5
41
IFF (mA)
22.0
20.0
40
19.5
39
19.0
38
18.5
37
18.0
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
80
KLFF (mS)
249
248
247
6.2
6.0
5.8
−50
251
250
−25
0
25
50
75
100
125
150
36
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 36. Feedforward VVS to ICS(offset)
Conversion Ratio vs. Temperature
Figure 37. Line Feedforward Current on CS
Pin (@ VVS = 2 V) vs. Temperature
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NCL30186
TYPICAL CHARACTERISTICS
120
2.55
115
2.50
2.45
105
VHL (V)
Ioffset(MAX) (mA)
110
100
95
2.40
2.35
90
2.30
85
80
−50
−25
0
25
50
75
100
125
2.25
−50
150
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 38. Ioffset(MAX) vs. Temperature
Figure 39. Threshold for High−line Range
Detection vs. Temperature
2.60
40
2.55
38
36
THL(blank) (ms)
2.50
2.45
VLL (V)
−25
2.40
2.35
34
32
30
28
26
2.30
24
2.25
−25
0
25
50
75
100
125
22
20
−50
150
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 40. Threshold for Low−line Range
Detection vs. Temperature
Figure 41. Blanking Time for Low−line Range
Detection vs. Temperature
1.20
115
1.15
110
1.10
105
1.05
100
1.00
0.95
95
90
0.90
85
0.85
80
0.80
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
tOVLD (ms)
VZCD(short) (V)
2.20
−50
−25
0
25
50
75
100
125
150
75
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 42. Threshold Voltage for Output Short
Circuit Detection vs. Temperature
Figure 43. Short Circuit Detection Timer vs.
Temperature
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NCL30186
TYPICAL CHARACTERISTICS
5.00
2.20
2.10
4.75
RSD(clamp) (kW)
Trecovery (s)
4.50
4.25
4.00
3.75
3.50
3.00
−50
1.50
1.40
1.20
1.10
1.00
−50
−25
0
25
50
75
100
125
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 44. Auto−recovery Timer Duration vs.
Temperature
Figure 45. SD Pin Clamp Series Resistor vs.
Temperature
1.60
2.58
1.55
2.56
1.50
2.54
1.45
2.52
1.40
VOVP (V)
VSD(clamp) (V)
1.70
1.60
1.30
3.25
1.35
1.30
2.50
2.48
2.46
1.25
1.20
2.44
1.15
1.10
−50
2.42
−25
0
25
50
75
100
125
2.40
−50
150
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 46. SD Pin Clamp Voltage vs.
Temperature
Figure 47. SD Pin OVP Threshold Voltage vs.
Temperature
91
90
36
89
88
IOTP(REF) (mA)
34
32
30
28
26
24
22
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
38
TSD(delay) (ms)
2.00
1.90
1.80
−25
0
25
50
75
100
125
150
87
86
85
84
83
82
81
80
79
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 48. TSD(delay) vs. Temperature
Figure 49. IOTP(REF) vs. Temperature
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16
NCL30186
12.5
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11.0
−50
8.8
8.7
RTF(stop) (kW)
RTF(start) (kW)
TYPICAL CHARACTERISTICS
−25
0
25
50
75
100
125
8.2
8.1
8.0
7.9
7.8
7.7
7.6
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 50. RTF(start) vs. Temperature
Figure 51. RTF(stop) vs. Temperature
8.8
8.7
8.6
6.4
6.3
6.2
ROTP(on) (kW)
6.1
ROTP(off) (kW)
8.6
8.5
8.4
8.3
6.0
5.9
5.8
5.7
8.5
8.4
8.3
8.2
8.1
8.0
7.9
5.6
−25
0
25
50
75
100
125
7.8
7.7
7.6
−50
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 52. ROTP(off) vs. Temperature
Figure 53. ROTP(on) vs. Temperature
55
1.05
54
1.04
53
1.03
52
1.02
VBO(on) (V)
VREF(50) (%)
5.5
5.4
−50
51
50
49
1.01
1.00
0.99
48
0.98
47
0.97
46
45
−50
0.96
0.95
−50
−25
0
25
50
75
100
125
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 54. Ratio VREF(50) over VREF vs.
Temperature
Figure 55. Brown−out ON Level vs.
Temperature
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NCL30186
TYPICAL CHARACTERISTICS
0.95
0.94
0.93
tBO(blank) (ms)
0.91
0.90
0.89
0.88
0.87
0.86
0.85
−50
−25
0
25
50
75
100
125
150
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 56. Brown−out OFF Level vs.
Temperature
Figure 57. Brown−out Blanking Time vs.
Temperature
500
450
400
350
IBO(bias) (nA)
VBO(off) (V)
0.92
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
−50
300
250
200
150
100
50
0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 58. VS Pin Pulling−down Current vs.
Temperature
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18
150
NCL30186
Application Information
The NCL30186 is a driver for power−factor corrected
flyback and non−isolated buck−boost/ SEPIC converters. It
implements a current−mode, quasi−resonant architecture
including valley lockout and frequency fold−back
capabilities for maintaining high−efficiency performance
over a wide load range. A proprietary circuitry ensures both
accurate regulation of the output current (without the need
for a secondary−side feedback) and near−unity power factor
correction. The circuit contains a suite of powerful
protections to ensure a robust LED driver design without the
need of extra external components or overdesign
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30186 optimizes the
efficiency by turning on the MOSFET when its
drain−source voltage is minimal (valley). In light−load
conditions, the circuit changes valleys to reduce the
switching losses. For a stable operation, the valley at
which the MOSFET switches on remains locked until
the input voltage or the output current set−point
significantly changes.
• Primary−Side Constant−Current Control with
Power Factor Correction: a proprietary circuitry
allows the LED driver to achieve both near−unity
power factor correction and accurate regulation of the
output current without requiring any secondary−side
feedback (no optocoupler needed). A power factor as
high as 0.99 and an output current deviation below ±2%
are typically obtained.
• Linear or PWM dimming: the DIM pin allows
implementing both analog and PWM dimming.
• Main protection features:
♦ Over Temperature Thermal Fold−back/
Shutdown/Over Voltage Protection: the
NCL30186 features a gradual current foldback to
protect the driver from excessive temperature down
to 50% of the programmed current. If the
temperature continues to rise after this point to a
second level, the controller stops operating. This
mode would only be expected to be reached under
normal conditions if there is a severe fault. The first
and second temperature thresholds depend on the
ZCD
VCS
STOP
VVS
♦
♦
♦
♦
♦
NTC connected to the circuit SD pin. The SD pin
can also be used to shutdown the device by pulling
this pin below the VOTP(off) min level. A Zener
diode can also be used to pull−up the pin and stop
the controller for adjustable OVP protection. Both
protections are latching−off (A and C versions) or
auto−recovery (the circuit can recover operation
after 4−s delay has elapsed − B and D versions).
Cycle−by−cycle peak current limit: when the
current sense voltage exceeds the internal threshold
VILIM, the MOSFET is immediately turned off.
Winding or Output Diode Short−Circuit
Protection: an additional comparator senses the CS
signal and stops the controller if it exceeds 150% x
VILIM for 4 consecutive cycles. This feature can
protect the converter if a winding is shorted or if the
output diode is shorted or simply if the transformer
saturates. This protection is latching−off (A and C
versions) or auto−recovery (B and D versions).
Output Short−circuit protection: if the ZCD pin
voltage remains low for a 90−ms time interval, the
controller detects that the output or the ZCD pin is
grounded and hence, stops operation. This protection
is latching−off (A and C versions) or auto−recovery
(B and D versions).
Open LED protection: if the VCC pin voltage
exceeds the OVP threshold, the controller shuts
down and waits 4 seconds before restarting
switching operation.
Floating or Short Pin Detection: NCL30186
protections aid in pass safety tests. For instance, the
circuit stops operating when the CS pin is grounded
or open.
Power Factor and Constant Current Control
The NCL30186 embeds an analog/digital block to control
the power factor and regulate the output current by
monitoring the ZCD, VS and CS pin voltages (signals ZCD,
VS and VCS of Figure 59). This circuitry generates the
current setpoint (VCONTROL/4) and compares it to the
current sense signal (VCS) to dictate the MOSFET turning
off event when VCS exceeds VCONTROL/4.
VREF
PWM Latch reset
Power Factor and
Constant−Current
Control
COMP
DIM_disable
C1
Figure 59. Power Factor and Constant−Current Control
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19
NCL30186
the time to charge the VCC capacitor, initiate startup and
begin switching and the time to charge the output capacitor
until sufficient current flows into the LED string. To
speed−up this phase, the following defines the start−up
sequence:
• The COMP pin is grounded when the circuit is off. The
average COMP voltage needs to exceed the VS pin
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80−mA current source adds to the OTA sourced
current (60 mA max typically) to charge up the COMP
capacitance. The 80−mA current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
• If VCC drops below the VCC(off) threshold because the
circuit fails to start−up properly on the first attempt, a
new attempt takes place as soon as VCC is recharged to
VCC(on). The COMP voltage is not reset at that
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
• If the load is shorted, the circuit will operate in hiccup
mode with VCC oscillating between VCC(off) and
VCC(on) until the AUX_SCP protection trips
(AUX_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The NCL30186A and NCL3006C latch off in
this case. With the B and D versions, the AUX_SCP
protection forces the 4−s auto−recovery delay to reduce
the operation duty−ratio. Figure 60 illustrates a start−up
sequence with the output shorted to ground, in this
second case.
The VS pin provides the sinusoidal reference necessary
for shaping the input current. The obtained current reference
is further modulated so that when averaged over a half−line
period, it is equal to the output current reference (VREFX).
This averaging process is made by an internal Operational
Trans−conductance Amplifier (OTA) and the capacitor
connected to the COMP pin (C1 in Figure 59). Typical
COMP capacitance is 2.2 mF and should not be less than 1 mF
to ensure stability. The COMP ripple does not affect the
power factor performance as the circuit digitally eliminates
it when generating the current setpoint.
If the VS pin properly conveys the sinusoidal shape, power
factor will be close to 1. Also, the Total Harmonic Distortion
(THD) will be low, especially if the output voltage ripple is
small. In any case, the output current will be well regulated
following the equation below:
I out +
V REFX
2N PSR sense
(eq. 1)
Where:
• NPS is the secondary to primary transformer turns NPS
= NS / NP
• Rsense is the current sense resistor (see Figure 1).
• VREFX is the output current internal reference. VREFX =
VREF (250 mV in A and B versions and 200 mV in C
and D versions, typically) at full load.
The output current reference (VREFX) is VREF unless
thermal fold−back is activated by the SD pin voltage being
reduced below 1 V typical (see “protections” section) or
unless the DIM pin voltage is below VDIM100 (see analog
dimming section).
If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.
Start−up Sequence
Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
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20
NCL30186
VCC(on)
VCC
VCC(off)
(‧‧‧ )
(‧‧‧ )
time
AUX_SCPtrips
as t 1 + t2 + t3 = tOVLD
(tOVLD ^90 ms)
DRV
t1
t3
t1
t2
t3
time
t2
trecovery (^4 s )
trecovery (^4 s )
Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery versions)
Zero Crossing Detection Block
situation, the NCL30186 features a time−out circuit that
generates pulses if the voltage on ZCD pin stays below the
55−mV threshold for 6.5 ms nominal. The time−out also acts
as a substitute clock for the valley detection and simulates
a missing valley in case the free oscillations are too damped.
The ZCD pin detects when the drain−source voltage of the
power MOSFET reaches a valley by crossing below the
55−mV internal threshold (VZCD(TH)). At startup or in case
of extremely damped free oscillations, the ZCD comparator
may not be able to detect the valleys. To avoid such a
t ZCD(blank1)
t ZCD(blank)
FF_mode
t ZCD(blank2)
ZCD
+
V ZCD(TH)
−
Clock
Time−Out
V ZCD(short)
+
+
−
−
S
Q
Q
90−ms Timer
R
4−s Timer (auto−recovery version)
Vcc<Vcc(reset) (latching−off version)
Figure 61. Zero Current Detection Block
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21
Aux_SCP
NCL30186
• After the appropriate number of “clock” pulses in
If the ZCD pin or the auxiliary winding happen to be
shorted, the time−out function would normally make the
controller keep switching and hence lead to improper LED
current value. The “AUX_SCP” protection prevents such a
stressful operation: a secondary timer starts counting that is
only reset when the ZCD voltage exceeds the VZCD(short)
threshold (1 V typically). If this timer reaches 90 ms (no
ZCD voltage pulse having exceeded VZCD(short) for this time
period), the controller detects a fault and stops operation for
4 seconds (B and D versions) or latches off (A and C
versions).
The “clock” shown in Figure 61 is used by the “valley
selection frequency foldback” circuitry of the block diagram
(Figure 3), to generate the next DRV pulse (if no fault
prevents it):
• Immediately when the clock occurs in QR mode at low
line or valley 2 at high line (full load)
thermal foldback mode
For an optimal operation, the maximum ZCD level
should be maintained below 5 V to stay safely below the
built in clamping voltage of the pin.
Line Range Detection
As sketched in Figure 62, this circuit detects the low−line
range if the VS pin remains below the VLL threshold (2.3 V
typical) for more than the 25−ms blanking time. High−line
is detected as soon as the VS pin voltage exceeds VHL (2.4 V
typical). These levels roughly correspond to 184−V rms and
192−V rms line voltages if the external resistors divider
applied to the VS pin is designed to provide a 1−V peak value
at 80 V rms.
Figure 62. Line Range Detection
efficiency over the line range by turning on the MOSFET at
the first valley in low−line conditions and at the second
valley in the high−line case. This is illustrated by Figure 63
that sketches the MOSFET Drain−Source voltage in both
cases. In the event that thermal foldback is activated,
additional valleys can be skipped as the power is reduced.
In the low−line range, conduction losses are generally
dominant. Adding a dead−time would further increase these
losses. Hence, only a short dead−time is necessary to reach
the MOSFET valley. In high−line conditions, switching
losses generally are the most critical. It is thus efficient to
skip one valley to lower the switching frequency. Hence,
under normal operation, the NCL30186 optimizes the
Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line
(right)
Line Feedforward
current. By adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset proportional
to the input voltage is added to the CS signal for the
MOSFET on−time.
To compensate for current regulation errors due to AC line
variation, the NCL30186 includes a method to add line
feedforward adjustment. As illustrated by Figure 64, the
input voltage is sensed by the VS pin and converted into a
www.onsemi.com
22
NCL30186
Bulk rail
vDD
VS
CS
I CS(offset)
RCS
Rsense
Q_drv
Figure 64. Line Feed−Forward Schematic
In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise.
PWM or Linear Dimming Detection
The DIM pin of the NCL30186 is provided to implement
linear and/or PWM dimming of the LED current.
Applying a voltage on the DIM pin voltage (VDIM) forces
the output current internal reference to operate in one of
three regions:
V REFX + 0
if V DIM v V DIM0
V REFX + V REF
if V DIM w V DIM100
V REFX +
V DIM * V DIM0
V
V DIM100 * V DIM0 REF
Where:
• NPS is the secondary to primary transformer turns
N PS + N SńN P
• Rsense is the current sense resistor (see Figure 1).
• VREF is the output current internal reference (250 mV
(eq. 2)
typically)
• Iout,nom is the full−load output current.
The DRV output is disabled whenever the DIM pin
voltage is lower than VDIM0 and the output current setpoint
is maximal when VDIM exceeds VDIM100. Thus, for PWM
dimming, a PWM signal with a low−state value below
VDIM0 and a high−state value above VDIM100 should be
applied.
In this case, the output current will be:
otherwise
VDIM0 and VDIM100 respectively, are 0.7 V and 2.45 V
typically.
The output current can then be controlled by the DIM pin
as follows:
I out + 0
if V DIM v V DIM0 (eq. 3)
V REF
if V DIM w V DIM100
I out + I out,nom +
2 N PSR sense
I out +
V DIM * V DIM0
I
V DIM100 * V DIM0 out,nom
I out ^ I out,nom @ d
(eq. 4)
Where d is the duty ratio of the DIM pin signal.
otherwise
VDIM
VDIM100
VDIM0
time
Iout
Iout,nom
0A
time
Figure 65. Pin DIM Chronograms
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23
NCL30186
Notes:
• The current does not immediately reach its new target
• If either the high−state (VDIM(high)) or low−state level
(VDIM(low)) of the input or both are between VDIM0 and
VDIM100, the output current will be proportionally
reduced as both analog and PWM dimming are
simultaneous active, thus the output current will be:
value when the PWM dimming signal state changes due
to system time constants like the time necessary to
charge or discharge the output capacitor to the required
level. The output current settling time can hence affect
the obtained output current, particularly if the PWM
signal frequency is high.
I out ^
I out ^
I out ^
ǒ
V DIM(high) * V DIM0
V DIM100 * V DIM0
V DIM(high) * V DIM0
V DIM100 * V DIM0
ǒ
d)
d)
V DIM(low) * V DIM0
V DIM100 * V DIM0
Ǔ
(1 * d) I out,nom if V DIM0 v V DIM(low) v V DIM(high) v V DIM100
d @ I out,nom
V DIM(low) * V DIM0
V DIM100 * V DIM0
(1 * d)
if V DIM0 v V DIM(high) v V DIM100 and V DIM(low) v V DIM0
Ǔ
if V DIM(high) w V DIM100 and V DIM0 v V DIM(low) v V DIM100
I out,nom
• If thermal foldback is activated as well, the current
Protections
The circuit incorporates a full suite of protection features
listed below to make the LED driver very rugged.
reduction is cumulative. For instance, if the DIM pin
voltage and the thermal foldback respectively, reduces
the output current setpoint by 50% and 20%
respectively, the output current will be 80%*50% that is
40% of its nominal level.
Output Short Circuit Situation
An overload fault is detected if the ZCD pin voltage
remains below VZCD(short) for 90 ms. In such a situation, the
circuit stops generating pulses until the 4−s delay
auto−recovery time has elapsed (B and D versions) or
latches off (A and C versions).
The DIM pin is pulled up internally by a 10−mA current source.
Thus, if the pin is let open, the controller is able to start.
For any power factor corrected single stage architecture
there will be a component of line ripple (100 / 120 Hz) on the
output. If PWM dimming is used, it is recommended to
select the dimming frequency to be sufficiently high not to
generating beat frequencies that could create optical
artifacts.
>> As a general rule, the minimum PWM frequency
should be at least 2.5x the line ripple frequency and not
be set near multiples of the line frequency.
Winding or Output Diode Short Circuit Protection
If a transformer winding happens to be shorted, the
primary inductance will collapse leading the current to ramp
up in a very abrupt manner. The VILIM comparator (current
limitation threshold) will trip to open the MOSFET and
eventually stop the current rise. However, because of the
abnormally steep slope of the current, internal propagation
delays and the MOSFET turn−off time, a current rise > 50%
of the nominal maximum value set by VILIM is possible. As
illustrated in Figure 66, an additional circuit monitors for
this current overshoot to detect a winding short circuit. The
leading edge blanking (LEB) time for short circuit
protection (LEB2) is significantly faster than the LEB time
for cycle−by−cycle protection (LEB1). Practically, if four
consecutive switching periods lead the CS pin voltage to
exceed (VCS(stop) = 150% * VILIM), the controller enters the
auto−recovery mode (4−s operation interruption between
active bursts with versions B and D) or latches off (versions
A and C).
www.onsemi.com
24
NCL30186
S
DRV
Q
Vdd
aux
UVLO
Q
TSD
CS
LEB1
+
Vcontrol / 4
PWMreset
VCC
Vcc
management
BONOK
UVLO
R
−
4−s timer
+
STOP
Ipkmax
−
V ILIMIT
AUX_SCP
SD Pin OVP
(OVP2)
LEB2
+
WOD_SCP
latch
VCCreset
(grand
reset)
VCC(ovp)
4−pulse
counter
−
OTP
V CS(stop)
S
S
OFF
Q
Q
R
4−s timer
latch
Q
Q
AUTORECOVERY
(B and D versions)
R
LATCHING−OFF
(A and C versions)
VCCreset
Figure 66. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
VCC Over Voltage Protection
Programmable Over Voltage Protection (OVP2)
The circuit stops generating pulses if VCC exceeds
VCC(OVP) and enters auto−recovery mode. This feature
protects the circuit in the event that the output LED string is
disconnected or an individual LED in the string happens to
fail open.
In addition to the VCC OVP protection, it is possible to
connect a Zener diode between VCC and the SD pin to
implement programmable VCC OVP monitoring (DZ of
Figure 67). The triggering level is (VZ+VOVP) where VOVP is
the 2.5−V internal threshold. If this protection trips, the
NCL30186A and NCL30186C latch off while the
NCL30186B and NCL30186D enter the auto−recovery mode.
Vdd
IOTP(REF)
NCL30186B / NCL30186D
(autorecovery versions)
SD PIN OVP (OVP2) DETECTION
S
+
Q
VCC
−
OFF
Q
VOVP
T SD(delay)
DZ
R
SD
4−s Timer
OTP DETECTION
−
NTC
NCL30186A / NCL30186C
(latching off versions)
+
TOTP(start)
VOTP(off) / VOTP(on)
S
Q
Q
Thermal
Foldback
R
VTF
grand reset
Clamp
Rclamp
Vclamp
Figure 67. Thermal Foldback and OVP/OTP Circuitry
www.onsemi.com
25
Latch
NCL30186
The SD pin is clamped to about 1.35 V (Vclamp ) through
a 1.6−kW resistor (Rclamp ). It is then necessary to inject about
ǒ
Ǔ
V OVP * V clamp
R clamp
that is
ǒ2.501.6* k1.35 ^ 700 mAǓ
typically, to trigger the OVP protection. This current helps
ensure an accurate detection by using the Zener diode far
from its knee region.
Programmable Over Temperature Foldback Protection
(OTP)
Figure 68. Output Current Reduction versus SD
Pin Voltage
Connect an NTC between the SD pin and ground to detect
an over−temperature condition. In response to a high
temperature (detected if VSD drops below VTF(start)), the
circuit gradually reduces the LED current down to 50% (>
50% reduction in output power) of its initial value when VSD
reaches VTF(stop), in accordance with the characteristic of
Figure 68 (Note 9).
At this point, if the temperature continues to rise and the
secondary OTP level is reached, (VSD drop below VOTP), the
circuit latches off (A and C versions) or enters auto−recovery
mode (B and D versions) and cannot resume operation until
VSD exceeds VOTP(on) to provide some temperature hysteresis
(around 10°C typically). The OTP thresholds nearly
correspond to the following resistances of the NTC:
• Thermal foldback starts when RNTC ≤ RTF(start)
(11.7 kW, typically)
• Thermal foldback stops when RNTC ≤ RTF(stop) (8.0 kW,
typically)
• OTP triggers when RNTC ≤ ROTP(off) (5.9 kW, typically)
• OTP is removed when RNTC ≤ ROTP(on) (8.0 kW,
typically) (Note 10)
At startup, when VCC reaches VCC(on), the OTP
comparator is blanked for at least 180 ms which allows the
SD pin voltage to reach its nominal value if a filtering
capacitor is connected to the SD pin. This avoids flickering
of the LED light during turn on.
Brown−Out Protection
The NCL30186 prevents operation when the line voltage
is too low for proper operation. As sketched in Figure 69, the
circuit detects a brown−out situation if the VS pin remains
below the VBO(off) threshold (0.9 V typical) for more than
the 25−ms blanking time. In this case, the controller stops
operating. Operation resumes as soon as the VS pin voltage
exceeds VBO(on) (1.0 V typical) and VCC is higher than
VCC(on). To ease recovery, the circuit overrides the VCC
normal sequence (no need for VCC cycling down below
VCC(off)). Instead, its consumption immediately reduces to
ICC(start) so that VCC rapidly charges up to VCC(on) and the
circuit re−starts operation.
Figure 69. Brown−out Circuit
9. The above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum level if PWM or
analog dimming is not engaged or a lower one based on the dimming value.
10. This condition is sufficient for operation recovery of the B and D versions. For the A and C versions which latches off when OTP is triggered,
the circuit further needs to be reset by the VCC drop below VCC(reset).
www.onsemi.com
26
NCL30186
Die Over Temperature (TSD)
Fault Management
The circuit stops operating if the junction temperature (TJ)
exceeds 150°C typically. The controller remains off until TJ
goes below nearly 100°C.
OFF Mode
The circuit turns off in the case of an incorrect feeding of the
circuit: “UVLO high”. The UVLO signal becomes high
when VCC drops below VCC(off) and remains high until
VCC exceeds VCC(on).
The circuit also turns off whenever a major faulty
condition prevents it from operating:
• Severe OTP (VSD level below VOTP(off))
• VCC OVP
• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD_SCP
high”
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
Pin Connection Faults
The circuit addresses most pin connection fault cases:
• CS Pin Short to Ground
The circuit senses the CS pin impedance every time it
starts−up and after DRV pulses terminated by the 36−ms
maximum on−time. If the measured impedance does
not exceed 120 W typically, the circuit stops operating.
In practice, it is recommended to place a minimum of
250 W in series between the CS pin and the current
sense resistor to take into account parasitics.
• Fault of the GND Connection
If the GND pin is properly connected, the supply
current drawn from the positive terminal of the VCC
capacitor, flows out of the GND pin to return to the
negative terminal of the VCC capacitor. If the GND pin
is not connected, the circuit ESD diodes offer another
return path. The accidental non−connection of the GND
pin is monitored by detecting that one of the ESD diode
is conducting. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the
circuit stops generating DRV pulses.
In this mode, the DRV pulses generation is interrupted.
In the case of a latching−off fault, the circuit stops pulsing
until the LED driver is unplugged and VCC drops below
VCC(reset). At that moment, the circuit resumes operation.
In the auto−recovery case, the circuit cannot generate
DRV pulses for the auto−recovery 4−s delay. When this time
has elapsed, the circuit recovers operation as soon as the
VCC voltage has exceeded VCC(on). In the B and D versions,
all these protections are auto−recovery. The SD pin OTP and
OVP, WOD_SCP and AUX_SCP functions are latching off
in the A and C versions (see Table 5).
More generally, incorrect pin connection situations
(open, grounded, shorted to adjacent pin) are covered by
ANDxxxx.
Table 5. PROTECTION MODES
AUX_SCP
WOD_SCP
SD Pin OTP
SD Pin OVP
NCL30186A*
Latching off
Latching off
Latching off
Latching off
NCL30186B
Auto−recovery
Auto−recovery
Auto−recovery
Auto−recovery
NCL30186C*
Latching off
Latching off
Latching off
Latching off
NCL30186D
Auto−recovery
Auto−recovery
Auto−recovery
Auto−recovery
ORDERING INFORMATION
Device
Package Type
Shipping
SOIC−8
(Pb−Free/Halide Free)
2500 / Tape & Reel
NCL30186ADR2G*
NCL30186BDR2G
NCL30186CDR2G*
NCL30186DDR2G
*Please contact local sales representative for availability
www.onsemi.com
27
NCL30186
PACKAGE DIMENSIONS
SOIC−10 NB
CASE 751BQ
ISSUE A
2X
0.10 C A-B
D
D
A
2X
0.10 C A-B
10
F
6
H
E
1
5
0.20 C
10X
B
2X 5 TIPS
L2
b
0.25
A3
L
C
SEATING
PLANE
DETAIL A
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
C A-B D
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
TOP VIEW
10X
h
X 45 _
0.10 C
0.10 C
M
A
A1
e
C
DETAIL A
SEATING
PLANE
END VIEW
SIDE VIEW
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
1.00
PITCH
10X 0.58
6.50
10X 1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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www.onsemi.com
28
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NCL30186/D