Maxim MAX6883ETE+ Dual-/triple-voltage, power-supply sequencers/supervisor Datasheet

19-3772; Rev 1; 10/05
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Applications
Multivoltage Systems
Networking Systems
Telecom
♦ Internal Charge Pumps to Enhance External
n-Channel FETs
♦ Capacitor-Adjustable Timeout Period Power-Good
Output (MAX6880/MAX6882)
♦ Adjustable Undervoltage Lockout or
Logic-Enable Input
♦ Internal 100Ω Pulldown for Each Output to
Discharge Capacitive Load Quickly
♦ 0.5V to 5.5V Nominal IN_/OUT_ Range
♦ 2.7V to 5.5V Operating Voltage Range
♦ Immune to Short Voltage Transients
♦ Small 4mm x 4mm 24-Pin or 16-Pin Thin QFN
Packages
Ordering Information
TEMP RANGE
PINPACKAGE
PKG
CODE
MAX6880ETG+
-40°C to +85°C
24 Thin QFN
T2444-4
MAX6881ETE+
-40°C to +85°C
16 Thin QFN
T1644-4
MAX6882ETE+
-40°C to +85°C
16 Thin QFN
T1644-4
MAX6883ETE+
-40°C to +85°C
16 Thin QFN
T1644-4
PART
+Denotes lead-free package.
N.C.
PG/RST
MARGIN
TOP VIEW
OUT3
Pin Configurations
GATE3
The MAX6880–MAX6883 feature capacitor-adjustable
slew-rate control to provide controlled turn-on characteristics. After all of the voltages reach 92.5% of their
final value, a power-good output (MAX6880/MAX6882)
signal is active. The power-good output (PG/RST) can
be delayed with an external capacitor to create a
power-on reset delay. After the initial power-up phase,
the MAX6880–MAX6883 continue to monitor the voltages. If any of the voltages falls below its threshold, the
MOSFETs are quickly turned off and the voltages are
tracked down together. An internal 100Ω pulldown
resistor ensures that the capacitance at the MOSFET’s
source is discharged quickly. The power-good output
goes low to provide a system reset.
The MAX6880–MAX6883 are available in small 4mm x
4mm 24-pin and 16-pin thin QFN packages and specified over the -40°C to +85°C extended operating temperature range.
♦ Capacitor-Adjustable Power-Up Sequencing
Delay
OUT2
The MAX6880–MAX6883 dual-/triple-voltage monitors
are designed to sequence power supplies during
power-up condition. When all of the voltages exceed
their respective thresholds, these devices turn on voltages to the system sequentially, enhancing n-channel
MOSFETs used as switches. The time between each
sequenced voltage is determined by an external
capacitor, thus allowing flexibility in delay timing. The
MAX6880/MAX6881 sequence three voltages and the
MAX6882/MAX6883 sequence two voltages.
These devices initially monitor all of the voltages and
when all of them are within their tolerances, the internal charge pumps enhance external n-channel
MOSFETs in a sequential manner to apply the voltages to the system. Internal charge pumps drive the
gate voltages 5V above the respective input voltage
thereby ensuring the MOSFETs are fully enhanced to
reduce the on-resistance.
Features
18
17
16
15
14
13
GATE2 19
12
N.C.
OUT1 20
11
N.C.
10
TIMEOUT
9
SLEW
8
DELAY
7
GND
GATE1 21
MAX6880
IN3 22
EP*
IN2 23
+
Storage Equipment
1
2
3
4
5
6
ABP
SET3
SET2
SET1
EN/UV
IN1 24
N.C.
Servers/Workstations
4mm x 4mm THIN QFN
Selector Guide appears at end of data sheet.
*EXPOSED PADDLE CONNECTED TO GND.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX6880–MAX6883
General Description
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
IN1, IN2, IN3.............................................................-0.3V to +6V
ABP .........................................-0.3V to the highest of VIN1 - VIN3
SET1, SET2, SET3 ....................................................-0.3V to +6V
GATE1, GATE2, GATE3 .........................................-0.3V to +12V
OUT1, OUT2, OUT3 .................................................-0.3V to +6V
MARGIN ...................................................................-0.3V to +6V
PG/RST, EN/UV ........................................................-0.3V to +6V
DELAY, SLEW, TIMEOUT .........................................-0.3V to +6V
OUT_ Current....................................................................±50mA
GND Current.....................................................................±50mA
Input/Output Current (all pins except
OUT_ and GND) ...........................................................±20mA
Continuous Power Dissipation (TA = +70°C)
16-Pin 4mm x 4mm Thin QFN
(derate 16.9mW/°C above +70°C) .............................1349mW
24-Pin 4mm x 4mm Thin QFN
(derate 20.8mW/°C above +70°C) .............................1667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, TA = -40°C to +85°C, unless otherwise specified. Typical values are
at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Voltage on the highest of IN_ to ensure that
PG/RST is valid and GATE_ = 0
Operating Voltage Range
SET_ Threshold Range
SET_ Threshold Hysteresis
SET_ Input Current
EN/UV Input Voltage
MAX
ICC
VTH
1.4
2.7
IN1 = 5.5V, IN2 = IN3 = 3.3V, no load
5.5
1.1
1.8
SET_ falling, TA = +25oC
0.4925
0.5
0.5075
SET_ falling, TA = -40 °C to +85°C
0.4875
0.5
0.5125
VTH_HYST
SET_ rising
ISET
SET_ = 0.5V
VEN_R
Input rising
VEN_F
Input falling
IEN
EN/UV Input Pulse Width
tEN
EN/UV falling, 100mV overdrive
DELAY, TIMEOUT Output Current
ID
(Notes 2, 3)
DELAY, TIMEOUT Threshold
Voltage
UNITS
V
EN/UV Input Current
0.5
-100
1.25
-5
VCC = 3.3V
(Note 4)
22.5
Sequence Slew-Rate Timebase
Accuracy
SR
CSLEW = 200pF
-15
100pF < CSLEW < 1nF
Slew-Rate Accuracy during PowerUp and Power-Down
CSLEW = 200pF, VIN_ = 5.5V (Note 4)
V
nA
V
+5
µA
2.88
µA
µs
2.5
1.25
IS
Timebase/CSLEW Ratio
1.28
7
2.12
mA
%
+100
1.286
1.22
SLEW Output Current
2
TYP
IN_
Voltage on the highest of IN_ to ensure the
device is fully operational
Supply Current
MIN
25
V
27.5
µA
+15
%
104
-50
_______________________________________________________________________________________
kΩ
+50
%
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, TA = -40°C to +85°C, unless otherwise specified. Typical values are
at TA = +25°C, unless otherwise noted.) (Note 1)
Power-Good Threshold
Power-Good Threshold Hysteresis
VTH_PG
VOUT_ falling
VHYS_PG
VOUT_ rising
91.5
92.5
IN_ +
4.2
IN_ +
5.0
93.5
0.5
%
%
IN_ +
5.8
V
GATE_ Output High
VGOH
ISOURCE = 0.5µA
GATE_ Pullup Current
IGUP
During power-up and power-down,
VGATE_ = 1V
2.5
4
µA
IGD
During power-up and power-down,
VGATE_ = 5V
2.5
4
µA
GATE_ Pulldown Current
IGDS
SET_ to GATE_ Delay
tD-GATE
When disabled, VGATE_ = 5V, VIN_ ≥ 2.7V
9.5
When disabled, VGATE_ = 5V, VIN_ ≥ 4V
20
SET falling, 25mV overdrive
10
mA
µs
VIN_ ≥ 2.7V, ISINK = 1mA, output asserted
0.3
VIN_ ≥ 4.0V, ISINK = 4mA, output asserted
0.4
V
PG/RST Output Low
VOL
Tracking Differential Voltage Stop
Ramp
VTRK
Differential between each of the OUT_ and
the ramp voltage during power-up and
power-down, Figure 1 (Note 5)
75
125
180
mV
Tracking Differential Fault Voltage
VTRK_F
Differential between each of the OUT_ and
the ramp voltage, Figure 1 (Note 5)
200
250
310
mV
Power-Low Threshold
VTH_PL
OUT_ falling
125
142
170
mV
Power-Low Hysteresis
VTH_PLHYS
OUT_ rising
10
IN_ > 2.7V (Note 6)
100
OUT to GND Pulldown Impedance
MARGIN Pullup Current
MARGIN Input Voltage
MARGIN Glitch Rejection
IIN
7
10
VIL
VIH
mV
Ω
13
0.8
2.0
100
µA
V
ns
Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at TA = +25°C and TA = +85°C.
Specifications at TA = -40°C to +85°C are guaranteed by design. These devices meet the parameters specified when at
least one of IN1/IN2/IN3 is between 2.7V to 5.5V, while the remaining IN1/IN2/IN3 are between 0 and 5.5V.
Note 2: A current ID = 2.5µA ±15% is generated internally and is used to set the DELAY and TIMEOUT periods and used as a reference for tDELAY and tTIMEOUT.
Note 3: The total DELAY is tDELAY = 200µs + (500kΩ x CDELAY). Leave DELAY unconnected for 200µs delay. The total TIMEOUT is
tTIMEOUT = 200µs + (500kΩ x CTIMEOUT). Leave TIMEOUT unconnected for 200µs timeout.
Note 4: A current IS = 25µA ±10% is generated internally and used as a reference for tFAULT, tRETRY, and slew rate.
Note 5: During power-up, only the condition OUT_ < ramp - VTRK is checked in order to stop the ramp. However, both conditions
OUT_ < ramp – VTRK_F and OUT_ > ramp + VTRK_F cause a fault. During power-down, only the condition OUT > ramp +
VTRK is checked in order to stop the ramp. However, both conditions OUT_ < ramp - VTRK_F and OUT_ > ramp + VTRK_F
cause a fault (see Figure 10). Therefore, if OUT1, OUT2, and OUT3 (during power-up tracking and power-down) differ by
more than 2 x VTRK_F, a fault condition is asserted.
Note 6: A 100Ω pulldown to GND activated by a fault condition. See the Internal Pulldown section.
_______________________________________________________________________________________
3
MAX6880–MAX6883
ELECTRICAL CHARACTERISTICS (continued)
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
125mV DOWN =
STOP RAMP THRESHOLD
250mV UP =
FAULT THRESHOLD
250mV UP =
FAULT THRESHOLD
250mV DOWN =
FAULT THRESHOLD
250mV DOWN =
FAULT THRESHOLD
125mV UP =
STOP RAMP THRESHOLD
REFERENCE RAMP
REFERENCE RAMP
POWER-UP
POWER-DOWN
Figure 1. Stop Ramp/Fault Window During Power-Up and Power-Down
EN/UV
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
VEN_R
VEN_F
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITORADJUSTED
SLEW RATE
OUT1 = 3.3V
OUT2 = 1.8V
OUT_
OUT3 = 0.7V
tDELAY
PG/RST
tDELAY
tDELAY
tTIMEOUT
Figure 2. Sequencing In Normal Mode
4
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
MAX6880–MAX6883
EN/UV
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
VEN_R
IN1 = 3.3V
IN2 = 1.8V
IN_
IN3 = 0.7V
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITORADJUSTED
SLEW RATE
OUT_ FORCED
BELOW VTH_PG
OUT1 = 3.3V
OUT2 = 1.8V
OUT_
OUT3 = 0.7V
tDELAY
tDELAY
PG/RST
tDELAY
tTIMEOUT
FORCED INTO QUICK SHUTDOWN WHEN OUT1 FALLS BELOW 92.5% of IN1
Figure 3. Sequencing In Fast Shutdown Mode
_______________________________________________________________________________________
5
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
EN/UV
EN/UV
BUS VOLTAGE MONITORED
THROUGH EN/UV INPUT
VEN_R
VEN_F
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITORADJUSTED
SLEW RATE
OUT1 = 3.3V
OUT2 = 1.8V
OUT_
OUT3 = 0.7V
tDELAY
tDELAY
tDELAY
tTIMEOUT
PG/RST = LOW
Figure 4. Timing Diagram (Aborted Sequencing)
EN/UV
VEN_R
OUT1
OUT1
OUT2
OUT2
OUT_
OUT3 IS SLOW
OUT3 IS SLOW
tDELAY
tDELAY
tFAULT
tDELAY
tDELAY
tRETRY
tFAULT
tDELAY
tDELAY
tFAULT AND tRETRY NOT TO SCALE
ALL SET > 0.5V AND IN_ ≥ 2.7V
Figure 5. tFAULT and tRETRY Timing Diagram in Sequencing
6
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
(VIN_ = 2.7V to 5.5V, CSLEW = 200pF, EN = MARGIN = ABP, TA = +25°C, unless otherwise noted.)
VCC SUPPLY CURRENT
vs. INPUT VOLTAGE
NORMALIZED POWER-GOOD TIMEOUT
vs. TEMPERATURE
1.1
TA = +25°C
TA = -40°C
0.9
0.8
3.0
3.5
4.0
4.5
5.0
0.95
0.90
0.85
MAX6880 toc03
100
10
1
0.80
5.5
-40
-15
10
35
60
0.1
0.0001
85
0.001
0.01
0.1
INPUT VOLTAGE (V)
TEMPERATURE (°C)
CDELAY (µF)
NORMALIZED SET_ THRESHOLD
vs. TEMPERATURE
NORMALIZED DELAY TIMEOUT
vs. TEMPERATURE
SLEW RATE
vs. CSLEW
1.002
1.001
1.000
0.999
0.998
0.997
1.20
0.996
1.15
1.10
1.05
1.00
0.95
1
10,000
SLEW RATE (V/s)
1.003
1.25
MAX6880 toc05
1.004
NORMALIZED DELAY TIMEOUT
MAX6880 toc04
1.005
0.90
1000
100
0.85
0.80
0.995
0.75
-15
10
35
60
85
10
-40
-15
10
35
60
85
100
1000
10,000
CSLEW (pF)
DELAY TIMEOUT
vs. CDELAY
NORMALIZED EN/UV THRESHOLD
vs. TEMPERATURE
IN_ TRANSIENT DURATION
vs. IN THRESHOLD OVERDRIVE
10
1
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.01
CDELAY (µF)
0.1
1
IN_ = 3.3V
27
24
21
18
15
12
PG/RST GOES LOW ABOVE THE CURVE
9
6
3
0.995
0.001
30
IN_ TRANSIENT DURATION (µs)
MAX6880 toc07
100
1.005
MAX6880 toc09
TEMPERATURE (°C)
1000
0.1
0.0001
10
TEMPERATURE (°C)
NORMALIZED EN_/UV THRESHOLD
-40
MAX6880 toc08
NORMALIZED SET_ THRESHOLD
1.00
0.75
2.5
DELAY TIMEOUT (ms)
1.05
MAX6880 toc06
1.0
1.10
1000
POWER-GOOD TIMEOUT (ms)
TA = +85°C
1.2
MAX6880 toc02
1.3
1.15
NORMALIZED POWER-GOOD TIMEOUT
MAX6880 toc01
VCC SUPPLY CURRENT (mA)
1.4
POWER-GOOD TIMEOUT
vs. CTIMEOUT
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
0
50
100
150
200
250
300
IN_ THRESHOLD OVERDRIVE (mV)
_______________________________________________________________________________________
7
MAX6880–MAX6883
Typical Operating Characteristics
Typical Operating Characteristics (continued)
(VIN_ = 2.7V to 5.5V, CSLEW = 200pF, EN = MARGIN = ABP, TA = +25°C, unless otherwise noted.)
GATE_ VOLTAGE LOW
vs. SINK CURRENT
GATE_ OUTPUT VOLTAGE HIGH
vs. GATE SOURCE CURRENT
1.4
9
8
GATE VOLTAGE (V)
1.2
1.0
0.8
0.6
SEQUENCING MODE
MAX6880 toc12
MAX6880 toc11
10
MAX6880 toc10
1.6
GATE_ VOLTAGE LOW (V)
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
EN/UV
2V/div
OUT1
1V/div
7
6
OUT2
1V/div
OUT3
1V/div
5
4
3
0.4
2
0.2
1
0
0
0
1
2
3
4
5
6
7
8
9
10
0
GATE SINK CURRENT (mA)
0.5
1.0
1.5
2.0
2.5
20ms/div
3.0
GATE SOURCE CURRENT (µA)
FAST SHUTDOWN WITH RETRY
FAST SHUTDOWN WITH RETRY
MAX6880 toc13
MAX6880 toc14
EN/UV
2V/div
OUT1
2V/div
OUT2
2V/div
OUT1
1V/div
OUT3 PULLED BELOW
92.5% OF IN3 FOR
SEQUENCING MODE
OUT3
2V/div
OUT2
1V/div
OUT3
1V/div
40ms/div
8
PG/RST
1V/div
100ms/div
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
PIN
NAME
FUNCTION
MAX6880
MAX6881
MAX6882
MAX6883
1, 11,
12, 15
—
—
1, 8, 9, 10
N.C.
No Connection. Not internally connected.
2
—
1
—
ABP
Internal Supply Bypass Input. Bypass ABP with a 1µF capacitor to
GND. ABP maintains the device supply voltage during rapid powerdown conditions.
3
2
—
—
SET3
4
3
2
2
SET2
5
4
3
3
SET1
6
5
4
4
EN/UV
7
6
5
5
GND
Externally Adjusted IN_ Undervoltage Lockout Threshold. Connect
SET_ to an external resistor-divider network to set the desired
undervoltage threshold for each IN_ supply (see the Typical
Application Circuit). All SET_ inputs must be above the internal
SET_ threshold (0.5V) to enable sequencing functionality.
Logic-Enable Input or Undervoltage Lockout Monitor Input. EN/UV
must be high (EN/UV > VEN_R) to enable voltage sequencing
power-up operation. OUT_ begins tracking down when EN/UV <
VEN_F. Connect EN/UV to an external resistor-divider network to set
the external UVLO threshold.
Ground
8
7
6
6
DELAY
Sequence Delay Select Input. Connect a capacitor from DELAY
to GND to select the desired delay period before sequencing is
enabled (after all SET_ inputs and EN/UV are above their respective
thresholds) or between supply sequences. Leave DELAY
unconnected for the default 200µs delay period.
9
8
7
7
SLEW
Slew-Rate Adjustment Input. Connect a capacitor from SLEW
to GND to select the desired OUT_ slew rate.
10
—
8
—
13
—
9
—
PG/RST Timeout Period Adjust Input. PG/RST asserts high after the
timeout period when all OUT_ exceed their IN_ referenced
TIMEOUT threshold. Connect a capacitor from TIMEOUT to GND to set the
desired timeout period. Leave TIMEOUT unconnected for the
default 200µs delay period.
Margin Input, Active-Low. Drive MARGIN low to enable margin
mode (see the Margin section). The MARGIN functionality is
MARGIN disabled (returns to normal monitoring mode) after MARGIN returns
high. MARGIN is internally pulled up to ABP through a 10µA
current source.
_______________________________________________________________________________________
9
MAX6880–MAX6883
Pin Description
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Pin Description (continued)
PIN
NAME
FUNCTION
MAX6880
MAX6881
MAX6882
MAX6883
14
—
10
—
PG/RST
16
9
—
—
OUT3
Channel 3 Monitored Output Voltage. Connect OUT3 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
17
10
—
—
GATE3
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE3 to VIN3 + 5V to fully enhance the external n-channel
FET when power-up is complete.
18
11
11
11
OUT2
Channel 2 Monitored Output Voltage. Connect OUT2 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
19
12
12
12
GATE2
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE2 to VIN2 + 5V to fully enhance the external n-channel
FET when power-up is complete.
20
13
13
13
OUT1
Channel 1 Monitored Output Voltage. Connect OUT1 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
21
14
14
14
GATE1
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE1 to VIN1 + 5V to fully enhance the external n-channel
FET when power-up is complete.
22
15
—
—
IN3
23
16
15
15
IN2
24
1
16
16
IN1
EP
EP
EP
EP
EP
10
Power-Good Output, Open-Drain. PG_RST asserts high tTIMEOUT
after all OUT_ voltages exceed the VTH_PG thresholds.
Supply Input Voltage. IN1, IN2, or IN3 must be greater than the
internal undervoltage lockout (VABP = 2.7V) to enable the
sequencing functionality. Each IN_ input is simultaneously
monitored by SET_ inputs to ensure all supplies have stabilized
before power-up is enabled. If IN_ is connected to ground or left
unconnected and SET_ is above 0.5V, then no sequencing control
is performed on that channel. Each IN_ is internally pulled down by
a 100kΩ resistor.
Exposed Paddle. Connect exposed paddle to ground.
______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
IN1
TO LOAD
IN2 IN3
IN1
OUT1
GATE1
ABP
INTERNAL
VCC/UVLO
IN1
MAX6880
CHARGE
PUMP
SET1
RAMP
GENERATOR
IN2
COMP
GATE
CONTROLLER
SET2
IN3
COMP
CONTROL
LOGIC
IN2 TO OUT2
CONTROL BLOCK
SET3
VBUS
COMP
GATE2
OUT2
OUT1
OUT2
SEQUENCING
MONITOR
EN/UV
COMP
OUT3
IN1
IN3 TO OUT3
CONTROL BLOCK
GATE3
OUT3
IN2
IN3
VREF
PG CIRCUIT
MARGIN
GND
DELAY
SLEW
CSLEW
TIMEOUT
PG/RST
CTIMEOUT
______________________________________________________________________________________
11
MAX6880–MAX6883
Functional Diagram
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Detailed Description
The MAX6880–MAX6883 multivoltage power
sequencers/supervisors monitor three (MAX6880/
MAX6881) and two (MAX6882/MAX6883) system voltages and provide proper power-up and power-down
control for systems requiring voltage sequencing. These
devices ensure the controlled voltages sequence in the
proper order as system power supplies are enabled.
The MAX6880–MAX6883 generate all required voltages
and timing to control up to three external n-channel
pass FETs for the OUT1/OUT2/OUT3 supply voltages.
The MAX6880–MAX6883 feature adjustable undervoltage thresholds for each input supply. When all of the
voltages are above the adjusted thresholds these
devices turn on the external n-channel MOSFETs to
sequence the voltages to the system. The outputs are
turned on one after the other, OUT1 first and OUT3 last.
The MAX6880–MAX6883 feature internal charge pumps
to fully enhance the external FETs for low-voltage drops
at highpass currents. The MAX6880/MAX6882 also feature a power-good output (PG/RST) with a selectable
timeout period that can be used for system reset.
The MAX6880–MAX6883 monitor up to three voltages.
Devices may be configured to exclude any IN_. To disable sequencing operation of any IN_, connect the IN_
to ground (or leave unconnected) and connect SET_ to
a voltage greater than 0.5V. The channel exclusion feature adds more flexibility to the device in a variety of
different applications. As an example, the MAX6880
can sequence two voltages using IN1 and IN2 while
IN3 is left disabled.
Powering the MAX6880–MAX6883
These devices derive power from either IN1, IN2, or IN3
voltage inputs (see the Functional Diagram). In order to
ensure proper operation, at least one of the IN_ inputs
must be at least +2.7V.
The highest input voltage on IN1/IN2/IN3 supplies
power to the devices. Internal hysteresis ensures that
the supply input that initially powers these devices continues to power the MAX6880–MAX6883 when multiple
input voltages are within 100mV (typ) of each other.
Sequencing
The sequencing operation can be initiated after all
input conditions for power-up are met VEN/UV > 1.25V
and all SET_ inputs are above the internal SET_ threshold (0.5V). In sequencing mode, the outputs are turned
on sequentially, OUT1 first and OUT3 last. Before turning on each channel, a delay period is waited (programmable by connecting a capacitor from DELAY to
ground. The power-up phase for each channel ends
12
when its output voltage exceeds a fixed percentage
(VTH_PG) of the corresponding IN_ voltage. When all
channels have exceeded these thresholds, PG/RST
asserts high after tTIMEOUT, indicating a successful
sequence.
If there is a fault condition during the initial power-up
sequence, the process is aborted.
When powering down, all outputs turn off simultaneously, tracking each other. No reverse power-down
sequencing occurs.
The power-supply sequencing operation should be
completed within the selected fault timeout period
(tFAULT) (see Figure 5). The total sequencing time is
extended when the devices must vary the control slew
rate to allow slow supplies to catch up. If the external
FET is too small (RDS is too high for the selected load
current and IN_ source current), the OUT_ voltage may
never reach the control ramp voltage. For a slew rate of
935V/s, a fault is signaled if all outputs have not stabilized within 22ms. For a slew rate of 93.5V/s, a fault is
signaled if sequencing takes too long (more than
219ms).
The fault time period (tFAULT) is set through the capacitor at SLEW (CSLEW). Use the following formula to estimate the fault timeout period:
tFAULT = 2.191 x 108 x CSLEW
Autoretry Function
The MAX6880/MAX6881/MAX6882 feature autoretry
modes to power-on again after a fault condition has been
detected (see the Typical Operating Characteristics).
When a fault is detected, for a period of tRETRY, GATE_
remains off and the 100Ω pulldowns are turned on.
After the tRETRY period, the device waits tDELAY and
retry sequencing if all power-up conditions are met
(see Figure 5). These include all VSET_ > 0.5V, EN/UV >
VEN_R, and OUT_ voltages < VTH_PL. The autoretry
period tRETRY is a function of CSLEW (see Table 1).
Power-Up and Power-Down
During power-up, OUT_ is forced to follow the internal
reference ramp voltage by an internal loop that controls
the GATE_ of the external MOSFET. This phase must
be completed within the adjustable fault timeout period
(tFAULT); otherwise, the part forces a shutdown on all
GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing VEN/UV below VEN_F. The
reference voltage ramp ramps down at the capacitoradjusted slew rate. The control-loop comparators monitor each OUT_ voltage with respect to the common
______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Internal Pulldown
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ω internal pulldown at OUT_. The pulldown ensures that all OUT_ voltages are below VTH_PL
(referenced to GND) before power-up cycling is initiated. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
Stability Comment
No external compensation is required for sequencing
or slew-rate control.
Inputs
IN1/IN2/IN3
The highest voltage on IN1, IN2, or IN3 supplies power
to the device. The undervoltage threshold for each IN_
supply is set with an external resistor-divider from each
IN_ to SET_ to ground. To disable sequencing on any
IN_, connect IN_ to ground (or leave unconnected) and
connect SET_ to a voltage greater than 0.5V.
Undervoltage Lockout Threshold Inputs (SET_)
The MAX6880/MAX6881 feature three and the MAX6882/
MAX6883 feature two externally adjustable IN_ undervoltage lockout thresholds (SET1/SET2/SET3). The 0.5V
SET_ threshold enables monitoring IN_ voltages as low
as 0.5V. The undervoltage threshold for each IN_ supply is set with an external resistor-divider from each IN_
to SET_ to ground (see Figure 6). All SET_ inputs must
be above the internal SET_ threshold (0.5V) to enable
sequencing functionality. Use the following formula to
set the UVLO threshold:
VIN_ = VTH (R1 + R2) / R2
where VIN_ is the undervoltage lockout threshold and
VTH is the 500mV SET threshold.
MARGIN) (MAX6880/MAX6882)
Margin Input (M
MARGIN allows system-level testing while power supplies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
voltages below the adjusted thresholds to avoid signaling an error. The state of PG/RST does not change
while MARGIN is low. PG/RST and all monitoring functions are disabled while MARGIN is low. MARGIN
makes it possible to vary the supplies without a need to
adjust the thresholds to prevent sequencer alerts. Drive
MARGIN high or leave it unconnected for normal operating mode.
Slew-Rate Control Input (SLEW)
The reference ramp voltage slew rate during any controlled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
(CSLEW) from SLEW to ground. Use the following formula to calculate the typical slew rate:
Slew Rate = (9.35 x 10-8)/ CSLEW
where slew rate is in V/s and CSLEW is in farads.
The capacitor at CSLEW also sets the retry timeout period (tRETRY), see Table 1.
For example, if CSLEW = 100pF, we have tRETRY =
350ms, t FAULT = 21.91ms, slew rate = 935V/s. For
example, if CSLEW = 1nF, we have tRETRY = 3.5s, slew
rate = 93.5V/s.
CSLEW is the capacitor on SLEW pad, and must be
large enough so the parasitic PC board capacitance is
negligible. CSLEW should be in the range of 100pF <
CSLEW < 1nF.
VIN_
IN_
R1
MAX6880–
MAX6883
SET_
R2
Figure 6. Setting the Undervoltage (UVLO) Thresholds
______________________________________________________________________________________
13
MAX6880–MAX6883
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than VTRK, the control loop dynamically stops the
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
or less than the reference ramp voltage by more than
VTRK_F, a fault is signaled and the fast-shutdown mode
is initiated. In fast-shutdown mode, a 100Ω pulldown
resistor is connected from OUT_ to GND to quickly discharge capacitance at OUT_, and GATE_ is pulled low
with a strong IGDS current (see Figure 3).
Figure 4 shows the aborted sequencing mode. When
EN/UV goes low before tTIMEOUT expires, all the outputs go low, and the device goes into fast shutdown.
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Table 1. CSLEW Timing Formulas
TIME PERIOD
FORMULAS
Slew Rate
(9.35 x 10-8) / CSLEW
tRETRY
3.506 x 109 x CSLEW
tFAULT
2.191 x 108 x CSLEW
Limiting Inrush Current
The capacitor (CSLEW) at SLEW to ground, controls the
OUT_ slew rate, thus controlling the inrush current
required to charge the load capacitor at OUT_. Using
the programmed slew rate, limit the inrush current by
using the following formula:
IINRUSH = COUT x SR
where IINRUSH is in amperes, COUT is in farads, and SR
is in V/s.
Delay Time Input (DELAY)
To adjust the desired delay period (t DELAY ) before
sequencing is enabled, connect a capacitor (CDELAY)
between DELAY to ground (see Figures 2 to 5). The
selected delay time is also enforced when EN/UV rises
from low to high when all the input voltages are present.
Use the following formula to calculate the delay time:
tDELAY = 200µs + (500kΩ x CDELAY)
where tDELAY is in µs and CDELAY is in farads. Leave
DELAY unconnected for the default 200µs delay.
Timeout Period Input (TIMEOUT)
(MAX6880/MAX6882)
These devices feature a PG/RST timeout period.
Connect a capacitor (C TIMEOUT ) from TIMEOUT to
ground to program the PG/RST timeout period. After all
OUT_ outputs exceed their IN_ referenced thresholds
(VTH_PG), PG/RST remains low for the selected timeout
period tTIMEOUT (see Figure 3).
tTIMEOUT = 200µs + (500kΩ x CTIMEOUT)
where tTIMEOUT is in µs and CTIMEOUT is in farads.
Leave TIMEOUT unconnected for the default 200µs
timeout delay.
UV)
Logic-Enable Input (EN/U
Drive logic EN/UV input above VEN_R to initiate voltage
sequencing during power-up operation. Drive logic
EN/UV below V EN_F to initiate tracking power-down
operation. Connect EN/UV to an external resistordivider network to set the external undervoltage lockout
threshold.
14
ABP Input (MAX6880/MAX6882)
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. ABP takes the highest voltage of
IN_. Do not use ABP to provide power to external circuitry. ABP maintains the device supply voltage during
rapid power-down conditions.
OUT1/OUT2/OUT3
The MAX6880/MAX6881 monitor three OUT_ and the
MAX6882/MAX6883 monitor two OUT_ outputs to control the sequencing performance. After the internal supply (ABP) exceeds the minimum voltage (2.7V)
requirements, EN/UV > VEN_R, and IN1/IN2/IN3 are all
greater than their adjusted SET_ thresholds, OUT1/
OUT2/OUT3 begin to sequence.
During fault conditions, an internal pulldown resistor
(100Ω) on OUT_ is enabled to help discharge load
capacitance (100Ω is connected for fast power-down
control).
Outputs
GATE_
The MAX6880–MAX6883 feature up to three GATE_ outputs to drive up to three external n-channel FET gates.
The following conditions must be met before GATE_
begins enhancing the external n-channel FET_:
1) All SET_ inputs (SET1/SET2/SET3) are above their
0.5V thresholds.
2) At least one IN_ input is above the minimum operating voltage (2.7V).
3) EN/UV > 1.25V.
At power-up mode, GATE_ voltages are enhanced by
control loops so all OUT_ voltages sequence at a
capacitor-adjusted slew rate. Each GATE_ is internally
pulled up to 5V above its relative IN_ voltage to fully
enhance the external n-channel FET when power-up is
complete.
Power-Good Output (PG/RST) (MAX6880/MAX6882)
The MAX6880/MAX6882 include a power-good (PG/RST)
output. PG/RST is an open-drain output and requires an
external pullup resistor.
All the OUT_ outputs must exceed their IN_ referenced
thresholds (IN_ x VTH_PG) for the selected reset timeout
period tTIMEOUT (see the TIMEOUT Period Input section) before PG/RST asserts high. PG/RST stays low for
the selected reset timeout period (tTIMEOUT) after all
the OUT_ voltages exceed their IN_ referenced thresholds. PG/RST goes low when VSET_ < VTH or VEN/UV <
VEN_R (see Figure 2).
______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
MOSFET Selection
The external pass MOSFET is connected in series with
the sequenced power-supply source. Since the load
current and the MOSFET drain-to-source impedance
(RDS) determine the voltage drop, the on characteristics of the MOSFET affect the load supply accuracy.
The MAX6880–MAX6883 fully enhance the external
MOSFET out of its linear range to ensure the lowest
drain-to-source on-impedance. For highest supply
accuracy/lowest voltage drop, select a MOSFET with
an appropriate drain-to-source on-impedance with a
gate-to-source bias of 4.5V to 6.0V.
Layout and Bypassing
For better noise immunity, bypass each of the IN_
inputs to GND with 0.1µF capacitors installed as close
to the device as possible. Bypass ABP to GND with a
1µF capacitor installed as close to the device as possible. ABP is an internally generated voltage and must
not be used to supply power to external circuitry.
Selector Guide
PART
CHANNEL
TIMEOUT
SELECTABLE
PG/RST
MARGIN
PG THRESHOLD
VOLTAGE (%)
MAX6880
3
Yes
Yes
Yes
92.5
MAX6881
3
No
No
No
—
MAX6882
2
Yes
Yes
Yes
92.5
MAX6883
2
No
No
No
—
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________
15
MAX6880–MAX6883
Applications Information
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
MAX6880–MAX6883
Typical Application Circuit
IN1
OUT1
IN2
OUT2
IN3
OUT3
0.1µF
IN1
IN2
0.1µF
0.1µF
IN3
SET1
GATE1
GATE2
GATE3
OUT1
SET2
OUT2
MAX6880
SET3
OUT3
VBUS
EN/UV
PG/RST
MARGIN
ABP
SLEW
GND
DELAY TIMEOUT
1µF
16
______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
GATE2
OUT2
GATE3
OUT3
GATE2
OUT2
PG/RST
MARGIN
TOP VIEW
12
11
10
9
12
11
10
9
OUT1 13
8
SLEW
OUT1 13
8
TIMEOUT
GATE1 14
7
DELAY
GATE1 14
7
SLEW
6
GND
6
DELAY
5
GND
MAX6881
IN3 15
MAX6882
IN2 15
EP*
EP*
4
SET3
SET2
SET1
1
2
3
4
EN/UV
3
+
SET1
2
IN1 16
SET2
1
EN/UV
ABP
5
+
IN1
IN2 16
4mm x 4mm THIN QFN
GATE2
OUT2
N.C.
N.C.
4mm x 4mm THIN QFN
12
11
10
9
OUT1 13
8
N.C.
GATE1 14
7
SLEW
6
DELAY
5
GND
MAX6883
IN2 15
EP*
1
2
3
4
SET2
SET1
EN/UV
+
N.C.
IN1 16
4mm x 4mm THIN QFN
*EXPOSED PADDLE CONNECTED TO GND.
______________________________________________________________________________________
17
MAX6880–MAX6883
Pin Configurations (continued)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
18
______________________________________________________________________________________
E
1
2
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2005 Maxim Integrated Products
Heaney
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX6880–MAX6883
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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