Maxim MAX1088EKA-T 150ksps, 10-bit, 2-channel single-ended, and 1-channel true-differential adcs in sot23 Datasheet

19-2036; Rev 1; 8/07
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Features
The MAX1086–MAX1089 are low-cost, micropower, serial output 10-bit analog-to-digital converters (ADCs)
available in a tiny 8-pin SOT23. The MAX1086/MAX1088
operate with a single +5V supply. The MAX1087/MAX1089
operate with a single +3V supply. The devices feature a
successive-approximation ADC, automatic shutdown,
fast wake-up (1.4µs), and a high-speed 3-wire interface. Power consumption is only 0.5mW (VDD = +2.7V)
at the maximum sampling rate of 150ksps.
AutoShutdown™ (0.1µA) between conversions results in
reduced power consumption at slower throughput rates.
The MAX1086/MAX1087 provide 2-channel, singleended operation and accept input signals from 0 to
VREF. The MAX1088/MAX1089 accept true-differential
inputs ranging from 0 to VREF. Data is accessed using
an external clock through the 3-wire SPI™, QSPI™, and
MICROWIRE™-compatible serial interface. Excellent
dynamic performance, low-power, ease of use, and
small package size, make these converters ideal for
portable battery-powered data acquisition applications,
and for other applications that demand low power consumption and minimal space.
♦ Single-Supply Operation
+3V (MAX1087/MAX1089)
+5V (MAX1086/MAX1088)
♦ AutoShutdown Between Conversions
♦ Low Power
200µA at 150ksps
130µA at 100ksps
65µA at 50ksps
13µA at 10ksps
1.5µA at 1ksps
0.2µA in Shutdown
♦ True-Differential Track/Hold, 150kHz Sampling Rate
♦ Software-Configurable Unipolar/Bipolar
Conversion (MAX1088/MAX1089 only)
♦ SPI, QSPI, MICROWIRE-Compatible Interface for
DSPs and Processors
♦ Internal Conversion Clock
♦ 8-Pin SOT23 Package
Applications
Ordering Information
TEMP
RANGE
PART
PINPACKAGE
TOP
MARK
8 SOT23
AAEZ
AAEV
MAX1086EKA-T
-40°C to +85°C
Low Power Data Acquisition
MAX1087EKA-T
-40°C to +85°C
8 SOT23
Portable Temperature Monitors
MAX1087ETA+T
-40°C to +85°C
8 TDFN-EP*
AFM
MAX1088EKA-T
-40°C to +85°C
8 SOT23
AAFB
MAX1089EKA-T
-40°C to +85°C
*EP = Exposed pad.
+Denotes a lead-free package.
T = Tape and reel.
8 SOT23
AAEX
Flowmeters
Touch Screens
Pin Configurations
VDD
1
AIN1 (AIN+)
2
AIN2 (AIN-)
3
GND 4
8
MAX1086
MAX1087
MAX1088
MAX1089
SCLK
DOUT
CONVST
REF
TOP VIEW
8
7
6
5
SCLK
7
DOUT
6
CNVST
5
REF
MAX1087
1
2
3
4
AIN1
AIN2
GND
( ) ARE FOR THE MAX1088/MAX1089
VDD
+
SOT23-8
TDFN
AutoShutdown is a trademark of Maxim Integrated Products.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1086–MAX1089
General Description
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V
CNVST, SCLK, DOUT to GND......................-0.3V to (VDD+0.3V)
REF, AIN1(AIN+), AIN2(AIN-) to GND..........-0.3V to (VDD+0.3V)
Maximum Current Into Any Pin ...........................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 9.70mW/°C above TA = +70°C) ......777mW
8-Pin TDFN (derate 18.2mW/°C above TA = +70°C)...1454.5mW
Operating Temperature Ranges.........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088,
0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise
noted. Typical values at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1.0
LSB
DC ACCURACY (Note 1)
Resolution
10
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
±1.0
LSB
Offset Error
±0.5
±1.0
LSB
Gain Error (Note 3)
±1.0
±2.0
LSB
Gain Temperature Coefficient
Channel-to-Channel Offset
±0.8
ppm/°C
±0.1
LSB
Channel-to-Channel Gain Matching
±0.1
LSB
±0.1
mV
Input Common-Mode Rejection
CMR
No missing codes over temperature
VCM = 0V to VDD; zero scale input
DYNAMIC SPECIFICATIONS: (fIN (sine-wave) = 10kHz, VIN = 4.096Vp-p for MAX1086/MAX1088 or VIN = 2.5VPP
for MAX1087/MAX1089, 150ksps, fSCLK = 8MHz, AIN- = GND for MAX1088/MAX1089)
Signal to Noise Plus Distortion
SINAD
61
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
dB
Spurious-Free Dynamic Range
SFDR
Full-Power Bandwidth
-3dB point
Full-Linear Bandwidth
SINAD > 56dB
70
dB
1
MHz
100
kHz
CONVERSION RATE
Conversion Time
T/H Acquisition Time
tCONV
3.7
µs
tACQ
1.4
µs
Aperture Delay
30
ns
Aperture Jitter
<50
ps
Maximum Serial Clock Frequency
Duty Cycle
2
fSCLK
8
30
_______________________________________________________________________________________
MHz
70
%
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088,
0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise
noted. Typical values at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Unipolar
Input Voltage Range (Note 4)
Bipolar
Input Leakage Current
0
VREF
-VREF /2
VREF/2
±0.01
Channel not selected or conversion stopped
Input Capacitance
±1
34
V
µA
pF
EXTERNAL REFERENCE INPUT
Input Voltage Range
VREF
Input Current
IREF
VDD
+50mV
1.0
VREF = +2.5V at 150ksps
16
30
VREF = +4.096V at 150ksps
26
45
±0.01
±1
Acquisition/Between conversions
V
µA
DIGITAL INPUTS/OUTPUTS (SCLK, CNVST, DOUT)
Input Low Voltage
VIL
Input High Voltage
VIH
Input Leakage Current
CIN
Output Low Voltage
VOL
Output High Voltage
VOH
Three-State Leakage Current
Three-State Output Capacitance
±0.1
µA
V
15
pF
ISINK = 2mA
0.4
V
ISINK = 4mA
0.8
V
VDD
-0.5
ISOURCE = 1.5mA
V
±10
CNVST = GND
COUT
V
VDD -1
IL
Input Capacitance
0.8
CNVST = GND
15
µA
pF
POWER REQUIREMENTS
Positive Supply Voltage
VDD
MAX1086/MAX1088
4.75
5.0
5.25
MAX1087/MAX1089
2.7
3.0
3.6
fSAMPLE =150ksps
245
350
fSAMPLE =100ksps
150
fSAMPLE =10ksps
15
VDD = +3V
fSAMPLE =1ksps
Positive Supply Current
IDD
VDD = +5V
Positive Supply Rejection
PSR
V
2
fSAMPLE =150ksps
320
fSAMPLE =100ksps
215
fSAMPLE =10ksps
22
fSAMPLE =1ksps
2.5
400
Shutdown
0.2
5
VDD = 5V ±5%; full-scale input
±0.1
1.0
VDD = +2.7V to +3.6V; full-scale input
±0.1
±1.2
µA
mV
_______________________________________________________________________________________
3
MAX1086–MAX1089
ELECTRICAL CHARACTERISTICS (continued)
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
TIMING CHARACTERISTICS (Figures 1 and 2)
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088,
0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise
noted. Typical values at TA = +25°C.)
PARAMETERS
SYMBOL
SCLK Pulse Width High
CONDITIONS
MIN
tCH
SCLK Pulse Width Low
TYP
MAX
38
tCL
UNITS
ns
38
ns
SCLK Fall to DOUT Transition
tDOT
CLOAD = 30pF
SCLK Rise to DOUT Disable
tDOD
CLOAD = 30pF
CNVST Rise to DOUT Enable
tDOE
CLOAD = 30pF
80
ns
CNVST Fall to MSB Valid
tDOV
CLOAD = 30pF
3.7
µs
CNVST Pulse Width
tCSW
100
60
ns
500
ns
30
ns
Note 1: Unipolar input.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: The absolute input range for the analog inputs is from GND to VDD.
•••
CNVST
tCH
tCL
SCLK
•••
tDOE
DOUT
tDOT
tDOD
HIGH-Z
HIGH-Z
•••
Figure 1. Detailed Serial-Interface Timing Sequence
VDD
6kΩ
DOUT
DOUT
6kΩ
CL
GND
a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z
CL
GND
a) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z
Figure 2. Load Circuits for Enable/Disable Times
4
tCSW
_______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.6
1.0
0.6
0.4
0.2
0.2
0.2
-0.2
DNL (LSB)
0.4
0
0
-0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
200
400
600
800
1000
-1.0
0
1200
200
400
600
800
1000
1200
0
200
400
600
800
OUTPUT CODE
OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
SUPPLY CURRENT
vs. SAMPLING RATE
SUPPLY CURRENT
vs. SAMPLING RATE
0.8
SUPPLY CURRENT (µA)
0.6
1000
0.4
0.2
0
-0.2
-0.4
MAX1087/MAX1089
1000
100
SUPPLY CURRENT (µA)
MAX1086/MAX1088
MAX1086-9 toc05
1.0
10
1
-0.6
1000
1200
MAX1086-9 toc06
OUTPUT CODE
MAX1086-9 toc04
0
MAX1087/MAX1089
0.8
0.4
-1.0
MAX1086/MAX1088
100
10
1
-0.8
0.1
0.001
-1.0
200
400
600
800
1000
1200
OUTPUT CODE
10
1.0
0.1
0.001
1000
1.0
SAMPLING RATE (ksps)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
10
1000
SAMPLING RATE (ksps)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
330
280
230
0.50
MAX1086-9 toc08
380
0.45
SHUTDOWN CURRENT (nA)
MAX1086-9 toc07
0
SUPPLY CURRENT ( µA)
DNL (LSB)
MAX1086/MAX1088
0.8
INL (LSB)
INL (LSB)
0.6
1.0
MAX1086-9 toc03
MAX1087/MAX1089
0.8
MAX1086-9 toc01
1.0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1086-9 toc02
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
180
2.7
3.2
3.7
4.2
VDD (V)
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
VDD (V)
_______________________________________________________________________________________
5
MAX1086–MAX1089
Typical Operating Characteristics
(VDD = +3.0V, VREF = +2.5V for MAX1087/MAX1089 or VDD = +5.0V, VREF = +4.096V for MAX1086/MAX1088, 0.1µF capacitor at
REF, fSCLK = 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/1089, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.5V for MAX1087/MAX1089 or VDD = 5.0V, VREF = +4.096V for MAX1086MAX1088, 0.1µF capacitor at REF,
fSCLK = 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/89, TA = +25°C, unless otherwise noted.)
SHUTDOWN CURRENT
vs. TEMPERATURE
280
230
0.80
0.60
OFFSET ERROR (LSB)
SHUTDOWN CURRENT (nA)
250
330
1.00
MAX1086-9 toc10
300
MAX1086-9 toc09
380
OFFSET ERROR
vs. TEMPERATURE
200
150
100
MAX1086-9 toc11
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT (µA)
0.40
0.20
0.00
-0.20
-0.40
0.60
50
-0.80
0
180
-40
-20
0
20
40
60
-1.00
-40
80
-20
0
20
40
60
80
-40
0
20
GAIN ERROR
vs. TEMPERATURE
0.8
0.6
0.8
0.6
GAIN ERROR (LSB)
0.4
0.2
0
-0.2
MAX1086-9 toc13
1.0
MAX1086-9 toc12
1.0
0.4
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
2.7
3.2
3.7
4.2
4.7
-40
5.2
-20
0
20
40
60
80
TEMPERATURE (°C)
VDD (V)
GAIN ERROR
vs. SUPPLY VOLTAGE
FFT PLOT (SINAD)
0.8
0.6
MAX1086-9 toc15
20.00
MAX1086-9 toc14
1.0
0.00
-20.00
AMPLITUDE (dB)
0.4
0.2
0
-0.2
-40.00
-60.00
-80.00
-0.4
-100.00
-0.6
-120.00
-0.8
-1.0
-140.00
2.7
3.2
3.7
4.2
VDD (V)
6
40
TEMPERATURE (°C)
OFFSET ERROR
vs. SUPPLY VOLTAGE
OFFSET ERROR (LSB)
-20
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR (LSB)
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
4.7
5.2
0
15
30
45
60
FREQUENCY (kHz)
_______________________________________________________________________________________
60
80
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
NAME
PIN
MAX1086
MAX1087
MAX1088
MAX1089
FUNCTION
1
VDD
VDD
2
AIN1
AIN+
Analog Input Channel 1 (MAX1086/MAX1087) or Positive Analog Input (MAX1088/MAX1089)
3
AIN2
AIN-
Analog Input Channel 2 (MAX1086/MAX1087) or Negative Analog Input (MAX1088/MAX1089)
4
GND
GND
Ground
5
REF
REF
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF
capacitor to GND.
6
CNVST
CNVST
Conversion Start. A rising edge powers-up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1086/MAX1087) or input polarity (MAX1088/MAX1089).
7
DOUT
DOUT
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes highimpedance once data has been fully clocked out.
8
SCLK
SCLK
Serial Clock Input. Clocks out data at DOUT MSB first.
—
EP*
—
Positive Supply Voltage. +2.7V to +3.6V (MAX1087/MAX1089); +4.75V to +5.25V
(MAX1086/MAX1088). Bypass with a 0.1µF capacitor to GND.
Exposed Pad. Connect the exposed pad to ground or leave unconnected.
*MAX1087 TDFN package only.
Detailed Description
The MAX1086–MAX1089 analog-to-digital converters
(ADCs) use a successive-approximation conversion (SAR)
technique and an on-chip track-and-hold (T/H) structure to
convert an analog signal into a 10-bit digital result.
The serial interface provides easy interfacing to microprocessors (µPs). Figure 3 shows the simplified internal
structure for the MAX1086/MAX1087 (2–channels, single-ended) and the MAX1088/MAX1089 (1–channel,
true-differential).
True-Differential Analog Input Track/Hold
MAX1086–MAX1089
CNVST
SCLK
OSCILLATOR
INPUT SHIFT
REGISTER
CONTROL
AIN1
(AIN+)
AIN2
(AIN-)
T/H
10-BIT
SAR
ADC
REF
( ) ARE FOR MAX1088/MAX1089
Figure 3. Simplified Functional Diagram
DOUT
The equivalent circuit of Figure 4 shows the
MAX1086–MAX1089’s input architecture which is composed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1086/
MAX1087) or AIN+ (MAX1088/MAX1089). The negative
input capacitor is connected to GND (MAX1086/
MAX1087) or AIN- (MAX1088/MAX1089). The T/H enters
its hold mode on the falling edge of CNVST and the difference between the sampled positive and negative
input voltages is converted. The time required for the T/H
to acquire an input signal is determined by how quickly
its input capacitance is charged. If the input signal’s
source impedance is high, the acquisition time lengthens, and CNVST must be held high for a longer period of
time. The acquisition time, tACQ, is the maximum time
needed for the signal to be acquired, plus the power-up
time. It is calculated by the following equation:
tACQ = 7 x (RS + RIN) x 24pF + tPWR
_______________________________________________________________________________________
7
MAX1086–MAX1089
Pin Description
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
REF
GND
AIN2
AIN1(AIN+)
DOUT after 3.7µs. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, AIN2 will be selected for the next
conversion.
DAC
CIN+
COMPARATOR
+
HOLD
CINRIN-
GND(AIN-)
RIN+
HOLD
*( ) APPLIES TO MAX1088/1089
VDD/2
HOLD
TRACK
Figure 4. Equivalent Input Circuit
where RIN = 1.5kΩ, RS is the source impedance of the
input signal, and tPWR = 1µs is the power-up time of the
device.
Note: tACQ is never less than 1.4µs and any source
impedance below 300Ω does not significantly affect the
ADC‘s AC performance. A high impedance source can
be accommodated either by lengthening tACQ or by
placing a 1µF capacitor between the positive and negative analog inputs.
Selecting AIN1 or AIN2
(MAX1086/MAX1087)
Select between the MAX1086/MAX1087’s two positive
input channels using the CNVST pin. If AIN1 is desired
(Figure 5a), drive CNVST high to power-up the ADC
and place the T/H in track mode with AIN1 connected
to the positive input capacitor. Hold CNVST high for
tACQ to fully acquire the signal. Drive CNVST low to
place the T/H in hold mode. The ADC will then perform
a conversion and shutdown automatically. The MSB is
available at DOUT after 3.7µs. Data can then be
clocked out using SCLK. Be sure to clock out all 12 bits
of data (the 10-bit result plus two sub-bits) before driving CNVST high for the next conversion. If all 12 bits of
data are not clocked out before CNVST is driven high,
AIN2 will be selected for the next conversion.
If AIN2 is desired (Figure 5b), drive CNVST high for at
least 30ns. Next, drive it low for at least 30ns, and then
high again. This will power-up the ADC and place the
T/H in track mode with AIN2 connected to the positive
input capacitor. Now hold CNVST high for tACQ to fully
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
8
Selecting Unipolar or Bipolar Conversions
(MAX1088/MAX1089)
Initiate true-differential conversions with the
MAX1088/MAX1089’s unipolar and bipolar modes,
using the CNVST pin. AIN+ and AIN- are sampled at
the falling edge of CNVST. In unipolar mode, AIN+ can
exceed AIN- by up to V REF . The output format is
straight binary. In bipolar mode, either input can
exceed the other by up to VREF/2. The output format is
two’s complement.
Note: In both modes, AIN+ and AIN- must not exceed
VDD by more than 50mV or be lower than GND by more
than 50mV.
If unipolar mode is desired (Figure 5a), drive CNVST
high to power-up the ADC and place the T/H in track
mode with AIN+ and AIN- connected to the input
capacitors. Hold CNVST high for tACQ to fully acquire
the signal. Drive CNVST low to place the T/H in hold
mode. The ADC will then perform a conversion and
shutdown automatically. The MSB is available at DOUT
after 3.7µs. Data can then be clocked out using SCLK.
Be sure to clock out all 12 bits (the 10-bit result plus
two sub-bits) of data before driving CNVST high for the
next conversion. If all 12 bits of data are not clocked
out before CNVST is driven high, bipolar mode will be
selected for the next conversion.
If bipolar mode is desired (Figure 5b), drive CNVST
high for at least 30ns. Next, drive it low for at least 30ns
and then high again. This will place the T/H in track
mode with AIN+ and AIN- connected to the input
capacitors. Now hold CNVST high for t ACQ to fully
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
DOUT after 3.7µs. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, bipolar mode will be selected for
the next conversion.
Input Bandwidth
The ADCs input tracking circuitry has a 1MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
_______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
MAX1086–MAX1089
tCONV
tACQ
CNVST
1
SCLK
B9
MSB
DOUT
HIGH-Z
4
B8
B7
B6
8
B5
B4
B3
B2
12
B1
B0
LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 5a. Single Conversion AIN1 vs. GND (MAX1086/MAX1087), unipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
tCONV
tACQ
CNVST
SCLK
DOUT
HIGH-Z
1
B9
MSB
4
B8
B7
B6
8
B5
B4
B3
B2
12
B1
B0
LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 5b. Single Conversion AIN2 vs. GND (MAX1086/MAX1087), bipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
Analog Input Protection
Internal Clock
Internal protection diodes which clamp the analog input
to VDD and GND allow the analog input pins to swing
from GND - 0.3V to VDD + 0.3V without damage. Both
inputs must not exceed VDD by more than 50mV or be
lower than GND by more than 50mV for accurate conversions. If an off-channel analog input voltage exceeds
the supplies, limit the input current to 2mA.
The MAX1086–MAX1089 operate from an internal oscillator, which is accurate within 10% of the 4MHz specified
clock rate. This results in a worse case conversion time
of 3.7µs. The internal clock releases the system microprocessor from running the SAR conversion clock and
allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0 to
8MHz.
_______________________________________________________________________________________
9
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Output Data Format
Figures 5a and 5b illustrate the conversion timing for
the MAX1086–MAX1089. The 10-bit conversion result is
output in MSB first format, followed by two sub-bits (S1
and S0). Data on DOUT transitions on the falling edge
of SCLK. All 12-bits must be clocked out before CNVST
transitions again. For the MAX1088/MAX1089, data is
straight binary for unipolar mode and two’s complement for bipolar mode. For the MAX1086/MAX1087,
data is always straight binary.
Applications Information
Automatic Shutdown Mode
With CNVST low, the MAX1086–MAX1089 defaults to an
AutoShutdown state (<0.2µA) after power-up and
between conversions. After detecting a rising edge on
CNVST, the part powers up, sets DOUT low and enters
track mode. After detecting a falling-edge on CNVST, the
device enters hold mode and begins the conversion. A
maximum of 3.7µs later, the device completes conversion, enters shutdown and MSB is available at DOUT.
External Reference
An external reference is required for the MAX1086–
MAX1089. Use a 0.1µF bypass capacitor for best performance. The reference input structure allows a voltage range of +1V to VDD + 50mV.
Transfer Function
Figure 6 shows the unipolar transfer function for the
MAX1086–MAX1089. Figure 7 shows the bipolar transfer
function for the MAX1088/MAX1089. Code transitions
occur halfway between successive-integer LSB values.
Connection to Standard Interfaces
The MAX1086–MAX1089 feature a serial interface that is
fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the serial clock for the ADCs. Select a clock frequency up to
8MHz.
How to Perform a Conversion
1)
2)
3)
4)
5)
Use a general purpose I/O line on the CPU to hold
CNVST low between conversions.
Drive CNVST high to acquire AIN1(MAX1086/
MAX1087) or unipolar mode (MAX1088/MAX1089).
To acquire AIN2(MAX1086/MAX1087) or bipolar
mode (MAX1088/MAX1089), drive CNVST low and
high again.
Hold CNVST high for 1.4µs.
Drive CNVST low and wait approximately 3.7µs for
conversion to complete. After 3.7µs, the MSB is
available at DOUT.
Activate SCLK for a minimum of 12 rising clock
edges. DOUT transitions on SCLK’s falling edge
OUTPUT CODE
MAX1088/MAX1089
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
MAX1086–
MAX1089
011 . . . 111
FS = VREF
2
011 . . . 110
ZS = 0
11 . . . 110
11 . . . 101
000 . . . 010
000 . . . 001
000 . . . 000
FS = VREF
ZS = GND
V
1LSB = REF
1024
00 . . . 011
-VREF
2
V
1LSB = REF
1024
-FS =
111 . . . 111
111 . . . 110
111 . . . 101
00 . . . 010
100 . . . 001
00 . . . 001
100 . . . 000
00 . . . 000
0
1
2
3
INPUT VOLTAGE (LSB)
FS
FS - 3/2LSB
0
- FS
INPUT VOLTAGE (LSB)
*VCOM ≤ VREF / 2 *VIN = (AIN+) - (AIN-)
Figure 6. Unipolar Transfer Function
10
Figure 7. Bipolar Transfer Function
______________________________________________________________________________________
+FS - 1LSB
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
SCLK’s rising edge. The first 10 bits are the data and
the next two bits are sub-bits (S1, S0). DOUT then
goes high impedance (Figure 9b).
SPI and MICROWIRE Interface
PIC16 and SSP Module and
PIC17 Interface
When using SPI interface (Figure 8a) or MICROWIRE
(Figure 8a and 8b), set CPOL = CPHA = 0. Two 8-bit
readings are necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µP on
SCLK’s rising edge. The first 8-bit data stream contains
the first 8-bits of DOUT starting with the MSB. The second 8-bit data stream contains the remaining two result
bits (B1, B0) and two trailing sub-bits (S1, S0). DOUT
then goes high impedance.
QSPI Interface
Using the high-speed QSPI interface (Figure 9a) with
CPOL = 0 and CPHA = 0, the MAX1086–MAX1089
support a maximum fSCLK of 8MHz. One 8- to16-bit
reading is necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µP on
The MAX1086–MAX1089 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchronous serial port (SSP) module
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master. This is done by initializing its synchronous serial port control register (SSPCON) and
synchronous serial port status register (SSPSTAT) to
the bit patterns shown in Tables 1 and 2.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit readings (Figure
10b) are necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µC on
SCLK’s rising edge. The first 8-bit data stream contains
I/O
CNVST
I/O
CNVST
SCK
SCLK
SK
SCLK
MISO
DOUT
SI
DOUT
VDD
MICROWIRE
SPI
MAX1086–
MAX1089
SS
MAX1086–
MAX1089
Figure 8a. SPI Connections
Figure 8b. MICROWIRE Connections
Table 1. Detailed SSPCON Register Content
CONTROL BIT
MAX1086–MAX1089
SETTINGS
SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)
WCOL
Bit 7
X
Write Collision Detection Bit
SSPOV
Bit 6
X
Receive Overflow Detect Bit
SSPEN
Bit 5
1
Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
CKP
Bit 4
0
SSPM3
Bit 3
0
SSPM2
Bit 2
0
SSPM1
Bit 1
0
SSPM0
Bit 0
1
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
X = Don’t care
______________________________________________________________________________________
11
MAX1086–MAX1089
and is available in MSB-first format. Observe the
SCLK to DOUT valid timing characteristic. Clock
data into the µP on SCLK’s rising-edge.
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
CNVST
1ST BYTE READ
1
2ND BYTE READ
4
12
8
16
SCLK
B9
MSB
DOUT
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
the first eight data bits starting with the MSB. The second 8-bit data stream contains the remaining bits, D1
through D0, and the two sub-bits S1 and S0.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
CS
CNVST
SCK
SCLK
MISO
QSPI
High-frequency noise in the power supply (VDD) may
degrade the performance of the ADC’s fast comparator.
Bypass VDD to the star ground with a 0.1µF capacitor,
located as close as possible to the MAX1086–MAX1089s
power supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
DOUT
VDD
MAX1086–
MAX1089
SS
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise operation, ensure the ground return to the star ground’s
power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog
and reference inputs.
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
CONTROL BIT
MAX1086–MAX1089
SETTINGS
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
Bit 6
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Bit 5
X
Data Address Bit
P
Bit 4
X
Stop Bit
S
Bit 3
X
Start Bit
R/W
Bit 2
X
Read/Write Bit Information
UA
Bit 1
X
Update Address
BF
Bit 0
X
Buffer Full Status Bit
SMP
Bit 7
CKE
D/A
X = Don’t care
12
______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
1
4
16
12
8
SCLK
B9
MSB
DOUT
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
HIGH-Z
S0
SAMPLING INSTANT
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
Definitions
VDD
VDD
SCLK
SCK
DOUT
SDI
CNVST
I/O
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The static linearity parameters for the MAX1086–MAX1089 are
measured using the endpoint method.
PIC16/PIC17
MAX1086–
MAX1089
Differential Nonlinearity
GND
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller
CNVST
1ST BYTE READ
1
2ND BYTE READ
4
12
8
16
SCLK
DOUT
B9
MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
______________________________________________________________________________________
13
MAX1086–MAX1089
CNVST
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 ✕ log (SignalRMS / NoiseRMS)
SUPPLIES
+3V OR +5V
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
R* = 5Ω
0.1µF
VDD
Effective Number of Bits
VLOGIC = +5V/+3V GND
GND
+5V/+3V DGND
Total Harmonic Distortion
MAX1086–
MAX1089
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 11. Power-Supply and Grounding Connections
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples. Aperture delay (tAD) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-todigital noise is caused by quantization error only and
results directly from the ADC’s resolution (N-bits):
SNR = (6.02 ✕ N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
14
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
⎛
⎞
THD = 20 ⋅log ⎜ ⎛⎝ V22 + V32 + V4 2 + V52 ⎞⎠ / V1⎟
⎝
⎠
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion
component.
Chip Information
TRANSISTOR COUNT: 6922
PROCESS: BiCMOS
______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
SOT23, 8L.EPS
MARKING
0
0
PACKAGE OUTLINE, SOT-23, 8L BODY
21-0078
G
1
______________________________________________________________________________________
1
15
MAX1086–MAX1089
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
16
______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
COMMON DIMENSIONS
PACKAGE VARIATIONS
SYMBOL
MIN.
MAX.
PKG. CODE
N
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
A
0.70
0.80
T633-2
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
D
2.90
3.10
T833-2
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
E
2.90
3.10
T833-3
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
A1
0.00
0.05
T1033-1
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
L
0.20
0.40
T1033-2
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
k
0.25 MIN.
T1433-1
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
A2
0.20 REF.
T1433-2
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
Revison History
Pages changed at Rev 1: 1, 2, 7, 15, 16, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX1086–MAX1089
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)