Cypress CY14B101KA-ZS25XC 1 mbit (128k x 8/64k x 16) nvsram with real time clock Datasheet

PRELIMINARY
CY14B101KA/CY14B101MA
1 Mbit (128K x 8/64K x 16) nvSRAM with
Real Time Clock
Features
■
■
1 Mbit nvSRAM
❐ 20 ns, 25 ns, and 45 ns access times
❐ Internally organized as 128K x 8 (CY14B101KA) or 64K x 16
(CY14B101MA)
❐ Hands off automatic STORE on power down with only a small
capacitor
❐ STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power down
❐ RECALL to SRAM initiated on power up or by software
■ High Reliability
❐ Infinite Read, Write, and RECALL cycles
❐ 200,000 STORE cycles to QuantumTrap
❐ 20 year data retention
■ Real Time Clock
❐ Full featured Real Time Clock
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Capacitor or battery backup for RTC
❐ Backup current of 300 nA
Logic Block Diagram[1, 2, 3]
Industry Standard Configurations
❐ Single 3V +20%, –10% operation
❐ Commercial and Industrial temperatures
❐ 44-pin and 54-pin TSOP II and 48-pin SSOP packages
❐ Pb-free and RoHS compliance
Functional Description
The Cypress CY14B101KA/CY14B101MA combines a 1 Mbit
nonvolatile static RAM with a full featured real time clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written an infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
VCC
Quatrum
Trap
1024 X 1024
R
O
W
A5
A6
A7
A8
A9
A12
A13
A14
A15
A 16
D
E
C
O
D
E
R
VCA
P
POWER
CONTROL
STORE
VRTCbat
VRTCcap
RECALL
STORE/RECALL
CONTROL
STATIC RAM
ARRAY
1024 X 1024
SOFTWARE
DETECT
HSB
A14 - A2
DQ0
DQ1
DQ2
DQ3
RTC
I
N
P
U
T
B
U
F
F
E
R
S
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
Xout
Xin
INT
COLUMN I/O
MUX
A 16- A0
OE
COLUMN DEC
WE
DQ12
DQ13
CE
DQ14
BLE
A0 A1 A 2 A3 A 4 A10 A 11
DQ15
BHE
Notes
1. Address A0 - A16 for x8 configuration and Address A0 - A15 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-42880 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 09, 2009
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CY14B101KA/CY14B101MA
PRELIMINARY
Pinouts
Figure 1. Pin Diagram - 44-Pin, 54-Pin TSOP II, and 48-Pin SSOP
INT
[7
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x8)
Top View
(not to scale)
VCAP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
[6]
NC
[5]
NC[4]
NC
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
DQ0
A3
A2
A12
A11
A10
A1
A0
DQ1
DQ2
Xout
Xin
VRTCcap
VRTCbat
A16
A14
A12
A7
A6
A5
INT
A4
NC
NC
NC
VSS
NC
VRTCbat
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 - SSOP
(x8)
Top View
(not to scale)
48
47
VCC
46
45
44
43
42
41
40
HSB
WE
A13
A8
A9
39
38
37
36
NC
NC
NC
VSS
NC
35
34
33
32
31
30
29
28
27
26
25
A15
NC
A11
VRTCcap
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
INT
[7]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
54 - TSOP II
(x16)
Top View
(not to scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
[6]
NC
[5]
NC
[4]
NC
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ 11
DQ 10
DQ 9
DQ 8
VCAP
A14
A13
A12
A11
A10
NC
VRTCcap
VRTCbat
Pin Definitions
Pin Name
A0 – A16
A0 – A15
I/O Type
Input
DQ0 – DQ7
DQ0 – DQ15
NC
Input/Output
Description
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on
operation.
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
No Connect No Connects. This pin is not connected to the die.
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is
written to the specific address location.
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Xout
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
WE
CE
OE
Xin
Output
Input
Crystal Connection. Drives crystal on start up.
Crystal Connection. For 32.768 kHz crystal.
VRTCcap
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used.
VRTCbat
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.
Notes
4. Address expansion for 2 Mbit. NC pin not connected to die.
5. Address expansion for 4 Mbit. NC pin not connected to die.
6. Address expansion for 8 Mbit. NC pin not connected to die.
7. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-42880 Rev. *C
Page 2 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O Type
INT
Output
Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
HSB
VCAP
Description
Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation,
HSB is driven HIGH for short time with standard output high current.
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
AutoStore Operation
The CY14B101KA/CY14B101MA nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B101KA/CY14B101MA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. Refer the Truth Table For SRAM Operations on page
23 for a complete description of read and write modes.
The CY14B101KA/CY14B101MA stores data to the nvSRAM
using one of three storage operations. These three operations
are: Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device power
down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B101KA/CY14B101MA.
The CY14B101KA/CY14B101MA performs a read cycle
whenever CE and OE are LOW, and WE and HSB are HIGH.
The address specified on pins A0-16 or A0-15 determines which
of the 131,072 data bytes or 65,536 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of tAA (read cycle #1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle #2). The data output repeatedly responds to address
changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins IO0-7 are
written into the memory if it is valid tSD before the end of a
WE-controlled write, or before the end of an CE-controlled write.
The Byte Enable inputs (BHE, BLE) determine which bytes are
written, in the case of 16-bit words. It is recommended that OE
be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
Document #: 001-42880 Rev. *C
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 5. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
may corrupt the data stored in nvSRAM.
Figure 2. AutoStore Mode
Vcc
0.1uF
10kOhm
SRAM Read
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Vcc
WE
VCAP
VSS
VCAP
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 15 for the size of the VCAP. The voltage
on the VCAP pin is driven to VCC by a regulator on the chip. Place
Page 3 of 29
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PRELIMINARY
a pull up on WE to hold it inactive during power up. This pull up
is only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power up. This must be Verified
when using the pull up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101KA/CY14B101MA provides the HSB pin to
control and acknowledge the STORE operations. The HSB pin
is used to request a Hardware STORE cycle. When the HSB pin
is driven LOW, the CY14B101KA/CY14B101MA conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
begins only if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B101KA/CY14B101MA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B101KA/CY14B101MA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14B101KA/CY14B101MA remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power Up)
CY14B101KA/CY14B101MA
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on powerup, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14B101KA/CY14B101MA
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Document #: 001-42880 Rev. *C
Page 4 of 29
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PRELIMINARY
CY14B101KA/CY14B101MA
Table 1. Mode Selection
OE, BHE, BLE[3]
X
A15 - A0[8]
X
Mode
I/O
Power
Not Selected
Output High Z
Standby
H
L
X
Read SRAM
Output Data
Active
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[9]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[9]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[9]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[9]
CE
H
WE
X
L
L
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
To initiate the AutoStore enable sequence, the following
sequence of CE or OE controlled read operations must be
performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation.
Notes
8. While there are 17 address lines on the CY14B101KA (16 address lines on the CY14B101MA), only the 13 address lines (A14 - A2) are used to control software
modes. The remaining address lines are don’t care.
9. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-42880 Rev. *C
Page 5 of 29
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PRELIMINARY
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered from
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
Document #: 001-42880 Rev. *C
CY14B101KA/CY14B101MA
or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection
with Cypress to understand any impact on the VCAP voltage level
at the end of a tRECALL period.
Page 6 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
Data Protection
The CY14B101KA/CY14B101MA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC is less than VSWITCH. If the
CY14B101KA/CY14B101MA is in a write mode (both CE and
WE are LOW) at power up, after a RECALL or STORE, the write
is inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power up
or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Real Time Clock Operation
nvTIME Operation
The CY14B101KA/CY14B101MA offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
Internal double buffering of the clock and timer information
registers prevents accessing transitional internal clock data
during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or the clock
accuracy of the internal clock when accessing clock data. Clock
and alarm registers store data in BCD format.
RTC functionality is described with respect to CY14B101KA in
the following sections. The same description applies to
CY14B101MA, except for the RTC register addresses. The RTC
register addresses for CY14B101KA range from 0x1FFF0 to
0x1FFFF, while those for CY14B101MA range from 0x0FFF0 to
0x0FFFF. Refer to Table 3 on page 11 and Table 4 on page 12
for a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The time can be set to any calendar time and
the clock automatically keeps track of days of the week and
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. Stop internal updates to
the CY14B101KA time keeping registers before reading clock
data, to prevent reading of data in transition. Stopping the
register updates does not affect clock accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x1FFF0), and does not restart until a
‘0’ is written to the read bit. The RTC registers are then read while
the internal clock continues to run. After a ‘0’ is written to the read
bit (‘R’), all RTC registers are simultaneously updated within
20 ms.
Document #: 001-42880 Rev. *C
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x1FFF0) to a ‘1’
stops updates to the time keeping registers and enables the time
to be set. The correct day, date, and time is then written into the
registers and must be in 24-hour BCD format. The time written
is referred to as the “Base Time”. This value is stored in nonvolatile registers and used in the calculation of the current time.
Resetting the write bit to ‘0’ transfers the values of timekeeping
registers to the actual clock counters, after which the clock
resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Note The values entered in the timekeeping, alarm, calibration,
and interrupt registers need a STORE operation to be saved in
nonvolatile memory. Therefore, while working in AutoStore
disabled mode, the user must perform a STORE operation after
writing into the RTC registers for the RTC to work correctly.
Backup Power
The RTC in the CY14B101KA is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14B101KA consumes a
maximum of 300 nanoamps at room temperature. The user must
choose capacitor or battery values according to the application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal backup times are
approximately two times longer.
Table 2. RTC Backup Time
Capacitor Value
Backup Time
0.1F
72 hours
0.47F
14 days
1.0F
30 days
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3V lithium is recommended and the CY14B101KA
sources current only from the battery when the primary power is
removed. However, the battery is not recharged at any time by
the CY14B101KA. The battery capacity must be chosen for total
anticipated cumulative down time required over the life of the
system.
Page 7 of 29
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PRELIMINARY
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFF8 controls
the enable and disable of the oscillator. This bit is nonvolatile and
is shipped to customers in the “enabled” (set to 0) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, If the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail.The CY14B101KA has the ability to detect
oscillator failure when system power is restored. This is recorded
in the OSCF (Oscillator Failed bit) of the flags register at the
address 0x1FFF0. When the device is powered on (VCC goes
above VSWITCH) the OSCEN bit is checked for “enabled” status.
If the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to “1”. The system must check
for this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
to the “Base Time” (see Setting the Clock on page 7), which is
the value last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
Reset the value of OSCF to ‘0’ when the time registers are written
for the first time. This initializes the state of this bit which may
have become set when the system was first powered on.
To reset OSCF, set the write bit “W” (in the Flags register at
0x1FFF0) to a “1” to enable writes to the Flag register. Write a
“0” to the OSCF bit and reset the write bit to “0” to disable writes.
Calibrating the Clock
The RTC is driven by a quartz controlled crystal with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystals available in market
typically have an error of +20 ppm to +35 ppm. However,
CY14B101KA employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5
seconds to -5 seconds per month.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in Calibration register at 0x1FFF8. The
calibration bits occupy the five lower order bits in the Calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
Document #: 001-42880 Rev. *C
CY14B101KA/CY14B101MA
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags
register (0x1FFF0) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x1FFF0) to “1” to enable writes to the Flag register. Write a
value to CAL, and then reset the write bit to “0” to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x1FFF1-5) with the corresponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x1FFF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags
register clears the alarm flag bit (and all others). A hardware
interrupt pin may also be used to detect an alarm event.
To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register
- 0x1FFF0) to ‘1’ to enable writes to Alarm Registers. After writing
the alarm value, clear the ‘W’ bit back to “0” for the changes to
take effect.
Note CY14B101KA requires the alarm match bit for seconds
(0x1FFF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag
and Interrupt.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It
begins counting down from the value loaded in the Watchdog
Timer register.
The timer consists of a loadable register and a free running
counter. On power up, the watchdog time out value in register
0x1FFF7 is loaded into the Counter Load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
Page 8 of 29
[+] Feedback
PRELIMINARY
value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDT flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 3. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the Watchdog Interrupt
Enable (WIE) bit in the Interrupt register is set, a hardware
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the Flags registers.
.
Figure 3. Watchdog Timer Block Diagram
Clock
Divider
Oscillator
32,768 KHz
Zero
Compare
Interrupts
The CY14B101KA has Flags register, Interrupt register and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0x1FFF6). In addition, each has an associated flag bit
in the Flags register (0x1FFF0) that the host processor uses to
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An Interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in Interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
Interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the Flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
1 Hz
32 Hz
Counter
CY14B101KA/CY14B101MA
WDF
Note CY14B101KA generates valid interrupts only after the
Powerup Recall sequence is completed. All events on INT pin
must be ignored for tHRECALL duration after powerup.
Interrupt Register
Load
Register
WDS
D
Q
WDW
Q
write to
Watchdog
Register
Watchdog
Register
Power Monitor
The CY14B101KA provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
As described in the AutoStore Operation on page 3, when
VSWITCH is reached as VCC decays from power loss, a data
STORE operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, read and write operations to nvSRAM are inhibited and the clock functions are not
available to the user. The clock continues to operate in the
background. The updated clock data is available to the user
tHRECALL delay after VCC is restored to the device (see
AutoStore/Power Up RECALL on page 20).
Document #: 001-42880 Rev. *C
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in Flags register.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF Flag in Flags register.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in Flags
register.
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10k resistor while using the
interrupt in active LOW mode.
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags or Control register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the Flags registers to determine the cause.
All flags are cleared when the register is read. If the INT pin is
programmed for Level mode, then the condition clears and the
INT pin returns to its inactive state. If the pin is programmed for
Pulse mode, then reading the flag also clears the flag and the
pin. The pulse does not complete its specified duration if the
Flags register is read. If the INT pin is used as a host reset, then
the Flags register is not read during a reset.
Page 9 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
Flags Register
The Flag register has three flag bits: WDF, AF, and PF, which can
be used to generate an interrupt. These flags are set by the
watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts to be informed when a flag is set. These flags are automat-
ically reset when the register is read. The flags register is
automatically loaded with the value 0x00 on power up (except for
the OSCF bit; see Stopping and Starting the Oscillator on page
8).
Figure 4. RTC Recommended Component Configuration
Recommended Values
Y1 = 32.768 KHz (12.5 pF)
C1 = 10 pF
C2 = 67 pF
Note: The recommended values for C1 and C2 include
board trace capacitance.
C1
Y1
C2
Xout
Xin
Figure 5. Interrupt Block Diagram
WDF
Watchdog
Timer
WIE
PF
Power
Monitor
PFE
P/L
VCC
Pin
Driver
INT
VINT
H/L
VSS
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
AF
Clock
Alarm
AIE
Document #: 001-42880 Rev. *C
Page 10 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
Table 3. RTC Register Map[10, 11, 12]
BCD Format Data[11]
Register
D7
D6
D5
D4
D3
D2
D1
CY14B101MA
0x1FFFF
0x0FFFF
0x1FFFE
0x0FFFE
0
0
0
0x1FFFD
0x0FFFD
0
0
10s Day of
Month
0x1FFFC
0x0FFFC
0
0
0
0x1FFFB
0x0FFFB
0
0
10s Hours
0x1FFFA
0x0FFFA
0
10s Minutes
Minutes
Minutes: 00–59
0x1FFF9
0x0FFF9
0
10s Seconds
Seconds
Seconds: 00–59
0x1FFF8
0x0FFF8
OSCEN
(0)
0x1FFF7
0x0FFF7
WDS (0) WDW
(0)
0x1FFF6
0x0FFF6
WIE (0)
AIE
(0)
0x1FFF5
0x0FFF5
M (1)
0
10s Alarm Date
Alarm Day
Alarm, Day of Month:
01–31
0x1FFF4
0x0FFF4
M (1)
0
10s Alarm
Hours
Alarm Hours
Alarm, Hours: 00–23
0x1FFF3
0x0FFF3
M (1)
10 Alarm Minutes
Alarm Minutes
Alarm, Minutes: 00–59
0x1FFF2
0x0FFF2
M (1)
10 Alarm Seconds
Alarm, Seconds
Alarm, Seconds: 00–59
0x1FFF1
0x0FFF1
Centuries
Centuries: 00–99
0x1FFF0
0x0FFF0
10s Years
0
10s
Months
0
Cal
Sign
(0)
AF
Years
Years: 00–99
Months
Months: 01–12
Day Of Month
Day of Month: 01–31
0
Day of Week
Day of Week: 01–07
Hours
Hours: 00–23
Calibration Values [13]
Calibration (00000)
Watchdog [13]
WDT (000000)
PFE
(0)
0
H/L (1)
10s Centuries
WDF
D0
Function/Range
CY14B101KA
PF
OSCF
0
P/L
(0)
CAL
(0)
0
W (0)
0
R (0)
Interrupts [13]
Flags [13]
Notes
10. Upper byte D15-D8 (CY14B101MA) of RTC registers are reserved for future use.
11. The unused bits of RTC registers are reserved for future use and should be set to ‘0’.
12. ( ) designates values shipped from the factory.
13. This is a binary value, not a BCD value.
Document #: 001-42880 Rev. *C
Page 11 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
Table 4. Register Map Detail
Register
CY14B101KA
CY14B101MA
0x1FFFF
0x0FFFF
Description
Time Keeping - Years
D7
D6
D5
D4
D3
D2
10s Years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years;
upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The
range for the register is 0–99.
0x1FFFE
0x0FFFE
Time Keeping - Months
D7
D6
D5
D4
0
0
0
10s Month
D3
D2
D1
D0
Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range
for the register is 1–12.
0x1FFFD
0x0FFFD
Time Keeping - Date
D7
D6
0
0
D5
D4
D3
10s Day of Month
D2
D1
D0
Day of Month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit
and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3.
The range for the register is 1–31. Leap years are automatically adjusted for.
0x1FFFC
0x0FFFC
Time Keeping - Day
D7
D6
D5
D4
D3
0
0
0
0
0
D2
D1
D0
Day of Week
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is
a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day
value, because the day is not integrated with the date.
0x1FFFB
0x0FFFB
Time Keeping - Hours
D7
D6
0
0
D5
D4
D3
D2
10s Hours
D1
D0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower
digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from
0 to 2. The range for the register is 0–23.
0x1FFFA
0x0FFFA
Time Keeping - Minutes
D7
D6
0
D5
D4
D3
D2
10s Minutes
D1
D0
Minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5.
The range for the register is 0–59.
0x1FFF9
0x0FFF9
Time Keeping - Seconds
D7
0
D6
D5
10s Seconds
D4
D3
D2
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range
for the register is 0–59.
Document #: 001-42880 Rev. *C
Page 12 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
Table 4. Register Map Detail (continued)
Register
CY14B101KA
CY14B101MA
0x1FFF8
0x0FFF8
Description
Calibration/Control
D7
D6
D5
OSCEN
0
Calibration
Sign
D4
D3
D2
D1
D0
Calibration
OSCEN
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs.
Disabling the oscillator saves battery or capacitor power during storage.
Calibration
Sign
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0)
from the time-base.
Calibration
These five bits control the calibration of the clock.
0x1FFF7
0x0FFF7
WatchDog Timer
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to
0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is
write only. Reading it always returns a 0.
WDW
Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value
(D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value.
Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write
cycle is complete. This function is explained in more detail in Watchdog Timer on page 8.
WDT
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is
31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0
disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.
0x1FFF6
0x0FFF6
Interrupt Status/Control
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
0
H/L
P/L
0
0
WIE
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer
drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF
flag.
AIE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When
set to 0, the alarm match only affects the AF flag.
PFE
Power Fail Enable. When set to 1, the power fail monitor drives the INT pin and the PF flag. When
set to 0, the power fail monitor affects only the PF flag.
0
Reserved for future use
H/L
High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open
drain, active LOW.
P/L
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L)
until the flags register is read.
0x1FFF5
0x0FFF5
Alarm - Day
D7
D6
M
0
D5
D4
10s Alarm Date
D3
D2
D1
D0
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date
value.
M
Document #: 001-42880 Rev. *C
Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
Page 13 of 29
[+] Feedback
CY14B101KA/CY14B101MA
PRELIMINARY
Table 4. Register Map Detail (continued)
Register
CY14B101KA
CY14B101MA
0x1FFF4
0x0FFF4
Description
Alarm - Hours
D7
D6
M
0
D5
D4
D3
10s Alarm Hours
D2
D1
D0
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
0x1FFF3
Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the hours value.
0x0FFF3
Alarm - Minutes
D7
D6
M
0
D5
D4
D3
10s Alarm Minutes
D2
D1
D0
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
0x1FFF2
Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to
1 causes the match circuit to ignore the minutes value.
0x0FFF2
Alarm - Seconds
D7
D6
M
0
D5
D4
D3
10s Alarm Seconds
D2
D1
D0
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
0x1FFF1
Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to
1 causes the match circuit to ignore the seconds value.
0x0FFF1
Time Keeping - Centuries
D7
D6
0
0
D5
D4
D3
D2
10s Centuries
D1
D0
Centuries
Contains the BCD value of centuries. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 9. The range
for the register is 0-99 centuries.
0x1FFF0
0x0FFF0
Flags
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
WDF
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach
0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power up
AF
Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the
alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power up.
PF
Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold
VSWITCH. It is cleared to 0 when the Flags register is read or on power up.
OSCF
Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5
ms of operation. This indicates that RTC backup power failed and clock value is no longer valid.
This bit survives power cycle and is never cleared internally by the chip. The user must check for
this condition and write '0' to clear this flag.
CAL
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0,
the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
W
Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write
to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting
the W bit to 0 transfers the contents of the RTC registers to the time keeping counters if the time
is changed (a new base time is loaded). This bit defaults to 0 on power up.
R
Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates
are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding
register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.
Document #: 001-42880 Rev. *C
Page 14 of 29
[+] Feedback
PRELIMINARY
CY14B101KA/CY14B101MA
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
DC Output Current (1 output at a time, 1s duration).....15 mA
Maximum Accumulated Storage Time
At 150°C Ambient Temperature........................ 1000h
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
At 85°C Ambient Temperature..................... 20 Years
Latch Up Current .............................................. ..... > 200 mA
Ambient Temperature with Power Applied.. –55°C to +150°C
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Operating Range
Voltage Applied to Outputs
in High-Z State....................................... –0.5V to VCC + 0.5V
Commercial
Input Voltage.............................................–0.5V to Vcc+0.5V
Industrial
Range
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
–40°C to +85°C
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter
Description
Test Conditions
Power Supply Voltage
VCC
ICC1
Average Vcc Current tRC = 20 ns
Commercial
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads (IOUT = 0 mA) Industrial
ICC2
ICC3[14]
ICC4
ISB
IIX[15]
Average VCC Current
during STORE
Average VCC Current
at tRC= 200 ns,
VCC (Typ), 25°C
Average VCAP
Current during
AutoStore Cycle
VCC Standby Current
All Inputs Don’t Care, VCC = Max.
Average current for duration tSTORE
All I/P cycling at CMOS levels.
Values obtained without output loads (IOUT = 0 mA).
Max
3.6
65
65
50
70
70
52
10
35
Unit
V
mA
mA
mA
mA
mA
mA
mA
5
mA
CE > (VCC – 0.2V). VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
VCC = Max, VSS < VIN < VCC
5
mA
–1
+1
µA
–100
+1
µA
–1
+1
µA
2.0
VCC +
0.5
0.8
V
V
0.4
180
V
V
µF
VIH
VIL
Input LOW Voltage
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Storage Capacitor
VCAP
Typ[14]
3.0
All Inputs Don’t Care, VCC = Max.
Average current for duration tSTORE
Input Leakage
Current (except HSB)
Input Leakage
VCC = Max, VSS < VIN < VCC
Current (for HSB)
Off State Output
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH
Leakage Current
or WE < VIL
Input HIGH Voltage
IOZ
Min
2.7
IOUT = –2 mA
IOUT = 4 mA
Between VCAP pin and VSS, 5V Rated
VSS –
0.5
2.4
61
68
Notes
14. Typical values are at 25°C, VCC= VCC (Typ). Not 100% tested.
15. The HSB pin has IOUT = -2 uA for VOH of 2.4V when both active HIGH and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document #: 001-42880 Rev. *C
Page 15 of 29
[+] Feedback
CY14B101KA/CY14B101MA
PRELIMINARY
Capacitance
Parameter[16]
Description
Test Conditions
CIN
Input Capacitance
COUT
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = VCC (Typ)
Max
Unit
7
pF
7
pF
Thermal Resistance
Parameter[16]
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
48 SSOP
44 TSOP II
54 TSOP II
Unit
Test conditions follow standard
test methods and procedures for
measuring thermal impedance, in
accordance with EIA/JESD51.
TBD
31.11
30.73
°C/W
TBD
5.56
6.08
°C/W
Figure 6. AC Test Loads
577Ω
577Ω
3.0V
3.0V
R1
R1
OUTPUT
OUTPUT
R2
789Ω
30 pF
R2
789Ω
5 pF
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%) ........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
RTC Characteristics
Parameters
Description
VRTCbat
RTC Battery Pin Voltage
IBAK[17]
RTC Backup Current
Min
Typ[14]
1.8
3.0
TA (Min)
25°C
RTC Capacitor Pin Voltage
tOCS
RTC Oscillator Time to Start
RBKCHG
RTC Backup Capacitor Charge Current-Limiting
Resistor
Units
3.3
V
350
nA
500
nA
350
TA (Max)
VRTCcap[18]
Max
nA
TA (Min)
1.6
3.0
3.6
V
25°C
1.5
3.0
3.6
V
TA (Max)
1.4
3.0
3.6
V
1
2
sec
850
Ω
450
Notes
16. These parameters are guaranteed by design and are not tested.
17. From either VRTCcap or VRTCbat.
18. If VRTCcap > 0.3V or if no capacitor is connected to VRTCcap pin, the oscillator starts in tOCS time. If a backup capacitor is connected and vrtccap < 0.3V, the capacitor
must be allowed to charge to 0.3V for oscillator to start.
Document #: 001-42880 Rev. *C
Page 16 of 29
[+] Feedback
CY14B101KA/CY14B101MA
PRELIMINARY
AC Switching Characteristics
Parameters
Cypress
Alt
Parameters
Parameters
SRAM Read Cycle
tACS
tACE
[19]
tRC
tRC
Chip Enable Access Time
Read Cycle Time
tAA [20]
tAA
Address Access Time
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
12
20
ns
tOHA[20]
20 ns
Description
Min
25 ns
Max
Min
20
20
Max
45 ns
Min
25
25
Max
45
45
Unit
ns
ns
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE
[16, 21]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE
[16, 21]
tHZ
Chip Disable to Output Inactive
tLZOE
[16, 21]
tOLZ
Output Enable to Output Active
tHZOE [16, 21]
8
0
10
0
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
[16]
tPS
tPD
tDBE
tLZBE[16]
tHZBE[16]
SRAM Write Cycle
tWC
tWC
tPWE
tWP
tSCE
tCW
tDW
tSD
tHD
tDH
tAW
tAW
tAS
tSA
tHA
tWR
[16, 21, 22]
tWZ
tHZWE
Chip Disable to Power Standby
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
20
15
15
8
0
15
0
0
tLZWE [16, 21]
tBW
tOW
Output Active after End of Write
3
3
3
ns
-
Byte Enable to End of Write
15
20
30
ns
0
10
ns
ns
[16]
tPU
8
15
0
0
20
Byte Enable to Data Valid
Byte Enable to Output Active
Byte Disable to Output Inactive
0
25
10
0
15
12
0
8
25
20
20
10
0
20
0
0
8
ns
45
ns
20
15
ns
ns
ns
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
10
45
30
30
15
0
30
0
0
10
ns
Switching Waveforms
Figure 7. SRAM Read Cycle #1: Address Controlled [19, 20, 23]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
19. WE must be HIGH during SRAM read cycles.
20. Device is continuously selected with CE, OE and BHE/BLE LOW.
21. Measured ±200 mV from steady state output voltage.
22. If WE is low when CE goes low, the outputs remain in the high impedance state.
23. HSB must remain HIGH during Read and Write cycles.
Document #: 001-42880 Rev. *C
Page 17 of 29
[+] Feedback
PRELIMINARY
CY14B101KA/CY14B101MA
Figure 8. SRAM Read Cycle #2: CE Controlled [3, 19, 23]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 9. SRAM Write Cycle #1: WE Controlled [3, 22, 23, 24]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
tSA
tSD
Data Input
Input Data Valid
tHZWE
Data Output
tHD
Previous Data
tLZWE
High Impedance
Note
24. CE or WE must be >VIH during address transitions.
Document #: 001-42880 Rev. *C
Page 18 of 29
[+] Feedback
CY14B101KA/CY14B101MA
PRELIMINARY
Figure 10. SRAM Write Cycle #2: CE Controlled [3, 22, 23, 24]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 11. SRAM Write Cycle #3: BHE and BLE Controlled [3, 22, 23, 24, 25]
(Not applicable for RTC register writes)
tWC
Address
Address Valid
tSCE
CE
tSA
tHA
tBW
BHE, BLE
tAW
tPWE
WE
tSD
Data Input
tHD
Input Data Valid
High Impedance
Data Output
Note
25. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
Document #: 001-42880 Rev. *C
Page 19 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
AutoStore/Power Up RECALL
Parameters
20ns
Description
Min
tHRECALL [26] Power Up RECALL Duration
tSTORE [27] STORE Cycle Duration
tDELAY [28]
Time Allowed to Complete SRAM Write Cycle
VSWITCH
Low Voltage Trigger Level
tVCCRISE
[16]
[16]
VHDIS
tLZHSB[16]
tHHHD[16]
VCC Rise Time
25ns
Max
20
Min
45ns
Max
20
Min
Max
20
Unit
ms
8
8
8
ms
20
25
25
ns
2.65
2.65
2.65
V
150
150
150
µs
HSB Output Disable Voltage
1.9
1.9
1.9
V
HSB To Output Active Time
HSB High Active Time
5
500
5
500
5
500
µs
ns
Switching Waveforms
Figure 12. AutoStore or Power Up RECALL [29]
VCC
VSWITCH
VHDIS
27
VVCCRISE
Note
tSTORE
Note
27
tSTORE
30
tHHHD
Note
tHHHD
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
Read & Write
Inhibited
(RWI)
tHRECALL
POWER-UP
RECALL
Read & Write
tHRECALL
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
26. tHRECALL starts from the time VCC rises above VSWITCH.
27. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place
28. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
29. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
30. HSB pin is driven HIGH to VCC only by internal 100 kΩ resistor, HSB driver is disabled.
Document #: 001-42880 Rev. *C
Page 20 of 29
[+] Feedback
CY14B101KA/CY14B101MA
PRELIMINARY
Software Controlled STORE/RECALL Cycle
Parameters[31, 32]
tRC
tSA
tCW
tHA
tRECALL
tSS [33, 34]
20 ns
Min
Max
20
0
15
0
200
100
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Soft Sequence Processing Time
25 ns
Min
Max
25
0
20
0
200
100
45 ns
Min
Max
45
0
30
0
200
100
Unit
ns
ns
ns
ns
µs
µs
Switching Waveforms
Figure 13. CE & OE Controlled Software STORE/RECALL Cycle [32]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
35
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 14. AutoStore Enable/Disable Cycle
Address
tSA
CE
tRC
tRC
Address #1
Address #6
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tHZCE
tSS
35
Note
t DELAY
DQ (DATA)
Notes
31. The software sequence is clocked with CE controlled or OE controlled reads.
32. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.
33. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
34. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
35. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document #: 001-42880 Rev. *C
Page 21 of 29
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CY14B101KA/CY14B101MA
PRELIMINARY
Hardware STORE Cycle
Parameters
20ns
Description
Min
tDHSB
HSB To Output Active Time when write latch not set
tPHSB
Hardware STORE Pulse Width
25ns
Max
Min
45ns
Max
20
Min
25
15
15
Max
25
15
Unit
ns
ns
Switching Waveforms
Figure 15. Hardware STORE Cycle[27]
Write latch set
tPHSB
HSB (IN)
tSTORE
tDELAY
tHHHD
HSB (OUT)
tLZHSB
DQ (Data Out)
RWI
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
HSB (IN)
HSB (OUT)
tDELAY
tDHSB
tDHSB
RWI
Figure 16. Soft Sequence Processing[33, 34]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Document #: 001-42880 Rev. *C
Page 22 of 29
[+] Feedback
CY14B101KA/CY14B101MA
PRELIMINARY
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 5. Truth Table for x8 Configuration
CE
Inputs/Outputs[2]
WE
OE
Mode
Power
H
X
X
High Z
Deselect/Power down
Standby
L
H
L
Data Out (DQ0–DQ7)
Read
Active
L
H
H
High Z
Output Disabled
Active
L
L
X
Data in (DQ0–DQ7)
Write
Active
Table 6. Truth Table for x16 Configuration
CE
WE
OE
BHE[3]
BLE[3]
Inputs/Outputs[2]
Mode
Power
H
X
X
X
X
High-Z
Deselect/Power down
Standby
L
X
X
H
H
High-Z
Output Disabled
Active
L
H
L
L
L
Data Out (DQ0–DQ15)
Read
Active
L
H
L
H
L
Data Out (DQ0–DQ7)
DQ8–DQ15 in High-Z
Read
Active
L
H
L
L
H
Data Out (DQ8–DQ15)
DQ0–DQ7 in High-Z
Read
Active
L
H
H
L
L
High-Z
Output Disabled
Active
L
H
H
H
L
High-Z
Output Disabled
Active
L
H
H
L
H
High-Z
Output Disabled
Active
L
L
X
L
L
Data In (DQ0–DQ15)
Write
Active
L
L
X
H
L
Data In (DQ0–DQ7)
DQ8–DQ15 in High-Z
Write
Active
L
L
X
L
H
Data In (DQ8–DQ15)
DQ0–DQ7 in High-Z
Write
Active
Document #: 001-42880 Rev. *C
Page 23 of 29
[+] Feedback
PRELIMINARY
CY14B101KA/CY14B101MA
Part Numbering Nomenclature
CY 14 B 101 K A -ZS P 20 X C T
Option:
T - Tape and Reel
Temperature:
Blank - Std.
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
P - 54 Pin
Blank - 44 Pin
Die revision:
Blank: No Rev
A - 1st Rev
Package:
ZS - TSOP II
SP - TSSOP
Voltage:
B - 3.0V
Speed:
20 - 20 ns
25 - 25 ns
45 - 45 ns
Data Bus:
K - x8 + RTC
M - x16 + RTC
Density:
101 - 1 Mb
nvSRAM
14 - AutoStore + Software STORE + Hardware STORE
Cypress
Document #: 001-42880 Rev. *C
Page 24 of 29
[+] Feedback
PRELIMINARY
CY14B101KA/CY14B101MA
Ordering Information
Speed
(ns)
20
25
45
Ordering Code
Package
Diagram
Operating
Range
Package Type
CY14B101KA-ZS20XCT
51-85087
44-pin TSOPII
CY14B101KA-ZS20XC
51-85087
44-pin TSOPII
CY14B101MA-ZSP20XCT
51-85160
54-pin TSOPII
CY14B101MA-ZSP20XC
51-85160
54-pin TSOPII
CY14B101KA-SP20XCT
51-85061
48-pin SSOP
CY14B101KA-SP20XC
51-85061
48-pin SSOP
CY14B101KA-ZS20XIT
51-85087
44-pin TSOPII
CY14B101KA-ZS20XI
51-85087
44-pin TSOPII
CY14B101MA-ZSP20XIT
51-85160
54-pin TSOPII
CY14B101MA-ZSP20XI
51-85160
54-pin TSOPII
CY14B101KA-SP20XIT
51-85061
48-pin SSOP
CY14B101KA-SP20XI
51-85061
48-pin SSOP
CY14B101KA-ZS25XCT
51-85087
44-pin TSOPII
CY14B101KA-ZS25XC
51-85087
44-pin TSOPII
CY14B101MA-ZSP25XCT
51-85160
54-pin TSOPII
CY14B101MA-ZSP25XC
51-85160
54-pin TSOPII
CY14B101KA-SP25XCT
51-85061
48-pin SSOP
CY14B101KA-SP25XC
51-85061
48-pin SSOP
CY14B101KA-ZS25XIT
51-85087
44-pin TSOPII
CY14B101KA-ZS25XI
51-85087
44-pin TSOPII
CY14B101MA-ZSP25XIT
51-85160
54-pin TSOPII
CY14B101MA-ZSP25XI
51-85160
54-pin TSOPII
CY14B101KA-SP25XIT
51-85061
48-pin SSOP
CY14B101KA-SP25XI
51-85061
48-pin SSOP
CY14B101KA-ZS45XCT
51-85087
44-pin TSOPII
CY14B101KA-ZS45XC
51-85087
44-pin TSOPII
CY14B101MA-ZSP45XCT
51-85160
54-pin TSOPII
CY14B101MA-ZSP45XC
51-85160
54-pin TSOPII
CY14B101KA-SP45XCT
51-85061
48-pin SSOP
CY14B101KA-SP45XC
51-85061
48-pin SSOP
CY14B101KA-ZS45XIT
51-85087
44-pin TSOPII
CY14B101KA-ZS45XI
51-85087
44-pin TSOPII
CY14B101MA-ZSP45XIT
51-85160
54-pin TSOPII
CY14B101MA-ZSP45XI
51-85160
54-pin TSOPII
CY14B101KA-SP45XIT
51-85061
48-pin SSOP
CY14B101KA-SP45XI
51-85061
48-pin SSOP
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
All parts are Pb-free. This table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.
Document #: 001-42880 Rev. *C
Page 25 of 29
[+] Feedback
PRELIMINARY
CY14B101KA/CY14B101MA
Package Diagrams
Figure 17. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
1
23
10.262 (0.404)
10.058 (0.396)
11.938 (0.470)
11.735 (0.462)
22
OR E
K X A
SG
EJECTOR PIN
44
TOP VIEW
0.800 BSC
(0.0315)
BOTTOM VIEW
0.400(0.016)
0.300 (0.012)
10.262 (0.404)
10.058 (0.396)
BASE PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.10 (.004)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087-*A
Figure 18. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-42880 Rev. *C
Page 26 of 29
[+] Feedback
PRELIMINARY
Package Diagrams
CY14B101KA/CY14B101MA
(continued)
Figure 19. 48-Pin SSOP (51-85061)
Document #: 001-42880 Rev. *C
Page 27 of 29
[+] Feedback
PRELIMINARY
CY14B101KA/CY14B101MA
Document History Page
Document Title: CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock
Document Number: 001-42880
Orig. of
Rev. ECN No. Submission
Description of Change
Date
Change
**
2050747
See ECN
UNC/PYRS New Data Sheet
*A
2607447 11/18/2008
GVCH/AESA Removed 15 ns access speed, updated “Features”, added CY14B101MA (x16)
part, changed title to “CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K x 16)
nvSRAM with Real-Time-Clock”.
Added 54-pin TSOP II package related information, updated Logic block diagram,
added footnote 1 and 2.
Pin definition: Updated WE, HSB and NC pin description.
Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description,
Page 4: Updated Software store and software recall description
Updated Figure 2, Page 4: Updated Hardware store operation and Hardware
RECALL (Power up) description
Footnote 1 and 10 referenced for Mode selection Table
Added footnote 10, updated footnote 8 and 9
Page 6: updated Data protection description
Page 6: Updated starting and stopping the oscillator description
Page 7: Updated Calibrating the clock description
Page 8: Added Flags register
Updated table 4, added footnote 12 and 13
Updated Register map detail Table 5
Maximum Ratings: Added Max. Accumulated storage time
Changed Output short circuit current parameter name to DC output current
Changed ICC2 from 6 mA to 10 mA
Changed ICC3 from 15 mA to 35 mA
Changed ICC4 from 6 mA to 5 mA
Changed ISB from 3 mA to 5 mA
Added IIX for HSB
Updated ICC1, ICC3, ISB and IOZ Test conditions
Changed VCAP voltage min value from 68uF to 61uF
Added VCAP voltage max value to 180uF
Updated footnote 14 and 15, added footnote 16
Added Data retention and Endurance Table
Added thermal resistance value to 44/54 TSOP II packages
Updated Input Rise and Fall time in AC test Conditions
Changed VRTCcap min value from 1.2 to 1.5V for industrial Commercial
temperature
Changed VRTCcap min value from 2.7 to 3.6V for industrial Commercial
temperature
Updated RTC recommended component configuration values
Updated tOCS value for minimum and room temperature from 10 and 5sec to 2
and 1sec resp.
Referenced footnote 22 to tOHA parameter
Updated All switching waveforms
Updated footnote 22, added footnote 25
Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled)
Changed tSTORE max value from 15ms to 8ms
Updated tDELAY value
Added VHDIS, tHHHD and tLZHSB parameters
Updated footnote 29, added footnote 31 and 32
Software controlled STORE/RECALL Table: Changed tAS to tSA
Changed tGHAX to tHA, changed tHA value from 1ns to 0ns
Added Figure 14
Added tDHSB parameter, changed tHLHX to tPHSB
Updated tSS from 70 us to 100 us, added truth table for SRAM operations
Updated ordering information and part numbering nomenclature
Document #: 001-42880 Rev. *C
Page 28 of 29
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PRELIMINARY
CY14B101KA/CY14B101MA
Document Title: CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock
Document Number: 001-42880
Orig. of
Rev. ECN No. Submission
Description of Change
Date
Change
*B
2654484
02/05/09
GVCH/PYRS Changed the data sheet from Advance information to Preliminary
Changed X1, X2 pin names to Xout, Xin respectively
Updated Real Time Clock operation description
Added footnotes 11 and 12
Added default values to RTC Register Map” table 3
Updated flag register description in Register Map Detail” table 4
Changed C1, C2 values to 21pF, 21pF respectively
Changed IBAK value from 350 nA to 450 nA at hot temperature
Changed VRTCcap typical value from 2.4V to 3.0V
Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, tHZOE, tLZBE, tLZWE, tHZWEand tHZBE
Added footnote 24
Updated Figure 13
*C
2733909
07/09/09
GVCH/AESA Page 3; Added note to AutoStore Operation description
Page 4; Updated Hardware STORE (HSB) Operation description
Page 4; Updated Software STORE Operation description
Added best practices
Changed C1, C2 values to 10pF, 67pF respectively
Changed IBAK and VRTCcap parameter values
Added RBKCHG parameter
Updated VHDIS parameter description
Updated tDELAY parameter description
Updated footnote 28 and added footnote 35
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Document #: 001-42880 Rev. *C
Revised July 09, 2009
Page 29 of 29
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