SUTEX HV311 Hotswap, controllers with circuit breaker Datasheet

HV301/HV311
HV301
HV311
Demo Kit
Available
Hotswap, Controllers with Circuit Breaker
(Negative Supply Rail)
Features
General Description
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The Supertex HV301 and HV311 Hotswap Controllers provide
control of power supply connection during insertion of cards or
modules into live backplanes. They may be used in systems
where active control is implemented in the negative lead of
supplies ranging from ±10V to ±90V.
±10V to ±90V Operation
Built-in “normally on” turn-on clamp eliminates components
UV/OV Lock Out & Power-on-Reset(POR) for Debouncing
Sense resistor programmed circuit breaker
Programmable circuit breaker holdoff
Inrush control using either: i) servo or ii) feedback cap
Feedback to Ramp pin means no Gate Clamp needed
Application solution for input voltage step (diode “ORing”)
Programmable Auto-Retry (tens of seconds if desired)
Auto-Retry or Latched Operation
Enable through Open Drain interface to UV or OV
Low Power, <0.6mA , <0.4mA Sleep Mode
PWRGD Flag
Small SOIC-8 Package
During initial power application the gate of the external pass
device is clamped low to suppress contact bounce glitches by a
“normally on” circuit which does not require initialization of the
IC. Thereafter the UV/OV supervisors and power-on-reset work
together to suppress gate turn on until mechanical bounce has
ended. The HV301/311 then control the current inrush limit to a
programmed level using one of two possible methods, i) servo
control or ii) a drain to ramp capacitor. The above methods
eliminate the need for extra hold-off or current limiting components. The devices also include an electronic circuit breaker,
programmed by a sense resistor.
Applications
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After the load capacitance has fully charged, the HV301/311 will
transition into a low power mode, and enable the open drain
PWRGD. In low power mode the HV301/311 continues to monitor the input voltage and monitor the current level. If a load fault
occurs, the electronic circuit breaker will trip, the pass
element will be turned off, and the PWRGD will return to an
-48V Central Office Switching
-24V Cellular and Fixed Wireless Systems
-24V PBX Systems
Line Cards
-48V Powered Ethernet for VoIP
Distributed Power Systems
Power Supply Control
+48V Storage Networks
Electronic Circuit Breaker
(continued on Page 21)
Typical Application Circuit
GND
8
VDD
R1
487kΩ
R2
6.81kΩ
3
2
PWRGD / PWRGD
1
ENABLE / ENABLE
UV
HV301/
HV311
OV
DC/DC
PWM
CONVERTER
R3
9.76kΩ
VEE
4
SENSE
5
+5V
Cload
COM
RAMP
GATE
7
6
C2
0.75nF
C1
10nF
-48V
-48V
R4
12.5mΩ
Q1
IRF530
Notes: 1.
2.
3.
4.
Undervoltage Shutdown (UV) set to 35V.
Overvoltage Shutdown (OV) set to 65V.
Current Limit set to -1A.
CB set to 8A.
08/26/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products,
1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV301/HV311
Electrical Characteristics (-10V ≤ V
Symbol
Parameter
EE
≤ -90V, -40°C ≤ +85°C unless otherwise noted)
Min
Typ
Max
Units
Conditions
Supply (Referenced to VDD pin)
VEE
Supply Voltage
-10
V
IEE
Supply Current
600
700
µA
VEE = -48V, Mode = Limiting
IEE
Sleep Mode Suppy Current
400
450
µA
VEE = -48V, Mode = Sleep
-90
OV and UV Control (Referenced to VEE pin)
VUVH
UV High Threshold
1.26
V
Low to High Transition
VUVL
UV Low Threshold
1.16
V
High to Low Transition
VUVHY
UV Hysteresis
100
mV
IUV
UV Input Current
VOVH
OV High Threshold
1.26
1.0
nA
VUV = VEE +1.9V
V
Low to High Transition
High to Low Transition
VOVL
OV Low Threshold
1.16
V
VOVHY
OV Hysteresis
100
mV
IOV
OV Input Current
1.0
nA
VOV = VEE + 0.5V
Current Limit (Referenced to VEE pin)
VSENSE-CL
Current Limit Threshold Voltage
40
50
60
mV
VUV = VEE + 1.9V, VOV = VEE + 0.5V
VSENSE-CB
Circuit Breaker Threshold Voltage
80
100
120
mV
VUV = VEE + 1.9V, VOV = VEE + 0.5V
10
12
Gate Drive Output (Referenced to VEE pin)
VGATE
Maximum Gate Drive Voltage
8.5
V
VUV = VEE + 1.9V, VOV = VEE + 0.5V
IGATEUP
Gate Drive Pull-Up Current
500
µA
VUV = VEE + 1.9V, VOV = VEE + 0.5V
IGATEDOWN
Gate Drive Pull-Down Current
40
mA
VUV = VEE, VOV = VEE + 0.5V
Ramp Timing Control (Test Conditions: CLOAD=100µF, CRAMP=10nF, VUV=VEE+1.9V, VOV=VEE+0.5V, External MOSFET is IRF530*)
IRAMP
Ramp Pin Output Current
10
µA
VSENSE = 0V
(See Note 1)
tPOR
Time from UV to Gate Turn On
2.0
ms
tRISE
Time from Gate Turn On to VSENSE Limit
400
µs
tLIMIT
Duration of Current Limit Mode
tPWRGD
VRAMP
5.0
ms
Time from Current Limit to PWRGD
5.0
ms
Voltage on Ramp Pin in Current Limit Mode
3.6
V
tSTARTLIMIT
Start Up Time Limit
80
tCBTRIP
Circuit Breaker Delay Time
2.0
tAUTO
Automatic Restart Delay TIme
100
120
ms
5.0
µs
16
(See Note 2)
May be extended by external RC circuit
s
Power Good Output (Referenced to VEE pin)
VPWRGD(hi)
Applied Voltage to PWRGD
VPWRGD(lo)
PWRGD Low Voltage
IPWRGD(lk)
Maximum Leakage Current
90
V
PWRGD=Inactive
0.5
0.8
V
IPWRGD = 1mA, PWRGD=Active
<1.0
10
µA
PWRGD=Inactive, VPWRGD=90
tGATEHLOV OV Comparator Transition
500
ns
tGATEHLUV UV Comparator Transition
500
ns
Dynamic Characteristics
Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. Vth = 3V for an IRF530.
* IRF530 is a registered trademark of International Rectifier.
2
HV301/HV311
Ordering Information
General Description, cont’d.
inactive state. Thereafter a programmable auto-retry timer will
hold the device off to allow the pass element to cool before
resetting and restarting. The auto-retry can be disabled using a
single resistor if desired.
The HV301/HV311 includes a current mode servo-circuit which
can be used as a return to limit during input voltage steps such
as would be seen in a diode “ORed” situation when power
switches back to regulated supply from battery operation. The
HV301/HV311 allow independent programming of the trigger
level of this phenomenon so that it may be set at a different level
to the current limit level if desired. Under all circumstances the
maximum servo period is limited to 100ms to protect the pass
element.
Active State of
Power Good Signal
Package Options
HIGH
HV301LG
LOW
HV311LG
Pinout
PWRGD (HV301)
1
8
VDD
OV
2
7
RAMP
UV
3
6
GATE
VEE
4
5
SENSE
PWRGD (HV311)
PWRGD Logic
Model
HV301
HV311
Condition
PWRGD
INACTIVE (Not Ready)
0
VEE
ACTIVE (Ready)
1
HI Z
INACTIVE (Not Ready)
1
HI Z
ACTIVE (Ready)
0
VEE
Absolute Maximum Ratings
VEE reference to VDD pin
+0.3V to -100V
VPWRGD referenced to VEE Voltage
-0.3V to +100V
VUV and VOV referenced to VEE Voltage
Pin Description
PWRGD – The Power Good Output Pin is held inactive on initial
power application and will go active when the external MOSFET
is fully turned on. This pin may be used as an enable control
when connected directly to a PWM power module.
-0.3V to +12V
Operating Ambient Temperature
-40°C to +85°C
Operating Junction Temperature
-40°C to +125°C
Storage Temperature Range
-65°C to +150°C
8 Pin SO
OV – This OverVoltage (OV) sense pin, when raised above its
high threshold will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin falls
below the low threshold limit, initiating a new start-up cycle.
UV – This UnderVoltage (UV) sense pin, when below its low
threshold limit will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin
rises above the high threshold limit, initiating a new start-up
cycle.
Waveforms
VEE – This pin is the negative terminal of the power supply input
to the circuit.
VDD – This pin is the positive terminal of the power supply input
to the circuit.
Drain
50V/div
RAMP – This pin provides a current output so that a timing ramp
voltage is generated when a capacitor is connected.
VIN
50V/div
GATE – This is the Gate Driver Output for the external NChannel MOSFET.
Gate
5.00V/div
SENSE – The current sense resistor connected from this pin to
VEE Pin programs the circuit breaker trip limit.
Iinrush
500mA/div
5.00ms/div
3
HV301/HV311
Functional Block Diagram
UV
C
VIN
Regulator & POR
Vbg
UVLO
OV
PWRGD = HV301
Logic
C
PWRGD = HV311
~9.8V
C
Latch High
Sleep
P
U
L
L
H
I
G
H
D
I
S
A
B
L
E
VDD
2Vbg
10µA
1 : 2
mirror
RAMP
buffer
GATE
Transconductor
SENSE
Transconductor
5k
gm
5k
VEE
Clamp Mechanism
Once the internal under voltage lock out (UVLO) has been
satisfied, the circuit checks the input supply undervoltage (UV)
and overvoltage (OV) sense circuits to ensure that the input
voltage is within programmed limits. These limits are determined
by the selected values of resistors R1, R2 and R3, which form a
voltage divider.
Functional Description
Insertion into Hot Backplanes
Telecom, data networks and some computer applications require the ability to insert and remove circuit cards from systems
without powering down the entire system. All circuit cards have
some filter capacitance on the power rails, which is especially
true in circuit cards or network terminal equipment utilizing
distributed power systems. The insertion can result in high inrush
currents that can cause damage to connector and circuit cards
and may result in unacceptable disturbances on the system
backplane power rails.
Assuming the above conditions are satisfied and while continuing to hold the PWRGD output inactive and the external MOSFET
GATE voltage low, the current source feeding the RAMP pin is
turned on. The external capacitor connected to it begins to
charge, thus starting an initial time delay determined by the value
of the capacitor. During this time if the OV or UV limits are
exceeded, an immediate reset occurs and the capacitor connected to the RAMP pin is discharged.
The HV301 and HV311 are designed to facilitate the insertion of
these circuit cards or connection of terminal equipment by
eliminating these inrush currents and powering up these circuits
in a controlled manner after full connector insertion has been
achieved. The HV301 or HV311 is intended to provide this
function on supply rails in the range of ±10 to ±90 Volts.
When the voltage on the RAMP pin reaches an internally set
threshold voltage, the gate drive circuit begins to turn on the
external MOSFET. In servo mode, once the gate threshold is
reached, the resulting output current generates a voltage drop
on the sense resistor connected between the SENSE and VEE
pins, causing a decrease in the available current charging the
capacitor on the RAMP pin. This continuous feedback mechanism allows the output current to rise inverse exponentially over
a period of a few hundred microseconds to the sense resistor
programmed current limit set point.
Description of Operation
During initial power application, a unique proprietary circuit holds
off the external MOSFET, preventing an input glitch while an
internal regulator establishes an internal operating voltage of
approximately 10V. Until the proper internal voltage is achieved
all circuits are held reset, the PWRGD output is inactive and the
gate to source voltage of the external MOSFET is clamped low.
When the voltage drop on the sense resistor reaches 50mV the
RAMP pin current is reduced to zero and the voltage on the
4
HV301/HV311
Functional Description, cont’d.
RAMP pin will be fixed, indicating that the circuit is in current limit
mode. Depending on the value of the load capacitor and the
programmed current limit, charging may continue for some time,
but may not exceed a nominal 100ms preset time limit. Once the
load capacitor has been charged, the output current will drop,
reducing the voltage on the SENSE pin, which in turn will
increase the RAMP pin current, thus causing the voltage on the
capacitor connected to the RAMP pin to continue rising, thereby
providing yet another programmed delay. If due to output overload conditions during startup, PWRGD does not achieve an
active state within 100ms or the circuit breaker is tripped, the
circuit is reset, pulling down the GATE to VEE, discharging the
capacitor connected to the RAMP pin, changing PWRGD to an
inactive state. A timeout or circuit breaker fault will initiate an
auto-retry if enabled.
Inrush ~ 10µA•Cload/C2. (See Programming Inrush and ICB for
accurate formula on page 6.)
When the ramp voltage is within 1.2V of the regulated internal
supply voltage, the controller will force the GATE terminal to a
nominal 10V, the PWRGD pin will change to an active state, the
circuit breaker supervisor is enabled and the circuit will transition
to a low power sleep mode.
When the voltage on the SENSE pin rises to 100mV, indicating
an over current condition, the circuit breaker will trip in less than
5µs. This time may be extended by the addition of external
components.
At any time during the start up cycle or thereafter, crossing the
UV and OV limits (including hysteresis) will cause an immediate
reset of all internal circuitry. When the input supply voltage
returns to a value within the programmed UV and OV limits a new
start up sequence will be initiated.
On the other hand, in feedback capacitor mode, a current source
of 10µA from the RAMP pin limits the dv/dt of the feedback
capacitor which, in turn, programs Inrush according to
Design Information
From the second equation for an OV shut down threshold of 65V
the value of R3 may be calculated.
Setting UnderVoltage and OverVoltage Shut Down
The UV and OV pins are connected to comparators with nominal
1.21V thresholds and 100mV of hysteresis (1.21V ± 50mV).
They are used to detect under voltage and over voltage conditions at the input to the circuit. Whenever the OV pin rises above
its high threshold (1.26V) or the UV pin falls below its low
threshold (1.16V) the GATE voltage is immediately pulled low,
the PWRGD pin changes to its inactive state and the external
capacitor connected to the RAMP pin is discharged.
OVOFF = 1.26 =
R3 =
From the first equation for a UV shut down threshold of 35V the
value of R2 can be calculated.
The undervoltage and overvoltage shut down thresholds can be
programmed by means of the three resistor divider formed by
R1, R2 and R3. Since the input currents on the UV and OV pins
are negligible the resistor values may be calculated as follows:
UVOFF = 1.16 =
The closest 1% value is 6.81kΩ.
R3
R1 + R2 + R3
Then
R1 = 500kΩ − R2 − R3 = 483kΩ
Where |VEEUV(off)| and |VEEOV(off)| relative to VEE are Under & Over
Voltage Shut Down Threshold points.
The closest 1% value is 487kΩ.
If we select a divider current of 100µA at a nominal operating
input voltage of 50 Volts then
R1 + R2 + R3 =
35 × ( R2 + R3)
500kΩ
R2 = 1.16 × 500kΩ − 9.76kΩ = 6.81kΩ
35
× R2 + R3
R1 + R2 + R3
OVOFF = VOVH = 1.26 = VEEOV (off ) ×
1.26 × 500kΩ
= 9.69kΩ
65
The closest 1% value is 9.76kΩ.
Calculations can be based on either the desired input voltage
operating limits or the input voltage shutdown limits. In the
following equations the shutdown limits are assumed.
UVOFF = VUVL = 1.16 = VEEUV (off )
65 × R3
500kΩ
50V
= 500kΩ
100µA
5
HV301/HV311
Design Information, cont’d.
10V
C2
0.75nF
10µA
48V
Cload
Undervoltage/Overvoltage Operation
1 : 2
mirror
10µA
GND
Isink
VSENSE
UVOFF
UVON
RAMP
terminal
GATE
Termial
Vsense
10n=Cramp
VIN
Rsense
OVON
OVOFF
Pass
Transistor
5k
Internal Circuitry
ON
1.
OFF
Rsense =
From the calculated resistor values the OV and UV start up
threshold voltages can be calculated as follows:
UVON = VUVH = 1.26 = VEEUV (on)
Choose circuit breaker trip point eg. 8A as follows
100 mV 100 mV
=
= 12.5mΩ
ICB
8
2.
Choose inrush level, for example Inrush = 1A
× R2 + R3
R1 + R2 + R3
3.
Calculate Isink =
R3
R1 + R2 + R3
4.
OVON = VOVL = 1.16 = VEEOV (on) ×
Inrush *Rsense 1A × 12.5mΩ
=
= 2.5µA
5kΩ
5kΩ
Calculate C2 discharge limit
= 10µA -Isink = 7.5µA (typical) = iC 2
Where |VEEUV(on)| and |VEEOV(on)| are Under & Over Voltage Start
Up Threshold points relative to VEE.
4a. Adjust for Auto - retry disable, if used →
Then
VEEUV (on) = 1.26 × R1 + R2 + R3
R2 + R3
⇒ e.g. iC 2 = 10µA -Isink -1.6µA
VEEUV (on) = 1.26 × 487kΩ + 6.81kΩ + 9.76kΩ = 38.29V
6.81kΩ + 9.76kΩ
In this example we assume Auto - retry is enabled so
ignore 1.6µA, ∴ iC 2 = 10µA -Isink = 7.5µA
And
5.
VEEOV (on) = 1.16 × R1 + R2 + R3
R3
VEEOV (on)
Max Vt of a typical
power FET
Vt max
4V
≅
e.g.
= 1.6µA
R disable
2.5MΩ
Note: i = C
dv
dt
iC 2 = C 2 ×
dv
dt
Inrush = Cload ×
dv
dt
Note VIN is fixed and VRAMP is constant during limiting
= 1.16 × 487kΩ + 6.81kΩ + 9.76kΩ = 59.85V
9.76kΩ
dv
dv
across Cload =
across C 2 (as they share a
dt
dt
common node and their other terminals are fixed during inrush)
⇒
Therefore, the circuit will start when the input supply voltage is
in the range of 38.29V to 59.85V.
iC × Cload
iC2 Inrush
=
⇒ Inrush = 2
C2
Cload
C2
by conservation of charge on RAMP Node iC2 = 7.5µA
Programming Inrush and ICB (Circuit Breaker)
Inrush =
Method 1: Inrush independent of ICB
10V
=
Vin
C2
7.5µA
10µA
–
+
+
Cload=100µF
inrush
7.5µA × Cload
7.5µA × Cload
⇒ C2 =
C2
Inrush
7.5µA × 100 nF
= 750pF = 0.75nF
1A
–
7.5µA
GATE
0µA
(DRAIN)
+K–
RAMP
VSENSE
2.5µA
Cdb
0µA
10n
Note that RAMP is protected by AC divider and Gate
is clamped internally.
Cgd
Vgs
+
–
Cgs
gm(Vgs-Vt)
VSENSE
5k
Rsense=12.5mΩ
dv
on Cramp constant
df during limiting so no
current flowing into cap
6
HV301/HV311
Design Information, cont’d.
Programming Inrush and ICB, continued:
Timing (Servo Mode)
Method 2: Inrush = 1/2 ICB (Servo Mode)
1.
Choose ICB
contact
bounce
100mV
=
, e.g. 2A ⇒ R SENSE = 50mΩ
R SENSE
GND
VOUT
VIN
VOUT
50mv
50mV
2. Inrush =
, e.g.
= 1A
R SENSE
50mΩ
VUVL
VIN
-48V
VGATE
3.
Add compensation components from gate to drain if
necessary to reduce peaking.
tSTART
VRAMP
VRAMP
VGATE
VGATE
VGS(th)
VGS(lim)
VEE
tTH
Capacitor and/or
compensation resistor
will reduce peaking
tPOR
IIN
ILIM
90%
tRISE
tPWRGD
tLIM
active
PWRGD
inactive
i) start with 2nF from gate to source
Initialization
ii) increase to 10nF if needed
Limiting
Full On
The timing functions are defined by the following equations:
iii) add 1k series resistor from gate to capacitor if needed
t START = 2.4
CRAMP
I RAMP
tTH = VGS ( th )
CRAMP
I RAMP
t POR = t START + tTH
t RISE ≈
CRAMP
 I RAMP

R
g fs 
− SENSE 
RFB 
 0.9 I LIMIT
t LIMIT ≈ VIN
(
CLOAD
I LIMIT
t PWRGD = VINT − VGS (LIMIT ) − 1.2
7
) CI
RAMP
RAMP
HV301/HV311
Design Information, cont’d.
These equations assume that the load is purely capacitive and
the following definitions apply.
Start up Overload Protection
Start up must be achieved within a nominal 100ms as indicated
by the PWRGD pin transition to the active state or the circuit will
reset and an automatic restart will initiate. If there is an output
overload or short circuit during start up, the circuit will be in
current limit for the 100ms time limit (in servo mode). In feedback
capacitor mode the circuit breaker will shutdown the pass FET
before 100ms.
CRAMP is the external capacitor connected to the RAMP pin.
IRAMP is the output current from the RAMP pin, nominally
10µA, when the voltage drop on RSENSE resistor is zero.
VINT is the internally regulated supply voltage and can range
from 8.5V to 12V.
VGS(th) is the gate threshold voltage of the external pass
transistor and may be obtained from its datasheet.
Circuit Breaker
The circuit breaker will trip in less than 5µs when the voltage on
the SENSE pin reaches a nominal 100mV. A resistor in series
with the SENSE pin and a capacitor connected between the
SENSE and VEE pins may be added to delay the rate of voltage
rise on the SENSE pin, thus permitting a current overshoot and
delaying Circuit Breaker activation.
VGS(limit) is the external pass transistor gate-source voltage
required to obtain the limit current. It is dependent on the
pass transistor’s characteristics and may be obtained from
the transfer characteristics on the transistor datasheet.
gfs is the transconductance of the external pass transistor
and may be obtained from its datasheet.
Automatic Restart
RFB is the internal feedback resistor and is nominally 5kΩ.
The automatic restart delay time is directly proportional to the
capacitance at the RAMP pin. Automatic restart sequence is
activated whenever the 100ms timeout is reached during start up
or the circuit breaker is tripped.
ILIMIT is the load current when the voltage drop on the RSENSE
resistor is 50mV.
These equations may be used to calculate the minimum value of
CRAMP for the most critical system performance characteristics.
For maximum contact bounce duration protection choose a
value for tPOR and use the following equation:
CRAMP =
2.5µA
t POR × I RAMP
2.4 + VGS ( th )
2.5µA
If control of PWRGD active delay is the critical system parameter, then choose a value for tPWRGD and use the following
equation:
C RAMP =
Auto-retry can be approximated as a
555-timer with 2.5µA charge up and
charge down currents through 8V, to
a count of 256. Therefore,
Cramp
TAUTORETRY =
e.g.
2 × 8 × 256
× Cramp
2.5 µA
2 × 8 × 256
× Ion = 16.4s
2.5µA
Due to the 2.5µA max charge current a resistor which draws
more than 2.5µA below 8V will disable the autoretry. Try to
keep this resistor as big as possible, e.g. 2.5MΩ, for most
MOSFETs with max Vt of 4V this will vary the 10µA Ramp
current source by only 4/2.5MΩ=1.6µA.
t PWRGD × I RAMP
VINT − VGS(limit) − 1.2
8
HV301/HV311
Application Information
Supported External Pass Devices
Paralleling External Pass Transistors
The HV301 and HV311 are designed to support N-Channel
MOSFETs and IGBTs.
Due to variations in threshold voltages and gain characteristics
between samples of transistors reliable 50% current sharing is
not achievable. Some measure of paralleling may be accomplished by adding resistors in series with the source of each
device; however, it will cause increased voltage drop and power
dissipation.
Selection of External Pass Devices
Since the current limit is likely to be set just slightly higher than
maximum continuous load current in a typical system, the
continuous current rating of the device will have to be at least
equal to the current limit value.
Paralleling of external Pass devices is not recommended!
If a sufficiently high current rated external pass transistor cannot
be found then increased current capability may be achieved by
connecting independent hotswap circuits in parallel, since they
act as current sources during the load capacitor charging time
when the circuits are in current limit. For this application the
HV301 with active high PWRGD is recommended where the
PWRGD pins of multiple hot swap circuits can be connected in
a wired OR configuration.
The RDS(ON) of the device is likely to be selected based on
allowable voltage drop after the hot swap action has been
completed. Thus the continuous power dissipation rating of the
device can be determined from the following equation:
2
PCONT = RDS (ON ) × I LIMIT
The peak power rating may be calculated from the following
equation:
PPEAK = VIN × I LIMIT
Given these values an external pass transistor may be selected
from the manufacturers data sheet.
Selection of Current Sense Resistor
The power rating of the sense resistor must be greater than
2
Iload
× R , where Iload is the normal maximum operating load.
Kelvin Connection to Sense Resistor
Physical layout of the printed circuit board is critical for correct
current sensing. Ideally trace routing between the current sense
resistor and the VEE and SENSE pins should be direct and as
short as possible with zero current in the sense traces. The use
of Kelvin connection from SENSE pin and VEE pin to the respective ends of the current sense resistor is recommended.
To
To
VEE SENSE
Pin
Pin
To Negative
Terminal of
Power Source
Sense Resistor
To Source
of MOSFET
9
HV301/HV311
PWRGD Output
then the HV311 can be directly connected as shown below
(Application Circuit 1) since the open drain PWRGD output is
in a High-Z state until the external MOSFET is fully turned on and
the potential on the negative input of the converter is essentially
the same as the VEE pin of the HV311.
It is critical to have a detailed understanding of the ENABLE input
circuitry of the load (DC/DC PWM Converter) in order to make
the correct choice between the HV301 or HV311.
Many DC/DC PWM Converters reference their ENABLE inputs
to the negative input terminal. If the ENABLE input is active LOW
8
GND
VDD
PWRGD
1
R1
487kΩ
3
+
Cload
UV
R2
6.81kΩ
ENABLE
+5V
HV311
2
OV
R3
9.76kΩ
RAMP
7
VEE
SENSE
4
5
DC/DC
PWM
CONVERTER
COM
GATE
6
C1
10nF
-48V
R4
12.5mΩ
Q1
IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 1
10
HV301/HV311
Application Information, cont’d.
However, if the DC/DC PWM Converter with the ENABLE input
circuit configuration was active HIGH, then the apparent choice
of the HV301 would result in the creation of a current path
through the protective diode clamp of the ENABLE input and the
PWRGD output MOSFET of the HV301. For this situation the
HV311 should be used as shown below in Application Circuit 2.
GND
In some applications the PWRGD signal is used to activate load
circuitry on the isolated output side of the DC/DC PWM Converter. In this situation an optocoupler is needed to provide the
required isolation as shown below in Application Circuit 3.
8
VDD
PWRGD
1
R1
487kΩ
R2
6.81kΩ
+
3
2
UV
ENABLE
Cload
HV311
OV
R3
9.76kΩ
DC/DC
PWM
CONVERTER
RAMP
VEE
7
SENSE
4
+5V
5
COM
GATE
6
C1
10nF
-48V
Q1
IRF530
R4
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 2
Optocoupler
GND
Rload
8
VDD
PWRGD
1
R1
487kΩ
3
ENABLE
UV
R2
6.81kΩ
HV311
2
DC/DC
PWM
CONVERTER
OV
R3
9.76kΩ
RAMP
7
+5V
Cload
VEE
4
COM
SENSE GATE
5
6
C1
10nF
-48V
R4
12.5mΩ
Q1
IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 3
11
HV301/HV311
Application Information, cont’d.
When the details of the load ENABLE circuitry is not known,
using an optocoupler always provides a safe solution
(Application Circuit 4).
Filtering Voltage Spikes on Input Supply
In some systems over voltage spikes of very short duration may
exist. For these systems a small capacitor may be added from
the OV pin to the VEE pin to filter the voltage spikes (Application
Circuit 5).
Optocoupler
GND
8
VDD
PWRGD / PWRGD
1
R1
487kΩ
3
ENABLE / ENABLE
UV
R2
6.81kΩ
HV311
2
DC/DC
PWM
CONVERTER
OV
R3
9.76kΩ
RAMP
7
VEE
4
+5V
Cload
COM
SENSE GATE
5
6
C1
10nF
-48V
Q1
IRF530
R4
60mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 4
8
GND
VDD
R1
487kΩ
R2
6.81kΩ
3
2
PWRGD / PWRGD
1
ENABLE / ENABLE
UV
+5V
Cload
HV301/
HV311
OV
DC/DC
PWM
CONVERTER
R3
9.76kΩ
RAMP
VEE
7
4
COM
SENSE GATE
5
6
C2
-48V
C1
10nF
R4
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Q1
IRF530
Application Circuit 5
12
HV301/HV311
Application Information, cont’d.
Unfortunately this will also cause some delay in responding to
UV conditions. If this UV delay is not acceptable, then separate
resistor dividers can be provided for OV and UV with a capacitor
connected from OV pin to the VEE pin (Application Circuit 6).
Using Short Connector Pin
In some systems short connector pins are used to guarantee that
the power pins are fully mated before the hotswap control circuit
is enabled. For these systems the positive (VDD) end of the R1,
R2, and R3 resistor divider should be connected to the short pin
(Application Circuit 7).
8
GND
VDD
R1
475kΩ
PWRGD / PWRGD
ENABLE / ENABLE
3
UV
R3
511kΩ
R2
16.2kΩ
1
HV311
2
DC/DC
PWM
CONVERTER
OV
R4
10kΩ
RAMP
VEE
7
4
+5V
Cload
COM
SENSE GATE
5
6
C2
C1
10nF
-48V
Q1
IRF530
R5
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 6
Long
Pin
8
GND
Short
Pin
GND
R1
487kΩ
R2
6.81kΩ
VDD
3
2
PWRGD / PWRGD
1
ENABLE / ENABLE
UV
HV301/
HV311
OV
DC/DC
PWM
CONVERTER
R3
9.76kΩ
RAMP
7
+5V
Cload
VEE
4
COM
SENSE GATE
5
6
C1
10nF
-48V
Long
Pin
R4
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Q1
IRF530
Application Circuit 7
13
HV301/HV311
Application Information, cont’d.
If separate resistor dividers are used for OV and UV, then only
the positive (VDD) end of the UV resistor divider should be
connected to the short pin (Application Circuit 8).
mated before the hotswap control circuit is enabled and a single
resistor divider string (R1, R2 and R3) is used, then a 6.2V to 10V
zener diode must be connected from the UV pin to the VEE pin,
as seen below in Application Circuit 9.
If a system requires the use of a short connector pin on the
negative supply lead to guarantee that the power pins are fully
Long
Pin
GND
8
Short
Pin
GND
VDD
PWRGD / PWRGD 1
R1
475K
R2
16.2K
3
ENABLE / ENABLE
UV
R3
511K
HV311
2
+5V
Cload
DC/DC
PWM
CONVERTER
OV
R4
10K
VEE SENSE
5
RAMP
7
4
COM
GATE
6
C1
10nF
-48V Long
Pin
Q1
IRF530
R5
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 8
Long
Pin
8
GND
VDD
PWRGD / PWRGD
R1
487kΩ
3
R2
6.81kΩ
1
ENABLE / ENABLE
UV
HV311
2
DC/DC
PWM
CONVERTER
OV
R3
9.76kΩ
RAMP
VEE
7
Short
-48V Pin
+5V
Cload
4
COM
SENSE GATE
5
6
6.2V
C1
10nF
-48V
Long
Pin
R4
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Q1
IRF530
Application Circuit 9
14
HV301/HV311
Application Information, cont’d.
If a system requires the use of a short connector pin on the
negative supply lead to guarantee that the power pins are fully
mated before the hotswap control circuit is enabled and uses
separate resistor dividers for UV and OV, then a 6.2V to 10V
zener diode must be connected from the OV pin to the VEE pin and
only the OV divider should be connected to the short pin
(Application Circuit 10).
Increasing Under Voltage Hysteresis
If the internally fixed under voltage hysteresis is insufficient for a
particular system application, then it may be increased by using
separate resistor dividers for OV and UV and providing a resistor
feedback path from the GATE pin to the UV pin (Application
Circuit 11).
Long
Pin
GND
8
VDD
PWRGD / PWRGD
R1
475kΩ
1
ENABLE / ENABLE
3 UV
R2
16.2kΩ
HV301/
HV311
R3
511kΩ
2 OV
DC/DC
PWM
CONVERTER
R4
10kΩ
RAMP
VEE
4
7
Short
-48V Pin
-48V
COM
SENSE GATE
6
5
6.2V
C1
10nF
Long
Pin
R5
12.5mΩ
Q1
IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
GND
Application Circuit 10
8
VDD
PWRGD / PWRGD
R1
475kΩ
3
R2
16.2kΩ
+5V
Cload
ENABLE / ENABLE
UV
HV301/
HV311
OV
DC/DC
PWM
CONVERTER
R4
10kΩ
RAMP
7
+5V
Cload
R3
511kΩ
2
1
VEE
4
COM
SENSE GATE
5
6
R6
-48V
C1
10nF
R5
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Q1
IRF530
Application Circuit 11
15
HV301/HV311
Application Information, cont’d.
Reverse Polarity Protection
The UV and OV pins are protected against reverse polarity input
supplies by internal clamping diodes and the fault currents are
sufficiently limited by the impedance of the external resistor
divider, however, a low current diode with a 100V breakdown
rating must be inserted in series with the VDD pin.
This method (shown in Application Circuit 12) will protect the
hotswap control circuit however, due to the intrinsic diode in the
external MOSFET, the load will not be protected from reverse
polarity voltages.
D1
GND
8
VDD
PWRGD / PWRGD
R1
487kΩ
3
1
ENABLE / ENABLE
UV
HV311
R2
6.81kΩ
2
DC/DC
PWM
CONVERTER
OV
R3
9.76kΩ
RAMP
VEE
7
4
+5V
Cload
COM
SENSE GATE
5
6
C1
10nF
-48V
R4
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Q1
IRF530
Application Circuit 12
16
HV301/HV311
Application Information, cont’d.
Redundant Supplies
controllers. The HV311 is ideally suited for such applications
since two or more active low PWRGD signals can be connected
to a single active low ENABLE pin, thus enabling the load as long
as at least one primary power source is available. By adding low
current 100V diodes in series with the VDD pins, full reverse
polarity protection on either power source is also provided
(Application Circuit 13).
Many systems use redundant primary power supplies or battery
backup. When redundant AC powered sources are used they are
generally diode OR’ed to the load on the hot terminal.
For these systems, the use of independent hotswap controllers
is recommended with the diode OR’ing provided after the hotswap
D2
GND
8
VDD
PWRGD 1
R1
487kΩ
3
PS1
UV
HV301/
HV311
R2
6.81kΩ
2 OV
R3
9.76kΩ
RAMP
7
VEE
4
SENSE GATE
5
6
C1
10nF
-48V
D1
R4
60mΩ
Q1
IRF530
D2
GND
8
VDD
PWRGD
R1
487kΩ
3
PS2
ENABLE / ENABLE
UV
R2
6.81kΩ
2
1
HV301/
HV311
OV
DC/DC
PWM
CONVERTER
R3
9.76kΩ
RAMP
7
VEE
4
+5V
Cload
COM
SENSE GATE
5
6
C1
10nF
-48V
D1
R4
60mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Q1
IRF530
Application Circuit 13
17
HV301/HV311
Application Information, cont’d.
Use with Negative Ground
Current Limit Stability (Method 2 (Servo) Only)
Either the HV301 or HV311 may be used with any negative
ground systems where DC/DC PWM Converters have isolated
outputs and their inputs need not be ground referenced
(Application Circuit 14).
The closed loop current mode control system used in the HV301/
HV311 is very stable, especially when driving MOSFETs with
high gate capacitances (CISS). However, a peaking in ILIMIT near
the end of the current limit may be noted with some MOSFETs.
The current control loop can be frequency compensated to
eliminate this peaking by adding a series connected capacitor
and resistor between the gate and source of the external MOSFET.
The recommended starting values for C and R are 10nF and 1K.
These compensation values should be verified by board level
testing, which may yield satisfactory results with reduced component values.
+48V
8
VDD
R1
487kΩ
R2
6.81kΩ
3
2
PWRGD / PWRGD
1
ENABLE/ ENABLE
UV
OV
+5V
Cload
HV301/
HV311
COM
DC/DC PWM CONVERTER
R3
9.76kΩ
RAMP
7
VEE
4
SENSE GATE
5
6
C1
10nF
GND
R4
12.5mΩ
Q1
IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 14
18
HV301/HV311
Application Information cont’d.
Extending Circuit Breaker Delay
delay circuit will also effect the current control feedback loop and
will result in a current overshoot during the external pass device
turn on transition to current limit. If the time delay required for the
Circuit Breaker causes excessive current overshoot during the
turn on transition then the following circuit may be used, where
the RC filter is switched on after the completion of the current
limit control function of the hotswap controller.
Connecting a resistor in series with the SENSE pin and a
capacitor between the SENSE and VEE pins as shown in the
following diagram may be used to extend the Circuit Breaker
delay time beyond the 5µs internally set delay time (Application
Circuit 15).
The time delay achievable by this method is limited since this
8
GND
VDD
R1
487kΩ
R2
6.81kΩ
3
2
PWRGD / PWRGD
1
ENABLE/ ENABLE
UV
HV301/
HV311
OV
DC/DC
PWM
CONVERTER
R3
9.76kΩ
RAMP
VEE
SENSE GATE
7
4
5
-48V
+5V
Cload
C2
R4
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
COM
6
R5
Q1
IRF530
Application Circuit 15
19
HV301/HV311
Application Information cont’d.
Latched Operation
For those applications that need to disable the automatic retry
capability, the following circuit disables the auto retry feature.
GND
8
VDD
R1
487kΩ
R2
6.81kΩ
3
PWRGD / PWRGD
1
ENABLE / ENABLE
UV
HV301 / HV311
2
+5V
Cload
DC/DC
PWM
CONVERTER
OV
COM
R3
9.76kΩ
VEE
4
SENSE GATE
5
RAMP
6
7
2.5MΩ
-48V
Q1
IRF530
R4
12.5mΩ
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when VIN is close to OV.
Application Circuit 17
20
HV301/HV311
Package Dimensions
0.192 ± 0.005
(4.89 ± 0.11)
Inches
D
(Millimeters)
H
0.236 ± 0.008
(5.99 ± 0.20)
H1
E
0.154 ± 0.004
(3.91 ± 0.10)
0.193 ± 0.012
(4.90 ± 0.30)
h
7° (4 PLCS)
0.061 ± 0.008
(1.55 ± 0.20)
0.010 ± 0.002
C
(0.254 ± 0.051)
0.020 ± 0.009
(0.508 ± 0.229)
45°
A
L1
0° – 8°
e
B
A1
0.007 ± 0.003
(0.178 ± 0.076)
0.050
TYP.
(1.20)
0.016 ± 0.002
(0.406 ± 0.05)
L
0.035 ± 0.015
(0.889 ± 0.381)
0.0275 ± 0.0025
(0.698 ± 0.064)
Circled letters (e.g. B denote JEDEC reference dimensons.
08/26/02 rev.11b
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
21
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
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