HI5800 Data Sheet June 1999 File Number 2938.10 12-Bit, 3MSPS, Sampling A/D Converter Features The HI5800 is a monolithic, 12-bit, sampling Analog-toDigital Converter fabricated in the HBC10 BiCMOS process. It is a complete subsystem containing a sample and hold amplifier, voltage reference, two-step subranging A/D, error correction, control logic, and timing generator. The HI5800 is designed for high speed applications where wide bandwidth, accuracy and low distortion are essential. • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . .3MSPS LINEARITY HI5800BID ±1 LSB HI5800JCD HI5800KCD ±2 LSB ±1 LSB HI5800-EV • Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1.0 LSB • Buffered Sample and Hold Amplifier • Precision Voltage Reference • Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . ±2.5V Ordering Information PART NUMBER • 12-Bit, No Missing Codes Over Temperature • 20MHz Input BW Allows Sampling Beyond Nyquist TEMP. RANGE (oC) -40 to 85 40 Ld SBDIP 0 to 70 PKG. NO. PACKAGE 40 Ld SBDIP • Zero Latency/No Pipeline Delay D40.6 Applications D40.6 • High Speed Data Acquisition Systems • Medical Imaging 25 Evaluation Board • Radar Signal Analysis • Document and Film Scanners • Vibration/Waveform Spectrum Analysis • Digital Servo Control Pinout HI5800 (SBDIP) TOP VIEW REFIN 1 40 IRQ ROADJ 2 39 OVF RGADJ 3 38 AVCC AVCC 4 REFOUT 5 VIN 6 AGND 1 7 37 D11 (MSB) 36 D10 35 D9 34 D8 ADJ+ 8 33 DVCC ADJ- 9 32 DGND AVEE 10 31 AGND AVCC 11 30 AVEE AGND 12 29 D7 AVEE 13 28 D6 A0 14 27 D5 CS 15 26 D4 OE 16 25 D3 CONV 17 DVEE 18 24 D2 DGND 19 DVCC 20 22 D0 (LSB) 21 AVCC 23 D1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HI5800 Functional Block Diagram 7-BIT LATCH REFIN REFERENCE 7-BIT LATCH D1 OUTPUT LATCHES REFOUT ERROR CORRECTION D0 (LSB) D2 DIGITAL OUTPUTS D10 D11 (MSB) OVF ADJ+ ADJ- IRQ VIN 7-BIT DAC 7-BIT FLASH S AND H CS CONTROL LOGIC AND TIMING CONV OE AO X32 AVCC AVEE DVCC DVEE AGND RGADJ DGND ROADJ Typical Application Schematic C23 +10µF C22 0.1µF C1 0.01µF HI5800 (22) (LSB) D0 D0 (23) D1 D1 REF_IN (1) (24) D2 D2 REF_OUT (5) (25) D3 D3 (26) D4 D4 (27) D5 D5 (28) D6 D6 (29) D7 D7 (34) D8 D8 (35) D9 (36) D10 D10 AGND (7) AGND (12) AGND (31) DGND (19) DGND (32) VIN VIN (6) CONV D11 (40) IRQ (39) OVF IRQ OVF A0 CS OE (16) A0 (14) CS (15) GND 10µF, 0.1µF, AND 0.01µF CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE D9 (37) (MSB) D11 CONV (17) OE BNC (18) DVEE 0.1µF (33) DVCC (20) 0.1µF + 10µF (4) AVCC (11) AVCC R9 10K RO_ADJ (2) R10 10K RG_ADJ (3) (21) AVCC (38) ADJ+ (8) (10) AVEE (13) (30) AVEE R11 10K ADJ- (9) 2 + 0.1µF 0.1µF 10µF + 10µF + 10µF HI5800 Absolute Maximum Ratings Thermal Information Supply Voltages AVCC or DVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V AVEE or DVEE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V Analog Input Pins Reference Input REFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.75V Signal Input VIN . . . . . . . . . . . . . . . . . . . . . . . . . . ±(REFIN +0.2V) ROADJ , RGADJ , ADJ+, ADJ-. . . . . . . . . . . . . . . . . . . . . VEE to VCC Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VCC Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 40 15 Maximum Junction Temperature SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC Operating Conditions Temperature Range HI5800JCD/KCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC HI5800BID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVCC = +5V, DVCC = +5V, AVEE = -5V, DVEE = -5V; Internal Reference Used, Unless Otherwise Specified PARAMETER TEST CONDITIONS HI5800JCD HI5800KCD, HI5800BID 0oC TO 70oC 0oC TO 70oC -40oC TO 85oC MIN TYP MAX MIN TYP MAX UNITS 12 - - 12 - - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL fS = 3MHz, fIN = 45Hz Ramp - 0.7 ±2 - ±0.5 ±1 LSB Differential Linearity Error, DNL (Guaranteed No Missing Codes) fS = 3MHz, fIN = 45Hz Ramp - ±0.5 ±1 - ±0.3 ±1 LSB Offset Error, VOS (Adjustable to Zero) (Note 8) JCD, KCD - ±2 ±15 - ±2 ±15 LSB BID - - - - ±3 ±15 LSB Full Scale Error, FSE (Adjustable to Zero) (Note 8) JCD, KCD - ±2 ±15 - ±2 ±10 LSB BID - - - - ±3 ±15 LSB DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Throughput Rate No Missing Codes 3.0 - - 3.0 - - MSPS Signal to Noise Ratio (SNR) fS = 3MHz, fIN = 20kHz 66 69 - 68 71 - dB RMS Signal = ------------------------------RMS Noise fS = 3MHz, fIN = 1MHz 65 67 - 67 69 - dB Signal to Noise Ratio (SINAD) fS = 3MHz, fIN = 20kHz 66 68 - 68 71 - dB RMS Signal = -------------------------------------------------------------RMS Noise + Distortion fS = 3MHz, fIN = 1MHz 65 67 - 67 68 - dB Total Harmonic Distortion, THD fS = 3MHz, fIN = 20kHz - -74 -70 - -85 -74 dBc fS = 3MHz, fIN = 1MHz - -70 -68 - -77 -70 dBc Spurious Free Dynamic Range, SFDR fS = 3MHz, fIN = 20kHz 71 76 - 76 86 - dBc fS = 3MHz, fIN = 1MHz 68 72 - 71 77 - dBc Intermodulation Distortion, IMD fS = 3MHz, f1 = 49kHz, f2 = 50kHz (Note 3) - -74 -66 - -79 -70 dBc Differential Gain fS = 1MHz - 0.9 - - 0.9 - % Differential Phase fS = 1MHz - 0.05 - - 0.05 - Degrees Aperture Delay, tAD (Note 3) - 12 20 - 12 20 ns 3 HI5800 Electrical Specifications AVCC = +5V, DVCC = +5V, AVEE = -5V, DVEE = -5V; Internal Reference Used, Unless Otherwise Specified (Continued) HI5800JCD HI5800KCD, HI5800BID 0oC TO 70oC 0oC TO 70oC -40oC TO 85oC MIN TYP MAX MIN TYP MAX UNITS - 10 20 - 10 20 ps Input Voltage Range - ±2.5 ±2.7 - ±2.5 ±2.7 V Input Resistance 1 3 - 1 3 - MΩ PARAMETER TEST CONDITIONS Aperture Jitter, tAJ (Note 3) ANALOG INPUT Input Capacitance - 5 - - 5 - pF Input Current - ±1 ±10 - ±1 ±10 µA Input Bandwidth - 20 - - 20 - MHz 2.450 2.500 2.550 2.470 2.500 2.530 V INTERNAL VOLTAGE REFERENCE Reference Output Voltage, REFOUT (Loaded) Reference Output Current (Note 5) Reference Temperature Coefficient 2 - - 2 - - mA - 20 - - 13 - ppm/ oC REFERENCE INPUT Reference Input Range - 2.5 2.6 - 2.5 2.6 V Reference Input Resistance - 200 - - 200 - Ω 2.0 - - 2.0 - - V DIGITAL INPUTS Input Logic High Voltage, VIH (Note 6) - - 0.8 - - 0.8 V Input Logic Current, IIL Input Logic Low Voltage, VIL VIN = 0V, 5V - ±1 ±10 - ±1 ±10 µA Digital Input Capacitance, CIN VIN = 0V - 5 - - 5 - pF DIGITAL OUTPUTS Output Logic High Voltage, VOH IOUT = -160µA 2.4 4.3 - 2.4 4.3 - V Output Logic Low Voltage, VOL IOUT = 3.2mA - 0.22 0.4 - 0.22 0.4 V Output Logic High Current, IOH -0.160 -6 - -0.160 -6 - mA Output Logic Low Current, IOL 3.2 6 - 3.2 6 - mA - ±1 ±10 - ±1 ±10 µA - 10 - - 10 - pF Output Three-State Leakage Current, IOZ VOUT = 0V, 5V Digital Output Capacitance, COUT TIMING CHARACTERISTICS Minimum CONV Pulse, t1 (Notes 3, 4) 10 - - 10 - - ns CS to CONV Setup Time, t2 (Note 3) 10 - - 10 - - ns CONV to CS Setup Time, t3 (Note 3) 0 - - 0 - - ns Minimum OE Pulse, t4 (Notes 3, 5) 15 - - 15 - - ns CS to OE Setup Time, t5 (Note 3) 0 - - 0 - - ns OE to CS Setup Time, t6 (Note 3) 0 - - 0 - - ns IRQ Delay from Start Convert, t7 (Note 3) IRQ Pulse Width, t8 JCD, KCD BID Minimum Cycle Time for Conversion, t9 10 20 25 10 20 25 ns 190 200 230 190 200 230 ns - - - 180 195 230 ns - 325 333 - 325 333 ns IRQ to Data Valid Delay, t10 (Note 3) -5 0 +5 -5 0 +5 ns Minimum A0 Pulse, t11 (Notes 3, 5) 10 - - 10 - - ns 4 HI5800 Electrical Specifications AVCC = +5V, DVCC = +5V, AVEE = -5V, DVEE = -5V; Internal Reference Used, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS HI5800JCD HI5800KCD, HI5800BID 0oC TO 70oC 0oC TO 70oC -40oC TO 85oC MIN TYP MAX MIN TYP MAX UNITS Data Access from OE Low, t12 (Note 3) 10 18 25 10 18 25 ns LSB, Nibble Delay from A0 High, t13 (Note 3) - 10 20 - 10 20 ns MSB Delay from A0 Low, t14 (Note 3) - 14 20 - 14 20 ns CS to Float Delay, t15 (Note 3) 10 18 25 10 18 25 ns Minimum CS Pulse, t16 (Notes 3, 5) 15 - - 15 - - ns CS to Data Valid Delay, t17 (Note 3) 10 18 25 10 18 25 ns Output Fall 2 Time, tf (Note 3) - 5 20 - 5 20 ns Output Rise Time, tr (Note 3) - 5 20 - 5 20 ns IVCC - 170 220 - 170 220 mA IVEE - 150 190 - 150 190 mA IDVCC - 24 40 - 24 40 mA IDVEE - 2 5 - 2 5 mA Power Dissipation - 1.7 2.2 - 1.7 2.2 W - 0.01 - - 0.01 - %/% POWER SUPPLY CHARACTERISTICS VCC, VEE ±5% PSRR NOTES: 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Parameter guaranteed by design or characterization and not production tested. 4. Recommended pulse width for CONV is 60ns. 5. Recommended minimum pulse width is 25ns. 6. This is the additional current available from the REFOUT pin with the REFOUT pin driving the REFIN pin. 7. The A0 pin VIH at -40oC may exceed 2.0V by up to 0.4V at initial power up. 8. Excludes error due to internal reference temperature drift. Timing Diagrams CONV t1 CS t16 t7 IRQ ACQUIRE N N CONVERSION t8 N - 1 DATA DATA VALID N DATA AO OE t15 D0 - D11, OVF N DATA t12 FIGURE 1. SINGLE SHOT TIMING 5 t17 HI5800 Timing Diagrams (Continued) CS CS t2 t5 t3 CONV t6 OE t1 t4 FIGURE 2A. START CONVERSION SETUP TIME FIGURE 2B. OUTPUT ENABLE SETUP TIME CONV CS t7 N CONVERSION t8 ACQUIRE N IRQ N+1 CONVERSION ACQUIRE N + 1 t10 t9 DATA VALID N DATA N - 1 DATA N + 1 DATA t11 AO OE t13 D4 - D11 t14 D11 - D4 D3 - D0, 0000 D0 - D11, OVF D11 - D4 D11 - D4 N + 1 DATA N DATA t12 FIGURE 3. CONTINUOUS CONVERSION TIMING Typical Performance Curves 80 90 70 80 70 60 60 dB dB 50 40 50 40 30 30 20 20 10 10 0 20K 200K INPUT FREQUENCY (Hz) FIGURE 4. TYPICAL SNR vs INPUT FREQUENCY 6 2M 0 20K 200K INPUT FREQUENCY (Hz) FIGURE 5. TYPICAL THD vs INPUT FREQUENCY 2M HI5800 Typical Performance Curves (Continued) 80 90 70 80 60 70 60 dB dB 50 40 30 50 40 30 20 20 10 10 0 20K 200K 0 20K 2M 200K 2M INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) FIGURE 6. TYPICAL SINAD vs INPUT FREQUENCY FIGURE 7. TYPICAL SFDR vs INPUT FREQUENCY 11.5 12 11.25 10 11.0 ENOB dB 8 6 10.75 10.5 4 10.25 2 10.0 9.75 0 20K 200K 0.5 2M 1.0 1.50 VREF (V) 2.00 2.50 FIGURE 8. TYPICAL EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY FIGURE 9. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE (fS = 3MHz, fIN = 20kHz) 1.0 1.0 0.5 0.5 INL ERROR (LSB) DNL ERROR (LSB) INPUT FREQUENCY (Hz) 0 0 -0.5 -0.5 -1.0 -1.0 0 1000 2000 3000 CODE FIGURE 10. DIFFERENTIAL NON-LINEARITY 7 4000 0 1000 2000 3000 CODE FIGURE 11. INTEGRAL NON-LINEARITY 4000 HI5800 (Continued) 10 0 10 0 -25 -25 OUTPUT LEVEL (dB) OUTPUT LEVEL (dB) Typical Performance Curves -50 -75 -100 -50 -75 -100 -125 -135 -125 -135 0 365K 730K 1.095M 1.46M 0 365K 730K FREQUENCY (Hz) FIGURE 12. FFT SPECTRAL PLOT FOR fIN = 20kHz, fS = 3MHz 1.46M FIGURE 13. FFT SPECTRAL PLOT FOR fIN = 1MHz, fS = 3MHz 10 10 0 0 -25 -25 OUTPUT LEVEL (dB) OUTPUT LEVEL (dB) 1.095M FREQUENCY (Hz) -50 -75 -100 -50 49K 50K -75 -100 -125 -135 -125 -135 0 365K 730K 1.095M 1.46M 0 18.3K FIGURE 14. FFT SPECTRAL PLOT FOR fIN = 2MHz, fS = 3MHz 55K 73.3K 91.6K 110K FIGURE 15. INTERMODULATION DISTORTION PLOT FOR fIN = 49kHz, 50kHz at fS = 3MHz Pin Descriptions PIN # SYMBOL PIN DESCRIPTION 1 REFIN External Reference Input. 2 ROADJ DAC Offset Adjust (Connect to AGND If Not Used). 3 RGADJ DAC Gain Adjust (Connect to AGND If Not Used). 4 AVCC Analog Positive Power Supply, +5V. 5 REFOUT - NC No Connection. 6 VIN Analog Input Voltage. 7 AGND Analog Ground. 8 ADJ+ Sample/Hold Offset Adjust (Connect to AGND If Not Used). 9 ADJ- Sample/Hold Offset Adjust (Connect to AGND If Not Used). Internal Reference Output, +2.5V. 8 36.6K FREQUENCY (Hz) FREQUENCY (Hz) HI5800 Pin Descriptions (Continued) PIN # SYMBOL PIN DESCRIPTION 10 AVEE Analog Negative Power Supply, -5V. 11 AVCC Analog Positive Power Supply, +5V. 12 AGND Analog Ground. 13 AVEE Analog Negative Power Supply, -5V. 14 A0 Output Byte Control Input, active low. When low, data is presented as a 12-bit word or the upper byte (D11 - D4) in 8-bit mode. When high, the second byte contains the lower LSBs (D3 - D0) with 4 trailing zeroes. See Text. 15 CS Chip Select Input, active low. Dominates all control inputs. - NC No Connection. 16 OE Output Enable Input, active low. 17 CONV Convert Start Input. Initiates conversion on the falling edge. If held low, continuous conversion mode overrides and remains in effect until the input goes high. 18 DVEE Digital Negative Power Supply, -5V. 19 DGND Digital Ground. 20 DVCC Digital Positive Power Supply, +5V. 21 AVCC Analog Positive Power Supply, +5V. 22 D0 Data Bit 0, (LSB). 23 D1 Data Bit 1. 24 D2 Data Bit 2. 25 D3 Data Bit 3. - NC No Connection 26 D4 Data Bit 4. 27 D5 Data Bit 5. 28 D6 Data Bit 6. 29 D7 Data Bit 7. 30 AVEE Analog Negative Power Supply, -5V. 31 AGND Analog Ground. 32 DGND Digital Ground. 33 DVCC Digital Positive Power Supply, +5V. 34 D8 Data Bit 8. 35 D9 Data Bit 9. - NC No Connection. 36 D10 Data Bit 10. 37 D11 Data Bit 11 (MSB). 38 AVCC Analog Positive Power Supply, +5V. 39 OVF Overflow Output. Active high when either an overrange or underrange analog input condition is detected. 40 IRQ Interrupt ReQuest Output. Goes low when a conversion is complete. 9 HI5800 Description The HI5800 is a 12-bit, two-step, sampling analog-to-digital converter which uses a subranging technique with digital error correction. As illustrated in the block diagram, it uses a sample and hold front end, 7-bit, R-2R D/A converter which is laser trimmed to 14 bits accuracy, a 7-bit BiCMOS flash converter, precision bandgap reference, digital controller and timing generator, error correction logic, output latches and BiCMOS output drivers. The falling edge of the convert command signal puts the sample and hold (S/H) in the hold mode and the conversion process begins. At this point the Interrupt Request (IRQ) line is set high indicating that a conversion is in progress. The output of the S/H circuit drives the input of the 7-bit flash converter through a switch. After allowing the flash to settle, the intermediate output of the flash is stored in the latches which feed the D/A and error correction logic. The D/A reconstructs the analog signal and feeds the gain amplifier whose summing node subtracts the held signal of the S/H and amplifies the residue by 32. This signal is then switched to the flash for a second pass using the input switch. The output of the second flash conversion is fed directly to the error correction which reconstructs the twelve bit word from the fourteen bit input. The logic also decodes the overflow bit and the polarity of the overflow. The output of the error correction is then gated through the read controller to the output drivers. The data is ready on the bus as soon as the IRQ line goes low. I/O Control Inputs The converter has four active low inputs (CS, CONV, OE and A0) and fourteen outputs (D0 - D11, IRQ and OVF). All inputs and outputs are TTL compatible and will also interface to the newer TTL compatible families. All four inputs are CMOS high input impedance stages and all outputs are BiMOS drivers capable of driving 100pF loads. In order to initiate a conversion or read the data bus, CS should be held low. The conversion is initiated by the falling edge of the CONV command. The OE input controls the output bus directly and is independent of the conversion process. The data on the bus changes just before the IRQ goes low. Therefore if the OE line is held low all the time, the data on the bus will change just before the IRQ line goes low. The byte control signal A0 is also independent of the conversion process and the byte can be manipulated anytime. When A0 is low the 12-bits and overflow word is read on the bus. The bus can also be hooked up such that the upper byte (D11 - D4) is read when A0 is low. When A0 is high, the lower byte (D3 - D0) is output on the same eight pins with trailing zeros. In order to minimize switching noise during a conversion, byte manipulations done using the A0 signal should be done in the single shot mode and A0 should be changed during the acquisition phase. For accuracy, allow sufficient time for settling from any glitches before the next conversion. Once a conversion is started, the converter will complete the conversion and acquisition periods irrespective of the input 10 states. If during these cycles another convert command is issued, it will be ignored until the acquire phase is complete. Stand Alone Operation The converter can be operated in a stand alone configuration with bus inputs controlling the converter. The conversion will be started on the negative edge of the convert (CONV) pulse as long as this pulse is less than the converter throughput rate. If the converter is given multiple convert commands, it will ignore all but the first command until such time when the acquisition period of the next cycle is complete. At this point it will start a new conversion on the first negative edge of the input command. This allows the converter to be synchronized to a multiple of a faster external clock. The new output data of the conversion is available on the same cycle at the negative edge of the IRQ pulse and is valid until the next negative edge of the IRQ pulse. Data may be accessed at any time during these cycles. It should be noted that if the data bus is kept enabled all the time (OE is low), then the data will be updating just before the IRQ goes low. During this time, the data may not be valid for a few nanoseconds. Continuous Convert Mode The converter can be operated at its maximum rate by taking the CONV line low (supplying the first negative edge) and holding it low. This enables the continuous convert mode. During this time, at the end of the internal acquisition period, the converter automatically starts a new conversion. The data will be valid between the IRQ negative edges. Note that there is no pipeline delay on the data. The output data is available during the same cycle as the conversion and is valid until the next conversion ends. This allows data access to both previous and present conversions in the same cycle. When initiating a conversion or a series of conversions, the last signal (CS and CONV) to arrive dominates the function. The same condition holds true for enabling the bus to read the data (CS and OE). To terminate the bus operations, the first signal (CS and OE) to arrive dominates the function. Interrupt Request Output The interrupt request line (IRQ) goes high at the start of each conversion and goes low to indicate the start of the acquisition. During the time that IRQ is high, the internal sample and hold is in hold mode. At the termination of IRQ, the sample and hold switches to acquire mode which lasts approximately 100ns. If no convert command is issued for a period of time, the sample and hold simply remains in acquire mode tracking the analog input signal until the next conversion cycle is initiated. The IRQ line is the only output that is not three-stateable. Analog Input, VIN The analog input of the HI5800 is coupled into the input stage of the Sample and Hold amplifier. The input is a high impedance bipolar differential pair complete with an ESD protection circuit. Typically it has >3MΩ input impedance. With this high input impedance circuit, the HI5800 is easily HI5800 interfaced to any type of op amp without a requirement for a high drive capability. Adequate precautions should be taken while driving the input from high voltage output op amps to ensure that the analog input pin is not overdriven above the specified maximum limits. For a +2.5V reference, the analog input range is ±2.5V. This input range scales with the value of the external reference voltage if the internal reference is not used. For best performance, the analog ground pin next to the analog input should be utilized for signal return. Figures 16 and 17 illustrate the use of an input buffer as a level shifter to convert a unipolar signal to the bipolar input used by the HI5800. Figure 16 is an example of a noninverting buffer that takes a 0 to 2.5V input and shifts it to ±2.5V. The gain can be calculated from: is recommended that the output of the reference be decoupled with good quality capacitors to reduce the high frequency noise. Reference Input, REFIN The converter requires a voltage reference connected to the REFIN pin. This can be the above internal reference or it can be an external reference. It is recommended that adequate high frequency decoupling is provided at the reference input pin in order to minimize overall converter noise. A user trying to provide an external reference to a HI5800 is faced with two problems. First, the drift of the reference over temperature must be very low. Second, it must be capable of driving the 200Ω input impedance seen at the REFIN pin of the HI5800. Figure 18 is a recommended circuit for doing this that is capable of 2ppm/ oC drift over temperature. R1 R2 V OUT = 1 + ------------------------- × V IN – ---------------------- × V OFFSET R1 + R3 ( R1||R3 ) HA5177 HA5002 +15 +15 VOUT VFB R1R3 R1||R 3 = ---------------------R1 + R3 +15V + 10µ 0.1 R2 1kΩ VOFFSET VOUT + HA2841 HI5800 VIN -15V 0.1 FIGURE 16. NON-INVERTING BUFFER Figure 17 is an example of an inverting buffer that level shifts a 0V to 5V input to ±2.5V. Its gain can be calculated from: V OUT = ( – R2 ⁄ R1 ) × V IN – ( R2 ⁄ R3 ) × V OFFSET . R1 R2 VIN 1kΩ 1kΩ +15V VOFFSET - 0.1 2kΩ + HA2841 VOUT HI5800 VIN -15V 0.1 FIGURE 17. INVERTING BUFFER Note that the correct op amp must be chosen in order to not degrade the overall dynamic performance of the circuit. Recommended op amps are called out in the figures. Voltage Reference, REFOUT The HI5800 has a curvature corrected internal band-gap reference generator with a buffer amplifier capable of driving up to 15mA. The band-gap and amplifier are trimmed to give +2.50V. When connected to the reference input pin REFIN , the reference is capable of driving up to 2mA externally. Further loading may degrade the performance of the output voltage. It 11 10 kΩ - 10µ + 0.1 -15 FIGURE 18. EXTERNAL REFERENCE 0.1 VIN RB LOW TC RESISTOR R1 2kΩ C RA HI5800 REFIN 10Ω + -15 +15V R3 2kΩ R3 REF101 Supply and Ground Considerations The HI5800 has separate analog and digital supply and ground pins to help keep digital noise out of the analog signal path. For the best performance, the part should be mounted on a board that provides separate low impedance planes for the analog and digital supplies and grounds. Only connect the two grounds together at one place preferably as close as possible to the part. The supplies should be driven by clean linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the HI5800. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. Also, it is recommended that the turn-on power supply sequencing be such that the analog positive supply, AICC , come up first, followed by the remaining supplies. Refer to the Application Note “Using Intersil High Speed A/D Converters” (AN9214) for additional suggestions to consider when using the HI5800. Error Adjustments For most applications the accuracy of the HI5800 is sufficient without any adjustments. In applications where accuracy is of utmost importance three external adjustments are possible: S/H offset, D/A offset and D/A gain. Figure 19 illustrates the use of external potentiometers to reduce the HI5800 errors to zero. The D/A offset (ROADJ) and S/H offset (ADJ+ and ADJ-) trims adjust the voltage offset of the transfer curve while the HI5800 Typically only one of the offset trimpots needs to be used. The offset should first be adjusted to get code 2048 centered at a desired DC input voltage such as 0V. Next the gain trim can be adjusted by trimming the gain pot until the 4094 to 4095 code transition occurs at the desired voltage (2.500V - 1.5 LSBs for a 2.5V reference). The gain trim can also be done by adjusting the gain pot until the code 0 to 1 transition occurs at a particular voltage (-2.5V + 0.5 LSBs for a 2.5V reference). If a nonzero offset is needed, then the offset pot can be adjusted after the gain trim is finished. The gain trim is simplified if an offset trim to zero is done first with a nonzero offset trim done after the gain trim is finished. The D/A offset and S/H offset trimpots have an identical effect on the converter except that the S/H offset is a finer resolution trim. The D/A offset and D/A gain typically have an adjustment range of ±30 LSBs and the S/H offset typically has an adjustment range of ±20 LSBs. D/A gain trim (RGADJ) adjusts the tilt of the transfer curve around the curve midpoint (code 2048). The 10kΩ potentiometers can be installed to achieve the desired adjustment in the following manner. VCC ROADJ 10kΩ 10kΩ RGADJ VEE ADJ+ 10kΩ VEE ADJ- FIGURE 19. D/A OFFSET, D/A GAIN AND S/H OFFSET ADJUSTMENTS TABLE 1. I/O TRUTH TABLE INPUTS OUTPUT CS CONV OE A0 IRQ 1 X X X X No operation. FUNCTION 0 0 X X X Continuous convert mode. 0 X 0 0 X Outputs all 12-bits and OVF or upper byte D11 - D4 in 8 bit mode. 0 X 0 1 X In 8-bit mode, outputs lower LSBs D3 - D0 followed by 4 trailing zeroes and OVF (See text). 0 1 X X 0 Converter is in acquisition mode. 0 X X X 1 Converter is busy doing a conversion. 0 X 1 X X Data outputs and OVF in high impedance state. X’s = Don’t Care TABLE 2. A/D OUTPUT CODE TABLE CODE DESCRIPTION OUTPUT DATA (OFFSET BINARY) LSB = 2 (REFIN) 4096 (NOTE) INPUT VOLTAGE REFIN = 2.5V (V) OVF D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ≥+FS (Full Scale) ≥ +2.5000 1 1 1 1 1 1 1 1 1 1 1 1 1 +FS - 1 LSB +2.49878 0 1 1 1 1 1 1 1 1 1 1 1 1 +3/4 FS +1.8750 0 1 1 1 0 0 0 0 0 0 0 0 0 MSB LSB +1/2 FS +1.2500 0 1 1 0 0 0 0 0 0 0 0 0 0 +1 LSB +0.00122 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0.0000 0 1 0 0 0 0 0 0 0 0 0 0 0 -1 LSB -0.00122 0 0 1 1 1 1 1 1 1 1 1 1 1 -1/2 FS -3/4 FS -1.2500 0 0 1 0 0 0 0 0 0 0 0 0 0 -1.8750 0 0 0 1 0 0 0 0 0 0 0 0 0 -FS + 1 LSB -2.49878 0 0 0 0 0 0 0 0 0 0 0 0 1 ≤-FS ≤ -2.5000 1 0 0 0 0 0 0 0 0 0 0 0 0 NOTE: The voltages listed above represent the ideal center of each output code shown as a function of the reference voltage. 12 HI5800 If no external adjustments are required the following pins should be connected to analog ground (AGND) for optimum performance: ROADJ , RGADJ , ADJ+, and ADJ-. Typical Application Schematic A typical application schematic diagram for the HI5800 is shown with the block diagram. The adjust pins are shown with 10kΩ potentiometers used for gain and offset adjustments. These potentiometers may be left out and the respective pins should be connected to ground for best untrimmed performance. Signal-to-Noise Ratio (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: Definitions Static Performance Definitions Offset, Full scale, and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus full scale values. The results are all displayed in LSBs. Offset Error (VOS) The first code transition should occur at a level 1/2 LSB above the negative full scale. Offset is defined as the deviation of the actual code transition from this point. Note that this is adjustable to zero. Full Scale Error (FSE) The last code transition should occur for a analog input that is 11/2 LSBs below positive full scale. Full scale error is defined as the deviation of the actual code transition from this point. ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5dB. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. Intermodulation Distortion (IMD) Integral Linearity Error (INL) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present on the inputs. The ratio of the measured signal to the distortion terms is calculated. The IMD products used to calculate the total distortion are (f2-f1), (f2+f1), (2f1-f2), (2f1+f2), (2f2-f1), (2f2+f1), (3f1-f2), (3f1+f2), (3f2-f1), (3f2+f1), (2f2-2f1), (2f2+2f1), (2f1), (2f2), (2f1), (2f2), (4f1), (4f2). The data reflects the sum of all the IMD products. INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Full Power Input Bandwidth Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed for no missing codes over all temperature ranges. Power Supply Rejection (PSRR) Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error is noted. The number reported is the percent change in these parameters versus full scale divided by the percent change in the supply. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5800. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. Distortion results are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. 13 Full power input bandwidth is the frequency at which the amplitude of the fundamental of the digital output word has decreased 3dB below the amplitude of an input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. HI5800 Die Characteristics DIE DIMENSIONS: PASSIVATION: 202 mils x 283 mils x 19 mils Type: Sandwich Passivation - Nitride + Undoped Si Glass (USG) Thickness: Nitride - 4KÅ, USG - 8KÅ, Total - 12kÅ ±2kÅ METALLIZATION: Metal 1: Type: AlSiCu, Thickness: 6kÅ +1500A/-750Å Metal 2: Type: AlSiCu, Thickness: 16kÅ +2500A/-1100Å TRANSISTOR COUNT: 10K SUBSTRATE POTENTIAL (POWERED UP): VEE Metallization Mask Layout D10 D11 (MSB) AVCC OVF IRQ REF_IN RO_ADJ RG_ADJ REF_OUT AVCC AVCC REF_OUT HI5800 VIN AGND D9 AGND ADJ+ D8 ADJAVEE AVEE DVCC AVCC DGND AVCC AGND VEE AGND AVEE D7 AVEE D6 A0 D5 CS 14 D3 D2 D1 D6 (LSB) AVCC DVCC DVCC DGND DVEE DGND CONV OE D4 HI5800 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) D40.6 MIL-STD-1835 CDIP2-T40 (D-5, CONFIGURATION C) 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE LEAD FINISH c1 -A- -DBASE METAL E b1 M (b) M -Bbbb S C A - B S SECTION A-A D S D BASE PLANE Q S2 -C- SEATING PLANE A L S1 eA A A b2 b e eA/2 c aaa M C A - B S D S ccc M C A - B S D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. SYMBOL MIN MILLIMETERS MAX MIN MAX NOTES A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 2.096 - 53.24 4 E 0.510 0.620 15.75 4 e 12.95 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N 40 40 8 Rev. 0 4/94 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. 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