Numonyx M29W320FBB80N3F 16 mbit or 32 mbit (x 8 or x 16, boot block) 3 v supply flash memory Datasheet

M29W160FT M29W160FB
M29W320FT M29W320FB
16 Mbit or 32 Mbit (x 8 or x 16, boot block)
3 V supply Flash memory
Features
■
Supply voltage
– VCC = 2.5 V to 3.6 V (access time: 80 ns) or
2.7 to 3.6 V (access time: 70 ns) for
Program, Erase and Read
– VPP = 12 V for Fast Program (optional,
available in the M29W320FT/B only)
■
Access time: 70, 80 ns
■
Programming time
– 10 µs per byte/word typical
■
Memory organization:
– M29W160FT/B: 35 blocks including 1 boot
block (top or bottom location), 2 parameter
blocks and 32 main blocks
– M29W320FT: 67 blocks including 1 boot
block (top or bottom location), 2 parameter
blocks and 64 main blocks
■
Program/Erase controller
– Embedded byte/word program algorithms
■
Erase Suspend and Resume modes
– Read and Program another block during
Erase Suspend
■
Unlock Bypass Program command
– Faster production/batch programming
■
VPP/WP pin for Fast program and Write Protect
(available in the M29W320FT/B only)
■
Temporary block unprotection mode
■
Common Flash interface
– 64 bit security code
■
Low power consumption
– Standby and Automatic Standby
■
100,000 Program/Erase cycles per block
March 2008
TSOP48 (N)
12 x 20 mm
FBGA
TFBGA48 (ZA)
6 x 8 mm
■
Electronic signature
– Manufacturer code: 0020h
– Top device codes
M29W160FT: 22C4h
M29W320FT: 22CAh
– Bottom device codes
M29W160FB: 2249h
M29W320FB: 22CBh
■
Automotive device grade 3:
– Temperature: –40 to 125 °C
– Automotive grade certified
■
TSOP48 package is ECOPACK®
Rev 3
1/57
www.numonyx.com
1
Contents
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
2/57
2.1
Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Data input/output or Address input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 12
2.5
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8
VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9
Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10
Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11
Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.13
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
Block protection and Blocks unprotection . . . . . . . . . . . . . . . . . . . . . . . . 16
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M29W160FT, M29W160FB, M29W320FT, M29W320FB
5
Contents
4.5
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.9
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.11
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4
Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5
Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10
9.1
Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2
In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3/57
List of tables
M29W160FT, M29W160FB, M29W320FT, M29W320FB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/57
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program, Erase times and Program, Erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 24
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TSOP48 – 48 lead Plastic Thin Small Outline, 12 × 20 mm, package mechanical data . . 36
TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical data . . . . . . . 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Top boot block addresses, M29W160FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Bottom boot block addresses, M29W160FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Top boot block addresses, M29W320FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bottom boot block addresses, M29W320FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
M29W160FT, M29W160FB, M29W320FT, M29W320FB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
M29W160FT/B block addresses (x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M29W320FT/B block addresses (x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M29W160FT/B block addresses (x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M29W320FT/B block addresses (x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Accelerated Program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TSOP48 – 48 lead Plastic Thin Small Outline, 12 × 20 mm, package outline . . . . . . . . . . 36
TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package outline . . . . . . . . . . . . . . . 37
Programmer equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
In-system equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
In-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5/57
Description
1
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Description
The M29W160FT/B and M29W320FT/B are 16 Mbit (2 Mb x 8 or 1 Mb x 16) and 32 Mbit
(4 Mb x 8 or 2 Mb x 16) non-volatile memories, respectively. They can be read, erased and
reprogrammed. These operations can be performed using a single low voltage supply (2.5
to 3.6 V or 2.7 to 3.6 V for access time of 80 ns and 70 ns, respectively). On power-up the
memory defaults to its Read mode where it can be read in the same way as a ROM or
EPROM.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the command interface of the memory. An on-chip
Program/Erase controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see Figures 4, 5, 6 and 7, Block
addresses. The first or last 64 Kbytes have been divided into four additional blocks. The
16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the
two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining
32 Kbyte block is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12 x 20 mm) and TFBGA48 (0.8 mm pitch) packages.
The memory is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
6/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 1.
Description
Logic diagram
VCC VPP/WP(1)
15
A0-Amax(2)
W
E
G
DQ0-DQ14
M29W160FT
M29W160FB
M29W320FT
M29W320FB
DQ15A–1
RB
RP
BYTE
VSS
AI13246
1. The VPP/WP pin is available in the M29W320FT and M29W320FB only.
2. Amax is equal to A19 in the M29W160FT/B, and to A20 in the M29W320FT/B.
Table 1.
Signal names
Signal name
Function
Direction
A0-Amax(1)
Address inputs
Inputs
DQ0-DQ7
Data inputs/outputs
I/O
DQ8-DQ14
Data inputs/outputs
I/O
DQ15A–1
Data input/output or Address input
I/O
E
Chip Enable
Input
G
Output Enable
Input
W
Write Enable
Input
RP
Reset/Block Temporary Unprotect
Input
RB
Ready/Busy output
Output
BYTE
Byte/word Organization Select
Input
VPP/WP(2)
VPP/Write Protect
VCC
Supply voltage
VSS
Ground
NC
Not connected internally
1. Amax is equal to A19 in the M29W160FT/B, and to A20 in the M29W320FT/B.
2. The VPP/WP pin is available in the M29W320FT and M29W320FB only.
7/57
Description
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 2.
TSOP connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20/NC(1)
W
RP
NC
VPP/WP/NC(2)
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
M29W160FT
M29W160FB
12
37
M29W320FT
13 M29W320FB 36
24
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI13247
1. Pin 10 is NC (not connected) in the M29W160FT/B, and it is connected to A20 in the M29W320FT/B.
2. Pin 14 is NC (not connected) in the M29W160FT/B, and it is connected to the VPP/WP pin in the
M29W320FT/B.
8/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 3.
Description
TFBGA connections (top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP/
WP(1)
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
A20(2)
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI02985c
1. The above figure gives the TFBGA connections for the M29W320FT/B. On the M29W160FT/B, the
VPP/WP pin is NC (not connected).
2. The above figure gives the TFBGA connections for the M29W320FT/B. On the M29W160FT/B, A20 is NC
(not connected).
9/57
Description
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 4.
M29W160FT/B block addresses (x 8)
M29W160FT
Top Boot block addresses (x 8)
M29W160FB
Bottom Boot block addresses (x 8)
1FFFFFh
1FFFFFh
16 Kbyte
64 Kbyte
1FC000h
1FBFFFh
1F0000h
1EFFFFh
8 Kbyte
64 Kbyte
1FA000h
1F9FFFh
1E0000h
Total of 31
64 Kbyte blocks
8 Kbyte
1F8000h
1F7FFFh
32 Kbyte
1F0000h
1EFFFFh
01FFFFh
64 Kbyte
64 Kbyte
1E0000h
010000h
00FFFFh
32 Kbyte
Total of 31
64 Kbyte blocks
01FFFFh
008000h
007FFFh
8 Kbyte
006000h
005FFFh
64 Kbyte
8 Kbyte
010000h
00FFFFh
004000h
003FFFh
64 Kbyte
16 Kbyte
000000h
000000h
AI12390b
1. Also see Appendix A, Tables 19 and 20 for a full listing of the block addresses.
Figure 5.
M29W320FT/B block addresses (x 8)
M29W320FT
Top Boot block addresses (x 8)
M29W320FB
Bottom Boot block addresses (x 8)
3FFFFFh
3FFFFFh
16 Kbyte
64 Kbyte
3FC000h
3FBFFFh
3F0000h
3EFFFFh
8 Kbyte
64 Kbyte
3FA000h
3F9FFFh
3E0000h
Total of 63
64 Kbyte blocks
8 Kbyte
3F8000h
3F7FFFh
32 Kbyte
3F0000h
3EFFFFh
01FFFFh
64 Kbyte
64 Kbyte
3E0000h
010000h
00FFFFh
32 Kbyte
Total of 63
64 Kbyte blocks
01FFFFh
008000h
007FFFh
8 Kbyte
006000h
005FFFh
64 Kbyte
010000h
00FFFFh
8 Kbyte
004000h
003FFFh
64 Kbyte
000000h
16 Kbyte
000000h
AI13248b
1. Also see Appendix A, Tables 21 and 22 for a full listing of the block addresses.
10/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 6.
Description
M29W160FT/B block addresses (x 16)
M29W160FT
Top Boot block addresses (x 16)
M29W160FB
Bottom Boot block addresses (x 16)
FFFFFh
FFFFFh
8 Kword
32 Kword
FE000h
FDFFFh
F8000h
F7FFFh
4 Kword
32 Kword
FD000h
FCFFFh
F0000h
Total of 31
32 Kword blocks
4 Kword
FC000h
FBFFFh
16 Kword
F8000h
F7FFFh
0FFFFh
32 Kword
32 Kword
F0000h
08000h
07FFFh
16 Kword
Total of 31
32 Kword blocks
0FFFFh
04000h
03FFFh
4 Kword
03000h
02FFFh
32 Kword
4 Kword
08000h
07FFFh
02000h
01FFFh
32 Kword
8 Kword
00000h
00000h
AI12391b
1. Also see Appendix A, Tables 19 and 20 for a full listing of the block addresses.
Figure 7.
M29W320FT/B block addresses (x 16)
M29W320FT
Top Boot block addresses (x 16)
M29W320FB
Bottom Boot block addresses (x 16)
1FFFFFh
1FFFFFh
8 Kword
32 Kword
1FE000h
1FDFFFh
1F8000h
1F7FFFh
4 Kword
32 Kword
1FD000h
1FCFFFh
1F0000h
Total of 63
32 Kword blocks
4 Kword
1FC000h
1FBFFFh
16 Kword
1F8000h
1F7FFFh
00FFFFh
32 Kword
32 Kword
1F0000h
008000h
007FFFh
16 Kword
Total of 63
32 Kword blocks
00FFFFh
004000h
003FFFh
4 Kword
003000h
002FFFh
32 Kword
008000h
007FFFh
4 Kword
002000h
001FFFh
32 Kword
000000h
8 Kword
000000h
AI13250b
1. Also see Appendix A, Tables 21 and 22 for a full listing of the block addresses.
11/57
Signal descriptions
2
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-Amax)
Amax is equal to A19 in the M29W160FT/B, and to A20 in the M29W320FT/B.
The Address inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the command
interface of the Program/Erase controller.
2.2
Data inputs/outputs (DQ0-DQ7)
The Data inputs/outputs output the data stored at the selected address during a Bus Read
operation. During Bus Write operations they represent the commands sent to the command
interface of the Program/Erase controller.
2.3
Data inputs/outputs (DQ8-DQ14)
The Data inputs/outputs output the data stored at the selected address during a Bus Read
operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.
2.4
Data input/output or Address input (DQ15A-1)
When BYTE is High, VIH, this pin behaves as a Data input/output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of
the word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data input/output to include this pin when BYTE is High and
references to the Address inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
12/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
2.7
Signal descriptions
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s command interface.
2.8
VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin is only available in the M29W320FT/B devices. It provides two
functions. The VPP function allows the memory to use an external high voltage power supply
to reduce the time required for Unlock Bypass Program operations. The Write Protect
function provides a hardware method of protecting the 16 Kbyte Boot Block. The VPP/Write
Protect pin must not be left floating or unconnected.
When VPP/Write Protect is Low, VIL, the memory protects the 16 Kbyte Boot Block; Program
and Erase operations in this block are ignored while VPP/Write Protect is Low.
When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status
of the 16 Kbyte boot block. Program and Erase operations can now modify the data in the 16
Kbyte Boot Block unless the block is protected using Block Protection.
When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock
Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes.
During Unlock Bypass Program operations the memory draws IPP from the pin to supply the
programming circuits. See the description of the Unlock Bypass command in the command
interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than
tVHVPP, see Figure 16.
Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
A 0.1 µF capacitor should be connected between the VPP/Write Protect pin and the VSS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, IPP.
2.9
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all blocks that have been protected.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last.
See Section 2.10: Ready/Busy Output (RB), Table 15 and Figure 15., Reset/Temporary
Unprotect AC characteristics for more details.
Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
13/57
Signal descriptions
2.10
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 15 and Figure 15: Reset/Block Temporary Unprotect
AC waveforms.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11
Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus
modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8bit mode, when it is High, VIH, the memory is in 16-bit mode.
2.12
VCC supply voltage
The VCC supply voltage supplies the power for all operations (Read, Program, Erase etc.).
The command interface is disabled when the VCC supply voltage is less than the Lockout
voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data
during power up, power down and power surges. If the Program/Erase controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1 µF capacitor should be connected between the VCC supply voltage pin and the VSS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, ICC3.
2.13
VSS ground
The VSS ground is the reference for all voltage measurements. The two VSS pins of the
device must be connected to the system ground.
14/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
3
Bus operations
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 2. and Table 3., Bus
operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the command
interface. A valid Bus Read operation involves setting the desired address on the Address
inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The Data inputs/outputs will output the value, see Figure 12: Read mode
AC waveforms, and Table 12: Read AC characteristics, for details of when the output
becomes valid.
3.2
Bus Write
Bus Write operations write to the command interface. A valid Bus Write operation begins by
setting the desired address on the Address inputs. The Address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure 13. and Figure 14., Write AC waveforms,
and Tables 13 and 14, Write AC characteristics, for details of the timing requirements.
3.3
Output Disable
The Data inputs/outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to
the Standby supply current, ICC2, Chip Enable should be held within VCC ± 0.2 V. For the
Standby current level see Table 11: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
supply current, ICC3, for Program or Erase operations until the operation completes.
3.5
Automatic Standby
If CMOS levels (VCC ± 0.2 V) are used to drive the bus and the bus is inactive for 150 ns or
more the memory enters Automatic Standby where the internal supply current is reduced to
the Standby supply current, ICC2. The Data inputs/outputs will still output data if a Bus Read
operation is in progress.
15/57
Bus operations
3.6
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Special bus operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.7
Electronic signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2.
and Table 3, Bus operations.
3.8
Block protection and Blocks unprotection
Each block can be separately protected against accidental Program or Erase. Protected
blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment and the other for in-system use. Block Protect and Blocks
Unprotect operations are described in Appendix C.
Table 2.
Bus operations, BYTE = VIL(1)
Operation
G
Address inputs
DQ15A–1, A0-Amax
W
Data inputs/outputs
DQ14-DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell address
Hi-Z
Data output
Bus Write
VIL
VIH
VIL
Command address
Hi-Z
Data input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read manufacturer
code
VIL
VIL
VIH
A0=VIL, A1=VIL, A9=VID,
others VIL or VIH
Hi-Z
20h
VIH
A0=VIH, A1=VIL,
A9=VID, others VIL or
VIH
Hi-Z
C4h (M29W160FT)
CAh (M29W320FT)
49h (M29W160FB)
CBh (M29W320FB)
Output Disable
Read device code
1. X = VIL or VIH.
16/57
E
VIL
VIL
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 3.
Bus operations
Bus operations, BYTE = VIH(1)
Operation
Address inputs
A0-Amax
Data inputs/outputs
DQ15A–1, DQ14-DQ0
E
G
W
Bus Read
VIL
VIL
VIH
Cell address
Bus Write
VIL
VIH
VIL
Command address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read manufacturer
code
VIL
VIL
VIH
A0=VIL, A1=VIL, A9=VID,
others VIL or VIH
VIH
A0=VIH, A1=VIL,
A9=VID, others VIL or
VIH
Output Disable
Read device code
VIL
VIL
Data output
Data input
0020h
22C4h (M29W160FT)
22CAh (M29W320FT)
2249h (M29W160FB)
22CBh (M29W320FB)
1. X = VIL or VIH.
17/57
Command interface
4
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Command interface
All Bus Write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being
used, for a summary of the commands.
4.1
Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register.
Either one or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to Read mode. Once the program or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an Erase operation when issued while in Erase Suspend.
4.2
Auto Select command
The Auto Select command is used to read the manufacturer code, the device code and the
Block Protection status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset
commands are accepted in Auto Select mode, all other commands are ignored.
From the Auto Select mode the manufacturer code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The
manufacturer code for Numonyx is 0020h.
The device code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The
other address bits may be set to either VIL or VIH.
The Block Protection status of each block can be read using a Bus Read operation with
A0 = VIL, A1 = VIH, and A12-Amax specifying the address of the block. The other address
bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on
Data inputs/outputs DQ0-DQ7, otherwise 00h is output.
18/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
4.3
Command interface
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data, and starts the Program/Erase controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 6. Bus Read operations during the program operation will output the Status Register
on the Data inputs/outputs. See the section on the Status Register for more details.
After the program operation has completed the memory returns to the Read mode, unless
an error has occurred. When an error occurs the memory continues to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.4
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the access time to the device is long (as with
some EPROM programmers) considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.
4.5
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at
a time. The command requires two Bus Write operations, the final write operation latches
the address and data, and starts the Program/Erase controller.
The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. A protected block cannot be
programmed; the operation cannot be aborted and the Status Register is read. Errors must
be reset using the Read/Reset command, which leaves the device in Unlock Bypass mode.
See the Program command for details on the behavior.
4.6
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass mode.
19/57
Command interface
4.7
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase command and start the Program/Erase controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100 µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands. It is not possible to issue
any command to abort the operation. Typical chip erase times are given in Table 6. All Bus
Read operations during the Chip Erase operation will output the Status Register on the Data
inputs/outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.8
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase controller about 50 µs after the
last Bus Write operation. Once the Program/Erase controller starts it is not possible to select
any more blocks. Each additional block must therefore be selected within 50 µs of the last
block. The 50 µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register section for details
on how to identify if the Program/Erase controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100 µs, leaving the data unchanged. No error condition
is given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 6. All Bus Read operations
during the Block Erase operation will output the Status Register on the Data inputs/outputs.
See the section on the Status Register for more details.
After the Block Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Block Erase command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
20/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
4.9
Command interface
Erase Suspend command
The Erase Suspend command may be used to temporarily suspend a Block Erase operation
and return the memory to Read mode. The command requires one Bus Write operation.
The Program/Erase controller will suspend within the Erase Suspend Latency time (refer to
Table 6 for value) of the Erase Suspend command being issued. Once the Program/Erase
controller has stopped the memory will be set to Read mode and the Erase will be
suspended. If the Erase Suspend command is issued during the period when the memory is
waiting for an additional block (before the Program/Erase controller starts) then the Erase is
suspended immediately and will start immediately when the Erase Resume command is
issued. It is not possible to select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
4.10
Erase Resume command
The Erase Resume command must be used to restart the Program/Erase controller from
Erase Suspend. An erase can be suspended and resumed more than once.
4.11
Read CFI Query command
The Read CFI Query command is used to read data from the Common Flash interface (CFI)
memory area. This command is valid when the device is in the Read Array mode, or when
the device is in Auto Select mode.
One Bus Write cycle is required to issue the Read CFI Query command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
interface memory area.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Auto Select mode). A second Read/Reset command would be needed
if the device is to be put in the Read Array mode from Auto Select mode.
See Appendix B, Tables 23, 24, 25, 26, 27 and 28 for details on the information contained in
the common flash interface (CFI) memory area.
21/57
Command interface
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 4.
Commands, 16-bit mode, BYTE = VIH
Command
Length
Bus Write operations(1) (2) (3)
1st
2nd
3rd
4th
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
X
F0
3
555
AA
2AA
55
X
F0
Auto Select
3
555
AA
2AA
55
555
90
Program(6)
4
555
AA
2AA
55
555
A0
Unlock
Bypass(7)
3
555
AA
2AA
55
555
20
Unlock Bypass
Program(6)
2
X
A0
PA
PD
Unlock Bypass
Reset(8)
2
X
90
X
00
Chip Erase(6)
6
555
AA
2AA
55
555
Block Erase(6)
6+
555
AA
2AA
55
555
Erase
Suspend(9)
1
X
B0
Erase
Resume(10)
1
X
30
Read CFI
Query(11)
1
55
98
Read/Reset(4)
(5)
PA
PD
80
555
AA
2AA
55
555
10
80
555
AA
2AA
55
BA
30
1. X don’t care, PA Program Address, PD Program Data, BA any address in the block.
2. All values in the table are in hexadecimal.
3. The command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
4. After a Read/Reset command, read the memory as normal until another command is issued.
5. After an Auto Select command, read manufacturer ID, device ID or Block Protection status.
6. After this command read the Status Register until the Program/Erase controller completes and the memory
returns to Read mode. Add additional blocks during Block Erase command with additional Bus Write
operations until Timeout bit is set.
7. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
8. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
9. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and
Program commands on non-erasing blocks as normal.
10. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until
the Program/Erase controller completes and the memory returns to Read mode.
11. Command is valid when device is ready to read array data or when device is in Auto Select mode.
22/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 5.
Command interface
Commands, 8-bit mode, BYTE = VIL
Command
Length
Bus Write operations(1) (2) (3)
1st
2nd
3rd
4th
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
X
F0
3
AAA
AA
555
55
X
F0
3
AAA
AA
555
55
AAA
90
4
AAA
AA
555
55
AAA
A0
Unlock Bypass
3
AAA
AA
555
55
AAA
20
Unlock Bypass
Program(6)
2
X
A0
PA
PD
Unlock Bypass
Reset(8)
2
X
90
X
00
Chip Erase(6)
6
AAA
AA
555
55
AAA
555
55
AAA
Read/Reset(4)
(5)
Auto Select
Program(6)
(7)
(6)
6+ AAA
AA
Suspend(9)
1
X
B0
(10)
Erase Resume
1
X
30
Read CFI
Query(11)
1
AA
98
Block Erase
Erase
PA
PD
80
AAA
AA
555
55
AAA
10
80
AAA
AA
555
55
BA
30
1. X don’t care, PA Program Address, PD Program Data, BA any address in the block.
2. All values in the table are in hexadecimal.
3. The command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8DQ14 and DQ15 are don’t care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
4. After a Read/Reset command, read the memory as normal until another command is issued.
5. After an Auto Select command, read manufacturer ID, device ID or Block Protection status.
6. After this command read the Status Register until the Program/Erase controller completes and the memory
returns to Read mode. Add additional blocks during Block Erase command with additional Bus Write
operations until Timeout bit is set.
7. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
8. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
9. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and
Program commands on non-erasing blocks as normal.
10. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until
the Program/Erase controller completes and the memory returns to Read mode.
11. Command is valid when device is ready to read array data or when device is in Auto Select mode.
23/57
Command interface
Table 6.
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Program, Erase times and Program, Erase endurance cycles
Parameter
Min
Typ(1) (2)
Max(2)
Unit
29
120(3)
s
Chip Erase
Block Erase (64 Kbytes)
0.8
6
(4)
(4)
Erase Suspend Latency time
20
25
Program (byte or word)
13
200(3)
26
(3)
Chip Program (byte by byte)
Chip Program (word by word)
Program/Erase cycles (per block)
Data retention
13
120
(3)
60
µs
µs
s
s
100,000
cycles
20
years
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000
program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC.
24/57
s
M29W160FT, M29W160FB, M29W320FT, M29W320FB
5
Status Register
Status Register
Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.
The bits in the Status Register are summarized in Table 7: Status Register bits.
5.1
Data Polling bit (DQ7)
The Data Polling bit can be used to identify whether the Program/Erase controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.
In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the
Program/Erase controller has suspended the Erase operation.
Figure 8: Data polling flowchart, gives an example of how to use the Data Polling bit. A Valid
address is the address being programmed or an address within the block being erased.
5.2
Toggle bit (DQ6)
The Toggle bit can be used to identify whether the Program/Erase controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
bit is output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle bit will output when addressing a cell within a block
being erased. The Toggle bit will stop toggling when the Program/Erase controller has
suspended the Erase operation.
If any attempt is made to erase a protected block, the operation is aborted, no error is
signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a
protected block or a suspended block, the operation is aborted, no error is signalled and
DQ6 toggles for approximately 1µs.
Figure 9: Data toggle flowchart, gives an example of how to use the Data Toggle bit.
25/57
Status Register
5.3
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Error bit (DQ5)
The Error bit can be used to identify errors detected by the Program/Erase controller. The
Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’
5.4
Erase Timer bit (DQ3)
The Erase Timer bit can be used to identify the start of Program/Erase controller operation
during a Block Erase command. Once the Program/Erase controller starts erasing the Erase
Timer bit is set to ’1’. Before the Program/Erase controller starts the Erase Timer bit is set to
’0’ and additional blocks to be erased may be written to the command interface. The Erase
Timer bit is output on DQ3 when the Status Register is read.
5.5
Alternative Toggle bit (DQ2)
The Alternative Toggle bit can be used to monitor the Program/Erase controller during Erase
operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read.
During Chip Erase and Block Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error bit to be set the Alternative Toggle bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle bit does not change if
the addressed block has erased correctly.
26/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 7.
Status Register
Status Register bits(1)
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any address
DQ7
Toggle
0
–
–
0
Program During
Erase Suspend
Any address
DQ7
Toggle
0
–
–
0
Program Error
Any address
DQ7
Toggle
1
–
–
0
Chip Erase
Any address
0
Toggle
0
1
Toggle
0
Block Erase
before timeout
Erasing block
0
Toggle
0
0
Toggle
0
Non-erasing block
0
Toggle
0
0
No Toggle
0
Erasing block
0
Toggle
0
1
Toggle
0
Non-erasing block
0
Toggle
0
1
No Toggle
0
Erasing block
1
No Toggle
0
–
Toggle
1
Block Erase
Erase Suspend
Non-erasing block
Data read as normal
1
Good block address
0
Toggle
1
1
No Toggle
0
Faulty block address
0
Toggle
1
1
Toggle
0
Erase Error
1. Unspecified data bits should be ignored.
Figure 8.
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI03598
27/57
Status Register
Figure 9.
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Data toggle flowchart
START
READ DQ6
READ
DQ5 & DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
TWICE
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI01370C
28/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
6
Maximum rating
Maximum rating
Stressing the device above the rating listed in Table 8: Absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
operating sections of this specification is not implied. Refer also to the Numonyx SURE
Program and other relevant quality documents.
Table 8.
Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
Ambient temperature grade 3
–40
125
°C
TBIAS
Temperature under bias
–50
125
°C
TSTG
Storage temperature
–65
150
°C
–0.6
VCC+0.6
V
TA
(1)(2)
VIO
Input or output voltage
VCC
Supply voltage
–0.6
4
V
VID
Identification voltage
–0.6
13.5
V
1. Minimum voltage may undershoot to –2 V during transition and for less than 20 ns during transitions.
2. Maximum voltage may overshoot to VCC +2 V during transition and for less than 20 ns during transitions.
29/57
DC and AC parameters
7
M29W160FT, M29W160FB, M29W320FT, M29W320FB
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 9: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 9.
Operating and AC measurement conditions
M29W160FT/B, M29W320FT/B
Parameter
70
80
Min
Max
Min
Max
VCC supply voltage
2.7
3.6
2.5
3.6
V
Ambient operating temperature (grade 3)
–40
125
–40
125
°C
Load capacitance (CL)
30
30
Input rise and fall times
10
Input Pulse voltages
Input and output timing ref. voltages
pF
10
ns
0 to VCC
0 to VCC
V
VCC/2
VCC/2
V
Figure 10. AC measurement I/O waveform
VCC
VCC/2
0V
AI04498
Figure 11. AC measurement load circuit
VCC
VCC
25kΩ
DEVICE
UNDER
TEST
0.1µF
CL includes JIG capacitance
30/57
Unit
CL
25kΩ
AI04499
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Device capacitance(1)
Table 10.
Symbol
CIN
COUT
DC and AC parameters
Parameter
Input capacitance
Output capacitance
Test Condition
Min
Max
Unit
VIN = 0 V
6
pF
VOUT = 0 V
12
pF
1. Sampled only, not 100% tested.
Table 11.
DC characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
0 V ≤VIN ≤VCC
±1
µA
±1
µA
ILI
Input Leakage current
ILO
Output Leakage current
0 V ≤VOUT ≤VCC
ICC1
Supply current (Read)
E = VIL, G = VIH,
f = 6 MHz
4.5
10
mA
ICC2
Supply current (Standby)
E = VCC±0.2 V,
RP = VCC±0.2 V
35
100
µA
ICC3(1)
Supply current
(Program/Erase)
Program/Erase
controller active
20
mA
VIL
Input Low voltage
–0.5
0.8
V
VIH
Input High voltage
0.7VCC
VCC+0.3
V
VOL
Output Low voltage
IOL = 1.8 mA
0.45
V
VOH
Output High voltage
IOH = –100 µA
VID
Identification voltage
IID
Identification current
VLKO
Program/Erase Lockout
supply voltage
VCC–0.4
11.5
A9 = VID
1.8
V
12.5
V
100
µA
2.3
V
1. Sampled only, not 100% tested.
31/57
DC and AC parameters
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 12. Read mode AC waveforms
tAVAV
A0-Amax/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGLQV
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI13251
Table 12.
Read AC characteristics
M29Wxx0FT/B
Symbol
Alt
Parameter
Unit
70
80
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
70
80
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
70
80
ns
tELQX(1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
70
80
ns
tGLQX(1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
Min
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
30
35
ns
tEHQZ(1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
25
ns
tGHQZ(1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
25
25
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output
Transition
Min
0
0
ns
tELBL
tELBH
tELFL
Chip Enable to BYTE Low or High
tELFH
Max
5
5
ns
tBLQZ
tFLQZ BYTE Low to Output Hi-Z
Max
25
25
ns
tBHQV
tFHQV BYTE High to Output Valid
Max
30
30
ns
1. Sampled only, not 100% tested.
32/57
Test condition
M29W160FT, M29W160FB, M29W320FT, M29W320FB
DC and AC parameters
Figure 13. Write AC waveforms, Write Enable controlled
tAVAV
A0-Amax/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
Table 13.
AI13252
Write AC characteristics, Write Enable controlled
M29Wxx0FT/B
Symbol
Alt
Parameter
Unit
70
80
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
80
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
45
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
45
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
45
ns
Output Enable High to Write Enable Low
Min
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
ns
tWHRL(1)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
µs
1. Sampled only, not 100% tested.
33/57
DC and AC parameters
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 14. Write AC waveforms, Chip Enable controlled
tAVAV
A0-Amax/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
Table 14.
AI13253
Write AC characteristics, Chip Enable controlled
M29Wxx0FT/B
Symbol
Alt
Parameter
80
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
80
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
45
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
45
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
45
ns
Output Enable High Chip Enable Low
Min
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
ns
tEHRL(1)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
µs
1. Sampled only, not 100% tested.
34/57
Unit
70
M29W160FT, M29W160FB, M29W320FT, M29W320FB
DC and AC parameters
Figure 15. Reset/Block Temporary Unprotect AC waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Table 15.
Reset/Block Temporary Unprotect AC characteristics
M29Wxx0FT/B
Symbol
Alt
Parameter
Unit
70
80
tPHWL(1)
tPHEL
tPHGL(1)
tRH
RP High to Write Enable Low, Chip
Enable Low, Output Enable Low
Min
50
50
ns
tRHWL(1)
tRHEL(1)
tRHGL(1)
tRB
RB High to Write Enable Low, Chip
Enable Low, Output Enable Low
Min
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
ns
Max
10
10
µs
RP Rise time to VID
Min
500
500
ns
VPP Rise and Fall time
Min
250
250
ns
tPLYH(1)
tPHPHH(1)
tREADY RP Low to Read mode
tVIDR
tVHVPP(1)
1. Sampled only, not 100% tested.
Figure 16. Accelerated Program timing waveforms
VPP
VPP/WP
VIL or VIH
tVHVPP
tVHVPP
AI90202
35/57
Package mechanical
8
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Package mechanical
Figure 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 × 20 mm, package outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
1. Drawing is not to scale.
Table 16.
TSOP48 – 48 lead Plastic Thin Small Outline, 12 × 20 mm, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
36/57
Max
0.100
0.0039
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3°
0°
5°
0.0315
0°
5°
3°
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Package mechanical
Figure 18. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package outline
Table 17.
TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical
data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.0472
0.260
A2
0.0102
0.900
b
Max
0.350
0.450
0.0354
0.0138
0.0177
D
6.000
5.900
6.100
0.2362
0.2323
0.2402
D1
4.000
–
–
0.1575
–
–
ddd
0.100
0.0039
E
8.000
7.900
8.100
0.3150
0.3110
0.3189
E1
5.600
–
–
0.2205
–
–
e
0.800
–
–
0.0315
–
–
FD
1.000
–
–
0.0394
–
–
FE
1.200
–
–
0.0472
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
37/57
Part numbering
9
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Part numbering
Table 18.
Ordering information scheme
Example:
M29W160FB
70
N
3S E
Device type
M29
Operating voltage
W = VCC = 2.7 to 3.6 V (70 ns), 2.5 to 3.6 V (80 ns)
Device function
160F = 16 Mbit (x 8/x 16), Boot block, 0.11 µm
320F = 32 Mbit (x 8/x 16), Boot block, 0.11 µm
Array matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70 ns
80 = 80 ns
Package
N = TSOP48, 12 × 20 mm
ZA = TFBGA48, 6 x 8 mm, 0.80 mm pitch
Device grade
3 = Automotive grade certified(1), –40 to 125 °C
S = Extended voltage range(2), VCC(min) = 2.5 V
Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing
1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to
AEC Q001 & Q002 or equivalent.
2. This feature could not be available.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the Numonyx Sales Office nearest to you.
38/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Appendix A
Table 19.
Block address table
Block address table
Top boot block addresses, M29W160FT
#
Size (Kbytes)
Address range (x 8)
Address range (x 16)
34
16
1FC000h-1FFFFFh
FE000h-FFFFFh
33
8
1FA000h-1FBFFFh
FD000h-FDFFFh
32
8
1F8000h-1F9FFFh
FC000h-FCFFFh
31
32
1F0000h-1F7FFFh
F8000h-FBFFFh
30
64
1E0000h-1EFFFFh
F0000h-F7FFFh
29
64
1D0000h-1DFFFFh
E8000h-EFFFFh
28
64
1C0000h-1CFFFFh
E0000h-E7FFFh
27
64
1B0000h-1BFFFFh
D8000h-DFFFFh
26
64
1A0000h-1AFFFFh
D0000h-D7FFFh
25
64
190000h-19FFFFh
C8000h-CFFFFh
24
64
180000h-18FFFFh
C0000h-C7FFFh
23
64
170000h-17FFFFh
B8000h-BFFFFh
22
64
160000h-16FFFFh
B0000h-B7FFFh
21
64
150000h-15FFFFh
A8000h-AFFFFh
20
64
140000h-14FFFFh
A0000h-A7FFFh
19
64
130000h-13FFFFh
98000h-9FFFFh
18
64
120000h-12FFFFh
90000h-97FFFh
17
64
110000h-11FFFFh
88000h-8FFFFh
16
64
100000h-10FFFFh
80000h-87FFFh
15
64
0F0000h-0FFFFFh
78000h-7FFFFh
14
64
0E0000h-0EFFFFh
70000h-77FFFh
13
64
0D0000h-0DFFFFh
68000h-6FFFFh
12
64
0C0000h-0CFFFFh
60000h-67FFFh
11
64
0B0000h-0BFFFFh
58000h-5FFFFh
10
64
0A0000h-0AFFFFh
50000h-57FFFh
9
64
090000h-09FFFFh
48000h-4FFFFh
8
64
080000h-08FFFFh
40000h-47FFFh
7
64
070000h-07FFFFh
38000h-3FFFFh
6
64
060000h-06FFFFh
30000h-37FFFh
5
64
050000h-05FFFFh
28000h-2FFFFh
4
64
040000h-04FFFFh
20000h-27FFFh
3
64
030000h-03FFFFh
18000h-1FFFFh
2
64
020000h-02FFFFh
10000h-17FFFh
1
64
010000h-01FFFFh
08000h-0FFFFh
0
64
000000h-00FFFFh
00000h-07FFFh
39/57
Block address table
Table 20.
40/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Bottom boot block addresses, M29W160FB
#
Size (Kbytes)
Address range (x 8)
Address range (x 16)
34
64
1F0000h-1FFFFFh
F8000h-FFFFFh
33
64
1E0000h-1EFFFFh
F0000h-F7FFFh
32
64
1D0000h-1DFFFFh
E8000h-EFFFFh
31
64
1C0000h-1CFFFFh
E0000h-E7FFFh
30
64
1B0000h-1BFFFFh
D8000h-DFFFFh
29
64
1A0000h-1AFFFFh
D0000h-D7FFFh
28
64
190000h-19FFFFh
C8000h-CFFFFh
27
64
180000h-18FFFFh
C0000h-C7FFFh
26
64
170000h-17FFFFh
B8000h-BFFFFh
25
64
160000h-16FFFFh
B0000h-B7FFFh
24
64
150000h-15FFFFh
A8000h-AFFFFh
23
64
140000h-14FFFFh
A0000h-A7FFFh
22
64
130000h-13FFFFh
98000h-9FFFFh
21
64
120000h-12FFFFh
90000h-97FFFh
20
64
110000h-11FFFFh
88000h-8FFFFh
19
64
100000h-10FFFFh
80000h-87FFFh
18
64
0F0000h-0FFFFFh
78000h-7FFFFh
17
64
0E0000h-0EFFFFh
70000h-77FFFh
16
64
0D0000h-0DFFFFh
68000h-6FFFFh
15
64
0C0000h-0CFFFFh
60000h-67FFFh
14
64
0B0000h-0BFFFFh
58000h-5FFFFh
13
64
0A0000h-0AFFFFh
50000h-57FFFh
12
64
090000h-09FFFFh
48000h-4FFFFh
11
64
080000h-08FFFFh
40000h-47FFFh
10
64
070000h-07FFFFh
38000h-3FFFFh
9
64
060000h-06FFFFh
30000h-37FFFh
8
64
050000h-05FFFFh
28000h-2FFFFh
7
64
040000h-04FFFFh
20000h-27FFFh
6
64
030000h-03FFFFh
18000h-1FFFFh
5
64
020000h-02FFFFh
10000h-17FFFh
4
64
010000h-01FFFFh
08000h-0FFFFh
3
32
008000h-00FFFFh
04000h-07FFFh
2
8
006000h-007FFFh
03000h-03FFFh
1
8
004000h-005FFFh
02000h-02FFFh
0
16
000000h-003FFFh
00000h-01FFFh
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 21.
Block address table
Top boot block addresses, M29W320FT
#
Size (Kbyte/Kword)
Address range (x 8)
Address range (x 16)
66
16/8
3FC000h-3FFFFFh
1FE000h-1FFFFFh
65
8/4
3FA000h-3FBFFFh
1FD000h-1FDFFFh
64
8/4
3F8000h-3F9FFFh
1FC000h-1FCFFFh
63
32/16
3F0000h-3F7FFFh
1F8000h-1FBFFFh
62
64/32
3E0000h-3EFFFFh
1F0000h-1F7FFFh
61
64/32
3D0000h-3DFFFFh
1E8000h-1EFFFFh
60
64/32
3C0000h-3CFFFFh
1E0000h-1E7FFFh
59
64/32
3B0000h-3BFFFFh
1D8000h-1DFFFFh
58
64/32
3A0000h-3AFFFFh
1D0000h-1D7FFFh
57
64/32
390000h-39FFFFh
1C8000h-1CFFFFh
56
64/32
380000h-18FFFFh
1C0000h-1C7FFFh
55
64/32
370000h-37FFFFh
1B8000h-1BFFFFh
54
64/32
360000h-36FFFFh
1B0000h-1B7FFFh
53
64/32
350000h-35FFFFh
1A8000h-1AFFFFh
52
64/32
340000h-34FFFFh
1A0000h-1A7FFFh
51
64/32
330000h-33FFFFh
198000h-19FFFFh
50
64/32
320000h-32FFFFh
190000h-197FFFh
49
64/32
310000h-31FFFFh
188000h-18FFFFh
48
64/32
300000h-30FFFFh
180000h-187FFFh
47
64/32
2F0000h-2FFFFFh
178000h-17FFFFh
46
64/32
2E0000h-2EFFFFh
170000h-177FFFh
45
64/32
2D0000h-2DFFFFh
168000h-16FFFFh
44
64/32
2C0000h-2CFFFFh
160000h-167FFFh
43
64/32
2B0000h-2BFFFFh
158000h-15FFFFh
42
64/32
2A0000h-2AFFFFh
150000h-157FFFh
41
64/32
290000h-29FFFFh
148000h-14FFFFh
40
64/32
280000h-28FFFFh
140000h-147FFFh
39
64/32
270000h-27FFFFh
138000h-13FFFFh
38
64/32
260000h-26FFFFh
130000h-137FFFh
37
64/32
250000h-25FFFFh
128000h-12FFFFh
36
64/32
240000h-24FFFFh
120000h-127FFFh
35
64/32
230000h-23FFFFh
118000h-11FFFFh
34
64/32
220000h-22FFFFh
110000h-117FFFh
33
64/32
210000h-21FFFFh
108000h-10FFFFh
32
64/32
200000h-20FFFFh
100000h-107FFFh
41/57
Block address table
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 21.
42/57
Top boot block addresses, M29W320FT (continued)
#
Size (Kbyte/Kword)
Address range (x 8)
Address range (x 16)
31
64/32
1F0000h-1FFFFFh
0F8000h-0FBFFFh
30
64/32
1E0000h-1EFFFFh
0F0000h-0F7FFFh
29
64/32
1D0000h-1DFFFFh
0E8000h-0EFFFFh
28
64/32
1C0000h-1CFFFFh
0E0000h-0E7FFFh
27
64/32
1B0000h-1BFFFFh
0D8000h-0DFFFFh
26
64/32
1A0000h-1AFFFFh
0D0000h-0D7FFFh
25
64/32
190000h-19FFFFh
0C8000h-0CFFFFh
24
64/32
180000h-18FFFFh
0C0000h-0C7FFFh
23
64/32
170000h-17FFFFh
0B8000h-0BFFFFh
22
64/32
160000h-16FFFFh
0B0000h-0B7FFFh
21
64/32
150000h-15FFFFh
0A8000h-0AFFFFh
20
64/32
140000h-14FFFFh
0A0000h-0A7FFFh
19
64/32
130000h-13FFFFh
098000h-09FFFFh
18
64/32
120000h-12FFFFh
090000h-097FFFh
17
64/32
110000h-11FFFFh
088000h-08FFFFh
16
64/32
100000h-10FFFFh
080000h-087FFFh
15
64/32
0F0000h-0FFFFFh
078000h-07FFFFh
14
64/32
0E0000h-0EFFFFh
070000h-077FFFh
13
64/32
0D0000h-0DFFFFh
068000h-06FFFFh
12
64/32
0C0000h-0CFFFFh
060000h-067FFFh
11
64/32
0B0000h-0BFFFFh
058000h-05FFFFh
10
64/32
0A0000h-0AFFFFh
050000h-057FFFh
9
64/32
090000h-09FFFFh
048000h-04FFFFh
8
64/32
080000h-08FFFFh
040000h-047FFFh
7
64/32
070000h-07FFFFh
038000h-03FFFFh
6
64/32
060000h-06FFFFh
030000h-037FFFh
5
64/32
050000h-05FFFFh
028000h-02FFFFh
4
64/32
040000h-04FFFFh
020000h-027FFFh
3
64/32
030000h-03FFFFh
018000h-01FFFFh
2
64/32
020000h-02FFFFh
010000h-017FFFh
1
64/32
010000h-01FFFFh
008000h-00FFFFh
0
64/32
000000h-00FFFFh
000000h-007FFFh
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 22.
Block address table
Bottom boot block addresses, M29W320FB
#
Size (Kbyte/Kword)
Address range (x 8)
Address range (x 16)
66
64/32
3F0000h-3FFFFFh
1F8000h-1FFFFFh
65
64/32
3E0000h-3EFFFFh
1F0000h-1F7FFFh
64
64/32
3D0000h-3DFFFFh
1E8000h-1EFFFFh
63
64/32
3C0000h-3CFFFFh
1E0000h-1E7FFFh
62
64/32
3B0000h-3BFFFFh
1D8000h-1DFFFFh
61
64/32
3A0000h-3AFFFFh
1D0000h-1D7FFFh
60
64/32
390000h-39FFFFh
1C8000h-1CFFFFh
59
64/32
380000h-18FFFFh
1C0000h-1C7FFFh
58
64/32
370000h-37FFFFh
1B8000h-1BFFFFh
57
64/32
360000h-36FFFFh
1B0000h-1B7FFFh
56
64/32
350000h-35FFFFh
1A8000h-1AFFFFh
55
64/32
340000h-34FFFFh
1A0000h-1A7FFFh
54
64/32
330000h-33FFFFh
198000h-19FFFFh
53
64/32
320000h-32FFFFh
190000h-197FFFh
52
64/32
310000h-31FFFFh
188000h-18FFFFh
51
64/32
300000h-30FFFFh
180000h-187FFFh
50
64/32
2F0000h-2FFFFFh
178000h-17FFFFh
49
64/32
2E0000h-2EFFFFh
170000h-177FFFh
48
64/32
2D0000h-2DFFFFh
168000h-16FFFFh
47
64/32
2C0000h-2CFFFFh
160000h-167FFFh
46
64/32
2B0000h-2BFFFFh
158000h-15FFFFh
45
64/32
2A0000h-2AFFFFh
150000h-157FFFh
44
64/32
290000h-29FFFFh
148000h-14FFFFh
43
64/32
280000h-28FFFFh
140000h-147FFFh
42
64/32
270000h-27FFFFh
138000h-13FFFFh
41
64/32
260000h-26FFFFh
130000h-137FFFh
40
64/32
250000h-25FFFFh
128000h-12FFFFh
39
64/32
240000h-24FFFFh
120000h-127FFFh
38
64/32
230000h-23FFFFh
118000h-11FFFFh
37
64/32
220000h-22FFFFh
110000h-117FFFh
36
64/32
210000h-21FFFFh
108000h-10FFFFh
35
64/32
200000h-20FFFFh
100000h-107FFFh
34
64/32
1F0000h-1FFFFFh
0F8000h-0FBFFFh
33
64/32
1E0000h-1EFFFFh
0F0000h-0F7FFFh
32
64/32
1D0000h-1DFFFFh
0E8000h-0EFFFFh
43/57
Block address table
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 22.
44/57
Bottom boot block addresses, M29W320FB (continued)
#
Size (Kbyte/Kword)
Address range (x 8)
Address range (x 16)
31
64/32
1C0000h-1CFFFFh
0E0000h-0E7FFFh
30
64/32
1B0000h-1BFFFFh
0D8000h-0DFFFFh
29
64/32
1A0000h-1AFFFFh
0D0000h-0D7FFFh
28
64/32
190000h-19FFFFh
0C8000h-0CFFFFh
27
64/32
180000h-18FFFFh
0C0000h-0C7FFFh
26
64/32
170000h-17FFFFh
0B8000h-0BFFFFh
25
64/32
160000h-16FFFFh
0B0000h-0B7FFFh
24
64/32
150000h-15FFFFh
0A8000h-0AFFFFh
23
64/32
140000h-14FFFFh
0A0000h-0A7FFFh
22
64/32
130000h-13FFFFh
098000h-09FFFFh
21
64/32
120000h-12FFFFh
090000h-097FFFh
20
64/32
110000h-11FFFFh
088000h-08FFFFh
19
64/32
100000h-10FFFFh
080000h-087FFFh
18
64/32
0F0000h-0FFFFFh
078000h-07FFFFh
17
64/32
0E0000h-0EFFFFh
070000h-077FFFh
16
64/32
0D0000h-0DFFFFh
068000h-06FFFFh
15
64/32
0C0000h-0CFFFFh
060000h-067FFFh
14
64/32
0B0000h-0BFFFFh
058000h-05FFFFh
13
64/32
0A0000h-0AFFFFh
050000h-057FFFh
12
64/32
090000h-09FFFFh
048000h-04FFFFh
11
64/32
080000h-08FFFFh
040000h-047FFFh
10
64/32
070000h-07FFFFh
038000h-03FFFFh
9
64/32
060000h-06FFFFh
030000h-037FFFh
8
64/32
050000h-05FFFFh
028000h-02FFFFh
7
64/32
040000h-04FFFFh
020000h-027FFFh
6
64/32
030000h-03FFFFh
018000h-01FFFFh
5
64/32
020000h-02FFFFh
010000h-017FFFh
4
64/32
010000h-01FFFFh
008000h-00FFFFh
3
32/16
008000h-00FFFFh
004000h-007FFFh
2
8/4
006000h-007FFFh
003000h-003FFFh
1
8/4
004000h-005FFFh
002000h-002FFFh
0
16/8
000000h-003FFFh
000000h-001FFFh
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Appendix B
Common Flash interface (CFI)
Common Flash interface (CFI)
The common flash interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query command is issued the device enters CFI Query mode and the data
structure is read from the memory. Tables 23, 24, 25, 26, 27 and 28 show the addresses
used to retrieve the data.
The CFI data structure also contains a security area where a 64 bit unique security number
is written (see Table 28: Security code area). This area can be accessed only in Read mode
by the final user. It is impossible to change the security number after it has been written by
Numonyx. Issue a Read command to return to Read mode.
Table 23.
Query structure overview(1)
Address
Sub-section name
Description
x 16
x8
10h
20h
CFI query identification string
Command set ID and algorithm data
offset
1Bh
36h
System interface information
Device timing & voltage information
27h
4Eh
Device geometry definition
Flash device layout
40h
80h
Primary algorithm-specific
extended query table
Additional information specific to the
primary algorithm (optional)
61h
C2h
Security code area
64 bit unique device number
1. Query data are always presented on the lowest order data outputs.
45/57
Common Flash interface (CFI)
M29W160FT, M29W160FB, M29W320FT, M29W320FB
CFI query identification string(1)
Table 24.
Address
Data
Description
x 16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
Alternate vendor command set and control interface id
code second vendor - specified algorithm supported
19h
32h
0000h
Address for alternate algorithm extended query table
1Ah
34h
0000h
Value
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary algorithm command set and control interface ID
code 16 bit ID code defining a specific algorithm
AMD
Compatible
Address for primary algorithm extended query table (see
Table 27)
P = 40h
NA
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
46/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 25.
Common Flash interface (CFI)
CFI query system interface information
Address
Data
Description
Value
x 16
x8
1Bh
36h
0027h
VCC logic supply minimum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV
2.7 V
1Ch
38h
0036h
VCC logic supply maximum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV
3.6 V
1Dh
1Eh
1Fh
20h
21h
0000h M29W160FT/B
VPP [programming] supply minimum Program/Erase voltage
NA
00B5h M29W320FT/B
VPP [programming] supply minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
11.5 V
0000h M29W160FT/B
VPP [programming] supply maximum Program/Erase voltage
NA
00C5h M29W320FT/B
VPP [programming] supply maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12.5 V
3Ah
3Ch
3Eh
40h
42h
22h
44h
23h
46h
0004h Typical timeout per single byte/word program = 2n µs
0000h Typical timeout for minimum size write buffer program = 2 µs
000Ah Typical timeout per individual block erase = 2 ms
0000h Typical timeout for full chip erase =
0005h M29W320FT/B
25h
26h
48h
2n
1s
ms
NA
Maximum timeout for byte/word program = 2n times typical
n
Maximum timeout for byte/word program = 2 times typical
0000h Maximum timeout for write buffer program =
2n
times typical
256 µs
512 µs
NA
2n
0003h M29W160FT/B
Maximum timeout per individual block erase =
times typical
8s
0004h M29W320FT/B
Maximum timeout per individual block erase = 2n times typical
16 s
4Ah
4Ch
NA
n
0004h M29W160FT/B
24h
16 µs
n
0000h Maximum timeout for chip erase =
2n
times typical
NA
47/57
Common Flash interface (CFI)
Table 26.
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Device geometry definition
Address
Data
x 16
x8
27h
4Eh
Description
0015h M29W160FT/B device size = 2n in number of bytes
2 Mbyte
0016h M29W320FT/B device size = 2 in number of bytes
4 Mbyte
x 8, x 16
Async.
28h
29h
50h
52h
0002h
Flash device interface code description
0000h
2Ah
2Bh
54h
56h
0000h
Maximum number of bytes in multi-byte program or page = 2n
0000h
NA
2Ch
58h
Number of Erase Block Regions within the device.
0004h It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size.
4
2Dh
2Eh
5Ah
5Ch
0000h Region 1 information
0000h Number of identical size erase block = 0000h+1
1
2Fh
30h
5Eh
60h
0040h Region 1 information
0000h Block size in Region 1 = 0040h * 256 byte
31h
32h
62h
64h
0001h Region 2 information
0000h Number of identical size erase block = 0001h+1
33h
34h
66h
68h
0020h Region 2 information
0000h Block size in Region 2 = 0020h * 256 byte
35h
36h
6Ah
6Ch
0000h Region 3 information
0000h Number of identical size erase block = 0000h+1
37h
38h
6Eh
70h
0080h Region 3 Information
0000h Block size in Region 3 = 0080h * 256 byte
39h
3Ah
3Bh
3Ch
48/57
n
Value
72h
74h
76h
78h
16 Kbyte
2
8 Kbyte
1
32 Kbyte
001Eh M29W160FT/B Region 4 information
0000h Number of identical-size erase block = 001Eh+1
31
003Eh M29W320FT/B Region 4 information
0000h Number of identical-size erase block = 003Eh+1
63
0000h Region 4 information
0001h Block size in Region 4 = 0100h * 256 byte
64 Kbyte
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 27.
Common Flash interface (CFI)
Primary algorithm-specific extended query table
Address
Data
x 16
x8
40h
80h
Description
0050h
Value
"P"
41h
82h
42h
84h
Primary algorithm extended query table unique ASCII string
0052h
“PRI”
0049h
43h
86h
0031h Major version number, ASCII
"1"
44h
88h
0030h Minor version number, ASCII
"0"
45h
8Ah
Address Sensitive Unlock (bits 1 to 0)
0000h 00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h
8Ch
0002h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
47h
8Eh
0001h
Block Protection
00 = not supported, x = number of blocks in per group
1
48h
90h
0001h
Temporary Block Unprotect
00 = not supported, 01 = supported
49h
92h
0004h
Block Protect /Unprotect
04 = M29W400B
4Ah
94h
0000h Simultaneous operations, 00 = not supported
No
4Bh
96h
0000h Burst mode, 00 = not supported, 01 = supported
No
4Ch
98h
0000h
4Dh(1)
9Ah
VPP supply minimum Program/Erase voltage
00B5h bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5 V
(1)
4Eh
9Ch
VPP supply minimum Program/Erase voltage
00C5h bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5 V
4Fh(1)
9Eh
000xh
"R"
"I"
Yes
4
Page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page
word
Top/Bottom Boot Block Flag
02h = Bottom Boot device, 03h = Top Boot device
No
–
1. Only for the M29W320FT/B devices.
Table 28.
Security code area
Address
Data
x16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Description
64 bit: unique device number
49/57
Block protection
Appendix C
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Block protection
Block protection can be used to prevent any operation from modifying the data stored in the
Flash memory. Each Block can be protected individually. Once protected, Program and
Erase operations on the block fail to change the data.
There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is
described in the signal descriptions section.
Unlike the command interface of the Program/Erase controller, the techniques for protecting
and unprotecting blocks could change between different Flash memory suppliers.
9.1
Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Programming Equipment.
To protect a block follow the flowchart in Figure 19: Programmer equipment block protect
flowchart. During the Block Protect algorithm, the Amax-A12 address inputs indicate the
address of the block to be protected. The block will be correctly protected only if Amax-A12
remain valid and stable, and if Chip Enable is kept Low, VIL, all along the Protect and Verify
phases.
The Chip Unprotect algorithm is used to unprotect all the memory blocks at the same time.
This algorithm can only be used if all of the blocks are protected first. To unprotect the chip
follow Figure 20: Programmer equipment chip unprotect flowchart. Table 29: Programmer
technique bus operations, BYTE = VIH or VIL, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
9.2
In-system technique
The in-system technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP. This can be achieved without violating the maximum ratings of the
components on the microprocessor bus, therefore this technique is suitable for use after the
Flash memory has been fitted to the system.
To protect a block follow the flowchart in Figure 21: In-system equipment block protect
flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all
the blocks can be unprotected at the same time. To unprotect the chip follow Figure 22: Insystem equipment chip unprotect flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.
50/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Table 29.
Block protection
Programmer technique bus operations, BYTE = VIH or VIL
Operation
E
G
W
Address inputs
A0-Amax
Data inputs/outputs
DQ15A–1, DQ14-DQ0
Block Protect
VIL VID VIL Pulse
A9 = VID,
A12-Amax Block Address
Others = X
X
Chip Unprotect
VID VID VIL Pulse
A9 = VID, A12 = VIH, A15 = VIH
Others = X
X
VIH
A0 = VIL, A1 = VIH, A6 = VIL,
A9 = VID,
A12-Amax Block Address
Others = X
Pass = XX01h
Retry = XX00h
VIH
A0 = VIL, A1 = VIH, A6 = VIH,
A9 = VID,
A12-Amax Block Address
Others = X
Retry = XX01h
Pass = XX00h
Block Protection
VIL
Verify
Block
Unprotection
Verify
VIL
VIL
VIL
51/57
Block protection
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 19. Programmer equipment block protect flowchart
START
Set-up
ADDRESS = BLOCK ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Protect
Wait 4 µs
W = VIL(1)
Wait 100 µs
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
E = VIL(1)
Verify
Wait 4 µs
G = VIL
Wait 60 ns
Read DATA
DATA
NO
=
01h
YES
A9 = VIH
E, G = VIH
++n
= 25
NO
End
YES
PASS
A9 = VIH
E, G = VIH
FAIL
AI03469b
1. Address inputs Amax-A12 give the address of the block that is to be protected. It is imperative that they
remain stable during the operation.
2. During the Protect and Verify phases of the algorithm, Chip Enable E must be kept Low, VIL.
52/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Block protection
Figure 20. Programmer equipment chip unprotect flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Unprotect
Wait 4 µs
W = VIL
Wait 10 ms
W = VIH
E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1, A6 = VIH
E = VIL
Wait 4 µs
G = VIL
INCREMENT
CURRENT BLOCK
Verify
Wait 60 ns
Read DATA
NO
End
NO
++n
= 1000
DATA
=
00h
YES
LAST
BLOCK
YES
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
FAIL
PASS
NO
AI03470
53/57
Block protection
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Figure 21. In-system equipment block protect flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 100 µs
Verify
WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 4 µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
DATA
NO
=
01h
YES
End
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI03471
54/57
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Block protection
Figure 22. In-system equipment chip unprotect flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Wait 10 ms
Verify
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Wait 4 µs
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
NO
End
NO
++n
= 1000
YES
DATA
=
00h
INCREMENT
CURRENT BLOCK
YES
LAST
BLOCK
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI03472
55/57
Revision history
10
M29W160FT, M29W160FB, M29W320FT, M29W320FB
Revision history
Table 30.
56/57
Document revision history
Date
Revision
Changes
26-Jun-2006
1
Initial release.
20-Jul-2007
2
Document status promoted from Preliminary Data to full Datasheet.
TFBGA48 6 x 8 mm package added.
80 ns speed class added.
Voltage range extended when access time is 80 ns.
Small text changes.
26-Mar-2008
3
Applied Numonyx branding.
M29W160FT, M29W160FB, M29W320FT, M29W320FB
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