PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS843246 is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout Buffer designed for HiPerClockS™ Fibre Channel and Gigabit Ethernet applications and is a member of the HiperClockS™ family of High Performance Clock Solutions from ICS. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 26.5625MHz crystal for a Fibre Channel. The low phase noise characteristics of the ICS843246 make it an ideal clock for these demanding applications. • Six LVPECL outputs ICS • Crystal oscillator interface • Output frequency range: 53.125MHz to 333.3333MHz • Crystal input frequency range: 25MHz to 33.333MHz • RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.41ps (typical) • Full 3.3V or 3.3V core, 2.5V output supply mode • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free RoHS-compliant packages SELECT FUNCTION TABLE Inputs Function FB_SEL N_SEL1 N_SEL0 M Divide N Divide M/N 0 0 0 20 2 10 0 0 1 20 4 5 0 1 0 20 5 4 0 1 1 20 8 2.5 1 0 0 24 3 8 1 0 1 24 4 6 1 1 0 24 6 4 1 1 1 24 12 2 BLOCK DIAGRAM PIN ASSIGNMENT Q0 nQ0 PLL_BYPASS Pullup Q1 1 XTAL_IN OSC PLL nQ1 Output Divider 0 XTAL_OUT Q2 nQ2 Q3 Feedback Divider nQ3 FB_SEL Pulldown Q4 N_SEL1 Pullup nQ4 N_SEL0 Pullup Q5 nQ5 VCCO VCCO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS V CCA VCC FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 V EE V EE N_SEL0 XTAL_OUT XTAL_IN ICS843246 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm body package G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843246AM www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 29, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 VCCO 3, 4 5, 6 Type Description Power Output supply pins. nQ2, Q2 Output Differential output pair. LVPECL interface levels. nQ1, Q1 Output Differential output pair. LVPECL interface levels. 7, 8 nQ0, Q0 Output 9 PLL_BYPASS Input 10 VCCA Power Differential output pair. LVPECL interface levels. Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. 11 VCC Power Core supply pin. 12 13, 14 15, 18 16, 17 FB_SEL XTAL_IN, XTAL_OUT N_SEL0 N_SEL1 VEE Input 19, 20 nQ5, Q5 Output 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. Input Input Pullup Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 843246AM Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 3. CRYSTAL FUNCTION TABLE Inputs XTAL (MHz) FB_SEL Function N_SEL1 N_SEL0 M VCO (MHz) N Output (MHz) 25 0 0 0 20 500 2 250 25 0 0 1 20 500 4 125 25 0 1 0 20 500 5 10 0 25 0 1 1 20 500 8 62.5 25 1 0 0 24 600 3 200 25 1 0 1 24 600 4 150 25 1 1 0 24 600 6 100 25 1 1 1 24 600 12 50 26.5625 0 1 0 20 531.25 5 106.25 26.5625 1 0 0 24 637.5 3 212.5 26.5625 1 0 1 24 637.5 4 159.375 26.5625 1 1 0 24 637.5 6 106.25 26.5625 1 1 1 24 637.5 12 53.125 30 0 0 0 20 600 2 300 30 0 0 1 20 600 4 150 30 0 1 0 20 600 5 12 0 30 0 1 1 20 600 8 75 31.25 0 0 0 20 625 2 312.5 31.25 0 0 1 20 62 5 4 156.25 31.25 0 1 0 20 62 5 5 12 5 31.25 0 1 1 20 625 8 78.125 33.3333 0 0 0 20 666.6667 2 333.3333 33.3333 0 0 1 20 666.6667 4 166.6667 33.3333 0 1 0 20 666.6667 5 133.3333 33.3333 0 1 1 20 666.6667 8 83.3333 843246AM www.icst.com/products/hiperclocks.html 3 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 24 Lead SOIC 24 Lead TSSOP 50°C/W (0 lfpm) 70°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 107 mA ICCA Analog Supply Current 7 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 107 mA ICCA Analog Supply Current 7 mA TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current 843246AM Test Conditions Minimum 2 -0.3 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 Typical Maximum Units VCC + 0.3 V 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V -150 µA www.icst.com/products/hiperclocks.html 4 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1. 0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 33.333 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units 333.33 MHz NOTE: Characterized using an 18pf parallel resonant crystal. TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Minimum Output Frequency t jit(Ø) RMS Phase Jitter (Random) t sk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Typical 53.125 125MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% 0.41 ps TBD ps 380 ps 50 % PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 1 ms Maximum Units 333.33 MHz TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Minimum Output Frequency tjit(Ø) RMS Phase Jitter (Random) t sk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Typical 53.125 125MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% 0.41 ps TBD ps 360 ps 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 843246AM www.icst.com/products/hiperclocks.html 5 % 1 ms REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TYPICAL PHASE NOISE AT 125MHZ @ 3.3V ➤ 0 -10 -20 Gb Ethernet Filter -30 -40 125MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz ICS843246 -120 -130 -140 ➤ -150 -160 Phase Noise Result by adding Gb Ethernet Filter to raw data -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843246AM www.icst.com/products/hiperclocks.html 6 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2.8V±0.04V 2V 2V VCC, VCCA, VCCO Qx SCOPE VCC, VCCA Qx SCOPE VCCO LVPECL LVPECL V EE nQx nQx V EE -1.3V ± 0.165V -0.5V ± 0.125V 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT nQx nQ0:nQ5 Qx Q0:Q5 t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 843246AM www.icst.com/products/hiperclocks.html 7 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843246 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V CCA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VCC .01μF 10Ω V CCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS843246 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 843246AM www.icst.com/products/hiperclocks.html 8 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 843246AM 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE 843246AM www.icst.com/products/hiperclocks.html 10 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843246. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843246 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 107mA = 370.75mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW Total Power_MAX (3.465V, with all outputs switching) = 370.75mW + 180mW = 550.75mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.551W * 43°C/W = 93.7°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 50°C/W 43°C/W 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 843246AM www.icst.com/products/hiperclocks.html 11 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (V CCO_MAX • -V OH_MAX ) = 0.9V For logic low, VOUT = V OL_MAX =V CCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) = L L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) = L L [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843246AM www.icst.com/products/hiperclocks.html 12 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RELIABILITY INFORMATION TABLE 8A. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 50°C/W 43°C/W 500 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 8B. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843246 is: 3863 843246AM www.icst.com/products/hiperclocks.html 13 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER FOR 24 LEAD SOIC PACKAGE OUTLINE - G SUFFIX FOR Millimeters SYMBOL Minimum N 24 LEAD TSSOP TABLE 9B. PACKAGE DIMENSIONS TABLE 9A. PACKAGE DIMENSIONS SYMBOL Maximum Millimeters Minimum N 24 Maximum 24 A -- 2.65 A -- 1.20 A1 0.10 -- A1 0.05 0.15 A2 2.05 2.55 A2 0.80 1.05 B 0.33 0.51 b 0.19 0.30 C 0.18 0.32 c 0.09 0.20 D 15.20 15.85 D 7.70 7.90 E 7.40 7.60 E e H 1.27 BASIC E1 10.00 10.65 6.40 BASIC 4.30 e 4.50 0.65 BASIC h 0.25 0.75 L 0.45 0.75 L 0.40 1.27 α 0° 8° α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-013, MO-119 843246AM ICS843246 Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html 14 REV. A SEPTEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843246 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843246AM TBD 24 Lead SOIC tube 0°C to 70°C ICS843246AMT TBD 24 Lead SOIC 1000 tape & reel 0°C to 70°C ICS843246AMLF TBD 24 Lead "Lead-Free" SOIC tube 0°C to 70°C ICS843246AMLFT TBD 24 Lead "Lead-Free" SOIC 1000 tape & reel 0°C to 70°C ICS843246AG ICS843246AG 24 Lead TSSOP tube 0°C to 70°C ICS843246AGT ICS843246AG 24 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS843246AGLF TBD 24 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS843246AGLFT TBD 24 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843246AM www.icst.com/products/hiperclocks.html 15 REV. A SEPTEMBER 29, 2005