Very Low Power/Voltage CMOS SRAM 256K X 16 bit BSI BS616LV4017 FEATURES • Wide Vcc operation voltage : 2.4~5.5V • Very low power consumption : Vcc = 3.0V C-grade: 26mA (@55ns) operating current I-grade: 27mA (@55ns) operating current C-grade: 21mA (@70ns) operating current I-grade: 22mA (@70ns) operating current 0.45uA (Typ.) CMOS standby current Vcc = 5.0V C-grade: 63mA (@55ns) operating current I-grade: 65mA (@55ns) operating current C-grade: 53mA (@70ns) operating current I-grade: 55mA (@70ns) operating current 2.0uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin DESCRIPTION The BS616LV4017 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.45uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) ,active LOW output enable(OE) and three-state output drivers. The BS616LV4017 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV4017 is available in DICE form, JEDEC standard 44-pin TSOP Type II package and 48-ball BGA package. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE POWER DISSIPATION Operating STANDBY SPEED ( ns ) ( I CCSB1 , Max ) PKG TYPE ( I CC , Max ) 55ns :3.0~5.5V 70ns :2.7~5.5V Vcc= 3.0V 2.4V ~ 5.5V 55 /70 5uA 30uA 21mA 53mA 2.4V ~ 5.5V 55 /70 10uA 60uA 22mA 55mA Vcc= 5.0V Vcc = 5.0V Vcc =3.0V 70ns 70ns BS616LV4017DC BS616LV4017EC DICE O O +0 C to +70 C BS616LV4017AC BS616LV4017DI BS616LV4017EI BS616LV4017AI O O -40 C to +85 C BLOCK DIAGRAM PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 BS616LV4017EC BS616LV4017EI 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 TSOP2-44 BGA-48-0608 DICE TSOP2-44 BGA-48-0608 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 A12 A4 A3 A2 A1 Address A0 A17 A16 A15 A14 A13 A12 Input Buffer 22 2048 Row Memory Array Decoder 2048 x 2048 2048 16 DQ0 . . . . . . . . Data Input Buffer 16 Column I/O Write Driver Sense Amp 16 Data Output Buffer DQ15 16 128 Column Decoder 14 CE WE OE UB LB Control Address Input Buffer A11 A10 A9 A8 A7 A6 A5 Vcc Gnd Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616LV4017 1 Revision 2.1 Jan. 2004 BSI BS616LV4017 PIN DESCRIPTIONS Name Function A0-A17 Address Input These 18 address inputs select one of the 262,144 x 16-bit words in the RAM. CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0 - DQ15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write R0201-BS616LV4017 CE H WE OE LB UB D0~D7 D8~D15 X X X X High Z High Z ICCSB , I CCSB1 X X X H H High Z L L X H X H H X H X High Z High Z High Z High Z ICCSB , I CCSB1 ICC L L Dout H L L H L L L L H L L X Vcc CURRENT High Z ICC Dout ICC High Z Dout ICC Dout High Z ICC Din Din ICC H L X Din ICC L H Din X ICC 2 Revision 2.1 Jan. 2004 BSI BS616LV4017 ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V VTERM Terminal Voltage Respect to GND with TBIAS Temperature Under Bias -40 to +85 O C TSTG Storage Temperature -60 to +150 O C PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA AMBIENT TEMPERATURE RANGE O Commercial 0 Industrial -40 O C to +70 O C to +85 Vcc C 2.4V ~ 5.5V OC 2.4V ~ 5.5V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SYMBOL PARAMETER Input Capacitance Input/Output Capacitance CIN CDQ CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) PARAMETER NAME VIL VIH PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. Guaranteed Input Low Voltage (2) Vcc=3.0V Guaranteed Input High Voltage (2) Vcc=3.0V 2.0 Vcc=5.0V 2.2 -0.5 -- Vcc=5.0V UNITS 0.8 V 0.8 -- Vcc+0.3 V IIL Input Leakage Current Vcc = Max, V IN = 0V to Vcc -- -- 1 uA ILO Output Leakage Current Vcc = Max, CE = V IH , or OE,= V IH VI/O = 0V to Vcc -- -- 1 uA VOL Output Low Voltage Vcc = Max, I OL = 2.0mA -- -- 0.4 V Vcc=3.0V Vcc=5.0V VOH ICC Output High Voltage (5) Vcc = Min, I OH = -1.0mA Operating Power Supply Current CE=VIL ,I DQ= 0mA, Standby Current-TTL CE = V IH, I DQ= 0mA F=Fmax Vcc=3.0V 2.4 Vcc=5.0V 2.4 70ns Vcc=3.0V 70ns Vcc=5.0V (3) -- -- -- -- -- (4) Standby Current-CMOS CE ≧ Vcc-0.2V, V IN ≧ Vcc - 0.2V or VIN ≦0.2V Vcc=3.0V Vcc=5.0V 22 mA 0.5 Vcc=5.0V ICCSB1 V -- 55 Vcc=3.0V ICCSB 0.4 -- mA 1.0 0.45 10 2.0 60 uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . 4. IccSB1_MAX. is 5uA/30uA at Vcc=3.0V/5.0V and TA=70oC. 5. Icc_MAX. is 27mA(@3.0V)/65mA(@5.0V) under 55ns operation. R0201-BS616LV4017 3 Revision 2.1 Jan. 2004 BSI BS616LV4017 DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR ICCDR (3) tCDR tR PARAMETER TEST CONDITIONS MIN. TYP. Vcc for Data Retention CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 Data Retention Current CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- Chip Deselect to Data Retention Time See Retention Waveform Operation Recovery Time 0 TRC (2) (1) MAX. UNITS -- -- V 0.3 1.3 uA -- -- ns -- -- ns 1. Vcc = 1.5V, TA = + 25 C 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.8uA at TA=70OC. O LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE R0201-BS616LV4017 Vcc tR t CDR CE ≥ Vcc - 0.2V VIH 4 VIH Revision 2.1 Jan. 2004 BSI BS616LV4017 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V WAVEFORM INPUTS OUTPUTS Input Rise and Fall Times 1V/ns MUST BE STEADY MUST BE STEADY Input and Output Timing Reference Level 0.5Vcc MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L Output Load CL = 30pF+1TTL CL = 100pF+1TTL MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tRC Read Cycle Time 70 -- -- 55 -- -- ns tAVQV tAA Address Access Time -- -- 70 -- -- 55 ns tELQV tACS Chip Select Access Time -- -- 70 -- -- 55 ns tBA tBA (1) Data Byte Control Access Time -- -- 35 -- -- 30 ns tGLQV tOE Output Enable to Output Valid -- -- 35 -- -- 30 ns t E1LQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns tBE tBE Data Byte Control to Output Low Z 5 -- -- 5 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 5 -- -- 5 -- -- ns tEHQZ tCHZ Chip Deselect to Output in High Z -- -- 35 -- -- 30 ns tBDO tBDO Data Byte Control to Output High Z -- -- 35 -- -- 30 ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 30 -- -- 25 ns tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns CYCLE TIME : 70ns DESCRIPTION (LB,UB) (LB,UB) (LB,UB) CYCLE TIME : 55ns UNIT (Vcc = 2.7~5.5V) (Vcc = 3.0~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle. R0201-BS616LV4017 5 Revision 2.1 Jan. 2004 BSI BS616LV4017 SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE1 t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE t D OUT READ CYCLE3 t BDO (5) t (5) CHZ CLZ (1,4) t RC ADDRESS t AA OE t OH t OE t OLZ CE (5) t CLZ t t OHZ (5) t CHZ(1,5) ACS t BA LB,UB t BE t BDO D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS616LV4017 6 Revision 2.1 Jan. 2004 BSI BS616LV4017 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ tWHOX t OW CYCLE TIME : 70ns CYCLE TIME : 55ns MIN. TYP. MAX. MIN. TYP. MAX. (Vcc = 3.0~5.5V) (Vcc = 2.7~5.5V) DESCRIPTION UNIT Write Cycle Time 70 -- -- 55 -- -- ns Chip Select to End of Write 70 -- -- 55 -- -- ns 0 -- -- 0 -- -- ns Address Valid to End of Write 70 -- -- 55 -- -- ns Write Pulse Width 35 -- -- 30 -- -- ns 0 -- -- 0 -- -- ns Address Setup Time Write recovery Time (CE,WE) (LB,UB) 30 -- -- 25 -- -- ns -- -- 30 -- -- 25 ns Data to Write Time Overlap 30 -- -- 25 -- -- ns Data Hold from Write Time 0 -- -- 0 -- -- ns Output Disable to Output in High Z -- -- 30 -- -- 25 ns End of Write to Output Active 5 -- -- 5 -- -- ns Date Byte Control to End of Write Write to Output in High Z NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE (10) t CW (5) CE t BW LB,UB t AW WE (3) t WP t AS (2) (4,11) t OHZ D OUT t DH t DW D IN R0201-BS616LV4017 7 Revision 2.1 Jan. 2004 BSI BS616LV4017 WRITE CYCLE2 (1,6) t WC ADDRESS (10) t CW (5) CE t BW LB,UB t AW WE t WR t WP (3) (2) t AS (4,11) t OW t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. TCW is measured from the later of CE going low to the end of write. 11. The parameter is guaranteed but not 100% tested. R0201-BS616LV4017 8 Revision 2.1 Jan. 2004 BSI BS616LV4017 ORDERING INFORMATION BS616LV4017 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 A: BGA-48-0608 D: DICE Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP2-44 R0201-BS616LV4017 9 Revision 2.1 Jan. 2004 BSI BS616LV4017 1.4 Max. 0.25 ± 0.05 PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 0.1 D1 N D E D1 E1 48 8.0 6.0 5.25 3.75 0.35± 0.05 E1 E ± 0.1 e SOLDER BALL VIEW A 48 mini-BGA (6 x 8mm) R0201-BS616LV4017 10 Revision 2.1 Jan. 2004