HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM IDT7027S/L Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Military: 25/35/55ns (max) – Industrial: 25ns (max.) – Commercial: 20/25/35/55ns (max.) Low-power operation – IDT7027S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7027L Active: 750mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for bus matching capability. Dual chip enables allow for depth expansion without ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ external logic IDT7027 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin Ceramic Pin Grid Array (PGA) Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL UBL R/WR UBR CE0L CE1L CE0R CE1R OEL OER LBL LBR I/O8-15R I/O 8-15L I/O Control I/O 0-7L I/O Control I/O0-7R BUSY L (1,2) A14L BUSYR Address Decoder A0L 32Kx16 MEMORY ARRAY 7027 A14L A0L CE0L CE1L OEL R/WL . A14R A0R A14R ARBITRATION INTERRUPT SEMAPHORE LOGIC SEML (2) INT L Address Decoder (1,2) M/S NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). (2) A0R CE0R CE1R OER R/WR SEMR (2) INTR 3199 drw 01 MAY 2000 1 ©2000 Integrated Device Technology, Inc. DSC 3199/7 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM, designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7027 is packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. A8L A7L A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R A7R A8R Pin Configurations(1,2,3) INDEX 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 7 70 69 8 9 68 67 10 IDT7027PF PN100-1(4) 11 12 13 100-Pin TQFP Top View(5) 14 15 66 65 64 63 62 16 61 60 17 59 18 58 19 57 20 21 56 55 22 23 54 53 24 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O9L I/O8L Vcc I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R NC A9L A10L A11L A12L A13L A14L NC NC NC LBL UBL CE0L CE1L SEML Vcc R/WL OEL GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 6.42 A9R A10R A11R A12R A13R A14R NC NC NC LBR UBR CE0R CE1R SEMR GND R/WR OER GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R 3199 drw 02 . IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) 81 12 80 A10R 84 11 83 A7R 87 10 59 105 58 55 2 35 31 A7L 1 4 A10L 5 8 A13L 7 6 10 9 17 CE1L 13 UBL NC A14L 12 NC 11 21 GND 16 19 SEML OEL 14 25 15 28 22 18 20 I/O11L 23 I/O3L 33 I/O7L 29 24 GND I/O13L GND 36 I/O5L 32 NC I/O14L I/O10L GND 38 I/O2L 34 Vcc I/O0R 41 I/O0L 37 I/O4L I/O3R 42 I/O1R 40 I/O1L 106 A11L 3 39 108-Pin PGA Top View(5) I/O5R 45 I/O4R 43 I/O2R I/O7R 47 Vcc 46 44 IDT7027G G108-1 (4) NC 50 I/O8R 49 I/O6R NC 53 51 NC I/O15R I/O11R A3L A6L 56 48 102 A4L A8L 108 01 103 A5L 62 OER 54 GND I/O14R I/O12R I/O9R NC NC A1L A2L 66 CE0R 61 57 I/O13R I/O10R 52 98 100 107 02 71 NC 64 CE1R R/WR 60 NC A2R INTL A0L 67 63 GND 93 97 104 03 75 A12R M/S BUSYR BUSYL 101 04 70 LBR 65 89 94 99 05 79 68 SEMR GND A6R A0R GND 96 06 73 NC A9R 69 UBR 85 91 95 07 76 82 A3R INTR 72 NC A13R A5R 88 92 08 78 86 A1R 74 A14R A8R A4R 90 09 77 A11R I/O6L 30 NC 26 I/O8L 27 A9L A12L NC LBL CE0L Vcc R/WL NC I/O15L I/O12L I/O9L NC A B C D E F G H J K L M . 3199 drw 03 INDEX NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.21 in x 1.21 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A14L A0R - A14R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3199 tbl 01 3 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table I Chip Enable CE CE0 CE 1 Mode V IL V IH Po rt Se le c te d (TTL Active ) < 0.2V >V CC -0.2V Po rt Se le c te d (CM OS A ctive ) V IH X Po rt De s e le c te d (TTL Inac tiv e ) X V IL Po rt De s e le c te d (TTL Inac tiv e ) > V CC -0.2V X Po rt De s e le c te d (CM OS Inac tiv e ) X <0.2V Po rt De s e le c te d (CM OS Inac tiv e ) L H 3199 tbl 02 NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only. 2. Port "A" and "B" references are located where CE is used. 3. "H" = VIH and "L" = VIL. Truth Table II Non-Contention Read/Write Control Inputs(1) Outputs CE(2) R/W OE UB LB SEM I/O8-15 I/O0-7 Mode H X X X X H High-Z High-Z Deselected: Power-Down X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H High-Z DATAOUT Read Lower Byte Only L H L L L H DATAOUT DATAOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled 3199 tbl 03 NOTES: 1. A0L — A14L ≠ A0R — A14R. 2. Refer to Chip Enable Truth Table. Truth Table III Semaphore Read/Write Control Inputs(1) (2) CE Outputs R/W OE UB LB SEM I/O8-15 I/O0-7 H H L X X L DATAOUT DATAOUT Read Data in Semaphore Flag X H L H H L DATAOUT DATAOUT Read Data in Semaphore Flag H ↑ X X X L DATAIN DATAIN Write I/O0 into Semaphore Flag X ↑ X H H L DATAIN DATAIN Write I/O0 into Semaphore Flag L X X L X L ______ ______ Not Allowed L X X X L L ______ ______ Not Allowed Mode NOTES: 1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0 __I/O15). These eight semaphore flags are addressed by A0-A2. 2. Refer to Chip Enable Truth Table. 4 6.42 3199 tbl 04 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1,3) Symbol VTERM(2) TBIAS Rating Commercial & Industrial Military Unit Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V Temperature Under Bias -55 to +125 -65 to +135 o -65 to +150 o -65 to +150 50 50 GND Vcc O -55 C to+125 C 0V 5.0V + 10% 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% O Commercial C Industrial DC Output Current IOUT Ambient Temperature Grade Military Storage Temperature TSTG Maximum Operating Temperature and Supply Voltage(1) C 3199 tbl 06 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2. Industrial temperature: for other speeds packages and powers, contact your sales office. mA 3199 tbl 05 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol Parameter VCC Supply Voltage GND Ground Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VIH Input High Voltage 2.2 VIL Input Low Voltage -0.5(1) ____ (TA = +25°C, f = 1.0mhz) TQFP ONLY Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 3199 tbl 08 Min. ____ Capacitance(1) (2) 6.0 0.8 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. V V 3199 tbl 07 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7027S Symbol Parameter Test Conditions |ILI| Input Leakage Current(1) |ILO| Output Leakage Current VOL VOH Output Low Voltage Output High Voltage 7027L Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to VCC ___ 10 ___ 5 µA CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA IOL = 4mA ___ 0.4 ___ 0.4 V 2.4 ___ 2.4 ___ V IOH = -4mA 3199 tbl 09 NOTE: 1. At Vcc < 2.0V, input leakages are undefined. 5 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6,7) (VCC = 5.0V ± 10%) 7027X20 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) Standby Current CEL = CER = VIH (Both Ports - TTL Level SEMR = SEML = VIH Inputs) f = fMAX(3) Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH Full Standby Current Both Ports CEL and (Both Ports - All CMOS CER > VCC - 0.2V Level Inputs) VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V Full Standby Current (One Port - All CMOS Level Inputs) Version 7027X25 Com'l, Ind & Military 7027X35 Com'l & Military 7027X55 Com'l & Military Typ. (2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit mA COM'L S L 185 185 325 285 180 170 305 265 160 160 295 255 150 150 270 230 MIL & IND S L ____ ____ ____ ____ 170 170 345 305 160 160 335 295 150 150 310 270 COM'L S L 55 55 90 70 40 40 85 60 30 30 85 60 20 20 85 60 MIL & IND S L ____ ____ ____ ____ 40 40 100 80 30 30 100 80 20 20 100 80 COM'L S L 120 120 215 185 105 105 200 170 95 95 185 155 85 85 165 135 MIL & IND S L ____ ____ ____ ____ 105 105 230 200 95 95 215 185 85 85 195 165 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 S L 115 115 190 160 100 100 170 145 90 90 160 135 80 80 135 110 S L ____ ____ ____ ____ 100 100 200 175 90 90 190 165 80 80 175 150 CE"A" < 0.2V and COM'L CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs MIL & IND Disable d, f = fMAX(3) mA mA mA mA 3199 tbl 10 NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to Chip Enable Truth Table. 7. Industrial temperature: for other speeds, packages and powers contact your sales office. 6 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Test Conditions 5V 5V dInput Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Max. Input Timing Reference Levels 893Ω DATAOUT BUSY INT 1.5V Output Reference Levels 1.5V Output Load 893Ω DATAOUT 30pF 347Ω 5pF* 347Ω Figures 1 and 2 3199 tbl 11 3199 drw 04 Figure 2. Output Test Load (for tLZ, tHZ, tWZ, t OW) *Including scope and jig. Figure 1. AC Output Test Load AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Ranges(4,6) 7027X20 Com'l Only Symbol Parameter 7027X25 Com'l, Ind. & Military 7027X35 Com'l & Military 7027X55 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ 55 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ____ 55 ns tACE Chip Enable Access Time (3) ____ 20 ____ 25 ____ 35 ____ 55 ns tABE (3) ____ 20 ____ 25 ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 12 ____ 13 ____ 20 ____ 30 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns tHZ Output High-Z Time (1,2) ____ 12 ____ 15 ____ 15 ____ 25 ns 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 25 ____ 35 ____ 50 ns ns tPU Byte Enable Access Time Chip Enable to Power Up Time (2,5) (2,5) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 12 ____ 15 ____ 15 ____ tSAA Semaphore Address Access Time ____ 20 ____ 25 ____ 35 ____ 55 NOTES:. 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). 5. Refer to Chip Enable Truth Table. 6. Industrial temperature: for other speeds, packages and powers contact your sales office. 7 6.42 ns 3199 tbl 12 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) tRC ADDR (4) tAA (4) tACE (6) CE tAOE (4) OE tABE (4) UB, LB R/W tLZ tOH (1) DATAOUT VALID DATA (4) tHZ (2) BUSYOUT tBDD (3,4) 3199 drw 05 Timing of Power-Up Power-Down CE(6) ICC tPU tPD 50% 50% ISB 3199 drw 06 . NOTES: 1. Timing depends on which signal is asserted last, CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD . 5. SEM = VIH. 6. Refer to Chip Enable Truth Table. 8 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5,6) 7027X20 Com'l Only Symbol Parameter 7027X25 Com'l, Ind & Military 7027X35 Com'l & Military 7027X55 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit 20 ____ 25 ____ 35 ____ 55 ____ ns 15 ____ 20 ____ 30 ____ 45 ____ ns 15 ____ 20 ____ 30 ____ 45 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 15 ____ 20 ____ 25 ____ 40 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 15 ____ 15 ____ 15 ____ 30 ____ ns ____ 12 ____ 15 ____ 15 ____ 25 ns 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 12 ____ 15 ____ 15 ____ 25 ns 0 ____ 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ 5 ____ ns 5 ____ 5 ____ 5 ____ ns WRITE CYCLE tWC tEW tAW Write Cycle Time Chip Enable to End-of-Write Address Valid to End-of-Write tAS Address Set-up Time tWP Write Pulse Width tWR tDW (3) (3) Write Recovery Time Data Valid to End-of-Write (1,2) tHZ Output High-Z Time tDH Data Hold Time (4) tWZ Write Enable to Output in High-Z(1,2) tOW Output Active from End-of-Write (1,2,4) tSWRD SEM Flag Write to Read Time 5 ____ tSPS SEM Flag Contention Window 5 ____ 3199 tbl 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM CE= VIL and SEM = V IH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable Truth Table. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). 6. Industrial temperature: for other speeds, packages and powers contact your sales office. 9 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM (9,10) (9) UB or LB tAS (6) tWP tWR (3) (2) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 3199 drw 07 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9,10) (6) tAS tWR(3) tEW (2) UB or LB(9) R/W tDW tDH DATAIN 3199 drw 08 NOTES: 1. R/W or CE or UB and LB = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP ) of a CE = VIL and a R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = V IL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 10. Refer to Chip Enable Truth Table. 10 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tOH tSAA VALID ADDRESS A0-A2 tAW VALID ADDRESS tWR tACE tEW SEM tSOP tDW DATAIN VALID I/O0 tAS tWP DATAOUT VALID(2) tDH R/W tSWRD tAOE OE Write Cycle Read Cycle 3199 drw 09 NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table. 2. "DATA OUT VALID" represents all I/O's (I/O0-I/O15 ) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 3199 drw 10 NOTES: 1. DOR = D OL = VIL, CER = CE L = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. 11 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7) 7027X20 Com'l Only Symbol Parameter 7027X25 Com'l, Ind. & Military 7027X35 Com'l & Military 7027X55 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 20 ____ 20 ____ 20 ____ 45 ns tBDA BUSY Disable Time from Address Not Matched ____ 20 ____ 20 ____ 20 ____ 40 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 20 ____ 20 ____ 20 ____ 40 ns tBDC BUSY Acce ss Time from Chip Enable High ____ 17 ____ 17 ____ 20 ____ 35 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ 5 ____ ns ____ 30 ____ 30 ____ 35 ____ 40 ns 15 ____ 17 ____ 25 ____ 25 ____ ns tBDD tWH BUSY Disable to Valid Data (3) (5) Write Hold After BUSY BUSY TIMING (M/S=VIL) tWB BUSY Input to Write (4) 0 ____ 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 15 ____ 17 ____ 25 ____ 25 ____ ns ____ 45 ____ 50 ____ 60 ____ 80 ns ____ 30 ____ 35 ____ 45 ____ 65 ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) 3199 tbl 14 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V IH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). 7. Industrial temperature: for other speeds, packages and powers contact your sales office. 12 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5) tWC MATCH ADDR"A" tWP R/W"A" tDW tDH VALID DATAIN "A" t APS (1) MATCH ADDR"B" tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) 3199 drw 11 NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL (refer to Chip Enable Truth Table). 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB (3) BUSY"B" tWH R/W"B" (1) . (2) 3199 drw 12 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB is only for the "Slave" version. 13 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 3199 drw 13 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1) ADDR"A" ADDRESS "N" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 3199 drw 14 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 3. Refer to Chip Enable Truth Table. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2) 7027X20 Com'l Only Symbol Parameter 7027X25 Com'l, Ind & Military 7027X35 Com'l & Military 7027X55 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns 20 ____ 20 ____ 25 ____ 40 ns 20 ____ 20 ____ 25 ____ 40 ns tINS tINR Interrupt Set Time ____ Interrupt Reset Time ____ NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. Industrial temperature: for other speeds, packages and powers contact your sales office. 14 6.42 3199 tbl 15 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1,5) tWC ADDR"A" INTERRUPT SET ADDRESS (2) tAS (3) tWR (4) CE"A" R/W"A" tINS (3) INT"B" 3199 drw 15 tRC INTERRUPT CLEAR ADDRESS ADDR"B" tAS (2) (3) CE"B" OE"B" tINR (3) INT"B" 3199 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. See the Interrupt Truth Table IV. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 5. Refer to Chip Enable Truth Table. Truth Table IV Interrupt Flag(1,4) Left Port R/WL L X X X CEL L X X L OEL X X X L Right Port A14L-A0L 7FFF INTL X R/WR X CER X OER X A14R-A0R X INTR Function (2) Set Right INTR Flag (3) Reset Right INTR Flag L X X X L L 7FFF H X (3) L L X 7FFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag 7FFE L H 3199 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = VIL, then no change. 4. Refer to Chip Enable Truth Table. 15 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table V Address Bus Arbitration(4) Inputs Outputs CEL CER AOL-A14L AOR-A14R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 3199 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7027 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSY R outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of the actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of the actual logic level on the pin. 4. Refer to Chip Enable Truth Table. Truth Table VI Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D15 Left D0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7027. 2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. 3199 tbl 18 Functional Description The IDT7027 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7027 has an automatic power down feature controlled by CE0 and CE1. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FFE (HEX), where a write is defined as CER = R/WR = VIL per Truth Table IV. The left port clears the interrupt through access of address location 7FFE when CEL= OEL= VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFE and 7FFF are not used as mail-boxes by ignoring the interrupt, but as part of the random access memory. Refer to Truth Table IV for the interrupt operation. 16 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7027 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. A15 CE0 MASTER Dual Port RAM BUSYL BUSYR CE1 MASTER Dual Port RAM BUSYL BUSYL BUSYR CE0 SLAVE Dual Port RAM BUSYL BUSYR CE1 SLAVE Dual Port RAM BUSYL BUSYR BUSYR 3199 drw 17 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7027 RAMs. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT7027 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7027 RAM the BUSY pin is an output if the part is used as a Master (M/S pin = VIH), and the BUSY pin is an input if the part used as a Slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7027 is a fast Dual-Port 32K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port SRAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the DualPort SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table II where CE and SEM = VIH. Systems which can best use the IDT7027 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7027's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7027 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to 17 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7027 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table VI). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table VI). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q SEMAPHORE REQUEST FLIP FLOP Q D SEMAPHORE READ D0 WRITE SEMAPHORE READ 3199 drw 18 . Figure 4. IDT7027 Semaphore Logic semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. 18 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A 999 A A Power Speed Package Process/ Temperature Range Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to + 85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML PF G 100-pin TQFP (PN100-1) 108-pin PGA (G108-1) 20 25 35 55 Commercial Only Commercial, Industrial & Military Commercial & Military Commercial & Military S L Standard Power Low Power 7027 512K (32K x 16) Dual-Port RAM NOTE: 1. Industrial temperature range is available on selected TQFP packages in standard power. For other speeds, packages and powers contact your sales office. Speed in nanoseconds 3199 drw 19 Datasheet Document History 1/15/99: 5/19/99: 6/3/99: 11/10/99: 5/22/00: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Pages 4 and 16 Fixed typographical errors Changed drawing format Page 1 Corrected DSC number Replaced IDT logo Page 5 Increased storage temperature parameter Clarified TA parameter Page 6 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 19 6.42 for Tech Support: 831-754-4613 [email protected]