TI1 AM3352 Am335x arm cortex-a8 microprocessors (mpus) Datasheet

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AM335x ARM® Cortex™-A8 Microprocessors (MPUs)
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1 Device Summary
1.1
Features
• Highlights
– 500-MHz, 600-MHz, or 720-MHz ARM®
Cortex™-A8 32-Bit RISC Microprocessor
• NEON™ SIMD Coprocessor
• 32KB/32KB of L1 Instruction/Data Cache
with Single-Error Detection (parity)
• 256KB of L2 Cache with Error Correcting
Code (ECC)
– mDDR(LPDDR)/DDR2/DDR3 Support
– General-Purpose Memory Support (NAND,
NOR, SRAM, etc.) Supporting Up to 16-bit
ECC
– SGX530 Graphics Engine
– Programmable Real-Time Unit Subsystem
– Real-Time Clock (RTC)
– Up to Two USB 2.0 High-Speed OTG Ports
with Integrated PHY
– 10/100/1000 Ethernet Switch Supporting Up
to Two Ports
– Two Controller Area Network Ports (CAN)
– Six UARTs, Two McASPs, Two McSPI, and
Two I2C Ports
– 12-Bit Successive Approximation Register
(SAR) ADC
– Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
– Crypto Hardware Accelerators (AES, SHA,
PKA, RNG)
• MPU Subsystem
– 500-MHz, 600-MHz, or 720-MHz ARM®
Cortex™-A8 32-Bit RISC Microprocessor
– NEON™ SIMD Coprocessor
– 32KB of L1 Instruction Cache with
Single-Error Detection (parity)
– 32KB of L1 Data Cache with Single
Error-Detection (parity)
– 256KB of L2 Cache with Error Correcting
Code (ECC)
– 176KB of On-Chip Boot ROM
– 64KB of Dedicated RAM
– Emulation/Debug
• JTAG
• Embedded Trace Module
• Embedded Trace Buffer
– Interrupt Controller (up to 128 interrupt
requests)
• On-Chip Memory (Shared L3 RAM)
– 64 KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
– Accessible to all Masters
– Supports Retention for Fast Wake-Up
• External Memory Interfaces (EMIF)
– mDDR/DDR2/DDR3 Controller:
• mDDR: 200-MHz Clock (400-MHz Data
Rate)
• DDR2: 266-MHz Clock (532-MHz Data
Rate)
• DDR3: 303-MHz Clock (606-MHz Data
Rate)
• 16-Bit Data Bus
• 1 GB of Total Addressable Space
• Supports One x16, Two x8, or Four x4
Memory Device Configurations
• Supports Retention for Fast Wake-Up
– General-Purpose Memory Controller (GPMC)
• Flexible 8/16-Bit Asynchronous Memory
Interface with Up to seven Chip Selects
(NAND, NOR, Muxed-NOR, SRAM, etc.)
• Uses BCH Code to Support 4-Bit, 8-Bit, or
16-Bit ECC
• Uses Hamming Code to Support 1-Bit
ECC
– Error Locator Module (ELM)
• Used in Conjunction with the GPMC to
Locate Addresses of Data Errors from
1
2
3
4
5
6
7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
ARM is a registered trademark of ARM Ltd or its subsidiaries.
EtherCAT is a registered trademark of EtherCAT Technology Group.
POWERVR is a registered trademark of Imagination Technologies Limited.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
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Syndrome Polynomials Generated Using
a BCH Algorithm
• Supports 4-Bit, 8-Bit, and 16-Bit per
512-byte Block Error Location Based on
BCH Algorithms
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Programmable Real-Time Units (PRUs)
• 32-Bit Load/Store RISC Processor
Capable of Running at 200 MHz
• 8 KB Instruction RAM with Single-Error
Detection (parity)
• 8 KB Data RAM with Single-Error
Detection (parity)
• Single-Cycle 32-Bit Multiplier with 64-Bit
Accumulator
• Enhanced GPIO Module Provides
Shift-In/Out Support and Parallel Latch on
External Signal
– 12 KB of Shared RAM with Single-Error
Detection (parity)
– Three 120-byte Register Banks Accessible
by Each PRU
– Interrupt Controller Module (INTC) for
Handling System Input Events
– Local Interconnect Bus for Connecting
Internal and External Masters to the
Resources Inside the PRUSS
– Peripherals Inside the PRUSS
• One UART Port with Flow Control Pins,
Supports Up to 12 Mbps
• Two MII Ethernet Ports that Support
Industrial Ethernet, such as EtherCAT®
• One MDIO Port
• One Enhanced Capture (eCAP) Module
• Power Reset and Clock Management (PRCM)
Module
– Controls the entry and Exit of Stand-By and
Deep-Sleep Modes
– Responsible for Sleep Sequencing, Power
Domain Switch-Off Sequencing, Wake-Up
Sequencing and Power Domain Switch-On
Sequencing
– Clocks
• Integrated 15-35 MHz High-Frequency
Oscillator Used to Generate a Reference
Clock for Various System and Peripheral
Clocks
• Supports Individual Clock Enable/Disable
Control for Subsystems and Peripherals
to Facilitate Reduced Power
Consumption
• Five ADPLLs to Generate System Clocks
(MPU Subsystem, DDR Interface, USB
and Peripherals [MMC/SD, UART, SPI,
I2C, etc.], L3, L4, Ethernet, GFX [SGX530],
2
Device Summary
LCD Pixel Clock)
– Power
• Two Non-Switchable Power Domains
(Real-Time Clock [RTC], Wake-Up Logic
[WAKE-UP])
• Three Switchable Power Somains (MPU
Subsystem [MPU], SGX530 [GFX],
Peripherals and Infrastructure [PER])
• Implements SmartReflex™ Class 2B for
Core Voltage Scaling Based On Die
Temperature, Process Variation and
Performance (Adaptive Voltage Scaling
[AVS])
• Dynamic Voltage Frequency Scaling
(DVFS)
• Real-Time Clock (RTC)
– Real-Time Date (Day/Month/Year/Day of
Week) and Time (Hours/Minutes/Seconds)
Information
– Internal 32.768-kHz Oscillator, RTC Logic
and 1.1-V Internal LDO
– Independent Power-on-Reset
(RTC_PWRONRSTn) Input
– Dedicated Input Pin (EXT_WAKEUP) for
External Wake Events
– Programmable Alarm Can be Used to
Generate Internal Interrupts to the PRCM (for
Wake Up) or Cortex-A8 (for Event
Notification)
– Programmable alarm Can be Used with
External Output (PMIC_POWER_EN) to
Enable the Power Management IC to Restore
Non-RTC Power Domains
• Peripherals
– Up to Two USB 2.0 High-Speed OTG Ports
with Integrated PHY
– Up to Two Industrial Gigabit Ethernet MACs
(10/100/1000 Mbps)
• Integrated Switch
• Each MAC Supports MII/RMII/RGMII and
MDIO Interfaces
• Ethernet MACs and Switch Can Operate
Independent of Other Functions
• IEEE 1588 Precision Time Protocol (PTP)
– Up to Two Controller-Area Network (CAN)
Ports
• Supports CAN Version 2 Parts A and B
– Up to Two Multichannel Audio Serial Ports
(McASP)
• Transmit/Receive Clocks Up to 50 MHz
• Up to Four Serial Data Pins per McASP
Port with Independent TX/RX Clocks
• Supports Time Division Multiplexing
(TDM), Inter-IC Sound (I2S), and similar
Formats
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–
–
–
–
–
–
–
–
–
Supports Digital Audio Interface
Transmission (SPDIF, IEC60958-1, and
AES-3 Formats)
• FIFO Buffers for Transmit and Receive
(256 bytes)
Up to Six UARTs
• All UARTs Support IrDA, CIR and RTS,
CTS Flow Control
• UART1 Supports Full Modem control
Up to Two Master/Slave McSPI serial
Interfaces
• Up to Two Chip Selects
• Up to 48 MHz
Up to Three MMC/SD/SDIO Ports
• 1-Bit, 4-Bit and 8-Bit MMC/SD/SDIO
Modes
• MMCSD0 has dedicated Power Rail for
1.8-V or 3.3-V Operation
• Up to 48-MHz Data Transfer Rate
• Supports Card Detect and Write Protect
• Complies with MMC4.3 and SD/SDIO 2.0
Specifications
Up to Three I2C Master/Slave Interfaces
• Standard Mode (up to 100 kHz)
• Fast Mode (up to 400 kHz)
Up to Four Banks of General-Purpose IO
(GPIO)
• 32 GPIOs per Bank (Multiplexed with
Other Functional Pins)
• GPIOs Can be Used as Interrupt Inputs
(Up to Two Interrupt Inputs per Bank)
Up to Three External DMA Event Inputs That
Can Also be Used as Interrupt Inputs
Seven 32-Bit General-Purpose Timers
• DMTIMER1 is a 1-ms Timer Used for
Operating System (OS) Ticks
• DMTIMER4 - DMTIMER7 are Pinned Out
One Watchdog Timer
SGX530 3D Graphics Engine
• Tile-Based Architecture Delivering Up to
20 MPloy/sec
• Universal Scalable Shader Engine is a
Multi-Threaded Engine Incorporating
Pixel and Vertex Shader Functionality
• Advanced Shader Feature Set in Excess
of Microsoft VS3.0, PS3.0 and OGL2.0
• Industry Standard API Support of
Direct3D Mobile, OGL-ES 1.1 and 2.0,
OpenVG 1.0, and OpenMax
• Fine-Grained Task Switching, Load
Balancing and Power Management
• Advanced Geometry DMA Driven
Operation for Minimum CPU Interaction
• Programmable High-Quality Image
anti-Aliasing
Fully Virtualized Memory Addressing for
OS Operation in a Unified Memory
Architecture
– LCD Controller
• Up to 24-Bits Data Output; 8-Bits per
Pixel (RGB)
• Up to WXGA (1366x768) Resolution
• Integrated LCD Interface Display Driver
(LIDD) Controller
• Integrated Raster Controller
• Integrated DMA Engine to Pull Data from
the External Frame Buffer without
Burdening the Processor via Interrupts or
a Firmware Timer
• 512-Word Deep Internal FIFO
• Supported Display Types:
– Character Displays - Uses LCD
Interface Display Driver (LIDD)
Controller to Program these Displays
– Passive Matrix LCD Displays - Uses
LCD Raster Display Controller to
Provide Timing and Data for Constant
Graphics Refresh to a Passive Display
– Active Matrix LCD Displays - Uses
External Frame Buffer Space and the
Internal DMA Engine to Drive
Streaming Data to the Panel. Maximum
Resolution is WXGA (1366x768) at
60-Hz Refresh Rate
– 12-Bit Successive Approximation Register
(SAR) ADC
• 100K Samples per Second
• Input Can be Selected from any of the
Eight Analog Inputs Multiplexed Through
an 8:1 analog Switch
• Can be Configured to Operate as a 4-wire,
5-wire, or 8-wire Resistive Touch Screen
Controller (TSC) Interface
– Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
• Configurable as Three Capture Inputs or
Three Auxiliary PWM Outputs
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
• Dedicated 16-Bit Time-Base Counter with
Time and Frequency Controls
• Configurable as Six Single-Ended, Six
Dual-Edge Symmetric, or Three
Dual-Edge Asymmetric Outputs
– Up to Three 32-Bit Enhanced Quadrature
Pulse Encoder (eQPE) Modules
• Device Identification
– Contains Electrical fuse Farm (FuseFarm) of
Which Some Bits are Factory Programmable
•
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Device Summary
3
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• Production ID
• Device Part Number (Unique JTAG ID)
• Device Revision (readable by Host ARM)
• Debug Interface Support
– JTAG/cJTAG for ARM (Cortex-A8 and
PRCM), PRU Debug
– Embedded Trace Module (ETM) and
Embedded Trace Buffer (ETB)
– Supports Device Boundary Scan
– Supports IEEE1500
• DMA
– On-Chip Enhanced DMA Controller (EDMA)
has Three Third-Party Transfer Controllers
(TPTC) and One Third-Party Channel
Controller (TPCC), Which Supports Up to 64
Programmable Logical Channels and Eight
QDMA Channels. EDMA is Used for:
• Transfers to/from On-Chip Memories
• Transfers to/from External Storage (EMIF,
General-Purpose Memory Controller,
Slave Peripherals)
• Inter-Processor Communication (IPC)
1.2
•
•
•
•
•
•
•
•
•
– Integrates Hardware-Based Mailbox for IPC
and Spinlock for Process Synchronization
Between the Cortex-A8, PRCM, and Each
PRU
• Mailbox Registers that Generate
Interrupts
– Four Initiators (Cortex-A8, PRCM,
PRU0, PRU1)
• Spinlock has 128 Software-Assigned
Lock Registers
• Security
– Crypto Hardware accelerators (AES, SHA,
PKA, RNG)
• Boot Modes
– Boot Mode is Selected via Boot
Configuration Pins Latched on the Rising
Edge of the PWRONRSTn Reset Input Pin
• Packages:
– 298-Pin S-PBGA-N298 package
(ZCE Suffix), 0.65-mm Ball Pitch
– 324-Pin S-PBGA-N324 package
(ZCZ Suffix), 0.80-mm Ball Pitch
Applications
Gaming Peripherals
Home and Industrial Automation
Consumer Medical Appliances
Printers
Smart Toll Systems
Connected Vending Machines
Weighing Scales
Educational Consoles
Advanced Toys
1.3
Description
The AM335x microprocessors based on the ARM Cortex-A8 are enhanced with image, graphics
processing, peripherals and industrial interface options such as etherCAT and Profibus. The device
supports the following high-level operating systems (OSs), that are available free of charge from TI:
• Linux®
• Windows® CE
• Android™
The AM335x microrocessor contains these subsystems:
• Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor.
• POWERVR® SGX Graphics Accelerator subsystem for 3D graphics acceleration to support display and
gaming effects.
• Programmable Real-Time Unit Subsystem (PRUSS) enables the user to create a variety of digital
resources beyond native peripherals of the device. In addition, the PRUSS is separate from the ARM
core. This allows independent operation and clocking to give the device greater flexibility in complex
system solutions.
Note: The subsystem available on this device is the next-generation PRUSS (PRUSSv2).
4
Device Summary
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1.4
Functional Block Diagram
The AM335x microrocessor functional block diagram is shown in Figure 1-1.
ARM
Cortex-A8
(A)(B)(C)
500/600/720 MHz
Graphics
PowerVR
SGX
3D GFX
32K/32K L1 w/SED
256K L2 w/ECC
Crypto
176K ROM 64K RAM
64K
shared
RAM
Display
24-bit LCD controller (WXGA)
Touch screen controller
PRU subsystem
12K RAM
PRU x2
w/SED
200 MHz
8K/8K w/SED Peripherals
L3/L4 interconnect
System
UART x6
SPI x2
eDMA
Timers x7
WDT
2
I C x3
McASP x2
(4 channel)
CAN x2
(Ver. 2 A and B)
USB 2.0 HS
OTG + PHY x2
RTC
eHRPWM x3
eQEP x3
eCAP x3
ADC (8 channel)
12-bit SAR
JTAG /
ETM / ETB
Parallel
MMC/SD/
SDIO x3
GPIO
PRODUCT PREVIEW
Serial
Crystal
Oscillator x2
PRCM
EMAC (2-port) 10M/100M/1G
IEEE1588, and switch
(MII, RMII, RGMII)
Memory interface
LPDDR1 / DDR2 / DDR3
(16-bit, 200 / 266 / 303 MHz)
NAND/NOR (16-bit ECC)
A. Nominal voltage condition (1.1 V); available on ZCE and ZCZ packages.
B. Overdrive voltage condition (1.2 V); only available on ZCZ package.
C. Turbo voltage condition (1.26 V); only available on ZCZ package.
Figure 1-1. AM335x Functional Block Diagram
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Device Summary
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1
2
3
4
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........................................ 1
1.1
Features .............................................. 1
1.2
Applications .......................................... 4
1.3
Description ........................................... 4
1.4
Functional Block Diagram ............................ 5
Terminal Description ................................... 7
2.1
Pin Assignments ..................................... 7
2.2
Ball Characteristics ................................. 15
2.3
Signal Description .................................. 47
Device Operating Conditions ....................... 74
3.1
Absolute Maximum Ratings ........................ 74
3.2
Recommended Operating Conditions .............. 77
3.3
DC Electrical Characteristics ....................... 80
3.4
External Capacitors ................................. 84
Power and Clocking ................................... 88
4.1
Power Supplies ..................................... 88
4.2
Clock Specifications ................................ 93
Device Summary
5
Peripheral Information and Timings
5.1
5.2
5.3
6
.......................
LCD Controller (LCDC) ............................
5.4
External Memory Interfaces
5.5
5.6
mDDR(LPDDR)/DDR2/DDR3 Memory Controller
99
.....................................................
.............
Device Support ....................................
Documentation Support ...........................
107
129
145
Device and Documentation Support
155
6.1
155
6.2
7
...............
Parameter Information .............................. 99
Recommended Clock and Control Signal Transition
Behavior ............................................ 99
Ethernet Media Access Controller (EMAC)/Switch
..................................................... 100
156
Mechanical Packaging and Orderable
Information ............................................ 158
7.1
7.2
7.3
.......
Via Channel .......................................
Packaging Information ............................
Thermal Data for ZCE and ZCZ Packages
158
158
158
PRODUCT PREVIEW
6
Contents
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2 Terminal Description
2.1
Pin Assignments
NOTE
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An
attempt is made to use "ball" only when referring to the physical package.
2.1.1
ZCE Package Pin Maps (Top View)
PRODUCT PREVIEW
The pin maps below show the pin assignments on the ZCE package in three sections (left, middle, and
right).
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Terminal Description
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Table 2-1. ZCE Pin Map [Section Left - Top View]
PRODUCT PREVIEW
A
B
C
D
E
F
19
VSS
I2C0_SCL
UART1_TXD
UART1_RTSn
UART0_RXD
UART0_CTSn
18
SPI0_SCLK
SPI0_D0
I2C0_SDA
UART1_RXD
ECAP0_IN_PWM0_OUT
UART0_RTSn
17
SPI0_CS0
SPI0_D1
EXTINTn
XXXX
UART1_CTSn
UART0_TXD
16
WARMRSTn
SPI0_CS1
XXXX
XXXX
XXXX
VDDS
15
EMU0
XDMA_EVENT_INTR1
XDMA_EVENT_INTR0
XXXX
PWRONRSTn
XXXX
14
TDO
TCK
TMS
EMU1
XXXX
VDDSHV6
13
TRSTn
TDI
CAP_VBB_MPU
CAP_VDD_SRAM_MPU
VDDSHV6
VSS
12
AIN7
AIN5
VDDS_SRAM_MPU_BB
VDDS
VDDSHV6
VSS
11
AIN1
AIN3
XXXX
XXXX
VDDSHV6
VDD_CORE
10
AIN6
CAP_VDD_SRAM_CORE
VDDS_SRAM_CORE_BG
VSS
VSS
XXXX
9
VREFP
VREFN
XXXX
XXXX
VSS
VDD_CORE
8
AIN2
AIN0
AIN4
VSSA_ADC
VSS
VSS
7
RTC_KALDO_ENn
RTC_PWRONRSTn
PMIC_POWER_EN
VDDA_ADC
VSS
VSS
6
RTC_XTALIN
RESERVED
VDDS_RTC
CAP_VDD_RTC
XXXX
VSS
5
RTC_XTALOUT
EXT_WAKEUP
VDDS_PLL_DDR
XXXX
DDR_A4
XXXX
4
DDR_WEn
DDR_BA2
XXXX
XXXX
XXXX
DDR_A12
3
DDR_BA0
DDR_A3
DDR_A8
XXXX
DDR_A15
DDR_A0
2
DDR_A5
DDR_A9
DDR_CK
DDR_A7
DDR_A10
DDR_RASn
1
VSS
DDR_A6
DDR_CKn
DDR_A2
DDR_BA1
DDR_CASn
Pin map section location
Left
8
Terminal Description
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G
H
J
K
L
M
19
MMC0_CLK
MMC0_DAT3
MII1_COL
MII1_RX_ER
MII1_RX_DV
MII1_RX_CLK
18
MMC0_DAT0
MMC0_DAT2
MII1_CRS
RMII1_REF_CLK
MII1_TXD0
MII1_TXD1
17
MMC0_CMD
MMC0_DAT1
XXXX
MII1_TX_EN
XXXX
MII1_TXD3
16
USB0_DRVVBUS
VDDS_PLL_MPU
XXXX
VDD_CORE
XXXX
VDDS
15
VDDSHV4
VDDSHV4
VSS
VDD_CORE
VSS
VDDSHV5
14
XXXX
VDDSHV4
VSS
XXXX
VSS
VDDSHV5
13
XXXX
VDD_CORE
VDD_CORE
XXXX
VDD_CORE
VDD_CORE
12
VSS
VDD_CORE
VDD_CORE
VSS
VDD_CORE
VDD_CORE
11
VDD_CORE
VSS
VSS
VSS
VSS
VSS
10
XXXX
VSS
XXXX
XXXX
XXXX
VSS
9
VDD_CORE
VSS
VSS
VSS
VSS
VSS
8
VSS
VDD_CORE
VDD_CORE
VSS
VDD_CORE
VDD_CORE
7
XXXX
VDD_CORE
VDD_CORE
XXXX
VDD_CORE
VDD_CORE
6
XXXX
VDDS_DDR
VSS
XXXX
VSS
VDDS_DDR
5
VDDS_DDR
VDDS_DDR
VSS
VDDS_DDR
VSS
VDDS_DDR
4
DDR_A11
DDR_VREF
XXXX
VDDS_DDR
XXXX
DDR_D11
3
DDR_CKE
DDR_A14
XXXX
DDR_DQM1
XXXX
DDR_D10
2
DDR_RESETn
DDR_CSn0
DDR_A1
DDR_D8
DDR_DQSn1
DDR_D12
1
DDR_ODT
DDR_A13
DDR_VTP
DDR_D9
DDR_DQS1
DDR_D13
PRODUCT PREVIEW
Table 2-2. ZCE Pin Map [Section Middle - Top View]
Pin map section location
Middle
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Table 2-3. ZCE Pin Map [Section Right - Top View]
PRODUCT PREVIEW
N
P
R
T
U
V
W
19
MII1_TX_CLK
MII1_RXD1
MDC
USB0_VBUS
USB0_DP
USB0_ID
VSS
18
MII1_TXD2
MII1_RXD0
VDDA3P3V_USB0
USB0_CE
USB0_DM
GPMC_BEn1
GPMC_WPn
17
MII1_RXD3
MDIO
VDDA1P8V_USB0
XXXX
GPMC_CSn3
GPMC_AD15
GPMC_AD14
16
MII1_RXD2
VSSA_USB
XXXX
XXXX
XXXX
GPMC_CLK
GPMC_AD9
15
VDDSHV5
XXXX
GPMC_WAIT0
XXXX
GPMC_CSn2
GPMC_AD8
GPMC_AD7
14
XXXX
VSS
XXXX
VDDS
GPMC_AD6
GPMC_CSn1
GPMC_AD5
13
XXXX
VSS
VDDSHV1
GPMC_AD13
GPMC_AD12
GPMC_AD4
GPMC_AD3
12
VSS
VSS
VDDSHV1
GPMC_AD10
GPMC_AD11
GPMC_AD2
XTALOUT
11
VDD_CORE
VDD_CORE
VDDSHV1
XXXX
XXXX
VSS_OSC
XTALIN
10
XXXX
XXXX
VSS
VSS
VDDS_OSC
GPMC_ADVn_ALE
GPMC_AD0
9
VDD_CORE
VDD_CORE
VDDSHV1
XXXX
XXXX
GPMC_AD1
GPMC_OEn_REn
8
VSS
VSS
VDDSHV1
VDDS_PLL_CORE_LCD
GPMC_WEn
GPMC_BEn0_CLE
GPMC_CSn0
7
XXXX
VSS
VDDSHV6
LCD_HSYNC
LCD_VSYNC
LCD_DATA15
LCD_AC_BIAS_EN
6
XXXX
VDDSHV6
XXXX
VDDS
LCD_DATA13
LCD_DATA12
LCD_DATA14
5
VDDS_DDR
XXXX
VPP
XXXX
LCD_DATA10
LCD_DATA11
LCD_PCLK
4
DDR_D0
DDR_D1
XXXX
XXXX
XXXX
LCD_DATA8
LCD_DATA9
3
DDR_DQM0
DDR_D4
DDR_D7
XXXX
LCD_DATA7
LCD_DATA6
LCD_DATA5
2
DDR_D14
DDR_D2
DDR_DQSn0
DDR_D6
LCD_DATA1
LCD_DATA3
LCD_DATA4
1
DDR_D15
DDR_D3
DDR_DQS0
DDR_D5
LCD_DATA0
LCD_DATA2
VSS
Pin map section location
Right
10
Terminal Description
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2.1.2
ZCZ Package Pin Maps (Top View)
PRODUCT PREVIEW
The pin maps below show the pin assignments on the ZCZ package in three sections (left, middle, and
right).
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Terminal Description
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Table 2-4. ZCZ Pin Map [Section Left - Top View]
PRODUCT PREVIEW
A
B
C
D
E
F
18
VSS
EXTINTn
ECAP0_IN_PWM0_OUT
UART1_CTSn
UART0_CTSn
MMC0_DAT2
17
SPI0_SCLK
SPI0_D0
I2C0_SDA
UART1_RTSn
UART0_RTSn
MMC0_DAT3
16
SPI0_CS0
SPI0_D1
I2C0_SCL
UART1_RXD
UART0_TXD
USB0_DRVVBUS
15
XDMA_EVENT_INTR0
PWRONRSTn
SPI0_CS1
UART1_TXD
UART0_RXD
USB1_DRVVBUS
14
MCASP0_AHCLKX
EMU1
EMU0
XDMA_EVENT_INTR1
VDDS
VDDSHV6
13
MCASP0_ACLKX
MCASP0_FSX
MCASP0_FSR
MCASP0_AXR1
VDDSHV6
VDD_MPU
12
TCK
MCASP0_ACLKR
MCASP0_AHCLKR
MCASP0_AXR0
VDDSHV6
VDD_MPU
11
TDO
TDI
TMS
CAP_VDD_SRAM_MPU
VDDSHV6
VDD_MPU
10
WARMRSTn
TRSTn
CAP_VBB_MPU
VDDS_SRAM_MPU_BB
VDDSHV6
VDD_MPU
9
VREFN
VREFP
AIN7
CAP_VDD_SRAM_CORE
VDDS_SRAM_CORE_BG
VDDS
8
AIN6
AIN5
AIN4
VDDA_ADC
VSSA_ADC
VSS
7
AIN3
AIN2
AIN1
VDDS_RTC
VDDS_PLL_DDR
VDD_CORE
6
RTC_XTALIN
AIN0
PMIC_POWER_EN
CAP_VDD_RTC
VDDS
VDD_CORE
5
VSS_RTC
RTC_PWRONRSTn
EXT_WAKEUP
DDR_A6
VDDS_DDR
VDDS_DDR
4
RTC_XTALOUT
RTC_KALDO_ENn
DDR_BA0
DDR_A8
DDR_A2
DDR_A10
3
RESERVED
DDR_BA2
DDR_A3
DDR_A15
DDR_A12
DDR_A0
2
VDD_MPU_MON
DDR_WEn
DDR_A4
DDR_CK
DDR_A7
DDR_A11
1
VSS
DDR_A5
DDR_A9
DDR_CKn
DDR_BA1
DDR_CASn
Pin map section location
Left
12
Terminal Description
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G
H
J
K
L
M
18
MMC0_CMD
RMII1_REF_CLK
MII1_TXD3
MII1_TX_CLK
MII1_RX_CLK
MDC
17
MMC0_CLK
MII1_CRS
MII1_RX_DV
MII1_TXD0
MII1_RXD3
MDIO
16
MMC0_DAT0
MII1_COL
MII1_TX_EN
MII1_TXD1
MII1_RXD2
MII1_RXD0
15
MMC0_DAT1
VDDS_PLL_MPU
MII1_RX_ER
MII1_TXD2
MII1_RXD1
USB0_CE
14
VDDSHV6
VDDSHV4
VDDSHV4
VDDSHV5
VDDSHV5
VSSA_USB
13
VDD_MPU
VDD_MPU
VDD_MPU
VDDS
VSS
VDD_CORE
12
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VSS
11
VSS
VDD_CORE
VSS
VSS
VSS
VDD_CORE
10
VDD_CORE
VSS
VSS
VSS
VSS
VSS
9
VSS
VSS
VSS
VSS
VDD_CORE
VSS
8
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VSS
7
VDD_CORE
VSS
VSS
VSS
VDD_CORE
VSS
6
VDD_CORE
VSS
VSS
VDD_CORE
VDD_CORE
VSS
5
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VPP
4
DDR_RASn
DDR_A14
DDR_VREF
DDR_D12
DDR_D14
DDR_D1
3
DDR_CKE
DDR_A13
DDR_VTP
DDR_D11
DDR_D13
DDR_D0
2
DDR_RESETn
DDR_CSn0
DDR_DQM1
DDR_D10
DDR_DQSn1
DDR_DQM0
1
DDR_ODT
DDR_A1
DDR_D8
DDR_D9
DDR_DQS1
DDR_D15
PRODUCT PREVIEW
Table 2-5. ZCZ Pin Map [Section Middle - Top View]
Pin map section location
Middle
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Terminal Description
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Table 2-6. ZCZ Pin Map [Section Right - Top View]
PRODUCT PREVIEW
N
P
R
T
U
V
18
USB0_DM
USB1_CE
USB1_DM
USB1_VBUS
GPMC_BEn1
VSS
17
USB0_DP
USB1_ID
USB1_DP
GPMC_WAIT0
GPMC_WPn
GPMC_A11
16
VDDA1P8V_USB0
USB0_ID
VDDA1P8V_USB1
GPMC_A10
GPMC_A9
GPMC_A8
15
VDDA3P3V_USB0
USB0_VBUS
VDDA3P3V_USB1
GPMC_A7
GPMC_A6
GPMC_A5
14
VSSA_USB
VDDS
GPMC_A4
GPMC_A3
GPMC_A2
GPMC_A1
13
VDD_CORE
VDDSHV3
GPMC_A0
GPMC_CSn3
GPMC_AD15
GPMC_AD14
12
VDD_CORE
VDDSHV3
GPMC_AD13
GPMC_AD12
GPMC_AD11
GPMC_CLK
11
VSS
VDDSHV2
VDDS_OSC
GPMC_AD10
XTALOUT
VSS_OSC
10
VSS
VDDSHV2
VDDS_PLL_CORE_LCD
GPMC_AD9
GPMC_AD8
XTALIN
9
VDD_CORE
VDDS
GPMC_AD6
GPMC_AD7
GPMC_CSn1
GPMC_CSn2
8
VDD_CORE
VDDSHV1
GPMC_AD2
GPMC_AD3
GPMC_AD4
GPMC_AD5
7
VSS
VDDSHV1
GPMC_ADVn_ALE
GPMC_OEn_REn
GPMC_AD0
GPMC_AD1
6
VDDS
VDDSHV6
LCD_AC_BIAS_EN
GPMC_BEn0_CLE
GPMC_WEn
GPMC_CSn0
5
VDDSHV6
VDDSHV6
LCD_HSYNC
LCD_DATA15
LCD_VSYNC
LCD_PCLK
4
DDR_D5
DDR_D7
LCD_DATA3
LCD_DATA7
LCD_DATA11
LCD_DATA14
3
DDR_D4
DDR_D6
LCD_DATA2
LCD_DATA6
LCD_DATA10
LCD_DATA13
2
DDR_D3
DDR_DQSn0
LCD_DATA1
LCD_DATA5
LCD_DATA9
LCD_DATA12
1
DDR_D2
DDR_DQS0
LCD_DATA0
LCD_DATA4
LCD_DATA8
VSS
Pin map section location
Right
14
Terminal Description
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2.2
Ball Characteristics
Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE
column.
(b) Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are
effectively used for alternate functions, while some modes are not used and do not correspond to a
functional configuration.
5. TYPE: Signal direction
– I = Input
– O = Output
– I/O = Input/Output
– D = Open drain
– DS = Differential
– A = Analog
– PWR = Power
– GND = Ground
Note: In the safe_mode, the buffer is configured in high-impedance.
6. BALL RESET STATE: The state of the terminal at the power-on reset.
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
7. BALL RESET REL. STATE: The state of the terminal at the release of the System Control Module
reset (PRCM CORE_RSTPWRON_RET reset signal).
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
– Z: High-impedance.
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
8. RESET REL. MODE: The mode is automatically configured at the release of the System Control
Module reset (PRCM CORE_RSTPWRON_RET reset signal).
9. POWER: The voltage supply that powers the terminal’s I/O buffers.
10. HYS: Indicates if the input buffer is with hysteresis.
11. BUFFER STRENGTH: Drive strength of the associated output buffer.
12. PULLUP/DOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and
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Terminal Description
15
PRODUCT PREVIEW
The following table identifies the terminal characteristics signals multiplexed on each terminal for the ZCZ
and ZCE packages. The table column headers are explained below:
1. BALL NUMBER: Package ball number(s) associated with each signal(s).
2. PIN NAME: The name of the package pin or terminal.
Note: The table does not take into account subsystem terminal multiplexing options.
3. SIGNAL NAME: The signal name for that pin in the mode being used.
4. MODE: Multiplexing mode number.
(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the
terminal corresponds to the name of the terminal. There is always a function mapped on the
primary mode. Notice that primary mode is not necessarily the default mode.
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pulldown resistors can be enabled or disabled via software.
13. I/O CELL: IO cell information.
Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration.
PRODUCT PREVIEW
16
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages)
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
B8
B6
AIN0
AIN0
0
A (13)
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
50
NA
Analog
A11
C7
AIN1
AIN1
0
A (12)
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
50
NA
Analog
A8
B7
AIN2
AIN2
0
A (12)
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
50
NA
Analog
B11
A7
AIN3
AIN3
0
A (11)
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
50
NA
Analog
C8
C8
AIN4
AIN4
0
A (11)
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
50
NA
Analog
B12
B8
AIN5
AIN5
0
A
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
A10
A8
AIN6
AIN6
0
A
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
A12
C9
AIN7
AIN7
0
A
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
C13
C10
CAP_VBB_MPU
CAP_VBB_MPU
NA
A
D6
D6
CAP_VDD_RTC
CAP_VDD_RTC
NA
A
B10
D9
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_CORE
NA
A
D13
D11
CAP_VDD_SRAM_MPU
CAP_VDD_SRAM_MPU
NA
A
F3
F3
DDR_A0
ddr_a0
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
J2
H1
DDR_A1
ddr_a1
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
D1
E4
DDR_A2
ddr_a2
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
B3
C3
DDR_A3
ddr_a3
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
E5
C2
DDR_A4
ddr_a4
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
A2
B1
DDR_A5
ddr_a5
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
B1
D5
DDR_A6
ddr_a6
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
D2
E2
DDR_A7
ddr_a7
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
C3
D4
DDR_A8
ddr_a8
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
B2
C1
DDR_A9
ddr_a9
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
E2
F4
DDR_A10
ddr_a10
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
G4
F2
DDR_A11
ddr_a11
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
Terminal Description
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17
PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
PRODUCT PREVIEW
F4
E3
DDR_A12
ddr_a12
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
H1
H3
DDR_A13
ddr_a13
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
H3
H4
DDR_A14
ddr_a14
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
E3
D3
DDR_A15
ddr_a15
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
A3
C4
DDR_BA0
ddr_ba0
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
E1
E1
DDR_BA1
ddr_ba1
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
B4
B3
DDR_BA2
ddr_ba2
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
F1
F1
DDR_CASn
ddr_casn
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
C2
D2
DDR_CK
ddr_ck
0
O
L
0
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
G3
G3
DDR_CKE
ddr_cke
0
O
L
0
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
C1
D1
DDR_CKn
ddr_nck
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
H2
H2
DDR_CSn0
ddr_csn0
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
N4
M3
DDR_D0
ddr_d0
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
P4
M4
DDR_D1
ddr_d1
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
P2
N1
DDR_D2
ddr_d2
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
P1
N2
DDR_D3
ddr_d3
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
P3
N3
DDR_D4
ddr_d4
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
T1
N4
DDR_D5
ddr_d5
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
T2
P3
DDR_D6
ddr_d6
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
R3
P4
DDR_D7
ddr_d7
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
K2
J1
DDR_D8
ddr_d8
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
K1
K1
DDR_D9
ddr_d9
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
M3
K2
DDR_D10
ddr_d10
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
18
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
M4
K3
DDR_D11
ddr_d11
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
M2
K4
DDR_D12
ddr_d12
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
M1
L3
DDR_D13
ddr_d13
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
N2
L4
DDR_D14
ddr_d14
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
N1
M1
DDR_D15
ddr_d15
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
N3
M2
DDR_DQM0
ddr_dqm0
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
K3
J2
DDR_DQM1
ddr_dqm1
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
R1
P1
DDR_DQS0
ddr_dqs0
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
L1
L1
DDR_DQS1
ddr_dqs1
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
R2
P2
DDR_DQSn0
ddr_dqsn0
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
L2
L2
DDR_DQSn1
ddr_dqsn1
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
8
PU/PD
LVCMOS/SSTL/
HSTL
G1
G1
DDR_ODT
ddr_odt
0
O
L
0
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
F2
G4
DDR_RASn
ddr_rasn
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
G2
G2
DDR_RESETn
ddr_resetn
0
O
L
0
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
H4
J4
DDR_VREF
ddr_vref
0
AP (9) NA
NA
NA
VDDS_DDR /
VDDS_DDR
NA
NA
NA
Analog
J1
J3
DDR_VTP
ddr_vtp
0
I
NA
NA
NA
VDDS_DDR /
VDDS_DDR
NA
NA
NA
Analog
A4
B2
DDR_WEn
ddr_wen
0
O
H
1
0
VDDS_DDR /
VDDS_DDR
NA
8
PU/PD
LVCMOS/SSTL/
HSTL
E18
C18
ECAP0_IN_PWM0_OUT
eCAP0_in_PWM0_out
0
I/O
Z
L
7
4
PU/PD
LVCMOS
1
O
VDDSHV6 /
VDDSHV6
Yes
uart3_txd
spi1_cs1
2
I/O
pr1_ecap0_ecap_capin_apwm_o
3
I/O
spi1_sclk
4
I/O
mmc0_sdwp
5
I
xdma_event_intr2
6
I
gpio0_7
7
I/O
EMU0
0
I/O
H
H
0
6
PU/PD
LVCMOS
7
I/O
VDDSHV6 /
VDDSHV6
Yes
gpio3_7
A15
C14
EMU0
(10)
Terminal Description
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19
PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
D14
B14
PIN NAME [2]
EMU1
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
EMU1
0
I/O
gpio3_8
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
H
H
0
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
PRODUCT PREVIEW
C17
B18
EXTINTn
nNMI
0
I
Z
H
0
VDDSHV6 /
VDDSHV6
Yes
NA
PU/PD
LVCMOS
B5
C5
EXT_WAKEUP
EXT_WAKEUP
0
I
L
L
0
VDDS_RTC /
VDDS_RTC
Yes
NA
NA
LVCMOS
NA
R13
GPMC_A0
gpmc_a0
0
O
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
gmii2_txen
1
O
rgmii2_tctl
2
O
rmii2_txen
3
O
gpmc_a16
4
O
pr1_mii_mt1_clk
5
I
ehrpwm1_tripzone_input
6
I
gpio1_16
7
I/O
gpmc_a1
0
O
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
gmii2_rxdv
1
I
rgmii2_rctl
2
I
mmc2_dat0
3
I/O
gpmc_a17
4
O
pr1_mii1_txd3
5
O
ehrpwm0_synco
6
O
gpio1_17
7
I/O
gpmc_a2
0
O
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
gmii2_txd3
1
O
rgmii2_td3
2
O
mmc2_dat1
3
I/O
gpmc_a18
4
O
pr1_mii1_txd2
5
O
ehrpwm1A
6
O
gpio1_18
7
I/O
gpmc_a3
0
O
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
gmii2_txd2
1
O
rgmii2_td2
2
O
mmc2_dat2
3
I/O
gpmc_a19
4
O
pr1_mii1_txd1
5
O
ehrpwm1B
6
O
gpio1_19
7
I/O
NA
NA
NA
20
V14
U14
T14
GPMC_A1
GPMC_A2
GPMC_A3
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
NA
NA
NA
NA
R14
V15
U15
T15
PIN NAME [2]
GPMC_A4
GPMC_A5
GPMC_A6
GPMC_A7
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gpmc_a4
0
O
gmii2_txd1
1
O
rgmii2_td1
2
O
rmii2_txd1
3
O
gpmc_a20
4
O
pr1_mii1_txd0
5
O
eQEP1A_in
6
I
gpio1_20
7
I/O
gpmc_a5
0
O
gmii2_txd0
1
O
rgmii2_td0
2
O
rmii2_txd0
3
O
gpmc_a21
4
O
pr1_mii1_rxd3
5
I
eQEP1B_in
6
I
gpio1_21
7
I/O
gpmc_a6
0
O
gmii2_txclk
1
I
rgmii2_tclk
2
O
mmc2_dat4
3
I/O
gpmc_a22
4
O
pr1_mii1_rxd2
5
I
eQEP1_index
6
I/O
gpio1_22
7
I/O
gpmc_a7
0
O
gmii2_rxclk
1
I
rgmii2_rclk
2
I
mmc2_dat5
3
I/O
gpmc_a23
4
O
pr1_mii1_rxd1
5
I
eQEP1_strobe
6
I/O
gpio1_23
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
21
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
NA
NA
PRODUCT PREVIEW
NA
NA
W10
V9
22
V16
U16
T16
V17
U7
V7
PIN NAME [2]
GPMC_A8
GPMC_A9
GPMC_A10
GPMC_A11
GPMC_AD0
GPMC_AD1
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gpmc_a8
0
O
gmii2_rxd3
1
I
rgmii2_rd3
2
I
mmc2_dat6
3
I/O
gpmc_a24
4
O
pr1_mii1_rxd0
5
I
mcasp0_aclkx
6
I/O
gpio1_24
7
I/O
gpmc_a9
0
O
gmii2_rxd2
1
I
rgmii2_rd2
2
I
mmc2_dat7
3
I/O
gpmc_a25
4
O
pr1_mii_mr1_clk
5
I
mcasp0_fsx
6
I/O
gpio1_25
7
I/O
gpmc_a10
0
O
gmii2_rxd1
1
I
rgmii2_rd1
2
I
rmii2_rxd1
3
I
gpmc_a26
4
O
pr1_mii1_rxdv
5
I
mcasp0_axr0
6
I/O
gpio1_26
7
I/O
gpmc_a11
0
O
gmii2_rxd0
1
I
rgmii2_rd0
2
I
rmii2_rxd0
3
I
gpmc_a27
4
O
pr1_mii1_rxer
5
I
mcasp0_axr1
6
I/O
gpio1_27
7
I/O
gpmc_ad0
0
I/O
mmc1_dat0
1
I/O
gpio1_0
7
I/O
gpmc_ad1
0
I/O
mmc1_dat1
1
I/O
gpio1_1
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV3 Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
V12
W13
V13
W14
U14
W15
V15
W16
R8
T8
U8
V8
R9
T9
U10
T10
PIN NAME [2]
GPMC_AD2
GPMC_AD3
GPMC_AD4
GPMC_AD5
GPMC_AD6
GPMC_AD7
GPMC_AD8
GPMC_AD9
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gpmc_ad2
0
I/O
mmc1_dat2
1
I/O
gpio1_2
7
I/O
gpmc_ad3
0
I/O
mmc1_dat3
1
I/O
gpio1_3
7
I/O
gpmc_ad4
0
I/O
mmc1_dat4
1
I/O
gpio1_4
7
I/O
gpmc_ad5
0
I/O
mmc1_dat5
1
I/O
gpio1_5
7
I/O
gpmc_ad6
0
I/O
mmc1_dat6
1
I/O
gpio1_6
7
I/O
gpmc_ad7
0
I/O
mmc1_dat7
1
I/O
gpio1_7
7
I/O
gpmc_ad8
0
I/O
lcd_data23
1
O
mmc1_dat0
2
I/O
mmc2_dat4
3
I/O
ehrpwm2A
4
O
pr1_mii_mt0_clk
5
I
gpio0_22
7
I/O
gpmc_ad9
0
I/O
lcd_data22
1
O
mmc1_dat1
2
I/O
mmc2_dat5
3
I/O
ehrpwm2B
4
O
pr1_mii0_col
5
I
gpio0_23
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
23
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
T12
U12
PRODUCT PREVIEW
U13
T13
W17
24
T11
U12
T12
R12
V13
PIN NAME [2]
GPMC_AD10
GPMC_AD11
GPMC_AD12
GPMC_AD13
GPMC_AD14
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gpmc_ad10
0
I/O
lcd_data21
1
O
mmc1_dat2
2
I/O
mmc2_dat6
3
I/O
ehrpwm2_tripzone_input
4
I
pr1_mii0_txen
5
O
gpio0_26
7
I/O
gpmc_ad11
0
I/O
lcd_data20
1
O
mmc1_dat3
2
I/O
mmc2_dat7
3
I/O
ehrpwm0_synco
4
O
pr1_mii0_txd3
5
O
gpio0_27
7
I/O
gpmc_ad12
0
I/O
lcd_data19
1
O
mmc1_dat4
2
I/O
mmc2_dat0
3
I/O
eQEP2A_in
4
I
pr1_mii0_txd2
5
O
pr1_pru0_pru_r30_14
6
O
gpio1_12
7
I/O
gpmc_ad13
0
I/O
lcd_data18
1
O
mmc1_dat5
2
I/O
mmc2_dat1
3
I/O
eQEP2B_in
4
I
pr1_mii0_txd1
5
O
pr1_pru0_pru_r30_15
6
O
gpio1_13
7
I/O
gpmc_ad14
0
I/O
lcd_data17
1
O
mmc1_dat6
2
I/O
mmc2_dat2
3
I/O
eQEP2_index
4
I/O
pr1_mii0_txd0
5
O
pr1_pru0_pru_r31_14
6
I
gpio1_14
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
V17
V10
V8
V18
V16
W8
U13
R7
T6
U18
V12
V6
PIN NAME [2]
GPMC_AD15
GPMC_ADVn_ALE
GPMC_BEn0_CLE
GPMC_BEn1
GPMC_CLK
GPMC_CSn0
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gpmc_ad15
0
I/O
lcd_data16
1
O
mmc1_dat7
2
I/O
mmc2_dat3
3
I/O
eQEP2_strobe
4
I/O
pr1_ecap0_ecap_capin_apwm_o
5
I/O
pr1_pru0_pru_r31_15
6
I
gpio1_15
7
I/O
gpmc_advn_ale
0
O
timer4
2
I/O
gpio2_2
7
I/O
gpmc_be0n_cle
0
O
timer5
2
I/O
gpio2_5
7
I/O
gpmc_be1n
0
O
gmii2_col
1
I
gpmc_csn6
2
O
mmc2_dat3
3
I/O
gpmc_dir
4
O
pr1_mii1_rxlink
5
I
mcasp0_aclkr
6
I/O
gpio1_28
7
I/O
gpmc_clk
0
I/O
lcd_memory_clk
1
O
gpmc_wait1
2
I
mmc2_clk
3
I/O
pr1_mii1_crs
4
I
pr1_mdio_mdclk
5
O
mcasp0_fsr
6
I/O
gpio2_1
7
I/O
gpmc_csn0
0
O
gpio1_29
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV3
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
25
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
V14
U15
PRODUCT PREVIEW
U17
W9
R15
U8
26
U9
V9
T13
T7
T17
U6
PIN NAME [2]
GPMC_CSn1
GPMC_CSn2
GPMC_CSn3
GPMC_OEn_REn
GPMC_WAIT0
GPMC_WEn
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gpmc_csn1
0
O
gpmc_clk
1
I/O
mmc1_clk
2
I/O
pr1_edio_data_in6
3
I
pr1_edio_data_out6
4
O
pr1_pru1_pru_r30_12
5
O
pr1_pru1_pru_r31_12
6
I
gpio1_30
7
I/O
gpmc_csn2
0
O
gpmc_be1n
1
O
mmc1_cmd
2
I/O
pr1_edio_data_in7
3
I
pr1_edio_data_out7
4
O
pr1_pru1_pru_r30_13
5
O
pr1_pru1_pru_r31_13
6
I
gpio1_31
7
I/O
gpmc_csn3
0
O
mmc2_cmd
3
I/O
pr1_mii0_crs
4
I
pr1_mdio_data
5
I/O
EMU4
6
I/O
gpio2_0
7
I/O
gpmc_oen_ren
0
O
timer7
2
I/O
gpio2_3
7
I/O
gpmc_wait0
0
I
gmii2_crs
1
I
gpmc_csn4
2
O
rmii2_crs_dv
3
I
mmc1_sdcd
4
I
pr1_mii1_col
5
I
uart4_rxd
6
I
gpio0_30
7
I/O
gpmc_wen
0
O
timer6
2
I/O
gpio2_4
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV3
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
Terminal Description
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
W18
C18
B19
W7
U1
U17
C17
C16
R6
R1
PIN NAME [2]
GPMC_WPn
I2C0_SDA
I2C0_SCL
LCD_AC_BIAS_EN
LCD_DATA0 (3)
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gpmc_wpn
0
O
gmii2_rxerr
1
I
gpmc_csn5
2
O
rmii2_rxerr
3
I
mmc2_sdcd
4
I
pr1_mii1_txen
5
O
uart4_txd
6
O
gpio0_31
7
I/O
I2C0_SDA
0
I/OD
timer4
1
I/O
uart2_ctsn
2
I
eCAP2_in_PWM2_out
3
I/O
gpio3_5
7
I/O
I2C0_SCL
0
I/OD
timer7
1
I/O
uart2_rtsn
2
O
eCAP1_in_PWM1_out
3
I/O
gpio3_6
7
I/O
lcd_ac_bias_en
0
O
gpmc_a11
1
O
pr1_mii1_crs
2
I
pr1_edio_data_in5
3
I
pr1_edio_data_out5
4
O
pr1_pru1_pru_r30_11
5
O
pr1_pru1_pru_r31_11
6
I
gpio2_25
7
I/O
lcd_data0
0
I/O
gpmc_a0
1
O
pr1_mii_mt0_clk
2
I
ehrpwm2A
3
O
pr1_pru1_pru_r30_0
5
O
pr1_pru1_pru_r31_0
6
I
gpio2_6
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
H
H
7
VDDSHV1 /
VDDSHV3
Yes
6
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
27
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
U2
V1
PRODUCT PREVIEW
V2
W2
W3
28
R2
R3
R4
T1
T2
PIN NAME [2]
LCD_DATA1 (3)
LCD_DATA2 (3)
LCD_DATA3 (3)
LCD_DATA4 (3)
LCD_DATA5 (3)
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
lcd_data1
0
I/O
gpmc_a1
1
O
pr1_mii0_txen
2
O
ehrpwm2B
3
O
pr1_pru1_pru_r30_1
5
O
pr1_pru1_pru_r31_1
6
I
gpio2_7
7
I/O
lcd_data2
0
I/O
gpmc_a2
1
O
pr1_mii0_txd3
2
O
ehrpwm2_tripzone_input
3
I
pr1_pru1_pru_r30_2
5
O
pr1_pru1_pru_r31_2
6
I
gpio2_8
7
I/O
lcd_data3
0
I/O
gpmc_a3
1
O
pr1_mii0_txd2
2
O
ehrpwm0_synco
3
O
pr1_pru1_pru_r30_3
5
O
pr1_pru1_pru_r31_3
6
I
gpio2_9
7
I/O
lcd_data4
0
I/O
gpmc_a4
1
O
pr1_mii0_txd1
2
O
eQEP2A_in
3
I
pr1_pru1_pru_r30_4
5
O
pr1_pru1_pru_r31_4
6
I
gpio2_10
7
I/O
lcd_data5
0
I/O
gpmc_a5
1
O
pr1_mii0_txd0
2
O
eQEP2B_in
3
I
pr1_pru1_pru_r30_5
5
O
pr1_pru1_pru_r31_5
6
I
gpio2_11
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Terminal Description
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SPRS717 – OCTOBER 2011
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
V3
U3
V4
W4
T3
T4
U1
U2
PIN NAME [2]
LCD_DATA6 (3)
LCD_DATA7 (3)
LCD_DATA8 (3)
LCD_DATA9 (3)
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
lcd_data6
0
I/O
gpmc_a6
1
O
pr1_edio_data_in6
2
I
eQEP2_index
3
I/O
pr1_edio_data_out6
4
O
pr1_pru1_pru_r30_6
5
O
pr1_pru1_pru_r31_6
6
I
gpio2_12
7
I/O
lcd_data7
0
I/O
gpmc_a7
1
O
pr1_edio_data_in7
2
I
eQEP2_strobe
3
I/O
pr1_edio_data_out7
4
O
pr1_pru1_pru_r30_7
5
O
pr1_pru1_pru_r31_7
6
I
gpio2_13
7
I/O
lcd_data8
0
I/O
gpmc_a12
1
O
ehrpwm1_tripzone_input
2
I
mcasp0_aclkx
3
I/O
uart5_txd
4
O
pr1_mii0_rxd3
5
I
uart2_ctsn
6
I
gpio2_14
7
I/O
lcd_data9
0
I/O
gpmc_a13
1
O
ehrpwm0_synco
2
O
mcasp0_fsx
3
I/O
uart5_rxd
4
I
pr1_mii0_rxd2
5
I
uart2_rtsn
6
O
gpio2_15
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
29
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SPRS717 – OCTOBER 2011
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
U5
V5
PRODUCT PREVIEW
V6
U6
30
U3
U4
V2
V3
PIN NAME [2]
LCD_DATA10 (3)
LCD_DATA11 (3)
LCD_DATA12 (3)
LCD_DATA13 (3)
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
lcd_data10
0
I/O
gpmc_a14
1
O
ehrpwm1A
2
O
mcasp0_axr0
3
I/O
pr1_mii0_rxd1
5
I
uart3_ctsn
6
I
gpio2_16
7
I/O
lcd_data11
0
I/O
gpmc_a15
1
O
ehrpwm1B
2
O
mcasp0_ahclkr
3
I/O
mcasp0_axr2
4
I/O
pr1_mii0_rxd0
5
I
uart3_rtsn
6
O
gpio2_17
7
I/O
lcd_data12
0
I/O
gpmc_a16
1
O
eQEP1A_in
2
I
mcasp0_aclkr
3
I/O
mcasp0_axr2
4
I/O
pr1_mii0_rxlink
5
I
uart4_ctsn
6
I
gpio0_8
7
I/O
lcd_data13
0
I/O
gpmc_a17
1
O
eQEP1B_in
2
I
mcasp0_fsr
3
I/O
mcasp0_axr3
4
I/O
pr1_mii0_rxer
5
I
uart4_rtsn
6
O
gpio0_9
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Terminal Description
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
W6
V7
T7
W5
U7
V4
T5
R5
V5
U5
PIN NAME [2]
LCD_DATA14 (3)
LCD_DATA15 (3)
LCD_HSYNC
LCD_PCLK
LCD_VSYNC
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
lcd_data14
0
I/O
gpmc_a18
1
O
eQEP1_index
2
I/O
mcasp0_axr1
3
I/O
uart5_rxd
4
I
pr1_mii_mr0_clk
5
I
uart5_ctsn
6
I
gpio0_10
7
I/O
lcd_data15
0
I/O
gpmc_a19
1
O
eQEP1_strobe
2
I/O
mcasp0_ahclkx
3
I/O
mcasp0_axr3
4
I/O
pr1_mii0_rxdv
5
I
uart5_rtsn
6
O
gpio0_11
7
I/O
lcd_hsync
0
O
gpmc_a9
1
O
pr1_edio_data_in3
3
I
pr1_edio_data_out3
4
O
pr1_pru1_pru_r30_9
5
O
pr1_pru1_pru_r31_9
6
I
gpio2_23
7
I/O
lcd_pclk
0
O
gpmc_a10
1
O
pr1_mii0_crs
2
I
pr1_edio_data_in4
3
I
pr1_edio_data_out4
4
O
pr1_pru1_pru_r30_10
5
O
pr1_pru1_pru_r31_10
6
I
gpio2_24
7
I/O
lcd_vsync
0
O
gpmc_a8
1
O
pr1_edio_data_in2
3
I
pr1_edio_data_out2
4
O
pr1_pru1_pru_r30_8
5
O
pr1_pru1_pru_r31_8
6
I
gpio2_22
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
31
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
NA
NA
PRODUCT PREVIEW
NA
NA
NA
32
B13
B12
C12
A14
A13
PIN NAME [2]
MCASP0_FSX
MCASP0_ACLKR
MCASP0_AHCLKR
MCASP0_AHCLKX
MCASP0_ACLKX
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
mcasp0_fsx
0
I/O
ehrpwm0B
1
O
spi1_d0
3
I/O
mmc1_sdcd
4
I
pr1_pru0_pru_r30_1
5
O
pr1_pru0_pru_r31_1
6
I
gpio3_15
7
I/O
mcasp0_aclkr
0
I/O
eQEP0A_in
1
I
mcasp0_axr2
2
I/O
mcasp1_aclkx
3
I/O
mmc0_sdwp
4
I
pr1_pru0_pru_r30_4
5
O
pr1_pru0_pru_r31_4
6
I
gpio3_18
7
I/O
mcasp0_ahclkr
0
I/O
ehrpwm0_synci
1
I
mcasp0_axr2
2
I/O
spi1_cs0
3
I/O
eCAP2_in_PWM2_out
4
I/O
pr1_pru0_pru_r30_3
5
O
pr1_pru0_pru_r31_3
6
I
gpio3_17
7
I/O
mcasp0_ahclkx
0
I/O
eQEP0_strobe
1
I/O
mcasp0_axr3
2
I/O
mcasp1_axr1
3
I/O
EMU4
4
I/O
pr1_pru0_pru_r30_7
5
O
pr1_pru0_pru_r31_7
6
I
gpio3_21
7
I/O
mcasp0_aclkx
0
I/O
ehrpwm0A
1
O
spi1_sclk
3
I/O
mmc0_sdcd
4
I
pr1_pru0_pru_r30_0
5
O
pr1_pru0_pru_r31_0
6
I
gpio3_14
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
NA
NA
NA
R19
P17
C13
D12
D13
M18
M17
PIN NAME [2]
MCASP0_FSR
MCASP0_AXR0
MCASP0_AXR1
MDC
MDIO
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
mcasp0_fsr
0
I/O
eQEP0B_in
1
I
mcasp0_axr3
2
I/O
mcasp1_fsx
3
I/O
EMU2
4
I/O
pr1_pru0_pru_r30_5
5
O
pr1_pru0_pru_r31_5
6
I
gpio3_19
7
I/O
mcasp0_axr0
0
I/O
ehrpwm0_tripzone_input
1
I
spi1_d1
3
I/O
mmc2_sdcd
4
I
pr1_pru0_pru_r30_2
5
O
pr1_pru0_pru_r31_2
6
I
gpio3_16
7
I/O
mcasp0_axr1
0
I/O
eQEP0_index
1
I/O
mcasp1_axr0
3
I/O
EMU3
4
I/O
pr1_pru0_pru_r30_6
5
O
pr1_pru0_pru_r31_6
6
I
gpio3_20
7
I/O
mdio_clk
0
O
timer5
1
I/O
uart5_txd
2
O
uart3_rtsn
3
O
mmc0_sdwp
4
I
mmc1_clk
5
I/O
mmc2_clk
6
I/O
gpio0_1
7
I/O
mdio_data
0
I/O
timer6
1
I/O
uart5_rxd
2
O
uart3_ctsn
3
I
mmc0_sdcd
4
I
mmc1_cmd
5
I/O
mmc2_cmd
6
I/O
gpio0_0
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
33
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
L19
K17
PRODUCT PREVIEW
K19
M19
34
J17
J16
J15
L18
PIN NAME [2]
MII1_RX_DV
MII1_TX_EN
MII1_RX_ER
MII1_RX_CLK
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gmii1_rxdv
0
I
lcd_memory_clk
1
O
rgmii1_rctl
2
I
uart5_txd
3
O
mcasp1_aclkx
4
I/O
mmc2_dat0
5
I/O
mcasp0_aclkr
6
I/O
gpio3_4
7
I/O
gmii1_txen
0
O
rmii1_txen
1
O
rgmii1_tctl
2
O
timer4
3
I/O
mcasp1_axr0
4
I/O
eQEP0_index
5
I/O
mmc2_cmd
6
I/O
gpio3_3
7
I/O
gmii1_rxerr
0
I
rmii1_rxerr
1
I
spi1_d1
2
I/O
I2C1_SCL
3
I/OD
mcasp1_fsx
4
I/O
uart5_rtsn
5
O
uart2_txd
6
O
gpio3_2
7
I/O
gmii1_rxclk
0
I
uart2_txd
1
O
rgmii1_rclk
2
I
mmc0_dat6
3
I/O
mmc1_dat1
4
I/O
uart1_dsrn
5
I
mcasp0_fsx
6
I/O
gpio3_10
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
N19
J19
J18
P18
K18
H16
H17
M16
PIN NAME [2]
MII1_TX_CLK
MII1_COL
MII1_CRS
MII1_RXD0
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gmii1_txclk
0
I
uart2_rxd
1
I
rgmii1_tclk
2
O
mmc0_dat7
3
I/O
mmc1_dat0
4
I/O
uart1_dcdn
5
I
mcasp0_aclkx
6
I/O
gpio3_9
7
I/O
gmii1_col
0
I
rmii2_refclk
1
I/O
spi1_sclk
2
I/O
uart5_rxd
3
I
mcasp1_axr2
4
I/O
mmc2_dat3
5
I/O
mcasp0_axr2
6
I/O
gpio3_0
7
I/O
gmii1_crs
0
I
rmii1_crs_dv
1
I
spi1_d0
2
I/O
I2C1_SDA
3
I/OD
mcasp1_aclkx
4
I/O
uart5_ctsn
5
I
uart2_rxd
6
I
gpio3_1
7
I/O
gmii1_rxd0
0
I
rmii1_rxd0
1
I
rgmii1_rd0
2
I
mcasp1_ahclkx
3
I/O
mcasp1_ahclkr
4
I/O
mcasp1_aclkr
5
I/O
mcasp0_axr3
6
I/O
gpio2_21
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
35
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
P19
N16
PRODUCT PREVIEW
N17
L18
36
L15
L16
L17
K17
PIN NAME [2]
MII1_RXD1
MII1_RXD2
MII1_RXD3
MII1_TXD0
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gmii1_rxd1
0
I
rmii1_rxd1
1
I
rgmii1_rd1
2
I
mcasp1_axr3
3
I/O
mcasp1_fsr
4
I/O
eQEP0_strobe
5
I/O
mmc2_clk
6
I/O
gpio2_20
7
I/O
gmii1_rxd2
0
I
uart3_txd
1
O
rgmii1_rd2
2
I
mmc0_dat4
3
I/O
mmc1_dat3
4
I/O
uart1_rin
5
I
mcasp0_axr1
6
I/O
gpio2_19
7
I/O
gmii1_rxd3
0
I
uart3_rxd
1
I
rgmii1_rd3
2
I
mmc0_dat5
3
I/O
mmc1_dat2
4
I/O
uart1_dtrn
5
O
mcasp0_axr0
6
I/O
gpio2_18
7
I/O
gmii1_txd0
0
O
rmii1_txd0
1
O
rgmii1_td0
2
O
mcasp1_axr2
3
I/O
mcasp1_aclkr
4
I/O
eQEP0B_in
5
I
mmc1_clk
6
I/O
gpio0_28
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
Terminal Description
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
M18
N18
M17
G17
K16
K15
J18
G18
PIN NAME [2]
MII1_TXD1
MII1_TXD2
MII1_TXD3
MMC0_CMD
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
gmii1_txd1
0
O
rmii1_txd1
1
O
rgmii1_td1
2
O
mcasp1_fsr
3
I/O
mcasp1_axr1
4
I/O
eQEP0A_in
5
I
mmc1_cmd
6
I/O
gpio0_21
7
I/O
gmii1_txd2
0
O
dcan0_rx
1
I
rgmii1_td2
2
O
uart4_txd
3
O
mcasp1_axr0
4
I/O
mmc2_dat2
5
I/O
mcasp0_ahclkx
6
I/O
gpio0_17
7
I/O
gmii1_txd3
0
O
dcan0_tx
1
O
rgmii1_td3
2
O
uart4_rxd
3
I
mcasp1_fsx
4
I/O
mmc2_dat1
5
I/O
mcasp0_fsr
6
I/O
gpio0_16
7
I/O
mmc0_cmd
0
I/O
gpmc_a25
1
O
uart3_rtsn
2
O
uart2_txd
3
O
dcan1_rx
4
I
pr1_pru0_pru_r30_13
5
O
pr1_pru0_pru_r31_13
6
I
gpio2_31
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
L
L
7
VDDSHV5 /
VDDSHV5
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV4 /
VDDSHV4
Yes
6
PU/PD
LVCMOS
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
37
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
G19
G18
PRODUCT PREVIEW
H17
H18
38
G17
G16
G15
F18
PIN NAME [2]
MMC0_CLK
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
mmc0_clk
0
I/O
gpmc_a24
1
O
uart3_ctsn
2
I
uart2_rxd
3
I
dcan1_tx
4
O
pr1_pru0_pru_r30_12
5
O
pr1_pru0_pru_r31_12
6
I
gpio2_30
7
I/O
mmc0_dat0
0
I/O
gpmc_a23
1
O
uart5_rtsn
2
O
uart3_txd
3
O
uart1_rin
4
I
pr1_pru0_pru_r30_11
5
O
pr1_pru0_pru_r31_11
6
I
gpio2_29
7
I/O
mmc0_dat1
0
I/O
gpmc_a22
1
O
uart5_ctsn
2
I
uart3_rxd
3
I
uart1_dtrn
4
O
pr1_pru0_pru_r30_10
5
O
pr1_pru0_pru_r31_10
6
I
gpio2_28
7
I/O
mmc0_dat2
0
I/O
gpmc_a21
1
O
uart4_rtsn
2
O
timer6
3
I/O
uart1_dsrn
4
I
pr1_pru0_pru_r30_9
5
O
pr1_pru0_pru_r31_9
6
I
gpio2_27
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
H
H
7
VDDSHV4 /
VDDSHV4
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV4 /
VDDSHV4
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV4 /
VDDSHV4
Yes
6
PU/PD
LVCMOS
H
H
7
VDDSHV4 /
VDDSHV4
Yes
6
PU/PD
LVCMOS
Terminal Description
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SPRS717 – OCTOBER 2011
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
H19
F17
PIN NAME [2]
MMC0_DAT3
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
mmc0_dat3
0
I/O
gpmc_a20
1
O
uart4_ctsn
2
I
timer5
3
I/O
uart1_dcdn
4
I
pr1_pru0_pru_r30_8
5
O
pr1_pru0_pru_r31_8
6
I
gpio2_26
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
H
H
7
VDDSHV4 /
VDDSHV4
Yes
6
PU/PD
LVCMOS
C7
C6
PMIC_POWER_EN
PMIC_POWER_EN
0
O
H
1
0
VDDS_RTC /
VDDS_RTC
NA
6
NA
LVCMOS
E15
B15
PWRONRSTn
porz
0
I
Z
Z
0
VDDSHV6 /
VDDSHV6
Yes
NA
NA
LVCMOS
B6
A3
RESERVED
testout
0
O
NA
NA
NA
VDDSHV6 /
VDDSHV6
NA
NA
NA
Analog
K18
H18
RMII1_REF_CLK
rmii1_refclk
0
I/O
L
L
7
6
PU/PD
LVCMOS
1
I
VDDSHV5 /
VDDSHV5
Yes
xdma_event_intr2
spi1_cs0
2
I/O
uart5_txd
3
O
mcasp1_axr3
4
I/O
mmc0_pow
5
O
mcasp1_ahclkx
6
I/O
gpio0_29
7
I/O
A7
B4
RTC_KALDO_ENn
ENZ_KALDO_1P8V
0
I
Z
Z
0
VDDS_RTC /
VDDS_RTC
NA
NA
NA
Analog
B7
B5
RTC_PWRONRSTn
RTC_porz
0
I
Z
Z
0
VDDS_RTC /
VDDS_RTC
Yes
NA
NA
LVCMOS
A6
A6
RTC_XTALIN
OSC1_IN
0
I
Z
Z
0
VDDS_RTC /
VDDS_RTC
Yes
NA
NA (2)
LVCMOS
A5
A4
RTC_XTALOUT
OSC1_OUT
0
O
Z
Z
0
VDDS_RTC /
VDDS_RTC
NA
TBD
NA
LVCMOS
A18
A17
SPI0_SCLK
spi0_sclk
0
I/O
Z
H
7
6
PU/PD
LVCMOS
1
I
VDDSHV6 /
VDDSHV6
Yes
uart2_rxd
I2C2_SDA
2
I/OD
ehrpwm0A
3
O
pr1_uart0_cts_n
4
I
pr1_edio_sof
5
O
EMU2
6
I/O
gpio0_2
7
I/O
(14)
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
39
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SPRS717 – OCTOBER 2011
www.ti.com
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
A17
B16
PRODUCT PREVIEW
B18
B17
A16
C15
B17
B16
PIN NAME [2]
SPI0_CS0
SPI0_CS1
SPI0_D0
SPI0_D1
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
spi0_cs0
0
I/O
mmc2_sdwp
1
I
I2C1_SCL
2
I/OD
ehrpwm0_synci
3
I
pr1_uart0_txd
4
O
pr1_edio_data_in1
5
I
pr1_edio_data_out1
6
O
gpio0_5
7
I/O
spi0_cs1
0
I/O
uart3_rxd
1
I
eCAP1_in_PWM1_out
2
I/O
mmc0_pow
3
O
xdma_event_intr2
4
I
mmc0_sdcd
5
I
EMU4
6
I/O
gpio0_6
7
I/O
spi0_d0
0
I/O
uart2_txd
1
O
I2C2_SCL
2
I/OD
ehrpwm0B
3
O
pr1_uart0_rts_n
4
O
pr1_edio_latch_in
5
I
EMU3
6
I/O
gpio0_3
7
I/O
spi0_d1
0
I/O
mmc1_sdwp
1
I
I2C1_SDA
2
I/OD
ehrpwm0_tripzone_input
3
I
pr1_uart0_rxd
4
I
pr1_edio_data_in0
5
I
pr1_edio_data_out0
6
O
gpio0_4
7
I/O
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
B14
A12
TCK
TCK
0
I
H
H
0
VDDSHV6 /
VDDSHV6
Yes
NA
PU/PD
LVCMOS
B13
B11
TDI
TDI
0
I
H
H
0
VDDSHV6 /
VDDSHV6
Yes
NA
PU/PD
LVCMOS
A14
A11
TDO
TDO
0
O
H
H
0
VDDSHV6 /
VDDSHV6
NA
4
PU/PD
LVCMOS
C14
C11
TMS
TMS
0
I
H
H
0
VDDSHV6 /
VDDSHV6
Yes
NA
PU/PD
LVCMOS
40
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
A13
B10
TRSTn
nTRST
0
I
L
L
0
VDDSHV6 /
VDDSHV6
Yes
NA
PU/PD
LVCMOS
F17
E16
UART0_TXD
uart0_txd
0
O
Z
H
7
4
PU/PD
LVCMOS
1
I/O
VDDSHV6 /
VDDSHV6
Yes
spi1_cs1
dcan0_rx
2
I
I2C2_SCL
3
I/OD
eCAP1_in_PWM1_out
4
I/O
pr1_pru1_pru_r30_15
5
O
pr1_pru1_pru_r31_15
6
I
gpio1_11
7
I/O
uart0_ctsn
0
I
Z
H
7
4
PU/PD
LVCMOS
1
I
VDDSHV6 /
VDDSHV6
Yes
uart4_rxd
dcan1_tx
2
O
I2C1_SDA
3
I/OD
spi1_d0
4
I/O
timer7
5
I/O
pr1_edc_sync0_out
6
O
gpio1_8
7
I/O
uart0_rxd
0
I
Z
H
7
4
PU/PD
LVCMOS
1
I/O
VDDSHV6 /
VDDSHV6
Yes
spi1_cs0
dcan0_tx
2
O
I2C2_SDA
3
I/OD
eCAP2_in_PWM2_out
4
I/O
pr1_pru1_pru_r30_14
5
O
pr1_pru1_pru_r31_14
6
I
gpio1_10
7
I/O
uart0_rtsn
0
O
Z
H
7
4
PU/PD
LVCMOS
1
O
VDDSHV6 /
VDDSHV6
Yes
uart4_txd
dcan1_rx
2
I
I2C1_SCL
3
I/OD
spi1_d1
4
I/O
spi1_cs0
5
I/O
pr1_edc_sync1_out
6
O
gpio1_9
7
I/O
F19
E19
F18
E18
E15
E17
UART0_CTSn
UART0_RXD
UART0_RTSn
Terminal Description
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PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
41
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
C19
D18
PRODUCT PREVIEW
D19
E17
T18
D15
D16
D17
D18
M15
PIN NAME [2]
UART1_TXD
UART1_RXD
UART1_RTSn
UART1_CTSn
USB0_CE
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
uart1_txd
0
O
mmc2_sdwp
1
I
dcan1_rx
2
I
I2C1_SCL
3
I/OD
pr1_uart0_txd
5
O
pr1_pru0_pru_r31_16
6
I
gpio0_15
7
I/O
uart1_rxd
0
I
mmc1_sdwp
1
I
dcan1_tx
2
O
I2C1_SDA
3
I/OD
pr1_uart0_rxd
5
I
pr1_pru1_pru_r31_16
6
I
gpio0_14
7
I/O
uart1_rtsn
0
O
timer5
1
I/O
dcan0_rx
2
I
I2C2_SCL
3
I/OD
spi1_cs1
4
I/O
pr1_uart0_rts_n
5
O
pr1_edc_latch1_in
6
I
gpio0_13
7
I/O
uart1_ctsn
0
I
timer6
1
I/O
dcan0_tx
2
O
I2C2_SDA
3
I/OD
spi1_cs0
4
I/O
pr1_uart0_cts_n
5
I
pr1_edc_latch0_in
6
I
gpio0_12
7
I/O
USB0_CE
0
A
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
Z
0
VDDA*_USB0 /
VDDA*_USB0
TBD
TBD
TBD
Analog
TBD
TBD
TBD
Analog
VDDA*_USB0 /
VDDA*_USB0
TBD
TBD
TBD
Analog
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
(16)
T19
P15
USB0_VBUS
USB0_VBUS
0
A
Z
Z
0
VDDA*_USB0 /
VDDA*_USB0
(16)
U18
N18
USB0_DM
USB0_DM
0
A
Z
Z
0
G16
F16
USB0_DRVVBUS
USB0_DRVVBUS
0
O
L
0(PD)
0
gpio0_18
7
I/O
42
(5)
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
V19
P16
PIN NAME [2]
USB0_ID
SIGNAL NAME [3]
USB0_ID
MODE [4]
0
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
A
Z
Z
0
VDDA*_USB0 /
VDDA*_USB0
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
TBD
TBD
TBD
Analog
VDDA*_USB0 /
VDDA*_USB0
TBD
TBD
TBD
Analog
NA /
VDDA*_USB1
TBD
TBD
TBD
Analog
TBD
TBD
TBD
Analog
TBD
TBD
TBD
Analog
TBD
TBD
TBD
Analog
NA / VDDSHV6 Yes
4
PU/PD
LVCMOS
NA /
VDDA*_USB1
TBD
TBD
Analog
(16)
U19
N17
USB0_DP
USB0_DP
0
A
Z
Z
0
NA
P18
USB1_CE
USB1_CE
0
A
Z
Z
0
(5)
(17)
NA
P17
USB1_ID
USB1_ID
0
A
Z
Z
0
NA /
VDDA*_USB1
NA
T18
USB1_VBUS
USB1_VBUS
0
A
Z
Z
0
NA /
VDDA*_USB1
PRODUCT PREVIEW
(17)
(17)
NA
R17
USB1_DP
USB1_DP
0
A
Z
Z
0
NA
F15
USB1_DRVVBUS
USB1_DRVVBUS
0
O
L
0(PD)
0
gpio3_13
7
I/O
Z
Z
0
NA
R18
USB1_DM
USB1_DM
0
A
R17
N16
VDDA1P8V_USB0
VDDA1P8V_USB0
NA
PWR
NA
R16
VDDA1P8V_USB1
VDDA1P8V_USB1
NA
PWR
R18
N15
VDDA3P3V_USB0
VDDA3P3V_USB0
NA
PWR
NA
R15
VDDA3P3V_USB1
VDDA3P3V_USB1
NA
PWR
D7
D8
VDDA_ADC
VDDA_ADC
NA
PWR
D12, F16,
E6, E14, F9,
M16, T6, T14 K13, N6, P9,
P14
VDDS
VDDS
NA
PWR
R8, R9, R11,
R12, R13
P7, P8
VDDSHV1
VDDSHV1
NA
PWR
NA
P10, P11
VDDSHV2
VDDSHV2
NA
PWR
NA
P12, P13
VDDSHV3
VDDSHV3
NA
PWR
G15, H14,
H15
H14, J14
VDDSHV4
VDDSHV4
NA
PWR
M14, M15,
N15
K14, L14
VDDSHV5
VDDSHV5
NA
PWR
E11, E12,
E10, E11,
VDDSHV6
E13, F14, P6, E12, E13,
R7
F14, G14, N5,
P5, P6
VDDSHV6
NA
PWR
G5, H5, H6,
K4, K5, M5,
M6, N5
E5, F5, G5,
VDDS_DDR
H5, J5, K5, L5
VDDS_DDR
NA
PWR
U10
R11
VDDS_OSC
VDDS_OSC
NA
PWR
T8
R10
VDDS_PLL_CORE_LCD
VDDS_PLL_CORE_LCD
NA
PWR
C5
E7
VDDS_PLL_DDR
VDDS_PLL_DDR
NA
PWR
(6)
(6)
NA /
VDDA*_USB1
TBD
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
PRODUCT PREVIEW
H16
H15
VDDS_PLL_MPU
VDDS_PLL_MPU
NA
PWR
C6
D7
VDDS_RTC
VDDS_RTC
NA
PWR
C10
E9
VDDS_SRAM_CORE_BG
VDDS_SRAM_CORE_BG
NA
PWR
C12
D10
VDDS_SRAM_MPU_BB
VDDS_SRAM_MPU_BB
NA
PWR
F9, F11, G9,
G11, H7, H8,
H12, H13, J7,
J8, J12, J13,
K15, K16, L7,
L8, L12, L13,
M7, M8, M12,
M13, N9,
N11, P9, P11
F6, F7, G6,
VDD_CORE
G7, G10,
H11, J12, K6,
K8, K12, L6,
L7, L8, L9,
M11, M13,
N8, N9, N12,
N13
VDD_CORE
NA
PWR
NA
F10, F11,
F12, F13,
G13, H13,
J13
VDD_MPU
VDD_MPU
NA
PWR
NA
A2
VDD_MPU_MON
VDD_MPU_MON
NA
R5
M5
VPP
VPP
NA
PWR
B9
A9
VREFN
VREFN
0
AP
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
A9
B9
VREFP
VREFP
0
AP
Z
Z
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
A1, A19, D10,
E7, E8, E9,
E10, F6, F7,
F8, F12, F13,
G8, G12, H9,
H10, H11, J5,
J6, J9, J11,
J14, J15, K8,
K9, K11, K12,
L5, L6, L9,
L11, L14, L15,
M9, M10,
M11, N8,
N12, P7, P8,
P12, P13,
P14, R10,
T10, W1, W19
A1, A18, F8, VSS
G8, G9, G11,
G12, H6, H7,
H8, H9, H10,
H12, J6, J7,
J8, J9, J10,
J11, K7, K9,
K10, K11,
L10, L11, L12,
L13, M6, M7,
M8, M9, M10,
M12, N7,
N10, N11, V1,
V18
VSS
NA
GND
D8
E8
VSSA_ADC
VSSA_ADC
NA
GND
P16
M14, N14
VSSA_USB
VSSA_USB
NA
GND
V11
V11
VSS_OSC
VSS_OSC
NA
A
NA
A5
VSS_RTC
VSS_RTC
NA
GND
A16
A10
WARMRSTn
nRESETIN_OUT
0
I/OD
0
0
0
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
44
Terminal Description
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
C15
B15
A15
D14
PIN NAME [2]
XDMA_EVENT_INTR0
XDMA_EVENT_INTR1
SIGNAL NAME [3]
MODE [4]
BALL RESET
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
REL. STATE
[5]
STATE [6]
MODE [8] ZCZ POWER [9] [10]
[7]
xdma_event_intr0
0
I
timer4
2
I/O
clkout1
3
O
spi1_cs1
4
I/O
pr1_pru1_pru_r31_16
5
I
EMU2
6
I/O
gpio0_19
7
I/O
xdma_event_intr1
0
I
tclkin
2
I
clkout2
3
O
timer7
4
I/O
pr1_pru0_pru_r31_16
5
I
EMU3
6
I/O
gpio0_20
7
I/O
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
(7)
(4)
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
Z
0
VDDS_OSC /
VDDS_OSC
Yes
NA
PD (1)
LVCMOS
0
VDDS_OSC /
VDDS_OSC
NA
TBD
NA
LVCMOS
Z
(8)
BUFFER
STRENGTH
(mA) [11]
W11
V10
XTALIN
OSC0_IN
0
I
Z
W12
U11
XTALOUT
OSC0_OUT
0
O
(15)
PRODUCT PREVIEW
ZCE BALL
ZCZ BALL
NUMBER [1] NUMBER [1]
(1) A internal 15 kohm pull down is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
(2) An external pull-down resistor should be connected to this terminal to minmize leakage current when not using the oscillator.
(3) LCD_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
(4) Reset Release Mode = 7 if sysboot[5] is low. Mode = 3 if sysboot[5] is high.
(5) The internal USB PHY can be configured to multiplex the UART2_TX or UART2_RX signals to this terminal. For more details refer to USB GPIO Details section of the TRM.
(6) The internal USB PHY can be configured to multiplex the UART3_TX or UART3_RX signals to this terminal. For more details refer to USB GPIO Details section of the TRM.
(7) This terminal has an internal pull-down that remains on after reset is released if sysboot[5] is low on the rising edge or PWRONRSTn. This terminal will initially be driven low after reset is
released if sysboot[5] is high on the rising edge or PWRONRSTn, then it begins to toggle at the same frequency of the XTALIN terminal.
(8) This terminal has an internal pull-down turned on while reset is asserted.
(9) This terminal is a analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
(10) This terminal is a analog passive signal that connects to an external 50 ohm 2% reference resistor which is used to calibrate the DDR input/output buffers.
(11) This terminal is analog input that may also be configured as an open-drain output.
(12) This terminal is analog input that may also be configured as an open-source or open-drain output.
(13) This terminal is analog input that may also be configured as an open-source output.
(14) This terminal is high-Z when the oscillator is diasabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a
unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied.
(15) This terminal is high-Z when the oscillator is diasabled. This terminal is driven high if XTALIN is less than VIL, driven low if XTALIN is greater than VIH, and driven to a unknown value if
XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is enabled by default after power is applied.
(16) This terminal requires two power supplies, VDDA3P3v_USB0 and VDDA1P8v_USB0. The "*" character in the power supply name is a wild card that represents "3P3v" and "1P8v".
Terminal Description
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(17) This terminal requires two power supplies, VDDA3P3v_USB1 and VDDA1P8v_USB1. The "*" character in the power supply name is a wild card that represents "3P3v" and "1P8v".
PRODUCT PREVIEW
46
Terminal Description
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2.3
Signal Description
Many signals are available on multiple pins according to the software configuration of the pin multiplexing
options.
NOTE
PRODUCT PREVIEW
The Subsystem Multiplexing Signals are not described in the following tables. For more
information, see: TBD
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Terminal Description
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(1) SIGNAL NAME: The signal name
(2) DESCRIPTION: Description of the signal
(3) TYPE: Ball type for this specific function:
– I = Input
– O = Output
– I/O = Input/Output
– D = Open drain
– DS = Differential
– A = Analog
(4) BALL: Package ball location
Table 2-8. ADC Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
AIN0
Analog Input/Output
A
B8
B6
AIN1
Analog Input/Output
A
A11
C7
AIN2
Analog Input/Output
A
A8
B7
AIN3
Analog Input/Output
A
B11
A7
AIN4
Analog Input/Output
A
C8
C8
AIN5
Analog Input/Output
A
B12
B8
AIN6
Analog Input/Output
A
A10
A8
AIN7
Analog Input/Output
A
A12
C9
VREFN
Analog Reference Input Negative Terminal
AP
B9
A9
VREFP
Analog Reference Input Positive Terminal
AP
A9
B9
Table 2-9. Debug Subsystem Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
EMU0
MISC EMULATION PIN
I/O
A15
C14
EMU1
MISC EMULATION PIN
I/O
D14
B14
EMU2
MISC EMULATION PIN
I/O
A18, C15
A15, A17, C13
EMU3
MISC EMULATION PIN
I/O
B15, B18
B17, D13, D14
EMU4
MISC EMULATION PIN
I/O
B16, U17
A14, C15, T13
nTRST
JTAG TEST RESET (ACTIVE LOW)
I
A13
B10
TCK
JTAG TEST CLOCK
I
B14
A12
TDI
JTAG TEST DATA INPUT
I
B13
B11
TDO
JTAG TEST DATA OUTPUT
O
A14
A11
TMS
JTAG TEST MODE SELECT
I
C14
C11
Table 2-10. ECAT Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_edc_latch0_in
Data In
I
E17
D18
pr1_edc_latch1_in
Data In
I
D19
D17
pr1_edc_sync0_out
Data Out
O
F19
E18
pr1_edc_sync1_out
Data Out
O
F18
E17
pr1_edio_data_in0
Data In
I
B17
B16
pr1_edio_data_in1
Data In
I
A17
A16
pr1_edio_data_in2
Data In
I
U7
U5
pr1_edio_data_in3
Data In
I
T7
R5
pr1_edio_data_in4
Data In
I
W5
V5
pr1_edio_data_in5
Data In
I
W7
R6
48
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Table 2-10. ECAT Signals Description (continued)
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_edio_data_in6
Data In
I
V14, V3
T3, U9
pr1_edio_data_in7
Data In
I
U15, U3
T4, V9
pr1_edio_data_out0
Data Out
O
B17
B16
pr1_edio_data_out1
Data Out
O
A17
A16
pr1_edio_data_out2
Data Out
O
U7
U5
pr1_edio_data_out3
Data Out
O
T7
R5
pr1_edio_data_out4
Data Out
O
W5
V5
pr1_edio_data_out5
Data Out
O
W7
R6
pr1_edio_data_out6
Data Out
O
V14, V3
T3, U9
pr1_edio_data_out7
Data Out
O
U15, U3
T4, V9
pr1_edio_latch_in
Latch In
I
B18
B17
pr1_edio_sof
Start of Frame
O
A18
A17
Table 2-11. LCD Controller Signals Description
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
lcd_ac_bias_en
LCD AC bias enable chip select
O
W7
R6
lcd_data0
LCD data bus
I/O
U1
R1
lcd_data1
LCD data bus
I/O
U2
R2
lcd_data10
LCD data bus
I/O
U5
U3
lcd_data11
LCD data bus
I/O
V5
U4
lcd_data12
LCD data bus
I/O
V6
V2
lcd_data13
LCD data bus
I/O
U6
V3
lcd_data14
LCD data bus
I/O
W6
V4
lcd_data15
LCD data bus
I/O
V7
T5
lcd_data16
LCD data bus
O
V17
U13
lcd_data17
LCD data bus
O
W17
V13
lcd_data18
LCD data bus
O
T13
R12
lcd_data19
LCD data bus
O
U13
T12
lcd_data2
LCD data bus
I/O
V1
R3
lcd_data20
LCD data bus
O
U12
U12
lcd_data21
LCD data bus
O
T12
T11
lcd_data22
LCD data bus
O
W16
T10
lcd_data23
LCD data bus
O
V15
U10
lcd_data3
LCD data bus
I/O
V2
R4
lcd_data4
LCD data bus
I/O
W2
T1
lcd_data5
LCD data bus
I/O
W3
T2
lcd_data6
LCD data bus
I/O
V3
T3
lcd_data7
LCD data bus
I/O
U3
T4
lcd_data8
LCD data bus
I/O
V4
U1
lcd_data9
LCD data bus
I/O
W4
U2
lcd_hsync
LCD Horizontal Sync
O
T7
R5
lcd_memory_clk
LCD MCLK
O
L19, V16
J17, V12
lcd_pclk
LCD pixel clock
O
W5
V5
lcd_vsync
LCD Vertical Sync
O
U7
U5
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PRODUCT PREVIEW
SIGNAL NAME [1]
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2.3.1
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External Memory Interfaces
Table 2-12. External Memory Interfaces/DDR Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
ddr_a0
DDR SDRAM ROW/COLUMN ADDRESS
O
F3
F3
ddr_a1
DDR SDRAM ROW/COLUMN ADDRESS
O
J2
H1
ddr_a10
DDR SDRAM ROW/COLUMN ADDRESS
O
E2
F4
ddr_a11
DDR SDRAM ROW/COLUMN ADDRESS
O
G4
F2
ddr_a12
DDR SDRAM ROW/COLUMN ADDRESS
O
F4
E3
ddr_a13
DDR SDRAM ROW/COLUMN ADDRESS
O
H1
H3
ddr_a14
DDR SDRAM ROW/COLUMN ADDRESS
O
H3
H4
ddr_a15
DDR SDRAM ROW/COLUMN ADDRESS
O
E3
D3
ddr_a2
DDR SDRAM ROW/COLUMN ADDRESS
O
D1
E4
ddr_a3
DDR SDRAM ROW/COLUMN ADDRESS
O
B3
C3
ddr_a4
DDR SDRAM ROW/COLUMN ADDRESS
O
E5
C2
ddr_a5
DDR SDRAM ROW/COLUMN ADDRESS
O
A2
B1
ddr_a6
DDR SDRAM ROW/COLUMN ADDRESS
O
B1
D5
ddr_a7
DDR SDRAM ROW/COLUMN ADDRESS
O
D2
E2
ddr_a8
DDR SDRAM ROW/COLUMN ADDRESS
O
C3
D4
ddr_a9
DDR SDRAM ROW/COLUMN ADDRESS
O
B2
C1
ddr_ba0
DDR SDRAM BANK ADDRESS
O
A3
C4
ddr_ba1
DDR SDRAM BANK ADDRESS
O
E1
E1
ddr_ba2
DDR SDRAM BANK ADDRESS
O
B4
B3
ddr_casn
DDR SDRAM COLUMN ADDRESS STROBE.
(ACTIVE LOW)
O
F1
F1
ddr_ck
DDR SDRAM CLOCK (Differential+)
O
C2
D2
ddr_cke
DDR SDRAM CLOCK ENABLE
O
G3
G3
ddr_csn0
DDR SDRAM CHIP SELECT
O
H2
H2
ddr_d0
DDR SDRAM DATA
I/O
N4
M3
ddr_d1
DDR SDRAM DATA
I/O
P4
M4
ddr_d10
DDR SDRAM DATA
I/O
M3
K2
ddr_d11
DDR SDRAM DATA
I/O
M4
K3
ddr_d12
DDR SDRAM DATA
I/O
M2
K4
ddr_d13
DDR SDRAM DATA
I/O
M1
L3
ddr_d14
DDR SDRAM DATA
I/O
N2
L4
ddr_d15
DDR SDRAM DATA
I/O
N1
M1
ddr_d2
DDR SDRAM DATA
I/O
P2
N1
ddr_d3
DDR SDRAM DATA
I/O
P1
N2
ddr_d4
DDR SDRAM DATA
I/O
P3
N3
ddr_d5
DDR SDRAM DATA
I/O
T1
N4
ddr_d6
DDR SDRAM DATA
I/O
T2
P3
ddr_d7
DDR SDRAM DATA
I/O
R3
P4
ddr_d8
DDR SDRAM DATA
I/O
K2
J1
ddr_d9
DDR SDRAM DATA
I/O
K1
K1
ddr_dqm0
DDR WRITE ENABLE / DATA MASK FOR
DATA[7:0]
O
N3
M2
ddr_dqm1
DDR WRITE ENABLE / DATA MASK FOR
DATA[15:8]
O
K3
J2
ddr_dqs0
DDR DATA STROBE FOR DATA[7:0]
(Differential+)
I/O
R1
P1
50
Terminal Description
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Table 2-12. External Memory Interfaces/DDR Signals Description (continued)
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
ddr_dqs1
DDR DATA STROBE FOR DATA[15:8]
(Differential+)
I/O
L1
L1
ddr_dqsn0
DDR DATA STROBE FOR DATA[7:0]
(Differential-)
I/O
R2
P2
ddr_dqsn1
DDR DATA STROBE FOR DATA[15:8]
(Differential-)
I/O
L2
L2
ddr_nck
DDR SDRAM CLOCK (Differential-)
O
C1
D1
ddr_odt
ODT
O
G1
G1
ddr_rasn
DDR SDRAM ROW ADDRESS STROBE
(ACTIVE LOW)
O
F2
G4
ddr_resetn
DDR3 resetn
O
G2
G2
ddr_vref
Voltage Reference
AP
H4
J4
ddr_vtp
VTP Compensation pin
I
J1
J3
ddr_wen
DDR SDRAM WRITE ENABLE (ACTIVE LOW)
O
A4
B2
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
gpmc_a0
GPMC Address
O
U1
R1, R13
gpmc_a1
GPMC Address
O
U2
R2, V14
gpmc_a10
GPMC Address
O
W5
T16, V5
gpmc_a11
GPMC Address
O
W7
R6, V17
gpmc_a12
GPMC Address
O
V4
U1
gpmc_a13
GPMC Address
O
W4
U2
gpmc_a14
GPMC Address
O
U5
U3
gpmc_a15
GPMC Address
O
V5
U4
gpmc_a16
GPMC Address
O
V6
R13, V2
gpmc_a17
GPMC Address
O
U6
V14, V3
gpmc_a18
GPMC Address
O
W6
U14, V4
gpmc_a19
GPMC Address
O
V7
T14, T5
gpmc_a2
GPMC Address
O
V1
R3, U14
gpmc_a20
GPMC Address
O
H19
F17, R14
gpmc_a21
GPMC Address
O
H18
F18, V15
gpmc_a22
GPMC Address
O
H17
G15, U15
gpmc_a23
GPMC Address
O
G18
G16, T15
gpmc_a24
GPMC Address
O
G19
G17, V16
gpmc_a25
GPMC Address
O
G17
G18, U16
gpmc_a26
GPMC Address
O
NA
T16
gpmc_a27
GPMC Address
O
NA
V17
gpmc_a3
GPMC Address
O
V2
R4, T14
gpmc_a4
GPMC Address
O
W2
R14, T1
gpmc_a5
GPMC Address
O
W3
T2, V15
gpmc_a6
GPMC Address
O
V3
T3, U15
gpmc_a7
GPMC Address
O
U3
T15, T4
gpmc_a8
GPMC Address
O
U7
U5, V16
gpmc_a9
GPMC Address
O
T7
R5, U16
gpmc_ad0
GPMC Address & Data
I/O
W10
U7
gpmc_ad1
GPMC Address & Data
I/O
V9
V7
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Table 2-13. External Memory Interfaces/General Purpose Memory Controller Signals Description
Terminal Description
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Table 2-13. External Memory Interfaces/General Purpose Memory Controller Signals
Description (continued)
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
gpmc_ad10
GPMC Address & Data
I/O
T12
T11
gpmc_ad11
GPMC Address & Data
I/O
U12
U12
gpmc_ad12
GPMC Address & Data
I/O
U13
T12
gpmc_ad13
GPMC Address & Data
I/O
T13
R12
gpmc_ad14
GPMC Address & Data
I/O
W17
V13
gpmc_ad15
GPMC Address & Data
I/O
V17
U13
gpmc_ad2
GPMC Address & Data
I/O
V12
R8
gpmc_ad3
GPMC Address & Data
I/O
W13
T8
gpmc_ad4
GPMC Address & Data
I/O
V13
U8
gpmc_ad5
GPMC Address & Data
I/O
W14
V8
gpmc_ad6
GPMC Address & Data
I/O
U14
R9
gpmc_ad7
GPMC Address & Data
I/O
W15
T9
gpmc_ad8
GPMC Address & Data
I/O
V15
U10
gpmc_ad9
GPMC Address & Data
I/O
W16
T10
gpmc_advn_ale
GPMC Address Valid / Address Latch Enable
O
V10
R7
gpmc_be0n_cle
GPMC Byte Enable 0 / Command Latch Enable
O
V8
T6
gpmc_be1n
GPMC Byte Enable 1
O
U15, V18
U18, V9
gpmc_clk
GPMC Clock
I/O
V14, V16
U9, V12
gpmc_csn0
GPMC Chip Select
O
W8
V6
gpmc_csn1
GPMC Chip Select
O
V14
U9
gpmc_csn2
GPMC Chip Select
O
U15
V9
gpmc_csn3
GPMC Chip Select
O
U17
T13
gpmc_csn4
GPMC Chip Select
O
R15
T17
gpmc_csn5
GPMC Chip Select
O
W18
U17
gpmc_csn6
GPMC Chip Select
O
V18
U18
gpmc_dir
GPMC Data Direction
O
V18
U18
gpmc_oen_ren
GPMC Output / Read Enable
O
W9
T7
gpmc_wait0
GPMC Wait 0
I
R15
T17
gpmc_wait1
GPMC Wait 1
I
V16
V12
gpmc_wen
GPMC Write Enable
O
U8
U6
gpmc_wpn
GPMC Write Protect
O
W18
U17
52
Terminal Description
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2.3.2
General Purpose IOs
Table 2-14. General Purpose IOs/GPIO0 Signals Description
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
gpio0_0
GPIO
I/O
P17
M17
gpio0_1
GPIO
I/O
R19
M18
gpio0_10
GPIO
I/O
W6
V4
gpio0_11
GPIO
I/O
V7
T5
gpio0_12
GPIO
I/O
E17
D18
gpio0_13
GPIO
I/O
D19
D17
gpio0_14
GPIO
I/O
D18
D16
gpio0_15
GPIO
I/O
C19
D15
gpio0_16
GPIO
I/O
M17
J18
gpio0_17
GPIO
I/O
N18
K15
gpio0_18
GPIO
I/O
G16
F16
gpio0_19
GPIO
I/O
C15
A15
gpio0_2
GPIO
I/O
A18
A17
gpio0_20
GPIO
I/O
B15
D14
gpio0_21
GPIO
I/O
M18
K16
gpio0_22
GPIO
I/O
V15
U10
gpio0_23
GPIO
I/O
W16
T10
gpio0_26
GPIO
I/O
T12
T11
gpio0_27
GPIO
I/O
U12
U12
gpio0_28
GPIO
I/O
L18
K17
gpio0_29
GPIO
I/O
K18
H18
gpio0_3
GPIO
I/O
B18
B17
gpio0_30
GPIO
I/O
R15
T17
gpio0_31
GPIO
I/O
W18
U17
gpio0_4
GPIO
I/O
B17
B16
gpio0_5
GPIO
I/O
A17
A16
gpio0_6
GPIO
I/O
B16
C15
gpio0_7
GPIO
I/O
E18
C18
gpio0_8
GPIO
I/O
V6
V2
gpio0_9
GPIO
I/O
U6
V3
PRODUCT PREVIEW
SIGNAL NAME [1]
Table 2-15. General Purpose IOs/GPIO1 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
gpio1_0
GPIO
I/O
W10
U7
gpio1_1
GPIO
I/O
V9
V7
gpio1_10
GPIO
I/O
E19
E15
gpio1_11
GPIO
I/O
F17
E16
gpio1_12
GPIO
I/O
U13
T12
gpio1_13
GPIO
I/O
T13
R12
gpio1_14
GPIO
I/O
W17
V13
gpio1_15
GPIO
I/O
V17
U13
gpio1_16
GPIO
I/O
NA
R13
gpio1_17
GPIO
I/O
NA
V14
gpio1_18
GPIO
I/O
NA
U14
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Terminal Description
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Table 2-15. General Purpose IOs/GPIO1 Signals Description (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
gpio1_19
GPIO
I/O
NA
T14
gpio1_2
GPIO
I/O
V12
R8
gpio1_20
GPIO
I/O
NA
R14
gpio1_21
GPIO
I/O
NA
V15
gpio1_22
GPIO
I/O
NA
U15
gpio1_23
GPIO
I/O
NA
T15
gpio1_24
GPIO
I/O
NA
V16
gpio1_25
GPIO
I/O
NA
U16
gpio1_26
GPIO
I/O
NA
T16
gpio1_27
GPIO
I/O
NA
V17
gpio1_28
GPIO
I/O
V18
U18
gpio1_29
GPIO
I/O
W8
V6
gpio1_3
GPIO
I/O
W13
T8
gpio1_30
GPIO
I/O
V14
U9
gpio1_31
GPIO
I/O
U15
V9
gpio1_4
GPIO
I/O
V13
U8
gpio1_5
GPIO
I/O
W14
V8
gpio1_6
GPIO
I/O
U14
R9
gpio1_7
GPIO
I/O
W15
T9
gpio1_8
GPIO
I/O
F19
E18
gpio1_9
GPIO
I/O
F18
E17
Table 2-16. General Purpose IOs/GPIO2 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
gpio2_0
GPIO
I/O
U17
T13
gpio2_1
GPIO
I/O
V16
V12
gpio2_10
GPIO
I/O
W2
T1
gpio2_11
GPIO
I/O
W3
T2
gpio2_12
GPIO
I/O
V3
T3
gpio2_13
GPIO
I/O
U3
T4
gpio2_14
GPIO
I/O
V4
U1
gpio2_15
GPIO
I/O
W4
U2
gpio2_16
GPIO
I/O
U5
U3
gpio2_17
GPIO
I/O
V5
U4
gpio2_18
GPIO
I/O
N17
L17
gpio2_19
GPIO
I/O
N16
L16
gpio2_2
GPIO
I/O
V10
R7
gpio2_20
GPIO
I/O
P19
L15
gpio2_21
GPIO
I/O
P18
M16
gpio2_22
GPIO
I/O
U7
U5
gpio2_23
GPIO
I/O
T7
R5
gpio2_24
GPIO
I/O
W5
V5
gpio2_25
GPIO
I/O
W7
R6
gpio2_26
GPIO
I/O
H19
F17
gpio2_27
GPIO
I/O
H18
F18
gpio2_28
GPIO
I/O
H17
G15
54
Terminal Description
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Table 2-16. General Purpose IOs/GPIO2 Signals Description (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
gpio2_29
GPIO
I/O
G18
G16
gpio2_3
GPIO
I/O
W9
T7
gpio2_30
GPIO
I/O
G19
G17
gpio2_31
GPIO
I/O
G17
G18
gpio2_4
GPIO
I/O
U8
U6
gpio2_5
GPIO
I/O
V8
T6
gpio2_6
GPIO
I/O
U1
R1
gpio2_7
GPIO
I/O
U2
R2
gpio2_8
GPIO
I/O
V1
R3
gpio2_9
GPIO
I/O
V2
R4
Table 2-17. General Purpose IOs/GPIO3 Signals Description
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
gpio3_0
GPIO
I/O
J19
H16
gpio3_1
GPIO
I/O
J18
H17
gpio3_10
GPIO
I/O
M19
L18
gpio3_13
GPIO
I/O
NA
F15
gpio3_14
GPIO
I/O
NA
A13
gpio3_15
GPIO
I/O
NA
B13
gpio3_16
GPIO
I/O
NA
D12
gpio3_17
GPIO
I/O
NA
C12
gpio3_18
GPIO
I/O
NA
B12
gpio3_19
GPIO
I/O
NA
C13
gpio3_2
GPIO
I/O
K19
J15
gpio3_20
GPIO
I/O
NA
D13
gpio3_21
GPIO
I/O
NA
A14
gpio3_3
GPIO
I/O
K17
J16
gpio3_4
GPIO
I/O
L19
J17
gpio3_5
GPIO
I/O
C18
C17
gpio3_6
GPIO
I/O
B19
C16
gpio3_7
GPIO
I/O
A15
C14
gpio3_8
GPIO
I/O
D14
B14
gpio3_9
GPIO
I/O
N19
K18
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PRODUCT PREVIEW
SIGNAL NAME [1]
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Miscellaneous
Table 2-18. Miscellaneous/Miscellaneous Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
clkout1
Clock out1
O
C15
A15
clkout2
Clock out2
O
B15
D14
ENZ_KALDO_1P8V
Active low output enable for CAP_VDD_RTC
I
A7
B4
EXT_WAKEUP
EXT_WAKEUP
I
B5
C5
nNMI
External Interrupt to ARM Cortext A8 core
I
C17
B18
nRESETIN_OUT
Chip Reset
I/OD
A16
A10
OSC0_IN
HF OSCILLATOR RECEIVER
I
W11
V10
OSC0_OUT
HF OSCILLATOR DRIVER
O
W12
U11
PMIC_POWER_EN
PMIC_POWER_EN
O
C7
C6
porz
Power on Reset
I
E15
B15
tclkin
Timer Clock In
I
B15
D14
xdma_event_intr0
External DMA Event or Interrupt 0
I
C15
A15
xdma_event_intr1
External DMA Event or Interrupt 1
I
B15
D14
xdma_event_intr2
External DMA Event or Interrupt 2
I
B16, E18, K18
C15, C18, H18
56
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2.3.3.1
eCAP
Table 2-19. eCAP/eCAP0 Signals Description
SIGNAL NAME [1]
eCAP0_in_PWM0_out
DESCRIPTION [2]
enhanced capture 0 input or Auxiliary PWM0 out
TYPE
[3]
I/O
ZCE BALL [4]
E18
ZCZ BALL [4]
C18
Table 2-20. eCAP/eCAP1 Signals Description
SIGNAL NAME [1]
eCAP1_in_PWM1_out
DESCRIPTION [2]
enhanced capture 1 input or Auxiliary PWM1 out
TYPE
[3]
I/O
ZCE BALL [4]
B16, B19, F17
ZCZ BALL [4]
C15, C16, E16
Table 2-21. eCAP/eCAP2 Signals Description
SIGNAL NAME [1]
enhanced capture 2 input or Auxiliary PWM2 out
TYPE
[3]
I/O
ZCE BALL [4]
C18, E19
ZCZ BALL [4]
C12, C17, E15
PRODUCT PREVIEW
eCAP2_in_PWM2_out
DESCRIPTION [2]
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eHRPWM
Table 2-22. eHRPWM/eHRPWM0 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
ehrpwm0A
eHRPWM0 A output.
O
A18
A13, A17
ehrpwm0B
eHRPWM0 B output.
O
B18
B13, B17
ehrpwm0_synci
Sync input to eHRPWM0 module from an
external pin
I
A17
A16, C12
ehrpwm0_synco
Sync Output from eHRPWM0 module to an
external pin
O
U12, V2, W4
R4, U12, U2, V14
ehrpwm0_tripzone_input
eHRPWM0 trip zone input
I
B17
B16, D12
Table 2-23. eHRPWM/eHRPWM1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
ehrpwm1A
eHRPWM1 A output.
O
U5
U14, U3
ehrpwm1B
eHRPWM1 B output.
O
V5
T14, U4
ehrpwm1_tripzone_input
eHRPWM1 trip zone input
I
V4
R13, U1
PRODUCT PREVIEW
Table 2-24. eHRPWM/eHRPWM2 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
ehrpwm2A
eHRPWM2 A output.
O
U1, V15
R1, U10
ehrpwm2B
eHRPWM2 B output.
O
U2, W16
R2, T10
ehrpwm2_tripzone_input
eHRPWM2 trip zone input
I
T12, V1
R3, T11
58
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2.3.3.3
eQEP
Table 2-25. eQEP/eQEP0 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
eQEP0A_in
eQEP0A quadrature input
I
M18
B12, K16
eQEP0B_in
eQEP0B quadrature input
I
L18
C13, K17
eQEP0_index
eQEP0 index.
I/O
K17
D13, J16
eQEP0_strobe
eQEP0 strobe.
I/O
P19
A14, L15
Table 2-26. eQEP/eQEP1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
eQEP1A_in
eQEP1A quadrature input
I
V6
R14, V2
eQEP1B_in
eQEP1B quadrature input
I
U6
V15, V3
eQEP1_index
eQEP1 index.
I/O
W6
U15, V4
eQEP1_strobe
eQEP1 strobe.
I/O
V7
T15, T5
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
eQEP2A_in
eQEP2A quadrature input
I
U13, W2
T1, T12
eQEP2B_in
eQEP2B quadrature input
I
T13, W3
R12, T2
eQEP2_index
eQEP2 index.
I/O
V3, W17
T3, V13
eQEP2_strobe
eQEP2 strobe.
I/O
U3, V17
T4, U13
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PRODUCT PREVIEW
Table 2-27. eQEP/eQEP2 Signals Description
Terminal Description
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Timer
Table 2-28. Timer/Timer4 Signals Description
SIGNAL NAME [1]
timer4
DESCRIPTION [2]
Timer trigger event / PWM out
TYPE
[3]
I/O
ZCE BALL [4]
C15, C18, K17,
V10
ZCZ BALL [4]
A15, C17, J16,
R7
Table 2-29. Timer/Timer5 Signals Description
SIGNAL NAME [1]
timer5
DESCRIPTION [2]
Timer trigger event / PWM out
TYPE
[3]
I/O
ZCE BALL [4]
D19, H19, R19,
V8
ZCZ BALL [4]
D17, F17, M18,
T6
Table 2-30. Timer/Timer6 Signals Description
SIGNAL NAME [1]
timer6
DESCRIPTION [2]
Timer trigger event / PWM out
TYPE
[3]
I/O
ZCE BALL [4]
E17, H18, P17,
U8
ZCZ BALL [4]
D18, F18, M17,
U6
PRODUCT PREVIEW
Table 2-31. Timer/Timer7 Signals Description
SIGNAL NAME [1]
timer7
60
DESCRIPTION [2]
Timer trigger event / PWM out
Terminal Description
TYPE
[3]
I/O
ZCE BALL [4]
B15, B19, F19,
W9
ZCZ BALL [4]
C16, D14, E18,
T7
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2.3.4
PRU Subsystem
Table 2-32. PRU Subsystem/MII0 Signals Description
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mii0_col
MII Collision Detect
I
W16
T10
pr1_mii0_crs
MII Carrier Sense
I
U17, W5
T13, V5
pr1_mii0_rxd0
MII Receive Data bit 0
I
V5
U4
pr1_mii0_rxd1
MII Receive Data bit 1
I
U5
U3
pr1_mii0_rxd2
MII Receive Data bit 2
I
W4
U2
pr1_mii0_rxd3
MII Receive Data bit 3
I
V4
U1
pr1_mii0_rxdv
MII Receive Data Valid
I
V7
T5
pr1_mii0_rxer
MII Receive Data Error
I
U6
V3
pr1_mii0_rxlink
MII Receive Link
I
V6
V2
pr1_mii0_txd0
MII Transmit Data bit 0
O
W17, W3
T2, V13
pr1_mii0_txd1
MII Transmit Data bit 1
O
T13, W2
R12, T1
pr1_mii0_txd2
MII Transmit Data bit 2
O
U13, V2
R4, T12
pr1_mii0_txd3
MII Transmit Data bit 3
O
U12, V1
R3, U12
pr1_mii0_txen
MII Transmit Enable
O
T12, U2
R2, T11
pr1_mii_mr0_clk
MII Receive Clock
I
W6
V4
pr1_mii_mt0_clk
MII Transmit Clock
I
U1, V15
R1, U10
PRODUCT PREVIEW
SIGNAL NAME [1]
Table 2-33. PRU Subsystem/MII1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mii1_col
MII Collision Detect
I
R15
T17
pr1_mii1_crs
MII Carrier Sense
I
V16, W7
R6, V12
pr1_mii1_rxd0
MII Receive Data bit 0
I
NA
V16
pr1_mii1_rxd1
MII Receive Data bit 1
I
NA
T15
pr1_mii1_rxd2
MII Receive Data bit 2
I
NA
U15
pr1_mii1_rxd3
MII Receive Data bit 3
I
NA
V15
pr1_mii1_rxdv
MII Receive Data Valid
I
NA
T16
pr1_mii1_rxer
MII Receive Data Error
I
NA
V17
pr1_mii1_rxlink
MII Receive Link
I
V18
U18
pr1_mii1_txd0
MII Transmit Data bit 0
O
NA
R14
pr1_mii1_txd1
MII Transmit Data bit 1
O
NA
T14
pr1_mii1_txd2
MII Transmit Data bit 2
O
NA
U14
pr1_mii1_txd3
MII Transmit Data bit 3
O
NA
V14
pr1_mii1_txen
MII Transmit Enable
O
W18
U17
pr1_mii_mr1_clk
MII Receive Clock
I
NA
U16
pr1_mii_mt1_clk
MII Transmit Clock
I
NA
R13
Table 2-34. PRU Subsystem/UART0 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_uart0_cts_n
UART Clear to Send
I
A18, E17
A17, D18
pr1_uart0_rts_n
UART Request to Send
O
B18, D19
B17, D17
pr1_uart0_rxd
UART Receive Data
I
B17, D18
B16, D16
pr1_uart0_txd
UART Transmit Data
O
A17, C19
A16, D15
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PRU0
Table 2-35. PRU0/General Purpose Inputs Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
pr1_pru0_pru_r31_0
PRU0 Data In
I
NA
A13
pr1_pru0_pru_r31_1
PRU0 Data In
I
NA
B13
pr1_pru0_pru_r31_10
PRU0 Data In
I
H17
G15
pr1_pru0_pru_r31_11
PRU0 Data In
I
G18
G16
pr1_pru0_pru_r31_12
PRU0 Data In
I
G19
G17
pr1_pru0_pru_r31_13
PRU0 Data In
I
G17
G18
pr1_pru0_pru_r31_14
PRU0 Data In
I
W17
V13
pr1_pru0_pru_r31_15
PRU0 Data In
I
V17
U13
pr1_pru0_pru_r31_16
PRU0 Data In Capture Enable
I
B15, C19
D14, D15
pr1_pru0_pru_r31_2
PRU0 Data In
I
NA
D12
pr1_pru0_pru_r31_3
PRU0 Data In
I
NA
C12
pr1_pru0_pru_r31_4
PRU0 Data In
I
NA
B12
pr1_pru0_pru_r31_5
PRU0 Data In
I
NA
C13
pr1_pru0_pru_r31_6
PRU0 Data In
I
NA
D13
pr1_pru0_pru_r31_7
PRU0 Data In
I
NA
A14
pr1_pru0_pru_r31_8
PRU0 Data In
I
H19
F17
pr1_pru0_pru_r31_9
PRU0 Data In
I
H18
F18
Table 2-36. PRU0/General Purpose Outputs Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_pru0_pru_r30_0
PRU0 Data Out
O
NA
A13
pr1_pru0_pru_r30_1
PRU0 Data Out
O
NA
B13
pr1_pru0_pru_r30_10
PRU0 Data Out
O
H17
G15
pr1_pru0_pru_r30_11
PRU0 Data Out
O
G18
G16
pr1_pru0_pru_r30_12
PRU0 Data Out
O
G19
G17
pr1_pru0_pru_r30_13
PRU0 Data Out
O
G17
G18
pr1_pru0_pru_r30_14
PRU0 Data Out
O
U13
T12
pr1_pru0_pru_r30_15
PRU0 Data Out
O
T13
R12
pr1_pru0_pru_r30_2
PRU0 Data Out
O
NA
D12
pr1_pru0_pru_r30_3
PRU0 Data Out
O
NA
C12
pr1_pru0_pru_r30_4
PRU0 Data Out
O
NA
B12
pr1_pru0_pru_r30_5
PRU0 Data Out
O
NA
C13
pr1_pru0_pru_r30_6
PRU0 Data Out
O
NA
D13
pr1_pru0_pru_r30_7
PRU0 Data Out
O
NA
A14
pr1_pru0_pru_r30_8
PRU0 Data Out
O
H19
F17
pr1_pru0_pru_r30_9
PRU0 Data Out
O
H18
F18
62
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2.3.4.2
PRU1
Table 2-37. PRU1/General Purpose Inputs Signals Description
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_pru1_pru_r31_0
PRU1 Data In
I
U1
R1
pr1_pru1_pru_r31_1
PRU1 Data In
I
U2
R2
pr1_pru1_pru_r31_10
PRU1 Data In
I
W5
V5
pr1_pru1_pru_r31_11
PRU1 Data In
I
W7
R6
pr1_pru1_pru_r31_12
PRU1 Data In
I
V14
U9
pr1_pru1_pru_r31_13
PRU1 Data In
I
U15
V9
pr1_pru1_pru_r31_14
PRU1 Data In
I
E19
E15
pr1_pru1_pru_r31_15
PRU1 Data In
I
F17
E16
pr1_pru1_pru_r31_16
PRU1 Data In Capture Enable
I
C15, D18
A15, D16
pr1_pru1_pru_r31_2
PRU1 Data In
I
V1
R3
pr1_pru1_pru_r31_3
PRU1 Data In
I
V2
R4
pr1_pru1_pru_r31_4
PRU1 Data In
I
W2
T1
pr1_pru1_pru_r31_5
PRU1 Data In
I
W3
T2
pr1_pru1_pru_r31_6
PRU1 Data In
I
V3
T3
pr1_pru1_pru_r31_7
PRU1 Data In
I
U3
T4
pr1_pru1_pru_r31_8
PRU1 Data In
I
U7
U5
pr1_pru1_pru_r31_9
PRU1 Data In
I
T7
R5
PRODUCT PREVIEW
SIGNAL NAME [1]
Table 2-38. PRU1/General Purpose Outputs Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_pru1_pru_r30_0
PRU1 Data Out
O
U1
R1
pr1_pru1_pru_r30_1
PRU1 Data Out
O
U2
R2
pr1_pru1_pru_r30_10
PRU1 Data Out
O
W5
V5
pr1_pru1_pru_r30_11
PRU1 Data Out
O
W7
R6
pr1_pru1_pru_r30_12
PRU1 Data Out
O
V14
U9
pr1_pru1_pru_r30_13
PRU1 Data Out
O
U15
V9
pr1_pru1_pru_r30_14
PRU1 Data Out
O
E19
E15
pr1_pru1_pru_r30_15
PRU1 Data Out
O
F17
E16
pr1_pru1_pru_r30_2
PRU1 Data Out
O
V1
R3
pr1_pru1_pru_r30_3
PRU1 Data Out
O
V2
R4
pr1_pru1_pru_r30_4
PRU1 Data Out
O
W2
T1
pr1_pru1_pru_r30_5
PRU1 Data Out
O
W3
T2
pr1_pru1_pru_r30_6
PRU1 Data Out
O
V3
T3
pr1_pru1_pru_r30_7
PRU1 Data Out
O
U3
T4
pr1_pru1_pru_r30_8
PRU1 Data Out
O
U7
U5
pr1_pru1_pru_r30_9
PRU1 Data Out
O
T7
R5
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Removable Media Interfaces
Table 2-39. Removable Media Interfaces/MMC0 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
mmc0_clk
MMC/SD/SDIO Clock
I/O
G19
G17
mmc0_cmd
MMC/SD/SDIO Command
I/O
G17
G18
mmc0_dat0
MMC/SD/SDIO Data Bus
I/O
G18
G16
mmc0_dat1
MMC/SD/SDIO Data Bus
I/O
H17
G15
mmc0_dat2
MMC/SD/SDIO Data Bus
I/O
H18
F18
mmc0_dat3
MMC/SD/SDIO Data Bus
I/O
H19
F17
mmc0_dat4
MMC/SD/SDIO Data Bus
I/O
N16
L16
mmc0_dat5
MMC/SD/SDIO Data Bus
I/O
N17
L17
mmc0_dat6
MMC/SD/SDIO Data Bus
I/O
M19
L18
mmc0_dat7
MMC/SD/SDIO Data Bus
I/O
N19
K18
mmc0_pow
MMC/SD Power Switch Control
O
B16, K18
C15, H18
mmc0_sdcd
SD Card Detect
I
B16, P17
A13, C15, M17
mmc0_sdwp
SD Write Protect
I
E18, R19
B12, C18, M18
PRODUCT PREVIEW
Table 2-40. Removable Media Interfaces/MMC1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
mmc1_clk
MMC/SD/SDIO Clock
I/O
L18, R19, V14
K17, M18, U9
mmc1_cmd
MMC/SD/SDIO Command
I/O
M18, P17, U15
K16, M17, V9
mmc1_dat0
MMC/SD/SDIO Data Bus
I/O
N19, V15, W10
K18, U10, U7
mmc1_dat1
MMC/SD/SDIO Data Bus
I/O
M19, V9, W16
L18, T10, V7
mmc1_dat2
MMC/SD/SDIO Data Bus
I/O
N17, T12, V12
L17, R8, T11
mmc1_dat3
MMC/SD/SDIO Data Bus
I/O
N16, U12, W13
L16, T8, U12
mmc1_dat4
MMC/SD/SDIO Data Bus
I/O
U13, V13
T12, U8
mmc1_dat5
MMC/SD/SDIO Data Bus
I/O
T13, W14
R12, V8
mmc1_dat6
MMC/SD/SDIO Data Bus
I/O
U14, W17
R9, V13
mmc1_dat7
MMC/SD/SDIO Data Bus
I/O
V17, W15
T9, U13
mmc1_sdcd
SD Card Detect
I
R15
B13, T17
mmc1_sdwp
SD Write Protect
I
B17, D18
B16, D16
Table 2-41. Removable Media Interfaces/MMC2 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
mmc2_clk
MMC/SD/SDIO Clock
I/O
P19, R19, V16
L15, M18, V12
mmc2_cmd
MMC/SD/SDIO Command
I/O
K17, P17, U17
J16, M17, T13
mmc2_dat0
MMC/SD/SDIO Data Bus
I/O
L19, U13
J17, T12, V14
mmc2_dat1
MMC/SD/SDIO Data Bus
I/O
M17, T13
J18, R12, U14
mmc2_dat2
MMC/SD/SDIO Data Bus
I/O
N18, W17
K15, T14, V13
mmc2_dat3
MMC/SD/SDIO Data Bus
I/O
J19, V17, V18
H16, U13, U18
mmc2_dat4
MMC/SD/SDIO Data Bus
I/O
V15
U10, U15
mmc2_dat5
MMC/SD/SDIO Data Bus
I/O
W16
T10, T15
mmc2_dat6
MMC/SD/SDIO Data Bus
I/O
T12
T11, V16
mmc2_dat7
MMC/SD/SDIO Data Bus
I/O
U12
U12, U16
mmc2_sdcd
SD Card Detect
I
W18
D12, U17
mmc2_sdwp
SD Write Protect
I
A17, C19
A16, D15
64
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2.3.6
2.3.6.1
Serial Communication Interfaces
CAN
Table 2-42. CAN/DCAN0 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
dcan0_rx
DCAN0 Receive Data
I
D19, F17, N18
D17, E16, K15
dcan0_tx
DCAN0 Transmit Data
O
E17, E19, M17
D18, E15, J18
Table 2-43. CAN/DCAN1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
DCAN1 Receive Data
I
C19, F18, G17
D15, E17, G18
dcan1_tx
DCAN1 Transmit Data
O
D18, F19, G19
D16, E18, G17
PRODUCT PREVIEW
dcan1_rx
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GEMAC_CPSW
Table 2-44. GEMAC_CPSW/MII1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
gmii1_col
MII Colision
I
J19
H16
gmii1_crs
MII Carrier Sense
I
J18
H17
gmii1_rxclk
MII Receive Clock
I
M19
L18
gmii1_rxd0
MII Receive Data bit 0
I
P18
M16
gmii1_rxd1
MII Receive Data bit 1
I
P19
L15
gmii1_rxd2
MII Receive Data bit 2
I
N16
L16
gmii1_rxd3
MII Receive Data bit 3
I
N17
L17
gmii1_rxdv
MII Receive Data Valid
I
L19
J17
gmii1_rxer
MII Receive Data Error
I
K19
J15
gmii1_txclk
MII Transmit Clock
I
N19
K18
gmii1_txd0
MII Transmit Data bit 0
O
L18
K17
gmii1_txd1
MII Transmit Data bit 1
O
M18
K16
gmii1_txd2
MII Transmit Data bit 2
O
N18
K15
gmii1_txd3
MII Transmit Data bit 3
O
M17
J18
gmii1_txen
MII Transmit Enable
O
K17
J16
Table 2-45. GEMAC_CPSW/MII2 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gmii2_col
MII Colision
I
V18
U18
gmii2_crs
MII Carrier Sense
I
R15
T17
gmii2_rxclk
MII Receive Clock
I
NA
T15
gmii2_rxd0
MII Receive Data bit 0
I
NA
V17
gmii2_rxd1
MII Receive Data bit 1
I
NA
T16
gmii2_rxd2
MII Receive Data bit 2
I
NA
U16
gmii2_rxd3
MII Receive Data bit 3
I
NA
V16
gmii2_rxdv
MII Receive Data Valid
I
NA
V14
gmii2_rxer
MII Receive Data Error
I
W18
U17
gmii2_txclk
MII Transmit Clock
I
NA
U15
gmii2_txd0
MII Transmit Data bit 0
O
NA
V15
gmii2_txd1
MII Transmit Data bit 1
O
NA
R14
gmii2_txd2
MII Transmit Data bit 2
O
NA
T14
gmii2_txd3
MII Transmit Data bit 3
O
NA
U14
gmii2_txen
MII Transmit Enable
O
NA
R13
Table 2-46. GEMAC_CPSW/RGMII1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rgmii1_rclk
RGMII Receive Clock
I
M19
L18
rgmii1_rctl
RGMII Receive Control
I
L19
J17
rgmii1_rd0
RGMII Receive Data bit 0
I
P18
M16
rgmii1_rd1
RGMII Receive Data bit 1
I
P19
L15
rgmii1_rd2
RGMII Receive Data bit 2
I
N16
L16
rgmii1_rd3
RGMII Receive Data bit 3
I
N17
L17
rgmii1_tclk
RGMII Transmit Clock
O
N19
K18
66
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Table 2-46. GEMAC_CPSW/RGMII1 Signals Description (continued)
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rgmii1_tctl
RGMII Transmit Control
O
K17
J16
rgmii1_td0
RGMII Transmit Data bit 0
O
L18
K17
rgmii1_td1
RGMII Transmit Data bit 1
O
M18
K16
rgmii1_td2
RGMII Transmit Data bit 2
O
N18
K15
rgmii1_td3
RGMII Transmit Data bit 3
O
M17
J18
Table 2-47. GEMAC_CPSW/RGMII2 Signals Description
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rgmii2_rclk
RGMII Receive Clock
I
NA
T15
rgmii2_rctl
RGMII Receive Control
I
NA
V14
rgmii2_rd0
RGMII Receive Data bit 0
I
NA
V17
rgmii2_rd1
RGMII Receive Data bit 1
I
NA
T16
rgmii2_rd2
RGMII Receive Data bit 2
I
NA
U16
rgmii2_rd3
RGMII Receive Data bit 3
I
NA
V16
rgmii2_tclk
RGMII Transmit Clock
O
NA
U15
rgmii2_tctl
RGMII Transmit Control
O
NA
R13
rgmii2_td0
RGMII Transmit Data bit 0
O
NA
V15
rgmii2_td1
RGMII Transmit Data bit 1
O
NA
R14
rgmii2_td2
RGMII Transmit Data bit 2
O
NA
T14
rgmii2_td3
RGMII Transmit Data bit 3
O
NA
U14
PRODUCT PREVIEW
SIGNAL NAME [1]
Table 2-48. GEMAC_CPSW/RMII1 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii1_crs_dv
RMII Carrier Sense / Data Valid
I
J18
H17
rmii1_refclk
RMII Reference Clock
I/O
K18
H18
rmii1_rxd0
RMII Receive Data bit 0
I
P18
M16
rmii1_rxd1
RMII Receive Data bit 1
I
P19
L15
rmii1_rxer
RMII Receive Data Error
I
K19
J15
rmii1_txd0
RMII Transmit Data bit 0
O
L18
K17
rmii1_txd1
RMII Transmit Data bit 1
O
M18
K16
rmii1_txen
RMII Transmit Enable
O
K17
J16
Table 2-49. GEMAC_CPSW/RMII2 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii2_crs_dv
RMII Carrier Sense / Data Valid
I
R15
T17
rmii2_refclk
RMII Reference Clock
I/O
J19
H16
rmii2_rxd0
RMII Receive Data bit 0
I
NA
V17
rmii2_rxd1
RMII Receive Data bit 1
I
NA
T16
rmii2_rxer
RMII Receive Data Error
I
W18
U17
rmii2_txd0
RMII Transmit Data bit 0
O
NA
V15
rmii2_txd1
RMII Transmit Data bit 1
O
NA
R14
rmii2_txen
RMII Transmit Enable
O
NA
R13
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I2C
Table 2-50. I2C/I2C0 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
I2C0_SCL
I2C0 Clock
I/OD
B19
C16
I2C0_SDA
I2C0 Data
I/OD
C18
C17
Table 2-51. I2C/I2C1 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
I2C1_SCL
I2C1 Clock
I/OD
A17, C19, F18,
K19
A16, D15, E17,
J15
I2C1_SDA
I2C1 Data
I/OD
B17, D18, F19,
J18
B16, D16, E18,
H17
Table 2-52. I2C/I2C2 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
I2C2_SCL
I2C2 Clock
I/OD
B18, D19, F17
B17, D17, E16
I2C2_SDA
I2C2 Data
I/OD
A18, E17, E19
A17, D18, E15
68
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2.3.6.4
McASP
Table 2-53. McASP/MCASP0 Signals Description
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
mcasp0_aclkr
McASP0 Receive Bit Clock
I/O
L19, V18, V6
B12, J17, U18,
V2
mcasp0_aclkx
McASP0 Transmit Bit Clock
I/O
N19, V4
A13, K18, U1,
V16
mcasp0_ahclkr
McASP0 Receive Master Clock
I/O
V5
C12, U4
mcasp0_ahclkx
McASP0 Transmit Master Clock
I/O
N18, V7
A14, K15, T5
mcasp0_axr0
McASP0 Serial Data (IN/OUT)
I/O
N17, U5
D12, L17, T16,
U3
mcasp0_axr1
McASP0 Serial Data (IN/OUT)
I/O
N16, W6
D13, L16, V17,
V4
mcasp0_axr2
McASP0 Serial Data (IN/OUT)
I/O
J19, V5, V6
B12, C12, H16,
U4, V2
mcasp0_axr3
McASP0 Serial Data (IN/OUT)
I/O
P18, U6, V7
A14, C13, M16,
T5, V3
mcasp0_fsr
McASP0 Receive Frame Sync
I/O
M17, U6, V16
C13, J18, V12,
V3
mcasp0_fsx
McASP0 Transmit Frame Sync
I/O
M19, W4
B13, L18, U16,
U2
PRODUCT PREVIEW
SIGNAL NAME [1]
Table 2-54. McASP/MCASP1 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
mcasp1_aclkr
McASP1 Receive Bit Clock
I/O
L18, P18
K17, M16
mcasp1_aclkx
McASP1 Transmit Bit Clock
I/O
J18, L19
B12, H17, J17
mcasp1_ahclkr
McASP1 Receive Master Clock
I/O
P18
M16
mcasp1_ahclkx
McASP1 Transmit Master Clock
I/O
K18, P18
H18, M16
mcasp1_axr0
McASP1 Serial Data (IN/OUT)
I/O
K17, N18
D13, J16, K15
mcasp1_axr1
McASP0 Serial Data (IN/OUT)
I/O
M18
A14, K16
mcasp1_axr2
McASP0 Serial Data (IN/OUT)
I/O
J19, L18
H16, K17
mcasp1_axr3
McASP0 Serial Data (IN/OUT)
I/O
K18, P19
H18, L15
mcasp1_fsr
McASP1 Receive Frame Sync
I/O
M18, P19
K16, L15
mcasp1_fsx
McASP1 Transmit Frame Sync
I/O
K19, M17
C13, J15, J18
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SPI
Table 2-55. SPI/SPI0 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
spi0_cs0
SPI Chip Select
I/O
A17
A16
spi0_cs1
SPI Chip Select
I/O
B16
C15
spi0_d0
SPI Data
I/O
B18
B17
spi0_d1
SPI Data
I/O
B17
B16
spi0_sclk
SPI Clock
I/O
A18
A17
Table 2-56. SPI/SPI1 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
PRODUCT PREVIEW
spi1_cs0
SPI Chip Select
I/O
E17, E19, F18,
K18
C12, D18, E15,
E17, H18
spi1_cs1
SPI Chip Select
I/O
C15, D19, E18,
F17
A15, C18, D17,
E16
spi1_d0
SPI Data
I/O
F19, J18
B13, E18, H17
spi1_d1
SPI Data
I/O
F18, K19
D12, E17, J15
spi1_sclk
SPI Clock
I/O
E18, J19
A13, C18, H16
70
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2.3.6.6
UART
Table 2-57. UART/UART0 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
uart0_ctsn
UART Clear to Send
I
F19
E18
uart0_rtsn
UART Request to Send
O
F18
E17
uart0_rxd
UART Receive Data
I
E19
E15
uart0_txd
UART Transmit Data
O
F17
E16
Table 2-58. UART/UART1 Signals Description
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
uart1_ctsn
UART Clear to Send
I
E17
D18
uart1_dcdn
UART Clear to Send
I
H19, N19
F17, K18
uart1_dsrn
UART Request to Send
I
H18, M19
F18, L18
uart1_dtrn
UART Receive Data
O
H17, N17
G15, L17
uart1_rin
UART Transmit Data
I
G18, N16
G16, L16
uart1_rtsn
UART Request to Send
O
D19
D17
uart1_rxd
UART Receive Data
I
D18
D16
uart1_txd
UART Transmit Data
O
C19
D15
PRODUCT PREVIEW
SIGNAL NAME [1]
Table 2-59. UART/UART2 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
uart2_ctsn
UART Clear to Send
I
C18, V4
C17, U1
uart2_rtsn
UART Request to Send
O
B19, W4
C16, U2
uart2_rxd
UART Receive Data
I
A18, G19, J18,
N19
A17, G17, H17,
K18
uart2_txd
UART Transmit Data
O
B18, G17, K19,
M19
B17, G18, J15,
L18
Table 2-60. UART/UART3 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
uart3_ctsn
UART Clear to Send
I
G19, P17, U5
G17, M17, U3
uart3_rtsn
UART Request to Send
O
G17, R19, V5
G18, M18, U4
uart3_rxd
UART Receive Data
I
B16, H17, N17
C15, G15, L17
uart3_txd
UART Transmit Data
O
E18, G18, N16
C18, G16, L16
Table 2-61. UART/UART4 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
uart4_ctsn
UART Clear to Send
I
H19, V6
F17, V2
uart4_rtsn
UART Request to Send
O
H18, U6
F18, V3
uart4_rxd
UART Receive Data
I
F19, M17, R15
E18, J18, T17
uart4_txd
UART Transmit Data
O
F18, N18, W18
E17, K15, U17
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Table 2-62. UART/UART5 Signals Description
SIGNAL NAME [1]
TYPE
[3]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
uart5_ctsn
UART Clear to Send
I
H17, J18, W6
G15, H17, V4
uart5_rtsn
UART Request to Send
O
G18, K19, V7
G16, J15, T5
uart5_rxd
UART Receive Data
O
J19, P17, W4,
W6
H16, M17, U2, V4
uart5_txd
UART Transmit Data
O
K18, L19, R19,
V4
H18, J17, M18,
U1
PRODUCT PREVIEW
72
Terminal Description
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2.3.6.7
USB
Table 2-63. USB/USB0 Signals Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
USB0_CE
USB0 PHY Charger Enable
A
T18
M15
USB0_DM
USB0 PHY DATA PLUS
A
U18
N18
USB0_DP
USB0 PHY DATA MINUS
A
U19
N17
USB0_DRVVBUS
USB0 CONTROLLER VBUS CONTROL
OUTPUT
O
G16
F16
USB0_ID
USB0 PHY IDENTIFICATION (Mini-A or Mini-B
Plug)
A
V19
P16
USB0_VBUS
USB0 BUS VOLTAGE
A
T19
P15
Table 2-64. USB/USB1 Signals Description
DESCRIPTION [2]
TYPE
[3]
ZCE BALL [4]
ZCZ BALL [4]
USB1_CE
USB1 PHY Charger Enable
A
NA
P18
USB1_DM
USB0 PHY DATA MINUS
A
NA
R18
USB1_DP
USB0 PHY DATA PLUS
A
NA
R17
USB1_DRVVBUS
USB0 CONTROLLER VBUS CONTROL
OUTPUT
O
NA
F15
USB1_ID
USB0 PHY IDENTIFICATION (Mini-A or Mini-B
Plug)
A
NA
P17
USB1_VBUS
USB0 BUS VOLTAGE
A
NA
T18
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Terminal Description
PRODUCT PREVIEW
SIGNAL NAME [1]
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3 Device Operating Conditions
3.1
Absolute Maximum Ratings
Table 3-1. Absolute Maximum Ratings Over Junction Temperature Range (Unless Otherwise Noted)(1)(2)
PARAMETER
PRODUCT PREVIEW
MIN
MAX
VDD_MPU(3)
Supply voltage range for MPU domain
-0.5
1.5
V
VDD_CORE
Supply voltage range for core domain
-0.5
1.5
V
CAP_VDD_RTC(4)
Supply voltage range for RTC core domain
-0.5
1.5
V
VPP(5)
Supply voltage range for FUSE ROM domain
-0.5
2.2
V
VDDS_RTC
Supply voltage range for the RTC domain
-0.5
2.1
V
VDDS_OSC
Supply voltage range for the System oscillator
-0.5
2.1
V
VDDS_SRAM_CORE_BG
Supply voltage range for the Core SRAM LDOs
-0.5
2.1
V
VDDS_SRAM_MPU_BB
Supply voltage range for the MPU SRAM LDOs
-0.5
2.1
V
VDDS_PLL_DDR
Supply voltage range for the DPLL DDR
-0.5
2.1
V
VDDS_PLL_CORE_LCD
Supply voltage range for the DPLL Core and LCD
-0.5
2.1
V
VDDS_PLL_MPU
Supply voltage range for the DPLL MPU
-0.5
2.1
V
VDDS_DDR
Supply voltage range for the DDR IO domain
-0.5
2.1
V
VDDS
Supply voltage range for all dual-voltage IO domains
-0.5
2.1
V
VDDA1P8V_USB0
Supply voltage range for USBPHY
-0.5
2.1
V
VDDA1P8V_USB1
(6)
UNIT
Supply voltage range for USBPHY
-0.5
2.1
V
VDDA_ADC
Supply voltage range for ADC
-0.5
2.1
V
VDDSHV1
Supply voltage range for the dual-voltage IO domain
-0.5
3.8
V
VDDSHV2(6)
Supply voltage range for the dual-voltage IO domain
-0.5
3.8
V
(6)
VDDSHV3
Supply voltage range for the dual-voltage IO domain
-0.5
3.8
V
VDDSHV4
Supply voltage range for the dual-voltage IO domain
-0.5
3.8
V
VDDSHV5
Supply voltage range for the dual-voltage IO domain
-0.5
3.8
V
VDDSHV6
Supply voltage range for the dual-voltage IO domain
-0.5
3.8
V
VDDA3P3V_USB0
Supply voltage range for USBPHY
-0.5
4
V
VDDA3P3V_USB1(6)
Supply voltage range for USBPHY
-0.5
4
V
USB0_VBUS
Supply voltage range for USB VBUS comparator input
-0.5
5.25
V
USB1_VBUS(6)
Supply voltage range for USB VBUS comparator input
-0.5
5.25
V
DDR_VREF
Supply voltage range for the DDR SSTL/HSTL reference
voltage
-0.3
1.1
V
-0.5
2.1
V
-0.5
2.1
V
Steady State Max. Voltage
at all IO pins
USB0_ID
(6)
USB1_ID
-0.5V to NOM IO supply + 0.3 V
Supply voltage range for the USB ID input
Supply voltage range for the USB ID input
Transient Overshoot /
Undershoot specification at
IO PAD
30% of supply for up to 30% of signal
period
Storage temperature range,
Tstg(7)
-55
ESD-HBM (Human Body Model)
Electrostatic Discharge
(ESD) Performance
(8)
155
°C
±2000
ESD-CDM (Charged-Device Model)(9)
±500
ESD-CDM (Charged-Device Model) Corner Balls
±750
V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x.
(3) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE in the ZCE package.
(4) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
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from an external power supply.
(5) During functional operation, this pin is a no connect.
(6) Not availabe on the ZCE package.
(7) For tape and reel the storage temperature range is [-10°C; +50°C] with a maximum relative humidity of 70%. It is recommended
returning to ambient room temperature before usage.
(8) Based on JEDEC JESD22-A114E [Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)].
PRODUCT PREVIEW
(9) Based on JEDEC JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds
of Microelectronic Components).
Device Operating Conditions
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Table 3-2 summarizes the power consumption at the ball level.
Table 3-2. Maximum Current Ratings at Ball Level
PARAMETER
MAX
UNIT
Maximum current rating for the core domain
400
mA
Maximum current rating for the MPU domain; TURBO
720
Maximum current rating for the MPU domain; OPP120
600
Maximum current rating for the MPU domain; OPP100
500
Maximum current rating for the MPU domain; OPP50
300
SUPPLY NAME
VDD_CORE
VDD_MPU(1)
(2)
DESCRIPTION
mA
PRODUCT PREVIEW
CAP_VDD_RTC
Maximum current rating for RTC domain input/LDO output
2
mA
VDDS_RTC
Maximum current rating for the RTC domain
5
mA
VDDS_DDR
Maximum current rating for DDR IO domain
200
mA
VDDS
Maximum current rating for all dual-voltage IO domains
50
mA
VDDS_SRAM_CORE_BG
Maximum current rating for core SRAM LDOs
10
mA
VDDS_SRAM_MPU_BB
Maximum current rating for MPU SRAM LDOs
10
mA
VDDS_PLL_DDR
Maximum current rating for the DPLL DDR
10
mA
VDDS_PLL_CORE_LCD
Maximum current rating for the DPLL Core and LCD
20
mA
VDDS_PLL_MPU
Maximum current rating for the DPLL MPU
10
mA
VDDS_OSC
Maximum current rating for the system oscillator IOs
5
mA
VDDA1P8V_USB0
Maximum current rating for USBPHY 1.8 V
40
mA
VDDA1P8V_USB1(3)
Maximum current rating for USBPHY 1.8 V
10
mA
VDDA3P3V_USB0
Maximum current rating for USBPHY 3.3 V
40
mA
VDDA3P3V_USB1
(3)
Maximum current rating for USBPHY 3.3 V
10
mA
VDDA_ADC
Maximum current rating for ADC
10
mA
VDDSHV1
Maximum current rating for dual-voltage IO domain
50
mA
VDDSHV2(3)
Maximum current rating for dual-voltage IO domain
50
mA
(3)
VDDSHV3
Maximum current rating for dual-voltage IO domain
50
mA
VDDSHV4
Maximum current rating for dual-voltage IO domain
50
mA
VDDSHV5
Maximum current rating for dual-voltage IO domain
50
mA
VDDSHV6
Maximum current rating for dual-voltage IO domain
100
mA
(1) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE in the ZCE package.
(2) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(3) Not available on the ZCE package.
76
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3.2
Recommended Operating Conditions
The device is used under the recommended operating conditions described in Table 3-4.
Table 3-3. Reliability Data
Operating
Condition
Commercial
VDD_MPU(1)(2) VDD_CORE(2)
Junction
Temp (Tj)
Industrial
Life Time
(POH)(3)
Junction
Temp (Tj)
Extended
Life Time
(POH)(3)
Junction
Temp (Tj)
Life Time
(POH)(3)
TBD
Turbo
1.26 V ±4%
1.1 V ±4%
0°C to 90°C
TBD
-40°C to 90°C
TBD
-40°C to 105°C
OPP120
1.2 V ±4%
1.1 V ±4%
0°C to 90°C
100K
-40°C to 90°C
100K
-40°C to 105°C
70K
OPP100
1.1 V ±4%
1.1 V ±4%
0°C to 90°C
100K
-40°C to 90°C
100K
-40°C to 105°C
100k
OPP50
0.95 V ±4%
1.1 V ±4%
0°C to 90°C
100k
-40°C to 90°C
100k
-40°C to 105°C
100k
(1) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE in the ZCE package.
(2) Voltage specification at the device package pin.
(3) POH = Power-on hours when the device is fully functional.
NOTE
PRODUCT PREVIEW
Logic functions and parameter values are not assured out of the range specified in the
recommended operating conditions.
Table 3-4. Recommended Operating Conditions
PARAMETER
MIN
NOM
MAX
UNIT
Supply voltage range for core
domain
1.06
1.1
1.15
V
Supply voltage range for MPU
domain; TURBO
1.21
1.26
1.31
Supply voltage range for MPU
domain; OPP120
1.15
1.2
1.25
Supply voltage range for MPU
domain; OPP100
1.06
1.1
1.15
Supply voltage range for MPU
domain; OPP50
0.91
0.95
0.99
CAP_VDD_RTC(2)
Supply voltage range for RTC
domain input/LDO output
1.06
1.1
1.15
V
VDDS_RTC
Supply voltage range for RTC
domain
1.71
1.8
1.89
V
Supply voltage range for DDR
IO domain (DDR2)
1.71
1.8
1.89
Supply voltage range for DDR
IO domain (DDR3)
1.43
1.5
1.58
VDDS(3)
Supply voltage range for all
Dual Voltage IO domains
1.71
1.8
1.89
V
VDDS_SRAM_CORE_BG
Supply voltage range for Core
SRAM LDOs, Analog
1.71
1.8
1.89
V
VDDS_SRAM_MPU_BB
Supply voltage range for MPU
SRAM LDOs, Analog
1.71
1.8
1.89
V
VDDS_PLL_DDR
Supply voltage range for DPLL
DDR, Analog
1.71
1.8
1.89
V
VDDS_PLL_CORE_LCD
Supply voltage range for DPLL
CORE and LCD, Analog
1.71
1.8
1.89
V
VDDS_PLL_MPU
Supply voltage range for DPLL
MPU, Analog
1.71
1.8
1.89
V
VDDS_OSC
Supply voltage range for
system oscillator IO's, Analog
1.71
1.8
1.89
V
SUPPLY NAME
VDD_CORE
(1)
VDD_MPU
VDDS_DDR
DESCRIPTION
V
V
Device Operating Conditions
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Table 3-4. Recommended Operating Conditions (continued)
PARAMETER
SUPPLY NAME
DESCRIPTION
MIN
NOM
MAX
UNIT
PRODUCT PREVIEW
VDDA1P8V_USB0
Supply voltage range for USB
PHY, Analog, 1.8V
1.71
1.8
1.89
V
VDDA1P8V_USB1(4)
Supply voltage range for USB
PHY, Analog, 1.8V
1.71
1.8
1.89
V
VDDA3P3V_USB0
Supply voltage range for USB
PHY, Analog, 3.3V
3.14
3.3
3.47
V
VDDA3P3V_USB1(4)
Supply voltage range for USB
PHY, Analog, 3.3V
3.14
3.3
3.47
V
VDDA_ADC
Supply voltage range for ADC,
Analog
1.71
1.8
1.89
V
VDDSHV1
Supply voltage range for Dual
Voltage IO domain (1.8-V
operation)
1.71
1.8
1.89
V
VDDSHV2(4)
Supply voltage range for Dual
Voltage IO domain (1.8-V
operation)
1.71
1.8
1.89
V
VDDSHV3(4)
Supply voltage range for Dual
Voltage IO domain (1.8-V
operation)
1.71
1.8
1.89
V
VDDSHV4
Supply voltage range for Dual
Voltage IO domain (1.8-V
operation)
1.71
1.8
1.89
V
VDDSHV5
Supply voltage range for Dual
Voltage IO domain (1.8-V
operation)
1.71
1.8
1.89
V
VDDSHV6
Supply voltage range for Dual
Voltage IO domain (1.8-V
operation)
1.71
1.8
1.89
V
VDDSHV1
Supply voltage range for Dual
Voltage IO domain (3.3-V
operation)
3.14
3.3
3.47
V
VDDSHV2(4)
Supply voltage range for Dual
Voltage IO domain (3.3-V
operation)
3.14
3.3
3.47
V
VDDSHV3(4)
Supply voltage range for Dual
Voltage IO domain (3.3-V
operation)
3.14
3.3
3.47
V
VDDSHV4
Supply voltage range for Dual
Voltage IO domain (3.3-V
operation)
3.14
3.3
3.47
V
VDDSHV5
Supply voltage range for Dual
Voltage IO domain (3.3-V
operation)
3.14
3.3
3.47
V
VDDSHV6
Supply voltage range for Dual
Voltage IO domain (3.3-V
operation)
3.14
3.3
3.47
V
DDR_VREF
Voltage range for DDR
SSTL/HSTL reference input
(DDR2/DDR3)
0.49*VDDS_DDR
0.50*VDDS_DDR
0.51*VDDS_DDR
V
USB0_VBUS
Voltage range for USB VBUS
comparator input
0
5
V
USB1_VBUS(4)
Voltage range for USB VBUS
comparator input
0
5
V
USB0_ID
Voltage range for the USB ID
input
1.71
1.8
1.89
V
USB1_ID(4)
Voltage range for the USB ID
input
1.71
1.8
1.89
V
78
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Table 3-4. Recommended Operating Conditions (continued)
PARAMETER
SUPPLY NAME
MIN
DESCRIPTION
Commercial Temperature
Operating Temperature
Range, Tj
NOM
MAX
0
UNIT
90
Industrial Temperature
-40
90
Extended Temperature
-40
105
°C
(1) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE in the ZCE package.
(2) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(3) VDDS should be supplied irrespective of 1.8-V or 3.3-V mode of operation of the dual voltage IOs.
(4) Not available on the ZCE package.
Table 3-5. Operating Performance Points for ZCZ Package(1)
OPP
VDD_MPU(2)
VDD_CORE(2)
ARM (A8)
DDR3
DDR2
mDDR
L3/L4
Turbo
1.26 V ±4%
1.1 V ±4%
720 MHz
303 MHz
200 MHz
180 MHz
200/100 MHz
OPP120
1.2 V ±4%
1.1 V ±4%
600 MHz
303 MHz
200 MHz
180 MHz
200/100 MHz
1.1 V ±4%
1.1 V ±4%
500 MHz
303 MHz
200 MHz
180 MHz
200/100 MHz
OPP50
0.95 V ±4%
0.95 V ±4%
275 MHz
-
125 MHz
90 MHz
100/50 MHz
PRODUCT PREVIEW
OPP100
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Interfaces in this row are validated and available on OPP50.
Table 3-6. Operating Performance Points for ZCE Package(1)
OPP
VDD_CORE(2)
ARM (A8)
DDR3
DDR2
mDDR
L3/L4
OPP100
1.1 V ±4%
500 MHz
303 MHz
200 MHz
180 MHz
200/100 MHz
OPP50
0.95 V ±4%
275 MHz
-
125 MHz
90 MHz
100/50 MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Interfaces in this row are validated and available on OPP50.
Device Operating Conditions
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3.3
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DC Electrical Characteristics
Table 3-7 summarizes the dc electrical characteristics.
Note: The interfaces or signals described in Table 3-7 correspond to the interfaces or signals available in
multiplexing mode 0. All interfaces or signals multiplexed on the balls/pins described in Table 3-7 have the same
dc electrical characteristics.
Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted)
PARAMETER
MIN
NOM
MAX
UNIT
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(LPDDR - LVCMOS mode)
0.65 *
VDDS_DDR
PRODUCT PREVIEW
VIH
High-level input voltage
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
VOH
High level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 8 mA
VOL
Low level output voltage, driver enabled, pullup
or pulldown disbaled
IOL = 8 mA
V
0.07
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
IOZ
V
0.25
V
VDDS_DDR 0.4
V
0.4
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
0.35
*VDDS_DDR
V
10
-240
-80
80
240
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
10
µA
µA
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(DDR2 - SSTL mode)
VIH
High-level input voltage
DDR_VREF +
0.125
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
VOH
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 8 mA
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
IOL = 8 mA
VDDS_DDR 0.125
NA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
IOZ
80
V
0.4
V
10
-240
-80
80
240
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
Device Operating Conditions
V
V
VDDS_DDR 0.4
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
V
10
µA
µA
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Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) (continued)
PARAMETER
MIN
NOM
MAX
UNIT
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A
0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A
14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_
D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 pins
(DDR3 - HSTL mode)
High-level input voltage
DDR_VREF +
0.1
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
VOH
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 8 mA
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
IOL = 8 mA
V
VDDS_DDR 0.1
NA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
IOZ
V
VDDS_DDR 0.4
V
0.4
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
V
V
10
-240
-80
80
240
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
10
µA
µA
ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_T
XD,I2C0_SDA,I2C0_SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,PWRONRSTn,NMIn,TMS,TDO,USB0_DRVVBUS,U
SB1_DRVVBUS (VDDSHV6 = 1.8 V)
VIH
High-level input voltage
0.65 *
VDDSHV6
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
VOH
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 4 mA
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
IOL = 4 mA
V
0.18
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
IOZ
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
V
0.305
V
VDDSHV6 0.45
V
0.45
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
0.35 *
VDDSHV6
5
-161
-100
-52
52
100
170
5
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µA
µA
81
PRODUCT PREVIEW
VIH
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Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) (continued)
PARAMETER
MIN
NOM
MAX
UNIT
ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_T
XD,I2C0_SDA,I2C0_SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,PWRONRSTn,NMIn,TMS,TDO,USB0_DRVVBUS,U
SB1_DRVVBUS (VDDSHV6 = 3.3 V)
VIH
High-level input voltage
VIL
Low-level input voltage
2
VHYS
Hysteresis voltage at an input
VOH
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 4 mA
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
IOL = 4 mA
V
0.265
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
IOZ
V
0.44
V
VDDSHV6 0.2
V
0.2
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
0.8
V
18
-243
-100
-19
51
110
210
PRODUCT PREVIEW
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
18
µA
µA
TCK (VDDSHV6 = 1.8 V)
VIH
High-level input voltage
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
II
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
1.45
V
0.46
V
5
µA
0.4
V
-161
-100
-52
52
100
170
TCK (VDDSHV6 = 3.3 V)
VIH
High-level input voltage
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
2.15
V
0.46
0.4
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
82
Device Operating Conditions
V
18
-243
-100
-19
51
110
210
µA
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Table 3-7. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) (continued)
PARAMETER
MIN
NOM
MAX
UNIT
All other LVCMOS pins (VDDSHVx = 1.8 V; x=1-6)
High-level input voltage
0.65 *
VDDSHVx
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
VOH
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 6 mA
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
IOL = 6 mA
V
0.18
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
IOZ
V
0.305
V
VDDSHVx 0.45
V
0.45
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
0.35 *
VDDSHVx
V
5
-161
-100
-52
52
100
170
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
5
µA
µA
PRODUCT PREVIEW
VIH
All other LVCMOS pins (VDDSHVx = 3.3 V; x=1-6)
VIH
High-level input voltage
VIL
Low-level input voltage
2
VHYS
Hysteresis voltage at an input
VOH
High-level output voltage, driver enabled, pullup
or pulldown disbaled
IOH = 6 mA
VOL
Low-level output voltage, driver enabled, pullup
or pulldown disbaled
IOL = 6 mA
V
0.265
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
IOZ
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
V
0.44
V
VDDSHVx 0.2
V
0.2
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
0.8
18
-243
-100
-19
51
110
210
18
Device Operating Conditions
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µA
µA
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3.4
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External Capacitors
To improve module performance, decoupling capacitors are required to suppress the switching noise generated
by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to
the device, because this minimizes the inductance of the circuit board wiring and interconnects.
3.4.1
Voltage Decoupling Capacitors
Table 3-8 summarizes the Core voltage decoupling characteristics.
3.4.1.1
Core Voltage Decoupling Capacitors
To improve module performance, decoupling capacitors are required to suppress high-frequency switching noise
and to stabilize the supply voltage. A decoupling capacitor is most effective when located close to the AM335x
device, because this minimizes the inductance of the circuit board wiring and interconnects.
Table 3-8. Core Voltage Decoupling Characteristics
MIN
TYP
MAX
UNIT
CVDD_CORE(1)
PARAMETER
TBD
10.08
TBD
μF
CVDD_MPU(2)(3)
TBD
10.05
TBD
μF
(1) The typical value corresponds to 1 cap of 10 µF and 8 caps of 10 nF.
PRODUCT PREVIEW
(2) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE in the ZCE package.
(3) The typical value corresponds to 1 cap of 10 µF and 5 caps of 10 nF.
3.4.1.2
IO and Analog Voltage Decoupling Capacitors
Table 3-9 summarizes the power-supply decoupling capacitor recommendations.
Table 3-9. Power-Supply Decoupling Capacitor Characteristics
MIN
TYP
MAX
UNIT
CVDDA_ADC
PARAMETER
TBD
10
TBD
nF
CVDDA1P8V_USB0
TBD
10
TBD
nF
CCVDDA3P3V_USB0
TBD
10
TBD
nF
CVDDA1P8V_USB1(1)
CVDDA3P3V_USB1(1)
CVDDS(2)
CVDDS_DDR(3)
TBD
10
TBD
nF
TBD
10
TBD
nF
TBD
10.04
TBD
nF
TBD
10.06
TBD
nF
CVDDS_OSC
TBD
10
TBD
nF
CVDDS_PLL_DDR
TBD
10
TBD
nF
CVDDS_PLL_CORE_LCD
TBD
10
TBD
nF
CVDDS_SRAM_CORE_BG
TBD
10
TBD
nF
CVDDS_SRAM_MPU_BB
TBD
10
TBD
nF
CVDDS_PLL_MPU
TBD
10
TBD
nF
CVDDS_RTC
TBD
10
TBD
nF
CVDDSHV1(4)
TBD
10.02
TBD
nF
CVDDSHV2(4)
TBD
10.02
TBD
nF
(4)
TBD
10.02
TBD
nF
CVDDSHV3
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Table 3-9. Power-Supply Decoupling Capacitor Characteristics (continued)
MIN
TYP
MAX
UNIT
CVDDSHV4(4)
PARAMETER
TBD
10.02
TBD
nF
(4)
TBD
10.02
TBD
nF
CVDDSHV6(3)
TBD
10.06
TBD
nF
CVDDSHV5
(1) Not available on the ZCE package.
(2) Typical values consist of a 1 cap of 10 µF and 4 caps of 10 nF.
(3) Typical values consist of a 1 cap of 10 µF and 6 caps of 10 nF.
(4) Typical values consist of a 1 cap of 10 µF and 2 caps of 10 nF.
3.4.2
Output Capacitors
Internal low dropout output (LDO) regulators require external capacitors to stabilize their outputs. These
capacitors should be placed as close as possible to the respective terminals of the AM335x device. Table 3-10
summarizes the LDO output capacitor recommendations.
Table 3-10. Output Capacitor Characteristics
MIN
TYP
MAX
UNIT
0.7
1
1.3
μF
CCAP_VDD_RTC(1)(2)
0.7
1
1.3
μF
CCAP_VDD_SRAM_MPU(1)
0.7
1
1.3
μF
0.7
1
1.3
μF
CCAP_VDD_SRAM_CORE
CCAP_VBB_MPU
(1)
PRODUCT PREVIEW
PARAMETER
(1)
(1) LDO regulator outputs should not be used as a power source for any external components.
(2) The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the RTC_KLDO_ENn terminal is high.
Device Operating Conditions
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Figure 3-1 illustrates an example of the external capacitors.
AM335x Device
VDDS_PLL_MPU
MPU
PLL
VDD_MPU
CVDDS_PLL_MPU
MPU
CVDD_MPU
VDDS_PLL_CORE_LCD
CORE
PLL
VDD_CORE
CORE
CVDDS_PLL_CORE_LCD
LCD
PLL
CAP_VBB_MPU
CVDD_CORE
CCAP_VBB_MPU
VDDS
IO
CVDDS
VDDS_SRAM_MPU_BB
VDDSHV1
IOs
CVDDSHV1
CVDDS_SRAM_MPU_BB
MPU SRAM
LDO
Back Bias
LDO
PRODUCT PREVIEW
CVDDSHV2
VDDSHV2
IOs
CVDDSHV3
VDDSHV3
IOs
CVDDSHV4
VDDSHV4
IOs
CVDDSHV5
VDDSHV5
IOs
CVDDSHV6
VDDSHV6
IOs
CAP_VDD_SRAM_MPU
CCAP_VDD_SRAM_MPU
VDDS_SRAM_CORE_BG
CVDDS_SRAM_CORE_BG
CORE SRAM
LDO
Band Gap
Reference
CAP_VDD_SRAM_CORE
CCAP_VDD_SRAM_CORE
VDDA_3P3V_USBx
CVDDS_DDR
CVDDA_3P3V_USBx
VSSA_USB
USB PHYx
VDDA_1P8V_USBx
CVDDA_1P8V_USBx
VSSA_USB
VDDS_DDR
IOs
VDDA_ADC
CVDDA_ADC
ADC
CVDDS_RTC
VDDS_RTC
IOs
VSSA_ADC
VDDS_OSC
CVDDS_OSC
VDDS_PLL_DDR
DDR
PLL
CVDDS_PLL_DDR
CAP_VDD_RTC
RTC
A.
B.
CCAP_VDD_RTC
Decoupling capacitors must be placed as closed as possible of the power ball. Choose the ground located closest to
the power pin for each decoupling capacitor. In case of interconnecting powers, first insert the decoupling capacitor
and then interconnect the powers.
The decoupling capacitor value depends on the board characteristics.
Figure 3-1. External Capacitors
86
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3.4.3
VDD_MPU_MON Connections
Figure 3-2 shows the VDD_MPU_MON connectivity.
VDD_MPU
AM335x Device
Power
Management
IC
VDD_MPU_MON
Vfeedback
Connection for VDD_MPU_MON if voltage monitoring is used
AM335x Device
VDD_MPU_MON
PRODUCT PREVIEW
VDD_MPU
Power
Source
Connection for VDD_MPU_MON if voltage monitoring is NOT used
Figure 3-2. VDD_MPU_MON Connectivity
Device Operating Conditions
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4 Power and Clocking
4.1
Power Supplies
4.1.1
Power-Up Sequencing
1.8V
VDDS_RTC
1.8V
RTC_PWRONRSTn
1.8V
PMIC_POWER_EN
1.8V
All 1.8-V Supplies
1.8V/1.5V
VDDS_DDR
PRODUCT PREVIEW
3.3V
IO 3.3-V Supplies
1.1V
VDD_CORE, VDD_MPU
3.3V
PWRONRSTn
CLK_M_OSC
A.
B.
C.
D.
E.
RTC_PWRONRSTn should be asserted for at least 1ms.
When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
If the system uses LPDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other
1.8-V I/O power supplies.
VDDS_RTC can be ramped independent of other power supplies if PMIC_PWR_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
Figure 4-1. Preferred Power-Supply Sequencing with Dual-Voltage I/Os Configured as 3.3 V
88
Power and Clocking
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1.8V
VDDS_RTC
1.8V
RTC_PWRONRSTn
1.8V
PMIC_POWER_EN
3.3V
See Notes Below
All 1.8-V Supplies
All 3.3-V Supplies
1.8V
1.8V/1.5V
VDDS_DDR
1.1V
VDD_CORE, VDD_MPU
PRODUCT PREVIEW
PWRONRSTn
CLK_M_OSC
A.
B.
C.
D.
E.
F.
RTC_PWRONRSTn should be asserted for at least 1ms.
The 3.3-V I/O power supplies may be ramped simultaneously with the 1.8-V I/O power supplies if the voltage sourced
by any 3.3-V power supplies does not exceed the voltage sourced by any 1.8-V power supply by more than 2 V.
Serious reliability issues may occur if the system power supply design allows any 3.3-V I/O power supplies to exceed
any 1.8-V I/O power supplies by more than 2 V.
When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
If the system uses LPDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other
1.8-V I/O power supplies.
VDDS_RTC can be ramped independent of other power supplies if PMIC_PWR_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
Figure 4-2. Alternate Power-Supply Sequencing with Dual-Voltage I/Os Configured as 3.3 V
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1.8V
VDDS_RTC
1.8V
RTC_PWRONRSTn
1.8V
PMIC_POWER_EN
1.8V
All 1.8-V Supplies
1.8V/1.5V
VDDS_DDR
3.3V
All 3.3-V Supplies
1.1V
VDD_CORE, VDD_MPU
PRODUCT PREVIEW
1.8V
PWRONRSTn
CLK_M_OSC
A.
B.
C.
D.
E.
RTC_PWRONRSTn should be asserted for at least 1ms.
When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
If the system uses LPDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other
1.8-V I/O power supplies.
VDDS_RTC can be ramped independent of other power supplies if PMIC_PWR_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
Figure 4-3. Power-Supply Sequencing with Dual-Voltage I/Os Configured as 1.8 V
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1.8V
1.1V
VDDS_RTC,
CAP_VDD_RTC
1.8V
RTC_PWRONRSTn
1.8V
PMIC_POWER_EN
1.8V
VDDSHV 1-6
All other 1.8-V Supplies
1.8V/1.5V
VDDS_DDR
3.3V
All 3.3-V Supplies
1.1V
VDD_CORE, VDD_MPU
PRODUCT PREVIEW
1.8V
PWRONRSTn
CLK_M_OSC
A.
B.
C.
D.
E.
F.
RTC_PWRONRSTn should be asserted for at least 1ms.
The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled,
CAP_VDD_RTC should be sourced from an external 1.1-V power supply.
When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
If the system uses LPDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other
1.8-V I/O power supplies.
VDDS_RTC should be ramped at the same time or before VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_PWR_EN functionality is not required. If VDD_RTC is ramped after
VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence
shown provides the lowest leakage option.
Figure 4-4. Power-Supply Sequencing with Internal RTC LDO Disabled
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1.8V
VDDS_RTC,
All other 1.8-V Supplies
1.8V/1.5V
VDDS_DDR
3.3V
All 3.3-V Supplies
1.1V
VDD_CORE, VDD_MPU
VDD_RTC
PWRONRSTn
CLK_M_OSC
PRODUCT PREVIEW
A.
B.
C.
D.
E.
CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled,
CAP_VDD_RTC should be sourced from an external 1.1-V power supply. The PMIC_POWER_EN output cannot be
used when the RTC is disabled.
When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
If the system uses LPDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other
1.8-V I/O power supplies.
VDDS_RTC should be ramped at the same time or before VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_PWR_EN functionality is not required. If VDD_RTC is ramped after
VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence
shown provides the lowest leakage option.
Figure 4-5. Power-Supply Sequencing with RTC Feature Disabled
4.1.2
Power-Down Sequencing
PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies
are turned off.
The preferred way to sequence power down is to have all the power supplies ramped down sequentially in
the exact reverse order of the power-up sequencing. In other words, the power supply that has been
ramped up first should be the last one that should be ramped down. This will ensure there would be no
spurious current paths during the power-down sequence.
The VDDS power supply must ramp down after all 3.3-V VDDSHV power supplies. If there is no 3.3-V
VDDSHV power supply, the VDDS power supply may ramp down at the same time or after all 1.8-V
VDDSHV power supplies.
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4.2
Clock Specifications
4.2.1
Input Clock Specifications
The AM335x device has two clock inputs. Each clock input passes through an internal oscillator which can
be connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock
source (bypass mode). The oscillators automatically operate in bypass mode when their input is
connected to an external LVCMOS square-wave digital clock source. The oscillator associated with a
specific clock input must be enabled when the clock input is being used in either oscillator mode or bypass
mode.
The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to
clock all non-RTC functions and is connected to the XTALIN and XTALOUT terminals. This clock source is
referred to as the master oscillator (CLK_M_OSC) in the AM335x ARM Cortex-A8 Technical Reference
Manual (literature number SPRUH73). OSC0 is enabled by default after power is applied.
For more information related to recommended circuit topologies and crystal oscillator circuit requirements
for these clock inputs, see Section 4.2.2.
4.2.2
Input Clock Requirements
4.2.2.1
OSC0 Internal Oscillator Clock Source
Figure 4-6 shows the recommended crystal circuit. It is recommended that pre-production printed circuit
board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper
oscillator operation when combined with production crystal circuit components. In most cases, Rbias will
not be required and Rd will be a zero ohm resistor. These resistors may be removed from production PCB
designs after evaluating oscillator performance with production crystal circuit components installed on
pre-production PCBs.
The XTALIN terminal has a 15 - 40 kΩ internal pull-down resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
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PRODUCT PREVIEW
The OSC1 oscillator provides a 32.768-kHz reference clock to the real-time clock (RTC) and is connected
to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator
(CLK_32K_RTC) in the AM335x ARM Cortex-A8 Technical Reference Manual (literature number
SPRUH73). OSC1 is disabled by default after power is applied. This clock input is optional and may not
be required if the RTC is configured to receive a clock from the internal 32k RC oscillator (CLK_RC32K) or
peripheral PLL (CLK_32KHZ) which receives a reference clock from the OSC0 input.
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VSS_OSC
XTALIN
C1
XTALOUT
C2
Optional Rbias
Optional Rd
Crystal
A.
B.
PRODUCT PREVIEW
Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise
coupled into the oscillator. The VSS_OSC terminal provides a Kelvin ground reference for the external crystal
components. External crystal component grounds should only be connected to the VSS_OSC terminal and should not
be connected to the PCB ground plane.
C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL =
[(C1*C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x XTALIN and XTALOUT signals. For
recommended values of crystal circuit components, see Table 4-1.
Figure 4-6. OSC0 Crystal Circuit Schematic
Table 4-1. OSC0 Crystal Circuit Requirements
NAME
DESCRIPTION
MIN
fxtal
Crystal parallel resonance
frequency
Fundamental mode oscillation only
Crystal frequency
stability/tolerance
TYP
MAX
19.2, 24.0,
25.0, or
26.0
UNIT
MHz
-50.0
50.0
ppm
CC1
C1 capacitance
12.0
24.0
pF
CC2
C2 capacitance
12.0
24.0
pF
Cshunt
Shunt capacitance
ESR
Crystal effective series
resistance
94
Power and Clocking
5.0
pF
fxtal = 19.2 MHz, oscillator has nominal
negative resistance of 272 Ω and
worst-case negative resistance of 163 Ω
54.4
Ω
fxtal = 24.0 MHz, oscillator has nominal
negative resistance of 240 Ω and
worst-case negative resistance of 144 Ω
48.0
Ω
fxtal = 25.0 MHz, oscillator has nominal
negative resistance of 233 Ω and
worst-case negative resistance of 140 Ω
46.6
Ω
fxtal = 26.0 MHz, oscillator has nominal
negative resistance of 227 Ω and
worst-case negative resistance of 137 Ω
45.3
Ω
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4.2.2.2
OSC0 LVCMOS Digital Clock Source
Figure 4-7 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS
square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. In this
mode of operation, the XTALOUT terminal should not be used to source any external components. The
printed circuit board design should provide a mechanism to disconnect the XTALOUT terminal from any
external components or signal traces that may couple noise into OSC0 via the XTALOUT terminal.
The XTALIN terminal has a 15 - 40 kΩ internal pull-down resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
AM335x
VSS_OSC
XTALOUT
LVCMOS
Digital
Clock
Source
Figure 4-7. OSC0 LVCMOS Circuit Schematic
4.2.2.3
OSC1 Internal Oscillator Clock Source
Figure 4-8 shows the recommended crystal circuit. It is recommended that pre-production printed circuit
board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper
oscillator operation when combined with production crystal circuit components. In most cases, Rbias will
not be required and Rd will be a zero ohm resistor. These resistors may be removed from production PCB
designs after evaluating oscillator performance with production crystal circuit components installed on
pre-production PCBs.
The RTC_XTALIN terminal does not enable an internal pull-down resistor when OSC1 is disabled. If this
oscillator is disabled, the RTC_XTALIN terminal may float to an invalid logic level which may increase
leakage current through the oscillator input buffer. This should not be an issue for most applications that
use this oscillator to source the RTC clock since the RTC requires a continuous clock to maintain time.
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PRODUCT PREVIEW
XTALIN
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AM335x
RTC_XTALIN
RTC_XTALOUT
Optional Rbias
Crystal
Optional Rd
C1
A.
B.
C2
Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise
coupled into the oscillator.
C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL =
[(C1*C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For
recommended values of crystal circuit components, see Table 4-2.
PRODUCT PREVIEW
Figure 4-8. OSC1 Crystal Circuit Schematic
Table 4-2. OSC1 Crystal Circuit Requirements
NAME
DESCRIPTION
fxtal
Crystal parallel resonance
frequency
Fundamental mode oscillation only
MIN
TYP
MAX
Crystal frequency
stability/tolerance
Maximum RTC error = 10.512
minutes/year
-20.0
20.0
ppm
Maximum RTC error = 26.28
minutes/year
-50.0
50.0
ppm
32.768
UNIT
kHz
CC1
C1 capacitance
12.0
24.0
pF
CC2
C2 capacitance
12.0
24.0
pF
Cshunt
Shunt capacitance
ESR
Crystal effective series
resistance
4.2.2.4
fxtal = 32.768 kHz, oscillator has nominal
negative resistance of 725 kΩ and
worst-case negative resistance of 250 kΩ
5.0
pF
80
kΩ
OSC1 LVCMOS Digital Clock Source
Figure 4-9 shows the recommended oscillator connections when OSC1 is connected to an LVCMOS
square-wave digital clock source. The LVCMOS clock source is connected to the RTC_XTALIN terminal.
In this mode of operation, the RTC_XTALOUT terminal should not be used to source any external
components. The printed circuit board design should provide a mechanism to disconnect the
RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1
via the RTC_XTALOUT terminal.
The RTC_XTALIN terminal does not enable an internal pull-down resistor when OSC1 is disabled. If this
oscillator is disabled, the RTC_XTALIN terminal may float to an invalid logic level which may increase
leakage current through the oscillator input buffer. This should not be an issue for most applications that
use this oscillator to source the RTC clock since the RTC requires a continuous clock to maintain time.
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AM335x
RTC_XTALIN
RTC_XTALOUT
LVCMOS
Digital
Clock
Source
N/C
Figure 4-9. OSC1 LVCMOS Circuit Schematic
4.2.2.5
OSC1 Not Used
AM335x
RTC_XTALIN
RTC_XTALOUT
Rpd
N/C
Figure 4-10. OSC1 Not Used Schematic
4.2.3
Output Clock Specifications
The AM335x device has two clock output signals. The CLKOUT1 signal is always a replica of the OSC0
input clock which is referred to as the master oscillator (CLK_M_OSC) in the AM335x ARM Cortex-A8
Technical Reference Manual (literature number SPRUH73). The CLKOUT2 signal can be configured to
output the OSC0 input clock, which is referred to as the 32K oscillator (CLK_32K_RTC) in the AM335x
ARM Cortex-A8 Technical Reference Manual (literature number SPRUH73), or four other internal clocks.
For more information related to configuring these clock output signals, see the CLKOUT Signals section of
the AM335x ARM Cortex-A8 Technical Reference Manual (literature number SPRUH73).
4.2.4
Output Clock Characteristics
4.2.4.1
CLKOUT1
The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one
of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be
configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal.
The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level
applied to the LCD_DATA5 terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0
multiplexer will be configured to Mode 7 if the LCD_DATA5 terminal is low on the rising edge of
PWRONRSTn or Mode 3 if the LCD_DATA5 terminal is high on the rising edge of PWRONRSTn. This
allows the CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software
intervention. In this mode, the output will be held low while PWRONRSTn is active and will begin to toggle
after PWRONRSTn is released.
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PRODUCT PREVIEW
Figure 4-10 shows the recommended oscillator connections when OSC0 is not being used. An external 10
kΩ maximum pull-down resistor should be connected to the RTC_XTALIN terminal to prevent this input
from floating to an invalid logic level which may increase leakage current through the oscillator input
buffer. The RTC_XTALOUT terminal is a no connect (NC).
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CLKOUT2
The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one
of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be
configured for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal.
The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must
configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the
XDMA_EVENT_INTR1 terminal.
PRODUCT PREVIEW
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5 Peripheral Information and Timings
5.1
5.1.1
Parameter Information
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
For the mDDR(LPDDR)/DDR2/DDR3 memory controller interface, it is not necessary to use the IBIS
models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the
routing rules to ensure the mDDR(LPDDR)/DDR2/DDR3 memory controller interface timings are met.
5.2
Recommended Clock and Control Signal Transition Behavior
PRODUCT PREVIEW
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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Ethernet Media Access Controller (EMAC)/Switch
5.3.1
Ethernet MAC/Switch Electrical Data/Timing
The Ethernet MAC/Switch implemented in the AM335x device supports GMII mode, but the AM335x
design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package
terminals. Therefore, the AM335x device does not support GMII mode. MII mode is supported with the
remaining GMII signals.
The AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number
SPRUH73) and this document may reference internal signal names when discussing peripheral input and
output signals since many of the AM335x package terminals can be multiplexed to one of several
peripheral signals. For example, the AM335x terminal names for port 1 of the Ethernet MAC/Switch have
been changed from GMII to MII to indicate their Mode 0 function, but the internal signal is named GMII.
However, documents that describe the Ethernet switch reference these signals by their internal signal
name. For a cross-reference of internal signal names to terminal names, see Table 2-7.
Operation of the Ethernet MAC/Switch is not supported for OPP50.
Table 5-1. Ethernet MAC/Switch Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
PRODUCT PREVIEW
Input Conditions
tR
Input signal rise time
tF
Input signal fall time
1(1)
5(1)
ns
(1)
5(1)
ns
3
30
pF
1
Output Condition
CLOAD
Output load capacitance
(1) Except when specified otherwise.
5.3.1.1
Ethernet MAC/Switch MII Electrical Data/Timing
Table 5-2. Timing Requirements for GMII[x]_RXCLK - MII Mode
(see Figure 5-1)
10 Mbps
NO.
MIN
TYP
100 Mbps
TYP
MAX
UNIT
MAX
MIN
399.96
400.04
39.996
40.004
ns
1
tc(RX_CLK)
Cycle time, RX_CLK
2
tw(RX_CLKH)
Pulse Duration, RX_CLK high
140
260
14
26
ns
3
tw(RX_CLKL)
Pulse Duration, RX_CLK low
140
260
14
26
ns
4
tt(RX_CLK)
Transition time, RX_CLK
5
ns
5
4
1
3
2
GMII[x]_RXCLK
4
Figure 5-1. GMII[x]_RXCLK Timing - MII Mode
100
Peripheral Information and Timings
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Table 5-3. Timing Requirements for GMII[x]_TXCLK - MII Mode
(see Figure 5-2)
10 Mbps
NO.
MIN
100 Mbps
TYP
MAX
MIN
TYP
MAX
UNIT
1
tc(TX_CLK)
Cycle time, TX_CLK
399.96
400.04
39.996
40.004
ns
2
tw(TX_CLKH)
Pulse Duration, TX_CLK high
140
260
14
26
ns
3
tw(TX_CLKL)
Pulse Duration, TX_CLK low
140
260
14
26
ns
4
tt(TX_CLK)
Transition time, TX_CLK
5
ns
5
4
1
3
2
GMII[x]_TXCLK
4
Figure 5-2. GMII[x]_TXCLK Timing - MII Mode
10 Mbps
NO.
1
2
MIN
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
tsu(RX_DV-RX_CLK)
Setup time, RX_DV valid before RX_CLK
tsu(RX_ER-RX_CLK)
Setup time, RX_ER valid before RX_CLK
th(RX_CLK-RXD)
Hold time RXD[3:0] valid after RX_CLK
th(RX_CLK-RX_DV)
Hold time RX_DV valid after RX_CLK
th(RX_CLK-RX_ER)
Hold time RX_ER valid after RX_CLK
100 Mbps
TYP
MAX
MIN
TYP
MAX
UNIT
8
8
ns
8
8
ns
1
2
GMII[x]_MRCLK (Input)
GMII[x]_RXD[3:0], GMII[x]_RXDV,
GMII[x]_RXER (Inputs)
Figure 5-3. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode
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PRODUCT PREVIEW
Table 5-4. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
(see Figure 5-3)
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Table 5-5. Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
(see Figure 5-4)
NO.
1
PARAMETER
td(TX_CLK-TXD)
Delay time, TX_CLK high to TXD[3:0] valid
td(TX_CLK-TX_EN)
Delay time, TX_CLK to TX_EN valid
10 Mbps
MIN
5
TYP
100 Mbps
MAX
MIN
25
5
TYP
MAX
25
UNIT
ns
1
GMII[x]_TXCLK (input)
GMII[x]_TXD[3:0],
GMII[x]_TXEN (outputs)
Figure 5-4. GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode
PRODUCT PREVIEW
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Peripheral Information and Timings
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5.3.1.2
Ethernet MAC/Switch RMII Electrical Data/Timing
Table 5-6. Timing Requirements for RMII[x]_REFCLK - RMII Mode
(see Figure 5-5)
NO.
MIN
TYP
MAX
UNIT
1
tc(REF_CLK)
Cycle time, REF_CLK
19.999
20.001
ns
2
tw(REF_CLKH)
Pulse Duration, REF_CLK high
7
13
ns
3
tw(REF_CLKL)
Pulse Duration, REF_CLK low
7
13
ns
1
2
RMII[x]_REFCLK
(Input)
3
Table 5-7. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
(see Figure 5-6)
NO.
1
2
MIN
tsu(RXD-REF_CLK)
Setup time, RXD[1:0] valid before REF_CLK
tsu(CRS_DV-REF_CLK)
Setup time, CRS_DV valid before REF_CLK
tsu(RX_ER-REF_CLK)
Setup time, RX_ER valid before REF_CLK
th(REF_CLK-RXD)
Hold time RXD[1:0] valid after REF_CLK
th(REF_CLK-CRS_DV)
Hold time, CRS_DV valid after REF_CLK
th(REF_CLK-RX_ER)
Hold time, RX_ER valid after REF_CLK
TYP
MAX
UNIT
4
ns
2
ns
1
2
RMII[x]_REFCLK (input)
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RXER (inputs)
Figure 5-6. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode
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PRODUCT PREVIEW
Figure 5-5. RMII[x]_REFCLK Timing - RMII Mode
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Table 5-8. Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
(see Figure 5-7)
NO.
1
2
3
PARAMETER
td(REF_CLK-TXD)
Delay time, REF_CLK high to TXD[1:0] valid
td(REF_CLK-TXEN)
Delay time, REF_CLK to TXEN valid
tr(TXD)
Rise time, TXD outputs
tr(TX_EN)
Rise time, TX_EN output
tf(TXD)
Fall time, TXD outputs
tf(TX_EN)
Fall time, TX_EN output
MIN
TYP
MAX
UNIT
2
13
ns
1
5
ns
1
5
ns
1
RMII[x]_REFCLK (Input)
RMII[x]_TXD[1:0],
RMII[x]_TXEN (Outputs)
2
3
Figure 5-7. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode
PRODUCT PREVIEW
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5.3.1.3
Ethernet MAC/Switch RGMII Electrical Data/Timing
RGMII mode is not supported for OPP50.
Table 5-9. Timing Requirements for RGMII[x]_RCLK - RGMII Mode
(see Figure 5-8)
10 Mbps
NO.
1
MIN
100 Mbps
TYP
MAX
MIN
TYP
1000 Mbps
MAX
MIN
TYP
MAX
UNIT
tc(RXC)
Cycle time, RXC
360
440
36
44
7.2
8.8
ns
2
tw(RXCH)
Pulse duration, RXC
high
160
240
16
24
3.6
4.4
ns
3
tw(RXCL)
Pulse duration, RXC low
160
240
16
24
3.6
4.4
ns
4
tt(RXC)
Transition time, RXC
0.75
ns
0.75
0.75
1
4
2
4
3
Figure 5-8. RGMII[x]_RCLK Timing - RGMII Mode
Table 5-10. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
(see Figure 5-9)
10 Mbps
NO.
MIN
100 Mbps
MAX
MIN
TYP
1000 Mbps
MAX
MIN
TYP
MAX
tsu(RD-RXC)
Setup time, RD[3:0] valid
before RXC high/low
1
1
1
tsu(RX_CTL-RXC)
Setup time, RX_CTL valid
before RXC high/low
1
1
1
th(RXC-RD)
Hold time, RD[3:0] valid
after RXC high/low
1
1
1
th(RXC-RX_CTL)
Hold time, RX_CTL valid
after RXC high/low
1
1
1
tt(RD)
Transition time, RD
0.75
0.75
0.75
tt(RX_CTL)
Transition time, RX_CTL
0.75
0.75
0.75
1
2
3
TYP
UNIT
ns
ns
ns
(A)
RGMII[x]_RCLK
1
1st Half-byte
2
2nd Half-byte
(B)
RGMII[x]_RD[3:0]
(B)
RGMII[x]_RCTL
RGRXD[3:0]
RGRXD[7:4]
RXDV
RXERR
3
A.
B.
RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the
respective timing requirements.
Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the
rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL
carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK.
Figure 5-9. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode
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RGMII[x]_RCLK
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Table 5-11. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
(see Figure 5-10)
10 Mbps
NO.
1
MIN
100 Mbps
TYP
MAX
MIN
1000 Mbps
TYP
MAX
MIN
TYP
MAX
UNIT
tc(TXC)
Cycle time, TXC
360
440
36
44
7.2
8.8
ns
2
tw(TXCH)
Pulse duration, TXC
high
160
240
16
24
3.6
4.4
ns
3
tw(TXCL)
Pulse duration, TXC low
160
240
16
24
3.6
4.4
ns
4
tt(TXC)
Transition time, TXC
0.75
ns
0.75
0.75
1
4
2
4
3
RGMII[x]_TCLK
Figure 5-10. RGMII[x]_TCLK Timing - RGMII Mode
Table 5-12. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
(see Figure 5-11)
PRODUCT PREVIEW
10 Mbps
NO.
MIN
1
2
TYP
100 Mbps
MAX
MIN
TYP
1000 Mbps
MAX
MIN
TYP
MAX
tsk(TD-TXC)
TD to TXC output skew
-0.5
0.5
-0.5
0.5
-0.5
0.5
tsk(TX_CTL-TXC)
TX_CTL to TXC output skew
-0.5
0.5
-0.5
0.5
-0.5
0.5
tt(TD)
Transition time, TD
0.75
0.75
0.75
tt(TX_CTL)
Transition time, TX_CTL
0.75
0.75
0.75
UNIT
ns
ns
(A)
RGMII[x]_TCLK
1
1
2
(B)
1st Half-byte
2nd Half-byte
(B)
TXEN
TXERR
RGMII[x]_TD[3:0]
RGMII[x]_TCTL
A.
B.
The Ethernet MAC/Switch implemented in the AM335x device supports internal delay mode, but timing closure was
not performed for this mode of operation. Therefore, the AM335x device does not support internal delay mode.
Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on
the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL
carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK.
Figure 5-11. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode
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5.4
External Memory Interfaces
The device includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• SDRAM controller (SDRC) or External Memory Interface (EMIF)
5.4.1
General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem/General-Purpose Memory Controller
section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference
Manual (literature number SPRUH73).
The GPMC is the unified memory controller used to interface external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
GPMC/NOR Flash—Synchronous Mode
Synchronous mode is not supported for OPP50.
Table 5-14 and Table 5-15 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-12 through Figure 5-16).
Table 5-13. GPMC/NOR Flash Timing Conditions—Synchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input signal rise time
1
5
ns
tF
Input signal fall time
1
5
ns
3
30
pF
Output Condition
CLOAD
Output load capacitance
Table 5-14. GPMC/NOR Flash Timing Requirements—Synchronous Mode
NO.
PARAMETER
OPP100
MIN
MAX
UNIT
F12
tsu(dV-clkH)
Setup time, input data gpmc_ad[15:0] valid before output clock gpmc_clk
high
3.2
ns
F13
th(clkH-dV)
Hold time, input data gpmc_ad[15:0] valid after output clock gpmc_clk high
2.5
ns
F21
tsu(waitV-clkH)
Setup time, input wait gpmc_wait[x](1) valid before output clock gpmc_clk
high
3.2
ns
F22
th(clkH-waitV)
Hold time, input wait gpmc_wait[x](1) valid after output clock gpmc_clk high
2.5
ns
(1) In gpmc_wait[x], x is equal to 0 or 1.
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Table 5-15. GPMC/NOR Flash Switching Characteristics—Synchronous Mode(2)
NO.
PARAMETER
OPP100
UNIT
MIN
MAX
F0
1 / tc(clk)
Frequency(15), output clock gpmc_clk
F1
tw(clkH)
Typical pulse duration, output clock gpmc_clk high
0.5P(12)
0.5P(12)
ns
F1
tw(clkL)
Typical pulse duration, output clock gpmc_clk low
0.5P(12)
0.5P(12)
ns
tdc(clk)
Duty cycle error, output clock gpmc_clk
–500
500
ps
100
(16)
PRODUCT PREVIEW
tJ(clk)
Jitter standard deviation
33.33
ps
tR(clk)
Rise time, output clock gpmc_clk
2
ns
tF(clk)
Fall time, output clock gpmc_clk
2
ns
tR(do)
Rise time, output data gpmc_ad[15:0]
2
ns
tF(do)
Fall time, output data gpmc_ad[15:0]
2
ns
F2
td(clkH-csnV)
Delay time, output clock gpmc_clk rising edge to output chip
select gpmc_csn[x](11) transition
F(6) – 2.2
F(6) + 4.5
ns
F3
td(clkH-csnIV)
Delay time, output clock gpmc_clk rising edge to output chip
select gpmc_csn[x](11) invalid
E(5) – 2.2
E(5) + 4.5
ns
F4
td(aV-clk)
Delay time, output address gpmc_a[27:1] valid to output clock
gpmc_clk first edge
B(2) – 4.5
B(2) + 2.3
ns
F5
td(clkH-aIV)
Delay time, output clock gpmc_clk rising edge to output address
gpmc_a[27:1] invalid
–2.3
4.5
ns
F6
td(be[x]nV-clk)
Delay time, output lower byte enable/command latch enable
gpmc_be0n_cle, output upper byte enable gpmc_be1n valid to
output clock gpmc_clk first edge
B(2) – 1.9
B(2) + 2.3
ns
F7
td(clkH-be[x]nIV)
Delay time, output clock gpmc_clk rising edge to output lower
byte enable/command latch enable gpmc_be0n_cle, output
upper byte enable gpmc_be1n invalid
D(4) – 2.3
D(4) + 1.9
ns
F8
td(clkH-advn)
Delay time, output clock gpmc_clk rising edge to output address
valid/address latch enable gpmc_advn_ale transition
G(7) + 2.3
G(7) + 4.5
ns
F9
td(clkH-advnIV)
Delay time, output clock gpmc_clk rising edge to output address
valid/address latch enable gpmc_advn_ale invalid
D(4) – 2.3
D(4) + 3.5
ns
F10
td(clkH-oen)
Delay time, output clock gpmc_clk rising edge to output enable
gpmc_oen transition
H(8) – 2.3
H(8) + 3.5
ns
F11
td(clkH-oenIV)
Delay time, output clock gpmc_clk rising edge to output enable
gpmc_oen invalid
E(5) – 2.3
E(5) + 3.5
ns
F14
td(clkH-wen)
Delay time, output clock gpmc_clk rising edge to output write
enable gpmc_wen transition
I(9) – 2.3
I(9) + 4.5
ns
F15
td(clkH-do)
Delay time, output clock gpmc_clk rising edge to output data
gpmc_ad[15:0] transition
J(10) – 2.3
J(10) + 1.9
ns
F17
td(clkH-be[x]n)
Delay time, output clock gpmc_clk rising edge to output lower
byte enable/command latch enable gpmc_be0n_cle transition
J(10) – 2.3
J(10) + 1.9
ns
F18
tw(csnV)
Pulse duration, output chip select gpmc_csn[x](11)
low
Read
A(1)
ns
Write
A(1)
ns
Pulse duration, output lower byte enable/command
latch enable gpmc_be0n_cle, output upper byte
enable gpmc_be1n low
Read
C(3)
ns
Write
(3)
ns
K
(13)
ns
K
(13)
ns
F19
F20
tw(be[x]nV)
tw(advnV)
, output clock gpmc_clk
MHz
Pulse duration, output address valid/address latch
enable gpmc_advn_ale low
C
Read
Write
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
With n being the page burst access number.
(2) B = ClkActivationTime * GPMC_FCLK(14)
(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK (14)
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
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For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(6) For csn falling edge (CS activated):
– Case GpmcFCLKDivider = 0:
– F = 0.5 * CSExtraDelay * GPMC_FCLK(14)
– Case GpmcFCLKDivider = 1:
– F = 0.5 * CSExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime
are even)
– F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) otherwise
– Case GpmcFCLKDivider = 2:
– F = 0.5 * CSExtraDelay * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime) is a multiple of 3)
– F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
– F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK(14) if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
PRODUCT PREVIEW
(7) For ADV falling edge (ADV activated):
– Case GpmcFCLKDivider = 0:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)
– Case GpmcFCLKDivider = 1:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
– G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise
– Case GpmcFCLKDivider = 2:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
– G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
– Case GpmcFCLKDivider = 0:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)
– Case GpmcFCLKDivider = 1:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
– G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise
– Case GpmcFCLKDivider = 2:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
– G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
– Case GpmcFCLKDivider = 0:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14)
– Case GpmcFCLKDivider = 1:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
– G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) otherwise
– Case GpmcFCLKDivider = 2:
– G = 0.5 * ADVExtraDelay * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
– G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK(14) if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
(8) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction):
– Case GpmcFCLKDivider = 0:
– H = 0.5 * OEExtraDelay * GPMC_FCLK(14)
– Case GpmcFCLKDivider = 1:
– H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime
are even)
– H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) otherwise
– Case GpmcFCLKDivider = 2:
– H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
– H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
– Case GpmcFCLKDivider = 0:
– H = 0.5 * OEExtraDelay * GPMC_FCLK(14)
– Case GpmcFCLKDivider = 1:
– H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime
are even)
– H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) otherwise
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Case GpmcFCLKDivider = 2:
– H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
– H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
– Case GpmcFCLKDivider = 0:
– I = 0.5 * WEExtraDelay * GPMC_FCLK(14)
– Case GpmcFCLKDivider = 1:
– I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime
are even)
– I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) otherwise
– Case GpmcFCLKDivider = 2:
– I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
– I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
PRODUCT PREVIEW
For WE rising edge (WE deactivated):
– Case GpmcFCLKDivider = 0:
– I = 0.5 * WEExtraDelay * GPMC_FCLK (14)
– Case GpmcFCLKDivider = 1:
– I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime
are even)
– I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) otherwise
– Case GpmcFCLKDivider = 2:
– I = 0.5 * WEExtraDelay * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
– I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK(14) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
(10) J = GPMC_FCLK(14)
(11) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
(12) P = gpmc_clk period in ns
(13) For read: K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(16) The jitter probability density can be approximated by a Gaussian function.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csn[x]
F4
gpmc_a[10:1]
Valid Address
F6
F7
F19
gpmc_be0n_cle
F19
gpmc_be1n
F6
F8
F8
F20
F9
gpmc_advn_ale
F11
PRODUCT PREVIEW
F10
gpmc_oen
F13
F12
gpmc_ad[15:0]
D0
gpmc_wait[x]
A.
B.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-12. GPMC/NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)
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F1
F0
F1
gpmc_clk
F2
F3
gpmc_csn[x]
F4
Valid Address
gpmc_a[10:1]
F6
F7
gpmc_be0n_cle
F7
gpmc_be1n
F6
F8
F8
F9
gpmc_advn_ale
F10
F11
gpmc_oen
F13
F13
F12
PRODUCT PREVIEW
gpmc_ad[15:0]
D0
F21
F12
D1
D2
D3
F22
gpmc_wait[x]
A.
B.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-13. GPMC/NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)
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F1
F1
F0
gpmc_clk
F2
F3
gpmc_csn[x]
F4
Valid Address
gpmc_a[10:1]
F17
F6
F17
F17
gpmc_be0n_cle
F17
F17
F17
gpmc_be1n
F6
F8
F8
F9
gpmc_advn_ale
F14
F14
F15
gpmc_ad[15:0]
D0
D1
F15
D2
PRODUCT PREVIEW
gpmc_wen
F15
D3
gpmc_wait[x]
A.
B.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-14. GPMC/NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)
Peripheral Information and Timings
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F1
F0
F1
gpmc_clk
F2
F3
gpmc_csn[x]
F6
F7
gpmc_be0n_cle
Valid
F6
F7
gpmc_be1n
Valid
F4
gpmc_a[27:17]
Address (MSB)
F12
F4
gpmc_ad[15:0]
F5
Address (LSB)
F13
D0
F8
D1
F12
D2
F8
D3
F9
gpmc_advn_ale
F10
F11
PRODUCT PREVIEW
gpmc_oen
gpmc_wait[x]
A.
B.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-15. GPMC/Multiplexed NOR Flash—Synchronous Burst Read
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csn[x]
F4
gpmc_a[27:17]
Address (MSB)
F17
F6
F17
F6
F17
F17
gpmc_be1n
F17
F17
gpmc_be0n_cle
F8
F8
F20
F9
gpmc_advn_ale
PRODUCT PREVIEW
F14
F14
gpmc_wen
F15
gpmc_ad[15:0]
Address (LSB)
D0
F22
D1
F15
F15
D2
D3
F21
gpmc_wait[x]
A.
B.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-16. GPMC/Multiplexed NOR Flash—Synchronous Burst Write
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5.4.1.2
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GPMC/NOR Flash—Asynchronous Mode
Table 5-17 and Table 5-18 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-17 through Figure 5-22).
Table 5-16. GPMC/NOR Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input signal rise time
1
5
ns
tF
Input signal fall time
1
5
ns
3
30
pF
Output Condition
CLOAD
Output load capacitance
Table 5-17. GPMC/NOR Flash Internal Timing Parameters—Asynchronous Mode(1)(2)
NO.
PARAMETER
PRODUCT PREVIEW
FI1
Delay time, output data gpmc_ad[15:0] generation from internal functional clock
GPMC_FCLK(3)
FI2
Delay time, input data gpmc_ad[15:0] capture from internal functional clock
GPMC_FCLK(3)
FI3
OPP100
MIN
OPP50
MAX
MIN
MAX
UNIT
6.5
6.5
ns
4
4
ns
Delay time, output chip select gpmc_csn[x] generation from internal functional
clock GPMC_FCLK(3)
6.5
6.5
ns
FI4
Delay time, output address gpmc_a[27:1] generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
FI5
Delay time, output address gpmc_a[27:1] valid from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
FI6
Delay time, output lower-byte enable/command latch enable gpmc_be0n_cle,
output upper-byte enable gpmc_be1n generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
FI7
Delay time, output enable gpmc_oen generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
FI8
Delay time, output write enable gpmc_wen generation from internal functional
clock GPMC_FCLK(3)
6.5
6.5
ns
FI9
Skew, internal functional clock GPMC_FCLK(3)
100
100
ps
(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
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Table 5-18. GPMC/NOR Flash Timing Requirements—Asynchronous Mode
NO.
PARAMETER
OPP100
MIN
FA5(1)
tacc(d)
OPP50
MAX
FA20
tacc1-pgmode(d)
FA21(3)
tacc2-pgmode(d)
UNIT
MAX
H(5)
H(5)
ns
Page mode successive data access time
P
(4)
P(4)
ns
Page mode first data access time
H(5)
H(5)
ns
Data access time
(2)
MIN
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)
(5) H = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
NO.
FA0
FA1
FA3
OPP100
PARAMETER
MIN
OPP50
MAX
MIN
tR(d)
Rise time, output data gpmc_ad[15:0]
tF(d)
Fall time, output data gpmc_ad[15:0]
tw(be[x]nV)
Pulse duration, output lower-byte
enable/command latch enable
gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid time
Read
Write
N(12)
N(12)
Pulse duration, output chip select
gpmc_csn[x](13) low
Read
A(1)
A(1)
Write
(1)
A(1)
Delay time, output chip select
gpmc_csn[x](13) valid to output
address valid/address latch enable
gpmc_advn_ale invalid
Read
tw(csnV)
td(csnV-advnIV)
2
MAX
Write
2
ns
2
2
ns
N(12)
N(12)
ns
A
B(2) – 0.2
B
(2)
– 0.2
B(2) + 2.0
B
(2)
UNIT
B(2) – 0.2
+ 2.0
B
(2)
B(2) + 2.0
– 0.2
B(2) + 2.0
ns
ns
FA4
td(csnV-oenIV)
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen invalid (Single
read)
C(3) – 0.2
C(3) + 2.0
C(3) – 0.2
C(3) + 2.0
ns
FA9
td(aV-csnV)
Delay time, output address gpmc_a[27:1] valid
to output chip select gpmc_csn[x](13) valid
J(9) – 0.2
J(9) + 2.0
J(9) – 0.2
J(9) + 2.0
ns
FA10
td(be[x]nV-csnV)
Delay time, output lower-byte enable/command
latch enable gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid to output chip select
gpmc_csn[x](13) valid
J(9) – 0.2
J(9) + 2.0
J(9) – 0.2
J(9) + 2.0
ns
FA12
td(csnV-advnV)
Delay time, output chip select gpmc_csn[x](13)
valid to output address valid/address latch
enable gpmc_advn_ale valid
K(10) – 0.2
K(10) + 2.0
K(10) – 0.2
K(10) + 2.0
ns
FA13
td(csnV-oenV)
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen valid
L(11) – 0.2
L(11) + 2.0
L
L(11) + 2.0
ns
FA16
tw(aIV)
Pulse durationm output address gpmc_a[26:1]
invalid between 2 successive R/W accesses
G(7)
FA18
td(csnV-oenIV)
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen invalid (Burst
read)
I(8) – 0.2
FA20
tw(aV)
Pulse duration, output address gpmc_a[27:1]
valid – 2nd, 3rd, and 4th accesses
FA25
td(csnV-wenV)
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen valid
– 0.2
G(7)
I(8) + 2.0
D(4)
E(5) – 0.2
(11)
I(8) – 0.2
ns
I(8) + 2.0
D(4)
E(5) + 2.0
E(5) – 0.2
ns
E(5) + 2.0
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ns
ns
117
PRODUCT PREVIEW
Table 5-19. GPMC/NOR Flash Switching Characteristics—Asynchronous Mode
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Table 5-19. GPMC/NOR Flash Switching Characteristics—Asynchronous Mode (continued)
NO.
PARAMETER
FA27
td(csnV-wenIV)
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen invalid
FA28
td(wenV-dV)
Delay time, output write enable gpmc_ wen
valid to output data gpmc_ad[15:0] valid
FA29
td(dV-csnV)
Delay time, output data gpmc_ad[15:0] valid to
output chip select gpmc_csn[x](13) valid
FA37
td(oenV-aIV)
Delay time, output enable gpmc_oen valid to
output address gpmc_ad[15:0] phase end
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
F(6) – 0.2
F(6) + 2.0
F(6) – 0.2
F(6) + 2.0
ns
2.0
ns
J(9) + 2.0
ns
2.0
ns
2.0
J(9) – 0.2
J(9) + 2.0
J(9) – 0.2
2.0
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) *
GPMC_FCLK(14)
(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
PRODUCT PREVIEW
(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(7) G = Cycle2CycleDelay * GPMC_FCLK(14)
(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *
GPMC_FCLK(14)
(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK(14)
(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csn[x]
FA9
gpmc_a[10:1]
Valid Address
FA0
FA10
gpmc_be0n_cle
Valid
FA0
gpmc_be1n
Valid
FA10
FA3
FA12
gpmc_advn_ale
FA13
gpmc_oen
Data IN 0
gpmc_ad[15:0]
Data IN 0
gpmc_wait[x]
A.
B.
C.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-17. GPMC/NOR Flash—Asynchronous Read—Single Word
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PRODUCT PREVIEW
FA4
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GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_csn[x]
FA16
FA9
FA9
gpmc_a[10:1]
Address 0
Address 1
FA0
FA10
FA0
FA10
gpmc_be0n_cle
Valid
Valid
FA0
gpmc_be1n
FA0
Valid
FA10
Valid
FA10
FA3
FA3
FA12
FA12
gpmc_advn_ale
PRODUCT PREVIEW
FA4
FA13
FA4
FA13
gpmc_oen
gpmc_ad[15:0]
Data Upper
gpmc_wait[x]
A.
B.
C.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-18. GPMC/NOR Flash—Asynchronous Read—32-bit
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GPMC_FCLK
gpmc_clk
FA21
FA20
FA20
FA20
Add1
Add2
Add3
D0
D1
D2
FA1
gpmc_csn[x]
FA9
Add0
gpmc_a[10:1]
Add4
FA0
FA10
gpmc_be0n_cle
FA0
FA10
gpmc_be1n
FA12
gpmc_advn_ale
FA13
gpmc_oen
gpmc_ad[15:0]
D3
D3
gpmc_wait[x]
A.
B.
C.
D.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in
number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input
page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside
AccessTime register bits field.
FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in
number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally
sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address
phases for successive input page data (excluding first input page data). FA20 value must be stored in
PageBurstAccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-19. GPMC/NOR Flash—Asynchronous Read—Page Mode 4x16-bit
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PRODUCT PREVIEW
FA18
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gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x]
FA9
gpmc_a[10:1]
Valid Address
FA0
FA10
gpmc_be0n_cle
FA0
FA10
gpmc_be1n
FA3
FA12
gpmc_advn_ale
FA27
FA25
PRODUCT PREVIEW
gpmc_wen
FA29
gpmc_ad[15:0]
Data OUT
gpmc_wait[x]
A.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-20. GPMC/NOR Flash—Asynchronous Write—Single Word
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csn[x]
FA9
gpmc_a[27:17]
Address (MSB)
FA0
FA10
gpmc_be0n_cle
Valid
FA0
FA10
gpmc_be1n
Valid
FA3
FA12
gpmc_advn_ale
FA13
gpmc_oen
FA29
gpmc_ad[15:0]
FA37
Address (LSB)
Data IN
Data IN
gpmc_wait[x]
A.
B.
C.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-21. GPMC / Multiplexed NOR Flash—Asynchronous Read—Single Word
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PRODUCT PREVIEW
FA4
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gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x]
FA9
gpmc_a[27:17]
Address (MSB)
FA0
FA10
gpmc_be0n_cle
FA0
FA10
gpmc_be1n
FA3
FA12
gpmc_advn_ale
FA27
FA25
PRODUCT PREVIEW
gpmc_wen
FA29
gpmc_ad[15:0]
FA28
Valid Address (LSB)
Data OUT
gpmc_wait[x]
A.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-22. GPMC/Multiplexed NOR Flash—Asynchronous Write—Single Word
124
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5.4.1.3
GPMC/NAND Flash—Asynchronous Mode
Table 5-21 and Table 5-22 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-23 through Figure 5-26).
Table 5-20. GPMC/NAND Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input signal rise time
1
5
ns
tF
Input signal fall time
1
5
ns
3
30
pF
Output Condition
CLOAD
Output load capacitance
Table 5-21. GPMC/NAND Flash Internal Timing Parameters—Asynchronous Mode(1)(2)
PARAMETER
OPP100
MIN
OPP50
MAX
MIN
MAX
UNIT
GNFI1
Delay time, output data gpmc_ad[15:0] generation from internal
functional clock GPMC_FCLK(3)
6.5
6.5
ns
GNFI2
Delay time, input data gpmc_ad[15:0] capture from internal functional
clock GPMC_FCLK(3)
4.0
4.0
ns
GNFI3
Delay time, output chip select gpmc_csn[x] generation from internal
functional clock GPMC_FCLK(3)
6.5
6.5
ns
GNFI4
Delay time, output address valid/address latch enable gpmc_advn_ale
generation from internal functional clock GPMC_FCLK(3)
6.5
6.5
ns
GNFI5
Delay time, output lower-byte enable/command latch enable
gpmc_be0n_cle generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
GNFI6
Delay time, output enable gpmc_oen generation from internal functional
clock GPMC_FCLK(3)
6.5
6.5
ns
GNFI7
Delay time, output write enable gpmc_wen generation from internal
functional clock GPMC_FCLK(3)
6.5
6.5
ns
GNFI8
Skew, functional clock GPMC_FCLK(3)
100
100
ps
PRODUCT PREVIEW
NO.
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
Table 5-22. GPMC/NAND Flash Timing Requirements—Asynchronous Mode
NO.
GNF12(1)
PARAMETER
tacc(d)
Access time, input data gpmc_ad[15:0]
OPP100
MIN
OPP50
MAX
J(2)
MIN
MAX
J(2)
UNIT
ns
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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Table 5-23. GPMC/NAND Flash Switching Characteristics—Asynchronous Mode
NO.
OPP100
PARAMETER
MIN
OPP50
MAX
MIN
MAX
UNIT
PRODUCT PREVIEW
tR(d)
Rise time, output data gpmc_ad[15:0]
2
2
ns
tF(d)
Fall time, output data gpmc_ad[15:0]
2
2
ns
GNF0
tw(wenV)
Pulse duration, output write enable gpmc_wen
valid
A(1)
GNF1
td(csnV-wenV)
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen valid
B(2) – 0.2
B(2) + 2.0
B(2) – 0.2
B(2) + 2.0
ns
GNF2
tw(cleH-wenV)
Delay time, output lower-byte enable/command
latch enable gpmc_be0n_cle high to output write
enable gpmc_wen valid
C(3) – 0.2
C(3) + 2.0
C(3) – 0.2
C(3) + 2.0
ns
GNF3
tw(wenV-dV)
Delay time, output data gpmc_ad[15:0] valid to
output write enable gpmc_wen valid
D(4) – 0.2
D(4) + 2.0
D(4) – 0.2
D(4) + 2.0
ns
GNF4
tw(wenIV-dIV)
Delay time, output write enable gpmc_wen
invalid to output data gpmc_ad[15:0] invalid
E(5) – 0.2
E(5) + 2.0
E(5) – 0.2
E(5) + 2.0
ns
GNF5
tw(wenIV-cleIV)
Delay time, output write enable gpmc_wen
invalid to output lower-byte enable/command
latch enable gpmc_be0n_cle invalid
F(6) – 0.2
F(6) + 2.0
F(6) – 0.2
F(6) + 2.0
ns
GNF6
tw(wenIV-csnIV)
Delay time, output write enable gpmc_wen
invalid to output chip select gpmc_csn[x](13)
invalid
G(7) – 0.2
G(7) + 2.0
G(7) – 0.2
G(7) + 2.0
ns
GNF7
tw(aleH-wenV)
Delay time, output address valid/address latch
enable gpmc_advn_ale high to output write
enable gpmc_wen valid
C(3) – 0.2
C(3) + 2.0
C(3) – 0.2
C(3) + 2.0
ns
GNF8
tw(wenIV-aleIV)
Delay time, output write enable gpmc_wen
invalid to output address valid/address latch
enable gpmc_advn_ale invalid
F(6) – 0.2
F(6) + 2.0
F(6) – 0.2
F(6) + 2.0
ns
GNF9
tc(wen)
Cycle time, write
H(8)
ns
+ 2.0
ns
K(10)
ns
ns
H(8)
(13)
GNF10 td(csnV-oenV)
Delay time, output chip select gpmc_csn[x]
valid to output enable gpmc_oen valid
GNF13 tw(oenV)
Pulse duration, output enable gpmc_oen valid
GNF14 tc(oen)
Cycle time, read
GNF15 tw(oenIV-csnIV)
A(1)
Delay time, output enable gpmc_oen invalid to
output chip select gpmc_csn[x](13) invalid
(9)
I
(9)
– 0.2
I
(9)
+ 2.0
I
(9)
– 0.2
I
K(10)
L(11)
(12)
M
L(11)
(12)
– 0.2 M
(12)
+ 2.0 M
ns
(12)
– 0.2 M
+ 2.0
ns
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK(14)
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay) * GPMC_FCLK(14)
(5) E = ((WrCycleTime – WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay) * GPMC_FCLK(14)
(6) F = ((ADVWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)
(7) G = ((CSWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(12) M = ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay)) * GPMC_FCLK(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
126
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GPMC_FCLK
GNF1
GNF6
GNF2
GNF5
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
(1)
Command
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
Figure 5-23. GPMC/NAND Flash—Command Latch Cycle
GNF1
GNF6
GNF7
GNF8
PRODUCT PREVIEW
GPMC_FCLK
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF9
GNF0
gpmc_wen
GNF3
gpmc_ad[15:0]
(1)
GNF4
Address
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
Figure 5-24. GPMC/NAND Flash—Address Latch Cycle
Peripheral Information and Timings
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
GNF14
GNF13
gpmc_oen
gpmc_ad[15:0]
DATA
gpmc_wait[x]
(1)
(2)
(3)
GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active
functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
PRODUCT PREVIEW
Figure 5-25. GPMC/NAND Flash—Data Read Cycle
GPMC_FCLK
GNF1
GNF6
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF9
GNF0
gpmc_wen
GNF3
gpmc_ad[15:0]
(1)
GNF4
DATA
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
Figure 5-26. GPMC / NAND Flash—Data Write Cycle
128
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5.5
LCD Controller (LCDC)
The LCD controller consists of two independent controllers, the raster controller and the LCD interface
display driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
• The raster controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the raster engine which, in turn,
outputs to the external LCD device.
• The LIDD controller supports the asynchronous LCD interface. It provides full-timing programmability of
control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 2048 x 2048 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate.
Table 5-24. LCD Controller Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
CLOAD
5.5.1
Output load capacitance
LIDD mode
5
60
pF
Raster mode
3
30
pF
LCD Interface Display Driver (LIDD Mode)
Table 5-25. Timing Requirements for LCD LIDD Mode
(see Figure 5-28 through Figure 5-36)
NO.
PARAMETER
16
tsu(LCD_DATA-LCD_MEMORY_CLK)
Setup time, LCD_DATA[15:0] valid before
LCD_MEMORY_CLK high
17
th(LCD_MEMORY_CLK-LCD_DATA)
18
tt(LCD_DATA)
OPP100
MIN
MAX
UNIT
18
ns
Hold time, LCD_DATA[15:0] valid after
LCD_MEMORY_CLK high
0
ns
Transition time, LCD_DATA[15:0]
1
3
pf
Table 5-26. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode
(see Figure 5-28 through Figure 5-36)
NO.
PARAMETER
OPP100
MIN
MAX
1
tc(LCD_MEMORY_CLK)
Cycle time, LCD_MEMORY_CLK
2
tw(LCD_MEMORY_CLKH)
Pulse duration, LCD_MEMORY_CLK high
0.45tc
0.55tc
ns
3
tw(LCD_MEMORY_CLKL)
Pulse duration, LCD_MEMORY_CLK low
0.45tc
0.55tc
ns
4
td(LCD_MEMORY_CLK-LCD_DATAV)
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] valid (write)
7
ns
5
td(LCD_MEMORY_CLK-LCD_DATAI)
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] invalid (write)
0
6
td(LCD_MEMORY_CLK-LCD_AC_BIAS_EN)
Delay time, LCD_MEMORY_CLK high to
LCD_AC_BIAS_EN
0
6.8
ns
7
tt(LCD_AC_BIAS_EN)
Transition time, LCD_AC_BIAS_EN
1
10
ns
8
td(LCD_MEMORY_CLK-LCD_VSYNC)
Delay time, LCD_MEMORY_CLK high to
LCD_VSYNC
0
7
ns
9
tt(LCD_VSYNC)
Transition time, LCD_VSYNC
1
10
ns
td(LCD_MEMORY_CLK-LCD_HYSNC)
Delay time, LCD_MEMORY_CLK high to
LCD_HSYNC
0
7
ns
10
23.7
UNIT
ns
ns
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PRODUCT PREVIEW
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Table 5-26. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD
Mode (continued)
(see Figure 5-28 through Figure 5-36)
NO.
OPP100
PARAMETER
MIN
MAX
UNIT
11
tt(LCD_HSYNC)
Transition time, LCD_HYSNC
1
10
ns
12
td(LCD_MEMORY_CLK-LCD_PCLK)
Delay time, LCD_MEMORY_CLK high to LCD_PCLK
0
7
ns
13
tt(LCD_PCLK)
Transition time, LCD_PCLK
1
10
ns
14
td(LCD_MEMORY_CLK-LCD_DATAZ)
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] high-Z
0
7
ns
15
td(LCD_MEMORY_CLK-LCD_DATA)
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] driven
0
7
ns
19
tt(LCD_MEMORY_CLK)
Transition time, LCD_MEMORY_CLK
1
2.5
ns
20
tt(LCD_DATA)
Transition time, LCD_DATA
1
10
ns
W_SU
(0 to 31)
CS_DELAY
(0 to 3)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
LCD_MEMORY_CLK
PRODUCT PREVIEW
6
6
LCD_MEMORY_CLK
(E1)
7
4
LCD_DATA[7:0]
5
Write Instruction
8
8
10
10
LCD_VSYNC
(RS)
9
LCD_HSYNC
(R/W)
6
6
11
LCD_AC_BIAS_EN
(E0)
7
A.
Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-27. Command Write in Hitachi Mode
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W_SU
(0 to 31)
CS_DELAY
(0 to 3)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
7
4
LCD_DATA[15:0]
5
Write Data
20
LCD_VSYNC
(RS)
10
10
LCD_HSYNC
(R/W)
11
6
6
LCD_AC_BIAS_EN
(E0)
PRODUCT PREVIEW
7
A.
Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-28. Data Write in Hitachi Mode
R_SU
(0 to 31)
R_STROBE
(1 to 63)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
14
7
16
17
15
LCD_DATA[15:0]
8
Read Command
18
8
LCD_VSYNC
(RS)
9
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
A.
Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-29. Command Read in Hitachi Mode
Peripheral Information and Timings
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R_SU
(0 to 31)
R_STROBE
(1 to 63)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
14
7
16
17
15
LCD_DATA[15:0]
Read Data
18
LCD_VSYNC
(RS)
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
7
PRODUCT PREVIEW
A.
Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 5-30. Data Read in Hitachi Mode
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W_HOLD
(1−15)
1
W_SU
(0−31)
W_STROBE
(1−63)
2
3
W_HOLD
(1−15)
W_SU
(0−31)
CS_DELAY
(0−3)
W_STROBE
(1−63)
CS_DELAY
(0−3)
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
6
6
4
5
LCD_MEMORY_CLK
(CS1) Async Mode
7
4
LCD_DATA[15:0]
5
Write Address
Write Data
20
6
6
6
6
10
10
LCD_AC_BIAS_EN
(CS0)
8
PRODUCT PREVIEW
7
8
LCD_VSYNC
(ALE)
9
10
10
LCD_HSYNC
(DIR)
11
12
12
12
12
LCD_PCLK
(EN)
A.
13
Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-31. Micro-Interface Graphic Display Motorola Write
Peripheral Information and Timings
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R_SU
(0−31)
W_HOLD
(1−15)
1
W_SU
(0−31)
W_STROBE
(1−63)
2
3
R_STROBE
(1−63)
CS_DELAY
(0−3)
R_HOLD
(1−15)
CS_DELAY
(0−3)
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
4
LCD_DATA[15:0]
5
16
14
17
15
Write Address
18
20
6
6
Read
Data
6
6
LCD_AC_BIAS_EN
(CS0)
7
PRODUCT PREVIEW
8
8
LCD_VSYNC
(ALE)
9
10
10
LCD_HSYNC
(DIR)
11
12
12
12
12
LCD_PCLK
(EN)
A.
13
Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-32. Micro-Interface Graphic Display Motorola Read
134
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R_SU
(0−31)
1
2
3
R_STROBE
(1−63)
R_HOLD
(1−15)
CS_DELAY
(0−3)
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
14
16
17
15
LCD_DATA[15:0]
Read
Status
18
6
6
LCD_AC_BIAS_EN
(CS0)
8
PRODUCT PREVIEW
7
8
LCD_VSYNC
(ALE)
9
LCD_HSYNC
(DIR)
12
12
LCD_PCLK
(EN)
13
A.
Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-33. Micro-Interface Graphic Display Motorola Status
Peripheral Information and Timings
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W_HOLD
(1−15)
1
W_SU
(0−31)
W_SU
(0−31)
W_STROBE
(1−63)
2
3
W_HOLD
(1−15)
CS_DELAY
(0−3)
W_STROBE
(1−63)
CS_DELAY
(0−3)
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
6
6
5
4
5
LCD_MEMORY_CLK
(CS1) Async Mode
7
4
LCD_DATA[15:0]
Write Address
Write Data
20
6
6
6
6
LCD_AC_BIAS_EN
(CS0)
7
PRODUCT PREVIEW
8
8
LCD_VSYNC
(ALE)
9
10
10
10
10
LCD_HSYNC
(WS)
11
LCD_PCLK
(RS)
A.
Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-34. Micro-Interface Graphic Display Intel Write
136
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R_SU
(0−31)
W_HOLD
(1−15)
1
W_SU
(0−31)
W_STROBE
(1−63)
2
3
R_STROBE
(1−63)
CS_DELAY
(0−3)
R_HOLD
(1−15)
CS_DELAY
(0−3)
LCD_MEMORY_CLK
(MCLK) Sync Mode
6
6
19
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
4
LCD_DATA[15:0]
5
16
14
17
15
Write Address
18
20
6
6
Read
Data
6
6
LCD_AC_BIAS_EN
(CS0)
8
PRODUCT PREVIEW
7
8
LCD_VSYNC
(ALE)
9
10
10
LCD_HSYNC
(WS)
11
12
12
LCD_PCLK
(RS)
A.
13
Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-35. Micro-Interface Graphic Display Intel Read
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R_SU
(0−31)
1
2
3
R_STROBE
(1−63)
R_HOLD
(1−15)
CS_DELAY
(0−3)
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
14
16
17
15
LCD_DATA[15:0]
Read
Status
18
6
6
LCD_AC_BIAS_EN
(CS0)
PRODUCT PREVIEW
7
8
8
LCD_VSYNC
(ALE)
9
LCD_HSYNC
(WS)
12
12
LCD_PCLK
(RS)
13
A.
Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-36. Micro-Interface Graphic Display Intel Status
138
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5.5.2
LCD Raster Mode
Table 5-27. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
(see Figure 5-38 through Figure 5-41)
PARAMETER
OPP50
MIN
OPP100
MAX
7.9
MIN
MAX
7.9
UNIT
1
tc(LCD_PCLK)
Cycle time, pixel clock
2
tw(LCD_PCLKH)
Pulse duration, pixel clock high
0.45tc
0.55tc
0.45tc
0.55tc
ns
3
tw(LCD_PCLKL)
Pulse duration, pixel clock low
0.45tc
0.55tc
0.45tc
0.55tc
ns
4
td(LCD_PCLK-LCD_DATAV)
Delay time, LCD_PCLK to LCD_DATA[23:0] valid
(write)
1
ns
5
td(LCD_PCLK-LCD_DATAI)
Delay time, LCD_PCLK to LCD_DATA[23:0] invalid
(write)
6
td(LCD_PCLK-LCD_AC_BIAS_EN) Delay time, LCD_PCLK to LCD_AC_BIAS_EN
7
tt(LCD_AC_BIAS_EN)
Transition time, LCD_AC_BIAS_EN
8
td(LCD_PCLK-LCD_VSYNC)
Delay time, LCD_PCLK to LCD_VSYNC
9
tt(LCD_VSYNC)
Transition time, LCD_VSYNC
10
td(LCD_PCLK-LCD_HSYNC)
Delay time, LCD_PCLK to LCD_HSYNC
-1.5
1
11
tt(LCD_HSYNC)
Transition time, LCD_HSYNC
0.5
2.4
12
tt(LCD_PCLK)
Transition time, LCD_PCLK
0.5
2.4
13
tt(LCD_DATA)
Transition time, LCD_DATA
0.5
2.4
1
-1.5
ns
-1
ns
-1.5
1
-1
1
ns
0.5
2.4
0.5
2.4
ns
-1.5
1
-1
1
ns
0.5
2.4
0.5
2.4
ns
-1
1
ns
0.5
2.4
ns
0.5
2.4
ns
0.5
2.4
ns
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
• Vertical front porch (VFP)
• Vertical sync pulse width (VSW)
• Vertical back porch (VBP)
• Lines per panel (LPP_B10 + LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
• Horizontal front porch (HFP)
• Horizontal sync pulse width (HSW)
• Horizontal back porch (HBP)
• Pixels per panel (PPLMSB + PPLLSB)
LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
• AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 5-37. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
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Data Pixels (From 1 to P)
1, 1
2, 1
1, 2
2, 2
P−2,
1
3, 1
P−1,
1
P, 1
P−1,
2
P, 2
1, 3
Data Lines (From 1 to L)
P, 3
LCD
PRODUCT PREVIEW
1,
L−2
P,
L−2
1,
L−1
2,
L−1
1, L
2, L
P−2,
L
3, L
P−1,
L−1
P,
L−1
P−1,
L
P, L
Figure 5-37. LCD Raster-Mode Display Format
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Frame Time
VBP
(0 to 255)
VSW
(1 to 64)
Line
Time
LPP_B10 + LPP
VFP
(1 to 2048)
(0 to 255)
VSW
(1 to 64)
LCD_HSYNC
LCD_VSYNC
LCD_DATA[23:0]
1, 1
P, 1
1, 2
P, 2
1, L-1
P, L-1
1, L
P, L
10
PRODUCT PREVIEW
LCD_AC_BIAS_EN
(ACTVID)
10
LCD_HSYNC
11
LCD_PCLK
LCD_DATA[23:0]
1, 1
2, 1
1, 2
P, 1
2, 2
P, 2
LCD_AC_BIAS_EN
(ACTVID)
PPLMSB + PPLLSB
HFP
HSW
HBP
PPLMSB + PPLLSB
16 × (1 to 2048)
(1 to 256)
(1 to 64)
(1 to 256)
16 × (1 to 2048)
Line 1
Line 2
Figure 5-38. LCD Raster-Mode Active
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Frame Time
VBP = 0
VFP = 0
VSW = 1
LPP_B10 + LPP
(1 to 2048)
Line
Time
LCD_HSYNC
LCD_VSYNC
1, L
Data
LCD_DATA[7:0]
1, L:
P, L
1, 1:
P, 1
1, 2:
P, 2
1, 3:
P, 3
1, 4:
P, 4
1, 5:
P, 5
1, 6:
P, 6
1, L
P, L
1, L−1
P, L−1
1, L−4
P, L−4
1, L−3
P, L−3
1, L−2
P, L−2
1, 1
P, 1
1, 2
P, 2
1, L−1
P, L−1
LCD_AC_BIAS_EN
PRODUCT PREVIEW
ACB
ACB
(0 to 255)
(0 to 255)
10
10
LCD_HSYNC
11
LCD_PCLK
LCD_DATA[7:0]
A.
1, 5
P, 5
2, 5
1, 6
2, 6
P, 6
PPLMSB + PPLLSB
HFP
HSW
HBP
PPLMSB + PPLLSB
16 x (1 to 2048)
(1 to 256)
(1 to 64)
(1 to 256)
16 x (1 to 2048)
Line 6
Line 5
The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-39. LCD Raster-Mode Passive
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6
LCD_AC_BIAS_EN
7
8
LCD_VSYNC
9
10
10
LCD_HSYNC
11
1
2
3
LCD_PCLK
(passive mode)
5
1, L
2, L
P, L
1, 1
2, 1
P, 1
PRODUCT PREVIEW
4
LCD_DATA[7:0]
(passive mode)
1
2
3
LCD_PCLK
(active mode)
5
4
LCD_DATA[23:0]
(active mode)
VBP = 0
VFP = 0
VWS = 1
1, L
2, L
P, L
PPLMSB + PPLLSB
16 x (1 to 2048)
HFP
(1 to 256)
HSW
(1 to 64)
HBP
(1 to 256)
Line L
A.
PPLMSB + PPLLSB
16 x (1 to 2048)
Line 1 (Passive Only)
The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-40. LCD Raster-Mode Control Signal Activation
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6
LCD_AC_BIAS_EN
8
LCD_VSYNC
10
10
LCD_HSYNC
11
1
2
3
LCD_PCLK
(passive mode)
4
PRODUCT PREVIEW
LCD_D[7:0]
(passive mode)
1, 1
P, 1
2, 1
1, 2
2, 2
1, 1
2, 1
5
P, 2
1
2
3
LCD_PCLK
(active mode)
4
LCD_DATA[23:0]
(active mode)
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
16 x (1 to 2048)
HFP
(1 to 256)
HSW
(1 to 64)
HBP
(1 to 256)
PPLMSB + PPLLSB
Line 1
A.
5
P, 1
16 x (1 to 2048)
Line 1 for active
Line 2 for passive
The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-41. LCD Raster-Mode Control Signal Deactivation
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5.6
mDDR(LPDDR)/DDR2/DDR3 Memory Controller
5.6.1
DDR2 Routing Guidelines
5.6.1.1
Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the DDR2 memory controller are shown in Table 5-28 and
Figure 5-42.
Table 5-28. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller
NO.
1
-1G
PARAMETER
tc(DDR_CLK)
Cycle time, DDR_CLK
MIN
MAX
3.76
8
UNIT
ns
1
Figure 5-42. DDR2 Memory Controller Clock Timing
5.6.1.2
DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application
Report (Literature Number: SPRAAV0).
5.6.1.2.1 DDR2 Interface Schematic
Figure 5-43 shows the DDR2 interface schematic for a x16 DDR2 memory system. The AM335x device
does not support a x32 DDR2 memory system.
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DDR2
DDR_D[0]
DQ0
DDR_D[7]
DDR_DQM[0]
DDR_DQS[0]
DQ7
LDM
LDQS
DDR_DQS[0]
DDR_D[8]
LDQS
DQ8
DDR_D[15]
DDR_DQM[1]
DDR_DQS[1]
DDR_DQS[1]
DQ15
UDM
UDQS
UDQS
T0
NC
NC
ODT
DDR_BA[0]
T0
BA0
DDR_BA[2]
DDR_A[0]
T0
T0
BA2
A0
DDR_A[14]
DDR_CS[0]
T0
T0
A14
CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
DDR_CLK
T0
T0
T0
T0
T0
T0
CAS
DDR_ODT[0]
DDR_ODT[1]
DDR_D[16]
PRODUCT PREVIEW
DDR_CLK
DDR_VREF
VREF
(B)
0.1 µF
DDR_RST
VDDS_DDR 1.8
RAS
WE
CKE
CK
CK
0.1 µF
VREF
(A)
1 K Ω 1%
VREF
(B)
0.1 µF
0.1 µF
1 K Ω 1%
NC
DDR_VTP
50 Ω (±2%)
T0
A.
B.
Termination is required. See terminator comments.
VDDS_DDR 1.8 is the power supply for the DDR2 memories and the AM335x DDR2 interface.
One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
Figure 5-43. 16-Bit DDR2 High-Level Schematic
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5.6.1.2.2 Compatible JEDEC DDR2 Devices
Table 5-29 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.
Table 5-29. Compatible JEDEC DDR2 Devices (Per Interface)
NO.
PARAMETER
1
JEDEC DDR2 device speed grade(1)
2
JEDEC DDR2 device bit width
3
JEDEC DDR2 device count
4
JEDEC DDR2 device ball count(2)
MIN
MAX
UNIT
DDR2-533
x8
x16
1
2
Devices
Bits
84
92
Balls
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball
DDR2 devices are the same.
5.6.1.2.3 PCB Stackup
PRODUCT PREVIEW
The minimum stackup required for routing the AM335x device is a four-layer stackup as shown in
Table 5-30. Additional layers may be added to the PCB stackup to accommodate other circuitry or to
reduce the size of the PCB footprint.
Table 5-30. Minimum PCB Stackup
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly horizontal
2
Plane
Ground
3
Plane
Power
4
Signal
Bottom routing mostly vertical
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Complete stackup specifications are provided in Table 5-31.
Table 5-31. PCB Stackup Specifications
NO.
PARAMETER
MIN
TYP
1
PCB routing/plane layers
4
2
Signal routing layers
2
3
Full ground layers under DDR2 routing region
2
4
Number of ground plane cuts allowed within DDR routing region
5
Number of ground reference planes required for each DDR2 routing layer
6
Number of layers between DDR2 routing layer and reference ground plane
7
PCB routing feature size
4
8
PCB trace width, w
4
9
PCB BGA escape via pad size(1)
10
13
Single-ended impedance, Zo
14
0
0
18
PCB BGA escape via hole size
MPU BGA pad size
Impedance control
Mils
Mils
20
10
ZCZ package
0.5
ZCE package
0.4
(3)
UNIT
1
(1)
11
MAX
50
Z-5
Z
Mils
Mils
mm
75
Ω
Z+5
Ω
PRODUCT PREVIEW
(1) A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the
MPU.
(2) For the DDR2 device BGA pad size, see the DDR2 device manufacturer documentation.
(3) Z is the nominal singled-ended impedance selected for the PCB specified by item 13.
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5.6.1.2.4 Placement
Figure 5-44 shows the required placement for the DDR2 devices. The dimensions for this figure are
defined in Table 5-32. The placement does not restrict the side of the PCB on which the devices are
mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for
proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the
placement.
X
Y
OFFSET
DDR2
Device
Y
Y
OFFSET
DDR2
Controller
A1
Microprocessor
Recommended DDR2
Device Orientation
Figure 5-44. AM335x Device and DDR2 Device Placement
Table 5-32. Placement Specifications
NO.
MAX
UNIT
1
X(1)(2)
PARAMETER
MIN
1750
Mils
2
Y(1)(2)
1280
Mils
650
Mils
(1)(2)(3)
3
Y Offset
4
DDR2 keepout region(4)
5
Clearance from non-DDR2 signal to DDR2 keepout region(5)
4
w
(1) For dimension definitions, see Figure 5-43.
(2) Measurements from center of MPU to center of DDR2 device.
(3) For single-memory systems, it is recommended that Y offset be as small as possible.
(4) DDR2 keepout region to encompass entire DDR2 routing area.
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
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5.6.1.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 5-45. The size of this region varies with
the placement and DDR routing. Additional clearances required for the keepout region are shown in
Table 5-32.
DDR2
Device
DDR2
Controller
A1
A1
PRODUCT PREVIEW
Region should encompass all DDR2 circuitry and varies depending
on placement. Non-DDR2 signals should not be routed on the DDR
signal layers within the DDR2 keep out region. Non-DDR2 signals may
be routed in the region provided they are routed on layers separated
from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the
1.8 V power plane should cover the entire keep out region.
Figure 5-45. DDR2 Keepout Region
5.6.1.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 5-33 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 5-33. Bulk Bypass Capacitors
No.
Parameter
Min
Max
Unit
1
DVDD18 bulk bypass capacitor count(1)
6
2
DVDD18 bulk bypass total capacitance
60
μF
3
DDR#1 bulk bypass capacitor count(1)
1
Devices
4
DDR#1 bulk bypass total capacitance(1)
5
DDR#2 bulk bypass capacitor count(2)
6
DDR#2 bulk bypass total capacitance(1)(2)
Devices
10
μF
1
Devices
10
μF
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors. Use half of these capacitors for DDR[0] and half for DDR[1].
(2) Only used on 32-bit wide DDR2 memory systems.
5.6.1.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, MPU/DDR power, and
MPU/DDR ground connections. Table 5-34 contains the specification for the HS bypass capacitors as well
as for the power connections on the PCB.
150
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Table 5-34. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
1
HS bypass capacitor package size(1)
2
Distance from HS bypass capacitor to device being bypassed
3
Number of connection vias for each HS bypass capacitor(2)
2
4
Trace length from bypass capacitor contact to connection via
1
5
Number of connection vias for each MPU power/ground ball
1
6
Trace length from MPU power/ground ball to connection via
7
Number of connection vias for each DDR2 device power/ground ball
8
Trace length from DDR2 device power/ground ball to connection via
9
DVDD18 HS bypass capacitor count(3)(4)
40
10
DVDD18 HS bypass capacitor total capacitance(4)
2.4
11
DDR device HS bypass capacitor count(3)(5)
12
DDR device HS bypass capacitor total capacitance(5)
MAX
UNIT
0402
10 Mils
250
Mils
Vias
30
Mils
Vias
35
Mils
1
Vias
35
8
Mils
Devices
μF
Devices
0.4
μF
(1) LxW, 10-mil units; i.e., a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(5) Per DDR device.
5.6.1.2.8 Net Classes
Table 5-35 lists the clock net classes for the DDR2 interface. Table 5-36 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 5-35. Clock Net Class Definitions
CLOCK NET CLASS
CK
MPU PIN NAMES
DDR_CLK/DDR_CLK
DQS0
DDR_DQS[0]/DDR_DQS[0]
DQS1
DDR_DQS[1]/DDR_DQS[1]
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(4) Use half of these capacitors for DDR[0] and half for DDR[1].
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Table 5-36. Signal Net Class Definitions
CLOCK NET CLASS
ASSOCIATED CLOCK
NET CLASS
ADDR_CTRL
CK
DQ0
DQS0
DDR_D[7:0], DDR_DQM[0]
DQ1
DQS1
DDR_D[15:8], DDR_DQM[1]
MPU PIN NAMES
DDR_BA[2:0], DDR_A[14:0], DDR_CS[x], DDR_CAS, DDR_RAS, DDR_WE,
DDR_CKE
5.6.1.2.9 DDR2 Signal Termination
Signal terminators are required in CK and ADDR_CTRL net classes. Serial terminators may be used on
data lines to reduce EMI risk; however, serial terminations are the only type permitted. ODT's are
integrated on the data byte net classes. They should be enabled to ensure signal integrity. Table 5-37
shows the specifications for the series terminators.
Table 5-37. DDR2 Signal Terminations
No.
Parameter
Min
1
CK net class(1)(2)
0
2
ADDR_CTRL net class(1)(2)(3)(4)
0
PRODUCT PREVIEW
3
(5)
Data byte net classes (DQS0-DQS3, DQ0-DQ3)
Typ
0
22
Max
Unit
10
Ω
Zo
Ω
0
Ω
(1) Only series termination is permitted, parallel or SST specifically disallowed on board.
(2) Only required for EMI reduction.
(3) Terminator values larger than typical only recommended to address EMI issues.
(4) Termination value should be uniform across net class.
(5) No external terminations allowed for data byte net classes. ODT is to be used.
5.6.1.2.10 DDR_VREF Routing
DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the MPU. VREF
is intended to be half the DDR2 power supply voltage and should be created using a resistive divider as
shown in Figure 5-43. Other methods of creating VREF are not recommended. Figure 5-46 shows the
layout guidelines for VREF.
VREF Bypass Capacitor
DDR2 Device
A1
VREF Nominal Minimum
Trace Width is 20 Mils
Microprocessor
A1
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
Figure 5-46. VREF Routing and Topology
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5.6.1.3
DDR2 CK and ADDR_CTRL Routing
Figure 5-47 shows the topology of the routing for the CLK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
T
C
A
DDR2
Controller
B
A1
Microprocessor
A1
Table 5-38. CK and ADDR_CTRL Routing Specification(1)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
Cente- to-center DQS-DQSN spacing
2w
2
CK differential pair skew length mismatch(1)(2)
25
Mils
3
CK B-to-CK C skew length mismatch
25
Mils
4
Center-to-center CK to other DDR2 trace spacing(3)
5
CK/ADDR_CTRL nominal trace length(4)
CACLM+50
Mils
6
ADDR_CTRL-to-CK skew length mismatch
100
Mils
7
ADDR_CTRL-to-ADDR_CTRL skew length mismatch
100
Mils
8
Center-to-center ADDR_CTRL to other DDR2 trace spacing(3)
9
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(3)
100
Mils
100
Mils
10
ADDR_CTRL A-to-B/ADDR_CTRL A-to-C skew length mismatch
11
ADDR_CTRL B-to-C skew length mismatch
4w
CACLM-50
CACLM
4w
(1)
3w
(1) Series terminator, if used, should be located closest to the MPU.
(2) Differential impedance should be 100 Ω.
(3) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 5-48 shows the topology and routing for the DQS and Dx net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
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Figure 5-47. CK and ADDR_CTRL Routing and Topology
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T
E0
T
E1
DDR2
Controller
A1
Microprocessor
T
A1
E2
T
E3
Figure 5-48. DQS and Dx Routing and Topology
Table 5-39. DQS and Dx Routing Specification(1)(2)
NO.
PARAMETER
PRODUCT PREVIEW
1
Center-to-center DQS-DQSN spacing
2
DQS E differential pair skew length mismatch(3)
3
Center-to-center DQS to other DDR2 trace spacing
4
DQS/Dx nominal trace length(2)(5)
5
Dx-to-DQS skew length mismatch(5)
MIN
TYP
MAX
UNIT
2w
(4)
25
Mils
DQLM+50
Mils
100
Mils
100
Mils
4w
DQLM-50
(5)
6
Dx-to-Dx skew length mismatch
7
Center-to-center Dx to other DDR2 trace spacing(4)(6)
4w
8
Center-to-center Dx to other Dx trace spacing(4)(7)
3w
DQLM
(1) Dx indicates a data line. E indicates length of DQS differential pair or Dx signal.
(2) Series terminator, if used, should be located closest to DDR.
(3) Differential impedance should be 100 Ω.
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) There is no need, and it is not recommended, to skew match across data bytes; i.e., from DQS0 and data byte 0 to DQS1 and data
byte 1.
(6) Data lines (Dx) from other DQS domains are considered other DDR2 trace.
(7) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.
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6 Device and Documentation Support
6.1
6.1.1
Device Support
Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of AM335x device applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any AM335x device application. DSP/BIOS™
For a complete listing of development-support tools for the AM335x microprocessor platform, visit the
Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest
TI field sales office or authorized distributor.
6.1.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(e.g., XAM3358ZCE). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
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Hardware Development Tools: Extended Development System (XDS™) Emulator XDS™
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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCE), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range, in megahertz (for example, 27 is 275-MHz). Figure 6-1
provides a legend for reading the complete device name for any AM335x device.
For orderable part numbers of AM335x devices in the ZCE and ZCZ package types, see the Package
Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AM335x ARM
Cortex-A8 Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
X
AM3358
PREFIX
X = Experimental device
Blank = Qualified device
(A)
ZCE
(
)
(
)
TEMPERATURE RANGE
Blank = 0°C to 90°C (commercial junction temperature)
A = -40°C to 105°C (extended temperature)
D = -40°C to 90°C (industrial temperature)
(B)
PRODUCT PREVIEW
PACKAGE TYPE
ZCE = 298-pin plastic BGA, with Pb-Free solder balls
ZCZ = 324-pin plastic BGA, with Pb-Free solder balls
SILICON REVISION
Blank = silicon revision 1.0
B.
)
DEVICE SPEED RANGE
27 = 275-MHZ Cortex-A8
50 = 500-MHZ Cortex-A8
60 = 600-MHZ Cortex-A8
72 = 720-MHz Cortex-A8
DEVICE
ARM Cortex-A8 MPU:
AM3352
AM3354
AM3356
AM3357
AM3358
AM3359
A.
(
The AM3358 device shown in this device nomenclature example is one of several valid part numbers for the AM335x
family of devices. For orderable device part numbers, see the Package Option Addendum of this document.
BGA = Ball Grid Array.
Figure 6-1. AM335x Device Nomenclature
6.2
6.2.1
Documentation Support
Related Documentation from Texas Instruments
The following documents describe the AM335x MPU. Copies of these documents are available on the
Internet at www.ti.com. Tip: Enter the literature number in the search box.
The current documentation that describes the AM335x MPU, related peripherals, and other technical
collateral, is available in the product folder at: www.ti.com.
6.2.2
SPRUH73
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual.
Collection of documents providing detailed information on the AM335x device including
power, reset, and clock control, interrupts, memory map, and switch fabric interconnect.
Detailed information on the microprocessor unit (MPU) subsystem as well as a functional
description of the peripherals supported on AM335x devices is also included.
SPRZ360
AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata. Describes the known
exceptions to the functional specifications for the AM335x ARM Cortex-A8 Microprocessors.
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
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innovation and growth of general knowledge about the hardware and software surrounding
these devices.
6.2.3
Related Documentation from Other Sources
The following documents are related to the AM335x MPU. Copies of these documents can be obtained
directly from the internet or from your Texas Instruments representative.
Cortex-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8
processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. To
determine the revision of the Cortex-A8 core used on your device, see the AM335x ARM Cortex-A8
Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
PRODUCT PREVIEW
ARM Core Cortex™-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different
revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. To
determine the revision of the Cortex-A8 core used on your device, see the AM335x ARM Cortex-A8
Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
Device and Documentation Support
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7 Mechanical Packaging and Orderable Information
7.1
Thermal Data for ZCE and ZCZ Packages
Table 7-1 provides thermal characteristics for the packages used on this device.
NOTE
Table 7-1 provides simulation data and may not represent actual use-case values.
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCE and ZCZ]
NAME
DESCRIPTION
ΘJC
ΘJB
ΘJA
PRODUCT PREVIEW
ZCZ
(°C/W) (2)
Junction-to-case (1S0P) (3)
N/A
10.3
10.2
Junction-to-board (2S2P) (3)
N/A
11.6
12.1
0.0
24.7
24.2
1.0
20.5
20.1
2.0
19.7
19.3
3.0
19.2
18.8
0.0
0.4
0.3
1.0
0.6
0.6
2.0
0.7
0.7
(3)
Junction-to-package top (2S2P) (3)
Junction-to-board (2S2P) (3)
ΨJB
7.2
ZCE
(°C/W) (2)
Junction-to-free air (2S2P)
ΨJT
(1)
(2)
(3)
AIR
FLOW (1)
3.0
0.9
0.8
0.0
11.9
12.7
1.0
11.7
12.3
2.0
11.7
12.3
3.0
11.6
12.2
m/s = meters per second.
°C/W = degress celsius per watt.
The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area
Array Surface Mount Package Thermal Measurements).
Via Channel
The ZCE package has been specially engineered with Via Channel™ technology. This allows larger than
normal PCB via and trace sizes and reduced PCB signal layers to be used in a PCB design with the
0.65-mm pitch package, and substantially reduces PCB costs. It allows PCB routing in only two signal
layers (four layers total) due to the increased layer efficiency of the Via Channel™ BGA technology.
7.3
Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
The figures below show the package drawings for the ZCE and ZCZ package options.
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PACKAGE OPTION ADDENDUM
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28-Oct-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
XAM3358ZCE
ACTIVE
NFBGA
ZCE
298
1
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
XAM3359ZCZ
ACTIVE
NFBGA
ZCZ
324
1
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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