Cypress CY8C23533 Psoc programmable system-on-chip Datasheet

CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip™
Features
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
❐ 4 Rail-to-Rail analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ High-Speed 8-Bit SAR ADC Optimized for Motor Control
■
■
■
■
■
Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
SROM
Flash 8K
CPUCore (M8C)
Interrupt
Controller
Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
Global Analog Interconnect
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
Flexible On-Chip Memory
❐ 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Analog
Block Array
2 Columns
4 Blocks
1 Row
4 Blocks
Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
Digital
Clocks
Multiply
Accum.
ANALOG SYSTEM
SAR8 ADC
Decimator
I2C
Analog
Ref
Analog
Input
Muxing
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Additional System Resources
2
❐ I C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-chip Precision Voltage Reference
Cypress Semiconductor Corporation
Document Number: 001-44369 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 05, 2008
[+] Feedback
CY8C23433, CY8C23533
PSoC Functional Overview
Digital System
The PSoC family consists of many mixed-signal array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
a low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts and
packages.
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 2
To System Bus
Digital Clocks
FromCore
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, consists of four main areas: PSoC Core, Digital System,
Analog System, and System Resources. Configurable global
busing allows combining all the device resources into a complete
custom system. The PSoC CY8C23x33 family can have up to
three IO ports that connect to the global digital and analog
interconnects, providing access to four digital blocks and four
analog blocks.
Port 1
Port 0
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
Row Input
Configuration
8
DBB00
DBB01
DCB02
4
DCB03
4
8
Row Output
Configuration
8
8
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 8 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Document Number: 001-44369 Rev. *B
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 1)
■
SPI master and slave (up to 1)
■
I2C slave and master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 1)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table titled PSoC Device Characteristics on page 4.
Page 2 of 37
[+] Feedback
CY8C23433, CY8C23533
The Analog system consists of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block consists of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
■
Filters (2 band pass, low-pass)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (1, with 16 selectable thresholds)
■
DAC (6 or 9 -bit DAC)
■
Multiplying DAC (6 or 9 -bit DAC)
■
High current output drivers (two with 30 mA drive)
■
1.3V reference (as a System Resource)
■
DTMF dialer
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
Analog System
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
ACB01
ASD11
ASC21
P0[7:0]
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The Analog Column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
ACI2[3:0]
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-44369 Rev. *B
Page 3 of 37
[+] Feedback
CY8C23433, CY8C23533
Getting Started
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, decimator,
low voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow:
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on the PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources available
for specific PSoC device groups.
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SAR8
ADC
up to 4
64
16
12
4
4
12
No
CY8C27x43
up to 2
44
8
12
4
4
12
No
CY8C24x94
56
1
4
48
2
2
6
No
CY8C23X33
up to 1
26
4
12
2
2[1]
4
Yes
CY8C24x23A up to 1
24
4
12
2
2
6
No
CY8C21x34
up to 1
28
4
28
0
2
4[2]
No
CY8C21x23
16
4
8
0
2
4[2]
No
0
3[3]
No
CY8C20x34
Digital
Rows
CY8C29x66
PSoC Part
Number
Digital
IO
Digital
Blocks
Table 1. PSoC Device Characteristics
1
up to 0
28
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Mixed-Signal
Array Technical Reference Manual.
For latest Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
at http://www.cypress.com/psoc.
To determine which PSoC device meets your requirements,
navigate through the PSoC Decision Tree in the Application Note
AN2209 at http://www.cypress.com and select Application Notes
under the Design Resources.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/onlinestore.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced
analog
and
CapSense.
Go
to
http://www.cypress.com.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located at the top of the web page, and select CYPros
Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support.
Application Notes
0
28
0
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to
http://www.cypress.com/psocapnotes.
Notes
1. One complete column, plus one Continuous Time Block.
2. Limited analog functionality.
3. Two analog blocks and one CapSense.
Document Number: 001-44369 Rev. *B
Page 4 of 37
[+] Feedback
CY8C23433, CY8C23533
Development Tools
PSoC Designer Software Subsystems
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP (refer section PSoC Designer
Subsystems on page 5).
Device Editor
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
Graphical Designer
Interface
Context
Sensitive
Help
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. Once the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
Results
Commands
PSoC
Designer
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Importable
Design
Database
Application Editor
Device
Database
Application
Database
PSoC
Designer
Core
Engine
Project
Database
PSoC
Configuration
Sheet
Manufacturing
Information
File
User
Modules
Library
Emulation
Pod
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries
automatically use absolute addressing or can be compiled in
relative mode, and linked with other software modules to get
absolute addressing.
C Language Compiler. A C language compiler is available that
supports the PSoC family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the PSoC family devices.
In-Circuit
Emulator
Document Number: 001-44369 Rev. *B
Device
Programmer
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Page 5 of 37
[+] Feedback
CY8C23433, CY8C23533
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and can operate
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides high
level functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by
interconnecting user modules to each other and the IO pins. At
this stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
Figure 4. User Module/Source Code Development Flows
Device Editor
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and the software. This substantially lowers the risk of
having to select a different part to meet the final design
requirements.
User
Module
Selection
Document Number: 001-44369 Rev. *B
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other uncommon peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
Placement
and
Parameter
-ization
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
Page 6 of 37
[+] Feedback
CY8C23433, CY8C23533
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Table 2. Acronyms Used (continued)
Acronym
Description
PWM
pulse width modulator
RAM
random access memory
ROM
read only memory
SC
switched capacitor
Units of Measure
A units of measure table is located in the section Electrical
Specifications on page 14. Table 8 on page 14 lists all the
abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms Used
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose IO
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
Document Number: 001-44369 Rev. *B
Page 7 of 37
[+] Feedback
CY8C23433, CY8C23533
Pinouts
The PSoC CY8C23X33 is available in 32-pin QFN and 28-pin SSOP packages. Every port pin (labeled with a “P”), except for Vss and
Vdd in the following table and figure, is capable of Digital IO.
32-Pin Part Pinout
Table 3. Pin Definitions - 32-Pin (QFN)
IO
2
IO
3
IO
I
4
IO
I
5
IO
AVref
6
P2[7]
GPIO
P2[5]
GPIO
P2[3]
Direct Switched Capacitor Block Input
P2[1]
Direct Switched Capacitor Block Input
P3[0][4] GPIO/ADC Vref (optional)
NC
7
IO
P1[7]
8
IO
P1[5]
9
NC
No Connection
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
No Connection
10
IO
P1[3]
GPIO
11
IO
P1[1]
GPIO, Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
12
Power
Vss
Ground Connection
13
IO
P1[0]
GPIO, Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
14
IO
P1[2]
GPIO
15
IO
P1[4]
GPIO, External Clock IP
IO
P1[6]
16
17
NC
18
Input
GPIO, P2[7]
GPIO, P2[5]
A, I, P2[3]
A, I, P2[1]
AVref, P3[0]
NC
I2C SCL, P1[7]
I2C SDA, P1[5]
1
2
3
4
5
6
7
8
QFN
(Top View)
24
23
22
21
20
19
18
17
P0[2], A, I
P0[0], A, I
P2[6], Vref
P2[4], AGnd
P2[2], A, I
P2[0], A, I
XRES
P1[6], GPIO
No Connection
GPIO
XRES Active High External Reset with Internal Pull Down
19
IO
I
20
IO
I
21
IO
22
IO
P2[6]
External Voltage Reference (VRef)
23
IO
I
P0[0]
Analog Column Mux Input and ADC Input
24
IO
I
P0[2]
Analog Column Mux Input and ADC Input
25
P2[0]
Direct Switched Capacitor Block Input
P2[2]
Direct Switched Capacitor Block Input
P2[4]
External Analog Ground (AGnd)
NC
No Connection
26
IO
I
P0[4]
Analog Column Mux Input and ADC Input
27
IO
I
P0[6]
Analog Column Mux Input and ADC Input
28
Figure 5. CY8C23533 32-Pin PSoC Device
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Vdd
P0[6], A, I
P0[4], A, I
NC
1
Description
32
31
30
29
28
27
26
25
Pin
Digital Analog Name
9
10
11
12
13
14
15
16
Type
NC
GPIO P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
GPIO P1[2]
GPIO, EXTCLK, P1[4]
NC
Pin
No.
Vdd
Supply Voltage
29
IO
Power
I
P0[7]
Analog Column Mux Input and ADC Input
30
IO
IO
P0[5]
Analog Column Mux Input, Column Output and
ADC Input
31
IO
IO
P0[3]
Analog Column Mux Input, Column Output and
ADC Input
32
IO
I
P0[1]
Analog Column Mux Input.and ADC Input
LEGEND: A = Analog, I = Input, and O = Output.
Note
4. Even though P3[0] is an odd port, it resides on the left side of the pinout.
Document Number: 001-44369 Rev. *B
Page 8 of 37
[+] Feedback
CY8C23433, CY8C23533
28-Pin Part Pinout
IO
2
IO
I
IO
Figure 6. CY8C23433 28-Pin PSoC Device
Pin Name
Digital
1
Analog
Pin Number
CY8C23433
Table 4. Pin Definitions - 28-Pin (SSOP)
P0[7]
P0[5]
Description
Analog Column Mux IP and ADC IP
Analog Column Mux IP and Column
O/P and ADC IP
AIO, P0[7]
1
28
Vdd
IO, P0[5]
2
27
P0[6], AIO, AnColMux and ADC IP
IO, P0[3]
3
26
P0[4], AIO, AnColMux and ADC IP
AIO, P0[1]
4
25
P0[2], AIO, AnColMux and ADC IP
IO, P2[7]
5
24
P0[0], AIO, AnColMux and ADC IP
IO, P2[5]
6
23
P2[6], VREF
AIO, P2[3]
7
22
P2[4], AGND
AIO, P2[1]
8
21
P2[2], AIO
SSOP
3
IO
IO
P0[3]
Analog Column Mux IP and Column
O/P and ADC IP
AVref, IO, P3[0]
9
20
P2[0], AIO
I2C SCL, IO, P1[7]
10
19
P3[1], IO
I2C SDA, IO, P1[5]
11
18
P1[6], IO
4
IO
I
P0[1]
Analog Column Mux IP and ADC IP
IO, P1[3]
12
17
P1[4], IO, EXTCLK
5
IO
P2[7]
GPIO
I2C SCL,ISSP SCL,XTALin,IO, P1[1]
13
16
P1[2], IO
Vss
14
15
P1[0],IO,XTALout,ISSP SDA,I2C SDA
6
IO
P2[5]
GPIO
7
IO
I
P2[3]
Direct Switched Capacitor Input
8
IO
I
P2[1]
Direct Switched Capacitor Input
9
IO
AVref
P3[0][5]
GPIO/ADC Vref (optional)
10
IO
P1[7]
I2C SCL
11
IO
P1[5]
I2C SDA
12
IO
P1[3]
GPIO
IO
P1[1][6]
GPIO, Xtal Input, I2C SCL, ISSP SCL
14
Power
Vss
Ground Pin
15
IO
P1[0][6]
GPIO, Xtal Output, I2C SDA, ISSP
SDA
16
IO
P1[2]
GPIO
17
IO
P1[4]
GPIO, External Clock IP
18
IO
P1[6]
GPIO
19
IO
P3[1][7]
GPIO
20
IO
I
P2[0]
Direct Switched Capacitor Input
21
IO
I
P2[2]
Direct Switched Capacitor Input
22
IO
P2[4]
External Analog Ground (AGnd)
23
IO
P2[6]
Analog Voltage Reference (VRef)
24
IO
I
P0[0]
Analog Column Mux IP and ADC IP
25
IO
I
P0[2]
Analog Column Mux IP and ADC IP
26
IO
I
P0[4]
Analog Column Mux IP and ADC IP
27
IO
I
P0[6]
Analog Column Mux IP and ADC IP
28
Power
Vdd
Supply Voltage
13
LEGEND: A = Analog, I = Input, and O = Output.
Notes
5. Even though P3[0] is an odd port, it resides on the left side of the pinout.
6. ISSP pin, which is not High Z at POR.
7. Even though P3[1] is an even port, it resides on the right side of the pinout.
Document Number: 001-44369 Rev. *B
Page 9 of 37
[+] Feedback
CY8C23433, CY8C23533
Register Reference
Register Mapping Tables
This section lists the registers of the CY8C23433 PSoC device
by using mapping tables, in offset order.
Register Conventions
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Table 5. Abbreviations
Convention
R
Description
Read register or bits
W
Write register or bits
L
Logical register or bits
C
Clearable register or bits
#
Access is bit specific
Document Number: 001-44369 Rev. *B
Page 10 of 37
[+] Feedback
CY8C23433, CY8C23533
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
Gray fields are reserved.
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
AMX_IN
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
SARADC_DL
SARADC_CR0
SARADC_CR1
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1 *
ACB01CR2 *
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
#
#
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
RW
RW
RW
RW
RW
RW
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
Addr
(0,Hex)
Addr
(0,Hex)
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
Name
Name
Table 6. Register Map Bank 0 Table: User Space
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
# Access is bit specific.
Document Number: 001-44369 Rev. *B
Page 11 of 37
[+] Feedback
CY8C23433, CY8C23533
Gray fields are reserved.
CPU_SCR1
CPU_SCR0
Access
BE
BF
Name
Access
Addr
(0,Hex)
Name
Access
7E
7F
Addr
(0,Hex)
3E
3F
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
Table 6. Register Map Bank 0 Table: User Space (continued)
FE
FF
#
#
# Access is bit specific.
DBB00FN
DBB00IN
DBB00OU
DBB01FN
DBB01IN
DBB01OU
DCB02FN
DCB02IN
DCB02OU
DCB03FN
DCB03IN
DCB03OU
Gray fields are reserved.
RW
RW
RW
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
AMD_CR1
ALT_CR0
RW
RW
RW
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SARADC_TRS
SARADC_TRCL
SARADC_TRCH
SARADC_CR2
SARADC_LCR
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
RW
RW
RW
#
RW
RW
RW
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
Access
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
Addr
(1,Hex)
Addr
(1,Hex)
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
Name
Name
Table 7. Register Map Bank 1 Table: Configuration Space
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
# Access is bit specific.
Document Number: 001-44369 Rev. *B
Page 12 of 37
[+] Feedback
CY8C23433, CY8C23533
Gray fields are reserved.
FLS_PR1
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
CPU_F
CPU_SCR1
CPU_SCR0
Access
RW
RW
Addr
(1,Hex)
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Name
RDI0RO0
RDI0RO1
Access
RW
RW
RW
Addr
(1,Hex)
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Name
Access
Name
ACB01CR0
ACB01CR1
ACB01CR2 *
Addr
(1,Hex)
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Access
Addr
(1,Hex)
Name
Table 7. Register Map Bank 1 Table: Configuration Space (continued)
RL
RW
#
#
# Access is bit specific.
Document Number: 001-44369 Rev. *B
Page 13 of 37
[+] Feedback
CY8C23433, CY8C23533
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C23433 PSoC device. For the latest electrical specifications,
visit http://www.cypress.com/psoc. Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Refer to
Table 24 on page 25 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 7. Voltage versus CPU Frequency
5.25
SLIMO Mode = 0
Figure 8. IMO Frequency Trim Options
5.25
4.75
Vdd Voltage
Vdd Voltage
lid g
Va ratin n
pe io
O Reg
4.75
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
3.00
93 kHz
12 MHz
3 MHz
93 kHz
24 MHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 8. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
°C
degree Celsius
μW
micro watts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nano ampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
W
ohm
MHz
megahertz
pA
pico ampere
MΩ
megaohm
pF
pico farad
μA
micro ampere
pp
peak-to-peak
μF
micro farad
ppm
μH
micro henry
ps
picosecond
μs
microsecond
sps
samples per second
μV
micro volts
s
sigma: one standard deviation
micro volts root-mean-square
V
volts
μVrms
Document Number: 001-44369 Rev. *B
parts per million
Page 14 of 37
[+] Feedback
CY8C23433, CY8C23533
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 9. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
-55
25
+100
°C
Ambient Temperature with Power Applied
-40
–
+85
°C
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
DC Input Voltage
Vss - 0.5
–
Vdd + 0.5
V
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5
V
TSTG
Storage Temperature
TA
Vdd
VIO
VIOZ
IMIO
Maximum Current into any Port Pin
ESD
Electro Static Discharge Voltage
LU
Latch-up Current
-25
–
+50
mA
2000
–
–
V
–
–
200
mA
Notes
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25°C ± 25°C.
Extended duration storage
temperatures above 65°C
degrade reliability.
Human Body Model ESD.
Operating Temperature
Table 10. Operating Temperature
Min
Typ
Max
Units
TA
Symbol
Ambient Temperature
Description
-40
–
+85
°C
TJ
Junction Temperature
-40
–
+100
°C
Document Number: 001-44369 Rev. *B
Notes
The temperature rise from
ambient to junction is package
specific. See Thermal Impedances by Package on page 35.
The user must limit the power
consumption to comply with this
requirement.
Page 15 of 37
[+] Feedback
CY8C23433, CY8C23533
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 11. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
Min
3.0
Typ
–
Max
5.25
IDD
Supply Current
–
5
8
IDD3
Supply Current
–
3.3
6.0
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[8]
–
3
6.5
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.[8]
–
4
25
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.[8]
–
4
7.5
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.[8]
–
5
26
VREF
Reference Voltage (Bandgap)
1.28
1.30
1.33
Units
Notes
V
See DC POR and LVD
Specifications on page 22.
mA Conditions are Vdd = 5.0V,
TA = 25°C, CPU = 3 MHz, SYSCLK
doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 93.75 kHz,
analog power = off.
SLIMO mode = 0. IMO = 24 MHz.
mA Conditions are Vdd = 3.3V,
TA = 25°C, CPU = 3 MHz, SYSCLK
doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 93.75 kHz, analog power =
off. SLIMO mode = 0.
IMO = 24 MHz.
μA Conditions are with internal slow
speed oscillator, Vdd = 3.3V,
-40°C ≤ TA ≤ 55°C,
analog power = off.
μA Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55°C
< TA ≤ 85°C, analog power = off.
μA Conditions are with properly
loaded, 1 μW max, 32.768 kHz
crystal. Vdd = 3.3V, -40°C ≤ TA ≤
55°C, analog power = off.
μA Conditions are with properly
loaded, 1μW max, 32.768 kHz
crystal. Vdd = 3.3 V, 55°C < TA ≤
85°C, analog power = off.
V
Trimmed for appropriate Vdd.
Vdd > 3.0V
Note
8. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 001-44369 Rev. *B
Page 16 of 37
[+] Feedback
CY8C23433, CY8C23533
DC General Purpose IO Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 12. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
RPU
Pull up Resistor
4
5.6
8
kΩ
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to
5.25V (maximum 40 mA on even
port pins (for example, P0[2],
P1[4]), maximum 40 mA on odd
port pins (for example, P0[3],
P1[5])). 80 mA maximum
combined IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to
5.25V (maximum 100 mA on
even port pins (for example,
P0[2], P1[4]), maximum 100 mA
on odd port pins (for example,
P0[3], P1[5])). 100 mA maximum
combined IOH budget.
0.8
V
Vdd = 3.0 to 5.25
V
Vdd = 3.0 to 5.25
VIL
Input Low Level
–
–
VIH
Input High Level
2.1
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C
Document Number: 001-44369 Rev. *B
Page 17 of 37
[+] Feedback
CY8C23433, CY8C23533
DC Operational Amplifier Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 13. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA Average Input Offset Voltage Drift
Min
Typ
Max
Units
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
–
7.0
35.0
μV/°C
Notes
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
0.0
–
V
0.5
–
Vdd
Vdd - 0.5
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics of the analog output
buffer.
–
–
dB
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
60
60
80
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
300
600
1200
2400
4600
400
800
1600
3200
6400
μA
μA
μA
μA
μA
52
80
–
dB
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
Document Number: 001-44369 Rev. *B
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
Page 18 of 37
[+] Feedback
CY8C23433, CY8C23533
Table 14. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
TCVOSOA Average Input Offset Voltage Drift
Min
Typ
Max
Units
–
–
1.65
1.32
10
8
mV
mV
–
7.0
35.0
μV/°C
Notes
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics of the analog output
buffer.
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
dB
60
60
80
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
300
600
1200
2400
4600
400
800
1600
3200
6400
μA
μA
μA
μA
μA
PSRROA
Supply Voltage Rejection Ratio
52
80
–
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
DC Low Power Comparator Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 15. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
0.2
–
Vdd - 1
V
VREFLPC
Low power comparator (LPC) reference voltage
range
ISLPC
LPC supply current
–
10
40
μA
VOSLPC
LPC voltage offset
–
2.5
30
mV
Document Number: 001-44369 Rev. *B
Page 19 of 37
[+] Feedback
CY8C23433, CY8C23533
DC Analog Output Buffer Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 16. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
Description
Min
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.1
Power = High
0.5 x Vdd + 1.1
VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
–
Power = High
–
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
–
Power = High
–
PSRROB Supply Voltage Rejection Ratio
52
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
Notes
1
1
–
–
W
W
–
–
–
–
V
V
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
VOUT >(Vdd - 1.25)
Min
Typ
Max
Units
Notes
–
3
12
mV
Table 17. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
Description
Input Offset Voltage (Absolute Value)
–
+6
–
μV/°C
0.5
-
Vdd - 1.0
V
–
–
1
1
–
–
W
W
VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.0
Power = High
0.5 x Vdd + 1.0
–
–
–
–
V
V
VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
0.8
2.0
2.0
4.3
mA
mA
Supply Voltage Rejection Ratio
52
64
–
dB
TCVOSOB Average Input Offset Voltage Drift
VCMOB
Common-Mode Input Voltage Range
ROUTOB
Output Resistance
Power = Low
Power = High
ISOB
PSRROB
Document Number: 001-44369 Rev. *B
VOUT > (Vdd - 1.25)
Page 20 of 37
[+] Feedback
CY8C23433, CY8C23533
DC Analog Reference Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 18. 5V DC Analog Reference Specifications
Symbol
Description
BG
Bandgap Voltage Reference
–
AGND = Vdd/2
–
AGND = 2 x BandGap
–
AGND = P2[4] (P2[4] = Vdd/2)
–
AGND = BandGap
–
AGND = 1.6 x BandGap
–
AGND Block to Block Variation
(AGND = Vdd/2)
–
RefHi = Vdd/2 + BandGap
–
RefHi = 3 x BandGap
–
RefHi = 2 x BandGap + P2[6]
(P2[6] = 1.3V)
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
–
Min
Typ
Max
Units
1.28
1.30
1.33
V
Vdd/2 - 0.04
Vdd/2 - 0.01
Vdd/2 + 0.007
V
2 x BG - 0.048
2 x BG - 0.030
2 x BG + 0.024
V
P2[4] - 0.011
P2[4]
P2[4] + 0.011
V
BG - 0.009
BG + 0.008
BG + 0.016
V
1.6 x BG - 0.022
1.6 x BG - 0.010
1.6 x BG + 0.018
V
-0.034
0.000
0.034
V
Vdd/2 + BG - 0.10
Vdd/2 + BG
Vdd/2 + BG + 0.10
V
3 x BG - 0.06
3 x BG
3 x BG + 0.06
V
2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077
V
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
V
P2[4] + P2[6] - 0.133
P2[4] + P2[6] - 0.016
P2[4] + P2[6]+ 0.100
V
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
V
–
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.04
Vdd/2 - BG + 0.024
Vdd/2 - BG + 0.04
V
–
RefLo = BandGap
BG - 0.06
BG
BG + 0.06
V
–
RefLo = 2 x BandGap - P2[6]
(P2[6] = 1.3V)
–
RefLo = P2[4] – BandGap
(P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134
V
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
V
P2[4] - P2[6] - 0.057
P2[4] - P2[6] + 0.026
P2[4] - P2[6] + 0.110
V
Typ
Max
Units
Table 19. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
BG
Bandgap Voltage Reference
–
AGND = Vdd/2
–
AGND = 2 x BandGap
–
AGND = P2[4] (P2[4] = Vdd/2)
–
AGND = BandGap
–
AGND = 1.6 x BandGap
–
AGND Column to Column Variation
(AGND = Vdd/2)
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
Document Number: 001-44369 Rev. *B
1.28
1.30
1.33
V
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.005
V
P2[4] - 0.008
P2[4] + 0.001
P2[4] + 0.009
V
Not Allowed
BG - 0.009
BG + 0.005
BG + 0.015
V
1.6 x BG - 0.027
1.6 x BG - 0.010
1.6 x BG + 0.018
V
-0.034
0.000
0.034
mV
Page 21 of 37
[+] Feedback
CY8C23433, CY8C23533
Table 19. 3.3V DC Analog Reference Specifications (continued)
Symbol
Description
Min
Typ
–
RefHi = 2 x BandGap + P2[6]
(P2[6] = 0.5V)
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] =
0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6]
= 0.5V)
Max
Units
P2[4] + P2[6] + 0.057
V
P2[4] - P2[6] + 0.092
V
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.075
P2[4] + P2[6] - 0.009
Not Allowed
P2[4] - P2[6] - 0.048
P2[4]- P2[6] + 0.022
DC Analog PSoC Block Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switch Cap)
Min
Typ
Max
Units
–
12.2
–
kΩ
–
80[9]
–
fF
DC POR and LVD Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 21. DC POR and LVD Specifications
Symbol
Description
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
Vdd must be greater than or equal
to 2.5V during startup or reset from
Watchdog.
–
2.82
4.55
2.95
4.70
V
V
2.850
2.95
3.06
4.37
4.50
4.62
4.71
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.99[10]
3.09
3.20
4.55
4.75
4.83
4.95
V0
V0
V0
V0
V0
V
V
Notes
9. CSC is a design guarantee parameter, not tested value
10. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-44369 Rev. *B
Page 22 of 37
[+] Feedback
CY8C23433, CY8C23533
DC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. DC Programming Specifications
Symbol
Description
VddIWRITE Supply Voltage for Flash Write Operations
Min
Typ
Max
Units
Notes
2.7
–
–
V
IDDP
Supply Current During Programming or Verify
–
5
25
mA
VILP
Input Low Voltage During Programming or
Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or
Verify
2.1
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
–
–
0.2
mA
Driving internal pull down
resistor
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
–
1.5
mA
Driving internal pull down
resistor
VOLV
Output Low Voltage During Programming or
Verify
–
–
Vss + 0.75
V
VOHV
Output High Voltage During Programming or
Verify
Vdd - 1.0
–
Vdd
V
FlashENPB Flash Endurance (per block)
(total)[11]
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
50,000
–
–
–
Erase/write cycles per block
1,800,000
–
–
–
Erase/write cycles
10
–
–
Years
Note
11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to 0xthe Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-44369 Rev. *B
Page 23 of 37
[+] Feedback
CY8C23433, CY8C23533
SAR8 ADC DC Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. SAR8 ADC DC Specifications
Symbol
Description
VADCVREF Reference voltage at pin P3[0] when configured
as ADC reference voltage
IADCVREF
Current when P3[0] is configured as ADC VREF
INL
Integral Non-linearity
INL
(limited
range)
Integral Non-linearity accommodating a shift in
the offset at 0x80
DNL
Differential Non-linearity
DNL
(limited
range)
Differential Non-linearity excluding 0x7F-0x80
transition
Min
Typ
Max
Units
Notes
3.0
–
5.25
V
The voltage level at P3[0]
(when configured as ADC
reference voltage) must
always be maintained to be
less than chip supply voltage
level on Vdd pin.
VADCVREF < Vdd.
3
–
–
mA
-1.5
–
+1.5
LSB
-1.2[12]
–
+1.2
LSB
The maximum LSB is over a
sub-range not exceeding
1/16 of the full-scale range.
0x7F and 0x80 points specs
are excluded here
-2.3
–
+2.3
LSB
ADC conversion is
monotonic over full range
-1
–
+1
LSB
ADC conversion is
monotonic over full range.
0x7F to 0x80 transition specs
are excluded here.
Notes
12. SAR converters require a stable input voltage during the sampling period. If the voltage into the SAR8 changes by more than 1 LSB during the sampling period then
the accuracy specifications may not be met
Document Number: 001-44369 Rev. *B
Page 24 of 37
[+] Feedback
CY8C23433, CY8C23533
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 24. 5V and 3.3V AC Chip-Level Specifications
Min
Typ
Max
FIMO24
Symbol
Internal Main Oscillator Frequency for 24
MHz
23.4
24
24.6[13],[14],[15]
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35[13],[14],[15] MHz Trimmed for 5V or 3.3V
operation using factory trim
values. See Figure 8 on page 14.
SLIMO mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.093
24
24.6[13],[14]
MHz
12
[13],[14]
MHz
FCPU2
Description
CPU Frequency (3.3V Nominal)
0.093
12.3
[13],[14],[16]
Units
Notes
MHz Trimmed for 5V or 3.3V
operation using factory trim
values. See Figure 8 on page 14.
SLIMO mode = 0.
F48M
Digital PSoC Block Frequency
0
48
F24M
Digital PSoC Block Frequency
0
24
24.6[14],[16]
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
75
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
FPLL
PLL Frequency
–
23.986
–
MHz Is a multiple (x732) of crystal
frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
0.5
–
50
ms
TPLLSLEWSLOW PLL Lock Time for Low Gain Setting
49.2
MHz Refer to the AC Digital Block
Specifications.
TOS
External Crystal Oscillator Startup to 1%
–
1700
2620
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
2800
3800
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2[13],[15]
Jitter24M1R
24 MHz Period Jitter (IMO) Root Mean
Squared
–
–
600
ps
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
The crystal oscillator frequency
is within 100 ppm of its final value
by the end of the Tosacc period.
Correct operation assumes a
properly loaded 1 uW maximum
drive level 32.768 kHz crystal.
3.0V ≤ Vdd ≤ 5.5V, -40 °C ≤ TA ≤
85°C.
ns
MHz Trimmed. Using factory trim
values.
Notes
13. 4.75V < Vdd < 5.25V.
14. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
15. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
16. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-44369 Rev. *B
Page 25 of 37
[+] Feedback
CY8C23433, CY8C23533
Figure 9. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 10. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 11. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
Document Number: 001-44369 Rev. *B
Page 26 of 37
[+] Feedback
CY8C23433, CY8C23533
AC General Purpose IO Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 25. 5V and 3.3V AC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FGPIO
GPIO Operating Frequency
0
–
12.3
MHz
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
Normal Strong Mode
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
Figure 14. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 26. 5V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
TROA
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
TSOA
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
SRROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
SRFOA
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
BWOA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Document Number: 001-44369 Rev. *B
Page 27 of 37
[+] Feedback
CY8C23433, CY8C23533
Table 27. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Document Number: 001-44369 Rev. *B
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
–
MHz
MHz
Page 28 of 37
[+] Feedback
CY8C23433, CY8C23533
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 15. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 16. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-44369 Rev. *B
0.01
0.1
Freq (kHz)
1
10
100
Page 29 of 37
[+] Feedback
CY8C23433, CY8C23533
AC Low Power Comparator Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC
AC Digital Block Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29. 5V and 3.3V AC Digital Block Specifications
Symbol
Min
Typ
Max
Units
50[17]
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
50[17]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[17]
–
–
ns
Disable Mode
50[17]
–
–
ns
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Width of SS_ Negated Between
Transmissions
50[17]
–
–
ns
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
49.2
MHz
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
49.2
MHz
Timer
Counter
Description
Capture Pulse Width
Enable Pulse Width
Notes
4.75V < Vdd < 5.25V
4.75V < Vdd < 5.25V
Dead Band Kill Pulse Width:
Transmitter Maximum Input Clock Frequency
Receiver
Maximum data rate at 4.1 MHz due
to 2 x over clocking.
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Maximum data rate at 6.15 MHz due
to 8 x over clocking.
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Maximum data rate at 6.15 MHz due
to 8 x over clocking.
Note
17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-44369 Rev. *B
Page 30 of 37
[+] Feedback
CY8C23433, CY8C23533
AC Analog Output Buffer Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 30. 5V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.5
2.5
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.2
2.2
μs
μs
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
BWOB
Small Signal Bandwidth, 20mVpp, 3 dB BW, 100 pF Load
Power = Low
Power = High
0.8
0.8
–
–
–
–
MHz
MHz
BWOB
Large Signal Bandwidth, 1Vpp, 3 dB BW, 100 pF Load
Power = Low
Power = High
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
Table 31. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
3.8
3.8
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.6
2.6
μs
μs
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
BWOB
Small Signal Bandwidth, 20mVpp, 3 dB BW, 100 pF Load
Power = Low
Power = High
0.7
0.7
–
–
–
–
MHz
MHz
BWOB
Large Signal Bandwidth, 1Vpp, 3 dB BW, 100 pF Load
Power = Low
Power = High
200
200
–
–
–
–
kHz
kHz
Document Number: 001-44369 Rev. *B
Page 31 of 37
[+] Feedback
CY8C23433, CY8C23533
AC External Clock Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Table 33. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
0.093
–
12.3
MHz
Frequency with CPU Clock divide by 2 or greater[19]
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
FOSCEXT
Frequency with CPU Clock divide by
FOSCEXT
1[18]
AC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 34. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
20
–
ms
TWRITE
Flash Block Write Time
–
20
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
SAR8 ADC AC Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 35. SAR8 ADC AC Specifications[20]
Symbol
Description
Min
Typ
Max
Units
Freq3
Input clock frequency 3V
–
–
3.075
MHz
Freq5
Input clock frequency 5V
–
–
3.075
MHz
Notes
18. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
19. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
20. The max sample rate in this R2R ADC is 3.0/8=375KSPS
Document Number: 001-44369 Rev. *B
Page 32 of 37
[+] Feedback
CY8C23433, CY8C23533
AC I2C Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C
and are for design guidance only.
Table 36. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Symbol
Standard Mode
Description
Min
Max
Fast Mode
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
0.6
–
μs
0
–
μs
–
ns
–
μs
THDDATI2C Data Hold Time
0
–
250
–
TSUSTOI2C Setup Time for STOP Condition
4.0
–
0.6
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
TSUDATI2C
Data Setup Time
100
[21]
Table 37. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Symbol
Standard Mode
Description
Fast Mode
Units
Min
Max
Min
Max
0
100
–
–
kHz
4.0
–
–
–
μs
FSCLI2C
SCL Clock Frequency
THDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
4.7
–
–
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
–
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
–
–
μs
0
–
–
–
μs
THDDATI2C Data Hold Time
TSUDATI2C
250
–
–
–
ns
TSUSTOI2C Setup Time for STOP Condition
Data Setup Time
4.0
–
–
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
–
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
–
–
ns
Figure 17. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
21. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
Figure 18.
I2C-bus specification) before the SCL line is released.
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode
Document Number: 001-44369 Rev. *B
Page 33 of 37
[+] Feedback
CY8C23433, CY8C23533
Packaging Information
This section illustrates the packaging specifications for the CY8C23x33 PSoC device, along with the thermal impedances for each
package, solder reflow peak temperature, and the typical package capacitance on crystal pins.
Figure 19. 32-Pin (5x5 mm) QFN
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED PAD
CYPRESS
COMPANY CONFIDENTIAL
2. BASED ON REF JEDEC # MO-248
3. PACKAGE WEIGHT: 0.0388g
4. DIMENSIONS ARE IN MILLIMETERS
Document Number: 001-44369 Rev. *B
TITLE
32L QFN 5 X 5 X 0.55 MM PACKAGE OUTLINE 3.5 X 3.5 EPAD
(SAWN TYPE)
SIZE
PART NO.
A
LQ32
001-42168 *C
DWG NO
001-42168
REV
*C
Page 34 of 37
[+] Feedback
CY8C23433, CY8C23533
Figure 20. 28-Pin (210-Mil) SSOP
51-85079 *C
Thermal Impedances
Capacitance on Crystal Pins
Table 38. Thermal Impedances by Package
Table 39. Typical Package Capacitance on Crystal Pins
Typical θJA[22]
Package
32 QFN
28 SSOP
Package
Package Capacitance
19.4°C/W
32 QFN
2.0 pF
95°C/W
28 SSOP
2.8 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 40. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature [23] Maximum Peak Temperature
32 QFN
240°C
260°C
28 SSOP
240°C
260°C
Notes
22. TJ = TA + POWER x θJA.
23. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-44369 Rev. *B
Page 35 of 37
[+] Feedback
CY8C23433, CY8C23533
Ordering Information
The following table lists the CY8C23X33 PSoC device family key package features and ordering codes.
Document Number: 001-44369 Rev. *B
Digital IO Pins
Analog Inputs
Analog Outputs
XRES Pin
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Analog Blocks
(Columns of 3)
256
256
256
256
Temperature
Range
8
8
8
8
Digital Blocks
(Rows of 4)
CY8C23533-24LQXI
CY8C23533-24LQXIT
CY8C23433-24PVXI
CY8C23433-24PVXIT
RAM
(Bytes)
32 Pin QFN
32 Pin QFN (Tape and Reel)
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
Flash
(Kbytes)
Package
Ordering
Code
Table 41. CY8C23X33 PSoC Device Family Key Features and Ordering Information
4
4
4
4
4
4
4
4
26
26
26
26
12
12
12
12
2
2
2
2
Yes
Yes
No
No
Page 36 of 37
[+] Feedback
CY8C23433, CY8C23533
Document History Page
Document Title: CY8C23433, CY8C23533 PSoC® Programmable System-on-Chip™
Document Number: 001-44369
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2044848
KIY/AESA
01/30/2008
Data sheet creation
*A
2482967
HMI/AESA
05/14/2008
Moved from Preliminary to Final. Part number changed to CY8C23433,
CY8C23533. Adjusted placement of the block diagram; updated description
of DAC; updated package pinout description, updated POR and LVD spec,
Added Csc , Flash Vdd, SAR ADC spec. Updated package diagram
001-42168 to *A. Updated data sheet template.
*B
2616862 OGNE/AESA
12/05/2008
Changed title to: “CY8C23433, CY8C23533 PSoC® Programmable
System-on-Chip™”
Updated package diagram 001-42168 to *C.
Changed names of registers on page 11.
"SARADC_C0" to "SARADC_CR0"
"SARADC_C1" to "SARADC_CR1"
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC Solutions
PSoC
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-44369 Rev. *B
Revised December 05, 2008
Page 37 of 37
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
[+] Feedback