MAX707, MAX708 mP Supervisory Circuits The MAX707/708 are cost−effective system supervisor circuits designed to monitor VCC in digital systems and provide a reset signal to the host processor when necessary. No external components are required. The reset output is driven active within 20 msec of VCC falling through the reset voltage threshold. Reset is maintained with 200 mS of delay time after VCC rise above the reset threshold. The MAX707/708 have a low quiescent current of 12 mA at VCC = 3.3 V, an active−high RESET and active−low RESET with a push−pull output. The output is guaranteed valid down to VCC = 1.0 V. The MAX707/708 have a Manual Reset MR input and a +1.25 V threshold detector for power−fail input PFI. These devices are available in a Micro8 and SOIC−8 package. Features • Precision Supply−Voltage Monitor • • • • • • • • MAX707: 4.63 V Reset Threshold Voltage MAX708: Standard Reset Threshold Voltages (Typical): 4.38 V, 3.08 V, 2.93 V, 2.63 V Reset Threshold Available from 1.6 V to 4.9 V with 100 mV Increments (Factory Option) 200 mS (Typ) Reset Timeout Delay 12 mA (VCC = 3.3 V) Quiescent Current Active_High and Active_Low Reset Output Guaranteed RESET_L and RESET Output Valid to VCC = 1.0 V Voltage Monitor for Power−Fail or Low−Battery Warning 8 Pin SOIC or Micro8 Package Pb−Free Packages are Available http://onsemi.com MARKING DIAGRAMS 8 1 xxx A Y W G 1 = Specific Device Code = Assembly Location = Year = Week = Pb−Free Package 8 xxxxx ALYWG G SOIC−8 ESA SUFFIX CASE 751 8 1 1 xxxxx = Specific Device Code AL = Assembly Lot Code Y = Year W = Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONFIGURATION Micro8 Applications • • • • xxx AYW G Micro8t CUA SUFFIX CASE 846A 8 Computers Embedded System Battery Powered Equipment Critical mP Power Supply Monitor RESET 1 8 NC RESET 2 7 PFO MR 3 6 PFI VCC 4 5 GND (Top View) SOIC−8 MR 1 8 RESET VCC 2 7 RESET GND 3 6 NC PFI 4 5 PFO (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 4 1 Publication Order Number: MAX707/D MAX707, MAX708 VCC RESET MR RESET GENERATOR VCC RESET + − VTH PFI + − PFO 1.25 V GND Figure 1. Representative Block Diagram MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Supply Voltage VCC 6.0 V Output Voltage Vout −0.3 to (VCC + 0.3) V Output Current (All Outputs) Iout 20 mA Input Current (VCC and GND) Iin 20 mA Thermal Resistance Junction−to−Air °C/W RqJA Micro8 SOIC−8 248 187 Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Range Tstg −40 to +125 °C LatchUp Performance ILATCHUP Positive Negative mA 300 280 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL−STD−883, Method 3015. Machine Model Method 200 V. 2. The maximum package power dissipation limit must not be exceeded. TJ(max) * TA with TJ(max) = 150°C PD + RqJA http://onsemi.com 2 MAX707, MAX708 ELECTRICAL CHARACTERISTICS (VCC = 1.0 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C, VCC = 3.3 V.) Characteristics Symbol Min Typ Max Unit Operating Voltage Range VCC 1.0 − 5.5 V Supply Current VCC = 3.3 V VCC = 5.5 V ICC − − 12 16 22 28 Reset Threshold MAX707 TA = +25°C TA = −40°C to +85°C MAX708 TA = +25°C TA = −40°C to +85°C MAX708T TA = +25°C TA = −40°C to +85°C MAX708S TA = +25°C TA = −40°C to +85°C MAX708R TA = +25°C TA = −40°C to +85°C VTH Reset Threshold Hysteresis VHYS mA V 4.56 4.50 4.63 4.70 4.75 4.31 4.25 4.38 4.45 4.50 3.03 3.00 3.08 3.13 3.15 2.89 2.85 2.93 2.97 3.00 2.59 2.55 2.63 2.67 2.70 − 0.01 VTH − mV VCC Falling Reset Delay (VCC = VTH + 0.2 V to VTH − 0.2 V) tPD − 20 − mS Reset Active Timeout Period tRP 140 200 330 mS RESET_L, RESET_H Output Low Voltage VCC w 1.0 V, Iol = 100 mA VCC u 2.7 V, Iol = 1.2 mA VCC u 4.5 V, Iol = 3.2 mA Vol − − − − − − 0.3 0.3 0.3 RESET_L, RESET_H Output High Voltage VCC w 1.0 V, Ioh = 50 mA VCC u 2.7 V, Ioh = 500 mA VCC u 4.5 V, Ioh = 800 mA Voh 0.8 VCC 0.8 VCC 0.8 VCC − − − − − − RMRI 50 − − KW tMR 1.0 − − mS − − 0.1 − mS MR_L High_level Input Threshold (VTH (max) t VCC t 5.5 V) VIH 0.7 VCC − − V MR_L Low_level Input Threshold (VTH (max) t VCC t 5.5 V) VIL − − 0.3 VCC V MR_L to RESET_L and RESET_H Output Delay (VTH (max) t VCC t 5.5 V) tMD − 0.2 − mS PFI Input Threshold (VCC = 3.3 V, PFI Falling) − 1.20 1.25 1.3 V PFI Input Current − −250 0.01 250 nA PFI to PFO Delay (VCC = 3.3 V, VOVERDRIVE = 15 mV) − − 3.0 − mS − − − − 0.3 0.3 0.8 VCC 0.8 VCC − − − − MR_L Pull−up Resistance MR_L Pulse Width (VTH (max) t VCC t 5.5 V) MR_L Glitch Rejection (VTH (max) t VCC t 5.5 V) PFO_L Output Low Voltage VCC = 2.7 V, Iol = 1.2 mA VCC = 4.5 V, Iol = 3.2 mA Vol PFO_L Output High Voltage VCC = 2.7 V, Ioh = 500 mA VCC = 4.5 V, Ioh = 800 mA Voh http://onsemi.com 3 V V V V MAX707, MAX708 PIN DESCRIPTION (Pin No. with parentheses is for Micro8 package.) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Symbol 1 (3) MR Manual Reset Input. MR can be driven from TTL/CMOS logic or from a manual Reset switch. This input, when floating, is internally pulled up to VCC with 50 kW resistor. 2 (4) VCC Supply Voltage: C = 100 nF is recommended as a bypass capacitor between VCC and GND. 3 (5) GND Ground Reference 4 (6) PFI Power Fail Voltage Monitor Input. When PFI is less than 1.25 V, PFO goes low. Connect PFI to GND or VCC when not used. 5 (7) PFO Power Fail Monitor Output. When PFI is less than 1.25 V, it goes low and sinks current. Otherwise, it remains high. 6 (8) NC 7 (1) RESET Active Low RESET can be triggered by VCC below the threshold level or by a low signal on MR. It remains low for 200 ms (typ.) after VCC rises above the reset threshold. 8 (2) RESET Active high RESET output the inverse of RESET one. Description Non−connective Pin IOUT, OUTPUT SOURCE CURRENT (mA) IOUT, OUTPUT SINK CURRENT (mA) Pin No. 3.0 TA = 25°C Vin = 1.5 V 2.5 2.0 1.5 1.0 0.5 Vin = 1.0 V 0 0.5 1.0 1.5 Vout = Vin − 2.0 V 16 Vin − 1.5 V 14 12 10 8 Vin − 1.0 V 6 4 Vin − 0.5 V 2 0 0 1.0 2.0 3.0 4.0 5.0 Vout, OUTPUT VOLTAGE (V) Vin, INPUT VOLTAGE (V) Figure 2. MAX707/708 Series 1.60 V Reset Output Sink Current vs. Output Voltage Figure 3. MAX707/708 Series 1.60 V Reset Output Source Current vs. Input Voltage 12 TA = 25°C Vin = 2.5 V 10 8 Vin = 2.0 V 6 4 Vin = 1.5 V 2 0 0 TA = 25°C 18 2.0 Iout, OUTPUT SOURCE CURRENT (mA) IOUT, OUTPUT SINK CURRENT (mA) 0 20 0.5 1.0 1.5 2.0 2.5 3.0 20 18 TA = 25°C Vout = Vin − 2.0 V 16 Vin −1.5 V 14 12 10 8 Vin − 1.0 V 6 4 Vin − 0.5 V 2 0 0.0 1.0 2.0 3.0 4.0 5.0 Vout, OUTPUT VOLTAGE (V) Vin, INPUT VOLTAGE (V) Figure 4. MAX707/708 Series 2.93 V Reset Output Sink Current vs. Output Voltage Figure 5. MAX707/708 Series 2.93 V Reset Output Source Current vs. Input Voltage http://onsemi.com 4 6.0 6.0 MAX707, MAX708 Iout, OUTPUT SOURCE CURRENT (mA) Vin = 4.0 V TA = 25°C 25 20 Vin = 3.0 V 15 10 Vin = 2.0 V 5 VDET, DETECTOR THRESHOLD VOLTAGE (VOLTS) 0 0.0 1.0 2.0 3.0 4.0 5.0 18 12 Vin − 1.5 V 10 Vin − 1.0 V 8 6 4 Vin − 0.5 V 2 0 0.0 1.0 2.0 3.0 4.0 5.0 Figure 7. MAX707/708 Series 4.90 V Reset Output Source Current vs. Input Voltage VDET+ 1615 1610 1605 1600 VDET− 1595 1590 −25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (°C) 3110 3100 3090 3080 4980 4960 4940 4920 VDET− −25 0 25 50 75 VDET− 3070 3060 −50 TPD, VCC, FALLING RESET DELAY (ms) VDET+ 4900 VDET+ −25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (°C) Figure 10. MAX707/708 Series 2.93 V Detector Threshold Voltage vs. Temperature 5020 5000 6.0 3120 Figure 8. MAX707/708 Series 1.60 V Detector Threshold Voltage vs. Temperature VDET, DETECTOR THRESHOLD VOLTAGE (VOLTS) Vout = Vin − 2.0 V 14 Figure 6. MAX707/708 Series 4.90 V Reset Output Sink Current vs. Output Voltage 1620 4880 −50 TA = 25°C 16 Vin, INPUT VOLTAGE (V) 1625 1585 −50 20 Vout, OUTPUT VOLTAGE (V) VDET, DETECTOR THRESHOLD VOLTAGE (VOLTS) Iout, OUTPUT SINK CURRENT (mA) 30 100 45 40 VTH = 4.90 V 35 30 VTH = 2.93 V 25 20 VTH = 1.60 V 15 10 5 0 −40 −20 0 20 40 60 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 9. MAX707/708 Series 4.90 V Detector Threshold Voltage vs. Temperature Figure 11. MAX707/708 Series VCC Falling Reset Delay vs. Temperature http://onsemi.com 5 80 MAX707, MAX708 APPLICATIONS INFORMATION one of these. It is effectively debounced by the 1.0 ms minimum reset pulse width. As MR is TTL/CMOS logic compatible, it can be driven by an external logic line. Microprocessor Reset To generate a processor reset, the manual Reset input allows different reset sources. A pushbutton switch can be VCC VTH VTH tRP RESET tRP MR tMD tMR Figure 12. RESET and MR Timing VCC Transient Rejection (overdrive) for glitch rejection. For a given overdrive, the point of the curve is the maximum width of the glitch allowed before the device generates a reset signal. Transient immunity can be improved by adding a capacitor (100 nF for example) in close proximity to the VCC pin of the MAX707/708. MAXIMUM TRANSIENT DURATION (ms) The MAX707/708 provides accurate VCC monitoring and reset timing during power−up, power−down, and brownout/sag conditions, and rejects negative glitches on the power supply line. Figure 13 shows the maximum transient duration vs. maximum negative excursion 300 250 VCC 200 VTH VTH = 4.90 V 150 Overdrive VTH = 3.08 V 100 VTH = 1.60 V 50 0 10 Duration 30 50 70 90 110 130 150 RESET COMPARATOR OVERDRIVE (mV) Figure 13. Maximum Transient Duration vs. Overdrive for Glitch Rejection at 255C http://onsemi.com 6 MAX707, MAX708 components are required to follow the reset I/O of the mP, the buffer should be connected as shown with the solid line. RESET Signal Integrity During Power−Down The MAX707/708 RESET output is valid until VCC falls below 1.0 V. Then, the output becomes an open circuit and no longer sinks current. This means CMOS logic inputs of the mP will be floating at an undetermined voltage. Most digital systems are completely shutdown well above this voltage. However, in the case RESET must be maintained valid to VCC = 0 V, a pull down resistor must be connected from RESET to ground to discharge stray capacitances and hold the output low (Figure 14). This resistor value, though not critical, should be chosen large enough not to load RESET and small enough to pull it to ground. R = 100 kW will be suitable for most applications. BUFFERED RESET TO OTHER SYSTEM COMPONENTS BUFFER VCC VCC mP MAX707/708 4.7 k RESET RESET GND GND VCC MAX707/708 Figure 15. Interfacing to Bidirectional Reset I/O RESET GND R Monitoring Additional Supply Levels 100 k When connecting a voltage divider to PFI and adjusting it properly, you can monitor a voltage different than the unregulated DC one. As shown in Figure 16, to increase noise immunity, hysteresis may be added to the power−fail comparator just by a resistor between PFO and PFI. Not to unbalance the potential divider network, R3 should be 10 times the sum of the two resistors R1 and R2. If required, a capacitor between PFI and GND will reduce the sensitivity of the circuit to high−frequency noise on the line being monitored. The PFO output may be connected to MR input to generate a low level on the RESET when VCC_1 drops out of tolerance. Thus a RESET is generated when one of the two voltages is below its threshold level. Figure 14. Ensuring RESET Valid to VCC = 0 V Interfacing with mPs with Bidirectional I/O Pins Some mPs have bidirectional reset pins. If, for example, the RESET output is driven high and the mP wants to put it low, indeterminate logic level may result. This can be avoided by adding a 4.7 kW resistor in series with the output of the MAX707/708 (Figure 15). If there are other components in the system that require a reset signal, they should be buffered so as not to load the reset line. If the other VCC_1 VCC_2 VCC_3 VCC VCC R1 RESET MAX707/708 VCC_2 PFO RESET mP 0V 0V MR PFI VH VCC_1 PFO GND VL GND R2 VL + 1.25 ) R1 R3 VH + 1.25 1.25 * Vcc_2 ǒ1.25 Ǔ ) R3 R2 (1 ) R1 VHYS + VH * VL + Figure 16. Monitoring Additional Supply Levels http://onsemi.com 7 R1 ) R3Ǔ ) ǒR2 R2 R3 Vcc_2 R3 MAX707, MAX708 ORDERING INFORMATION Marking Reset VCC Threshold (V) Package Shipping † MAX707ESA−T S707 4.63 SOIC−8 2500 Tape & Reel MAX707ESA−TG S707 4.63 SOIC−8 (Pb−Free) 2500 Tape & Reel MAX708ESA−T S708 4.38 SOIC−8 2500 Tape & Reel MAX708ESA−TG S708 4.38 SOIC−8 (Pb−Free) 2500 Tape & Reel MAX708RESA−T S708R 2.63 SOIC−8 2500 Tape & Reel MAX708RESA−TG S708R 2.63 SOIC−8 (Pb−Free) 2500 Tape & Reel MAX708SESA−T S708S 2.93 SOIC−8 2500 Tape & Reel MAX708SESA−TG S708S 2.93 SOIC−8 (Pb−Free) 2500 Tape & Reel MAX708TESA−T S708T 3.08 SOIC−8 2500 Tape & Reel MAX708TESA−TG S708T 3.08 SOIC−8 (Pb−Free) 2500 Tape & Reel MAX707CUA−T SAC 4.63 Micro8 4000 Tape & Reel MAX707CUA−TG SAC 4.63 Micro8 (Pb−Free) 4000 Tape & Reel MAX708CUA−T SAD 4.38 Micro8 4000 Tape & Reel MAX708CUA−TG SAD 4.38 Micro8 (Pb−Free) 4000 Tape & Reel MAX708RCUA−T SAG 2.63 Micro8 4000 Tape & Reel MAX708RCUA−TG SAG 2.63 Micro8 (Pb−Free) 4000 Tape & Reel MAX708SCUA−T SAF 2.93 Micro8 4000 Tape & Reel MAX708SCUA−TG SAF 2.93 Micro8 (Pb−Free) 4000 Tape & Reel MAX708TCUA−T SAE 3.08 Micro8 4000 Tape & Reel MAX708TCUA−TG SAE 3.08 Micro8 (Pb−Free) 4000 Tape & Reel Device †For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 MAX707, MAX708 PACKAGE DIMENSIONS Micro8 CASE 846A−02 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A−01 OBSOLETE, NEW STANDARD 846A−02. −A− −B− K PIN 1 ID G D 8 PL 0.08 (0.003) M T B S A DIM A B C D G H J K L S SEATING −T− PLANE 0.038 (0.0015) C L J H SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 3.20 0.126 6X 8X 4.24 0.167 0.65 0.0256 5.28 0.208 SCALE 8:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 −−− 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 −−− 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 MAX707, MAX708 PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AG NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 10 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MAX707/D