TI1 ADC12QS065 Quad 12-bit 65 msps a/d converter with lvds serialized output Datasheet

ADC12QS065
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SNOSAD6H – JULY 2005 – REVISED MARCH 2007
ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with
LVDS Serialized Outputs
Check for Samples: ADC12QS065
FEATURES
DESCRIPTION
•
•
The ADC12QS065 is a low power, high performance
CMOS 4-channel analog-to-digital converter with
LVDS serialized outputs. The ADC12QS065 digitizes
signals to 12 bits resolution at sampling rates up to
65 MSPS while consuming a typical 200 mW/ADC
from a single 3.3V supply. Sampled data is
transformed into high speed serial LVDS output data
streams. Clock and frame LVDS pairs aid in data
capture. The ADC12QS065’s six differential pairs
transmit data over backplanes or cable and also
make PCB design easier. In addition, the reduced
cable, PCB trace count, and connector size
tremendously reduce cost.
1
2
•
•
•
•
•
Single +3.3V Supply Operation
Internal Sample-and-Hold and Internal
Reference
Low Power Consumption
Power Down Mode
Clock and Data Frame Timing
780 Mbps Serial LVDS Data Rate (at 65 MHz
Clock)
LVDS Serial Output Rated for 100 Ohm Load
APPLICATIONS
•
•
•
•
•
Ultrasound
Medical Imaging
Communications
Portable Instrumentation
Digital Video
KEY SPECIFICATIONS
•
•
•
•
•
•
Resolution: 12 Bits
DNL: ±0.3 LSB (Typ)
SNR (fIN = 5 MHz): 69 dB (Typ)
SFDR (fIN = 5 MHz): 83 dB (Typ)
ENOB (at Nyquist): 11 Bits (Typ)
Power Consumption
– Operating, 65 MSPS, per ADC: 200 mW
(Typ)
– Power Down Mode: < 3 mW (Typ)
No missing codes performance is guaranteed over
the full operating temperature range. The pipeline
ADC architecture achieves 11 Effective Bits over the
entire Nyquist band at 65 MSPS.
When not converting, power consumption can be
reduced by pulling the PD (Power Down) pin high,
placing the converter into a low power state where it
typically consumes less than 3 mW total, and from
which recovery is less than 5 ms. The
ADC12QS065's speed, resolution and single supply
operation makes it well suited for a variety of
applications in ultrasound, imaging, video and
communications. Operating over the industrial (-40°C
to +85°C) temperature range, the ADC12QS065 is
available in a 60-pin WQFN package with exposed
pad (9x9x0.8mm, 0.5mm pin pitch).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
ADC12QS065
SNOSAD6H – JULY 2005 – REVISED MARCH 2007
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AGND
CLK
AGND
CLKB
48
47
46
DRGND
DGND
VDR
29
30
VDR
VREG
DRGND
DGND
PD
REFPD
VD
VCOM34
VREF
AGND
VA
16
VA
* Exposed pad must be soldered to ground
plane to ensure rated performance.
VREFT34
VIN4VIN4+
AGND
VREFB34
VIN3+
VIN3AGND
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
ADC12QS065
18
19
20
21
22
23
24
25
26
27
28
VIN2VIN2+
AGND
AGND
VA
VIN1+
VIN1AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
VA
AGND
51
50
49
VREFB12
VREFT12
VCOM12
INTREF
VD
60
59
58
57
56
55
54
53
52
AGND
VA
VA
Connection Diagram
DRGND
DO1DO1+
DO2DO2+
DRGND
FRAMEFRAME+
OUTCLKOUTCLK+
DRGND
DO3DO3+
DO4DO4+
Figure 1. 60-Lead WQFN
See NKA0060A Package
2
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Block Diagram
VIN1+
DO1+
12
ADC - Channel 1
Serializer
DO1-
VIN1-
VREFT12
VCOM12
VREFB12
VIN2+
DO2+
12
ADC - Channel 2
Serializer
VIN2-
DO2-
CLK
PLL
CLKB
FRAME+
Reference Select and Internal
Reference
VREF
FRAME-
Framing &
Serial Clock
Generator
OUTCLK+
OUTCLK-
VIN3+
DO3+
12
ADC - Channel 3
Serializer
DO3-
VIN3-
VREFT34
VCOM34
VREFB34
VIN4+
DO4+
12
ADC - Channel 4
Serializer
VIN4-
DO4-
ADC Channel Detail
VIN+
S/H
VIN-
2.5 bit
Converter
3
2.5 bit
Converter
2.5 bit
Converter
16
Digital Error Correction and Decode
2
12
To Serializer
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PIN DESCRIPTIONS
Pin No.
Symbol
Description
ANALOG I/O
3
7
9
13
VIN1+
VIN2+
VIN3+
VIN4+
4
6
10
12
VIN1VIN2VIN3VIN4-
Differential analog input pins. With a 1.0V reference voltage the differential full-scale
input signal level is 2.0 VP-P with each input pin voltage centered on a common mode
voltage, VCOM. The negative input pins may be connected to VCOM for single-ended
operation, but a differential input signal is required for best performance.
23
VREF
This pin is the reference select pin and the external reference input, used in conjunction
with the INTREF pin.
If the INTREF pin is set to VA , this pin is used as an internal reference select. With VREF
= VA, the internal 1.0V reference is selected. With VREF=AGND, the internal 0.5V
reference is selected.
If the INTREF pin is set to AGND, then this pin is the input for an external reference. A
voltage in the range of 0.8 to 1V may be applied to this pin. VREF should be bypassed to
AGND with a 1.0 µF capacitor when an external reference is used.
56
21
VREFT12
VREFT34
Top ADC Reference. This pin has to be driven to 1.9V if REFPD is high.
If REFPD is low, bypass this pin with a 0.1 µF low ESR capacitor to AGND and a 10 µF
low ESR capacitor to VREFB. These pins should not be loaded.
55
22
VCOM12
VCOM34
This is an analog output which can be used as a common mode voltage for the inputs. It
should be bypassed to AGND with a minimum of a 1.0 µF low ESR capacitor in parallel
with a 0.1 µF capacitor. These pins may also be used as a 1.5V temperature stable
reference voltage with a maximum load of 1mA.
57
20
VREFB12
VREFB34
Bottom ADC Reference. This pin has to be driven to 0.9V if REFPD is high.
If REFPD is low, bypass this pin with a 0.1 µF low ESR capacitor to AGND and a 10 µF
low ESR capacitor to VREFT. These pins should not be loaded.
29
VREG
This is the bypass pin for the internal 1.8V regulator. This pin should be bypassed to
AGND with a 1.0 µF capacitor
DIGITAL I/O
4
This pin acts as either a Non-Inverting Differential Clock input or a CMOS clock input. If
CLKB is used as the Inverting Clock input, CLK will act as the Non-Inverting Clock input.
If CLKB is tied to AGND, CLK will act as a CMOS clock input. ADC power consumption
will increase by about 40mW if a Differential Clock is used.
47
CLK
48
CLKB
54
INTREF
24
PD
25
REFPD
43
41
33
31
DO1+
DO2+
DO3+
DO4+
+ Serial Data Output. Non-inverting LVDS differential output.
44
42
34
32
DO1DO2DO3DO4-
- Serial Data Output. Inverting LVDS differential output.
38
39
FRAME+
FRAME-
LVDS output, it’s rising edge corresponds to the first serial bit of the output streams.
FRAME clock frequency is the same as the CLK frequency.
36
37
OUTCLK+
OUTCLK-
LVDS output clock. The data is valid on an output transition. Successive data bits are
captured on both edges of this clock. OUTCLK frequency is 6X the CLK frequency.
Inverting Differential Clock input. If tied to AGND, CLK acts as a CMOS clock input.
Internal reference enable input. When this pin is high, two internal reference choices are
selectable through the VREF pin. When this pin is low, an external reference must be
applied to VREF (pin 23).
Power Down pin that, when high, puts the converter into the Power Down mode.
With REFPD high, user must drive VREFT12, VREFT34 and VREFB12 & VREFB34
externally. With REFPD low, VREFT12, VREFT34 and VREFB12 & VREFB34 are driven
internally.
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PIN DESCRIPTIONS (continued)
Pin No.
Symbol
Description
ANALOG POWER
1,15,17,19,
58,59
VA
2,5,8,11,
14,16,18,
46,49,60
AGND
Positive analog supply pins. These pins should be connected to a quiet +3.3V source
and bypassed to AGND with 0.1 µF capacitors located near these power pins, and with
a 10 µF capacitor.
The ground return for the analog supply.
NOTE: The exposed pad on the WQFN package must be soldered to AGND.
DIGITAL POWER
26,53
VD
27, 52
DGND
28, 51
VDR
30,35,40, 45,50
DRGND
Positive digital supply pin. This pin should be connected to the same quiet +3.3V source
as is VA and be bypassed to DGND with a 0.1 µF capacitor located near the power pin
and with a 10 µF capacitor.
The ground return for the digital supply.
Positive driver supply pin for the ADC12QS065's output drivers. This pin should be
connected to a voltage source of +2.5V to VD and be bypassed to DR GND with a 0.1
µF capacitor. If the supply for this pin is different from the supply used for VA and VD, it
should also be bypassed with a 10 µF capacitor. VDR should never exceed the voltage
on VD. All bypass capacitors should be located near the supply pin.
The ground return for the ADC12QS065's output drivers.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3) (4)
VA, VD, VDR
3.8V
≤ 100 mV
|VA–VD|
−0.3V to (VA or VD +0.3V)
Voltage on any pin (excludes pins 29 to 45)
Voltage on any pin (pins 29 to 45)
-0.3V to 2V
Input Current at Any Pin (5)
±25 mA
Package Input Current (5)
±50 mA
See (6)
Package Dissipation at TA = 25°C
ESD Susceptibility
Soldering Temperature
Human Body Model
(7)
(3)
(4)
(5)
(6)
(7)
(8)
250V
Infrared (10 sec.) (8)
235°C
−65°C to +150°C
Storage Temperature
(1)
(2)
2500V
Machine Model (7)
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
Soldering process must comply with Texas Instruments' Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula
PDMAX = (TJmax - TA )/θJA. In the 60-pin WQFN, θJA is 20°C/W with the exposed pad soldered to a ground plane, so PDMAX = 2 W at
the maximum operating ambient temperature of 85°C. Note that the power consumption of this device under normal operation will
typically be about 900 mW. The values for maximum power dissipation listed above will be reached only when the device is operated in
a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Reflow Reflow temperature profiles are different for lead-free and non-lead-free packages.
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Operating Ratings (1) (2)
Operating Temperature
−40°C ≤ TA ≤ +85°C
Supply Voltage (VA, VD)
+3.0V to +3.6V
Output Driver Supply (VDR)
+2.4V to VD
VIN Differential Input Range
±VREF
VCM Input Common Mode Range (Differential Input)
VREF/2 to (VA - VREF/2 )
External VREF Voltage Range
0.8V to 1V
−0.3V to (VA + 0.3V)
Digital Input Pins Voltage Range (excludes pins 31 to 50)
≤100mV
|AGND–DGND|
Clock Duty Cycle
(1)
(2)
30% to 70%
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 5 KHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all
other limits TJ = 25°C (1) (2) (3) (4)
Symbol
Parameter
Conditions
Typical (5)
Limits (5)
Units
(Limits)
12
Bits (min)
LSB (max)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non Linearity
±0.7
±1.4
DNL
Differential Non Linearity
±0.3
±0.7
LSB (max)
PGE
Positive Gain Error
±1.5
±3.5
%FS (max)
NGE
Negative Gain Error
±1.1
±3.5
%FS (max)
TC GE
Gain Error Tempco
VOFF
Offset Error (VIN+ = VIN−)
±0.75
%FS (max)
TC VOFF
Offset Error Tempco
(1)
−40°C ≤ TA ≤ +85°C
7.5
±0.06
−40°C ≤ TA ≤ +85°C
ppm/°C
4.4
ppm/°C
Under Range Output Code
0
0
Over Range Output Code
4095
4095
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV.
As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
(5)
6
To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
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Converter Electrical Characteristics (continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 5 KHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all
other limits TJ = 25°C(1)(2)(3)(4)
Symbol
Parameter
Typical (5)
Conditions
Limits (5)
Units
(Limits)
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCM
Common Mode Input Voltage
VIN
Analog Differential Input Range
CIN
1.5
VIN Input Capacitance (each pin to GND)
VREF
VIN = 2.5 Vdc + 0.7 Vrms
(CLK LOW)
8
(CLK HIGH)
3
External Reference Voltage (6)
1.00
Reference Input Resistance
0.5
V (min)
2.0
V (max)
2.0
VP-P
pF
pF
0.8
V (min)
1
V (max)
1
MΩ (min)
0 dBFS Input, Output at −3 dB
300
MHz
fIN = 5 MHz, VIN = −1 dBFS
69.3
fIN = 33 MHz, VIN = −1 dBFS
68.5
fIN = 5 MHz, VIN = −1 dBFS
69
fIN = 33 MHz, VIN = −1 dBFS
68
fIN = 5 MHz, VIN = −1 dBFS
11.2
fIN = 33 MHz, VIN = −1 dBFS
11
fIN = 5 MHz, VIN = −1 dBFS
−82
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
SNR
Signal-to-Noise Ratio (7)
SINAD
Signal-to-Noise and Distortion (7)
ENOB
Effective Number of Bits (7)
THD
Total Harmonic Distortion
H2
Second Harmonic Distortion
H3
Third Harmonic Distortion
SFDR
Spurious Free Dynamic Range
IMD
Intermodulation Distortion
FPBW
Full Power Bandwidth
68.4
dBFS (min)
68
dBFS (min)
dBFS
dBFS
11
Bits (min)
-74.5
dBc (min)
Bits
fIN = 33 MHz, VIN = −1 dBFS
−78
fIN = 5 MHz, VIN = −1 dBFS
−92.5
fIN = 33 MHz, VIN = −1 dBFS
−83
fIN = 5 MHz, VIN = −1 dBFS
−83.3
fIN = 33 MHz, VIN = −1 dBFS
−80
fIN = 5 MHz, VIN = −1 dBFS
83.3
fIN = 33 MHz, VIN = −1 dBFS
80
dBc
fIN = 19.6 MHz and 20.2 MHz,
each = −7 dBFS
−78
dBFS
dBc
-79
dBc
dBc
-75.5
dBc
dBc
75.5
300
dBc
MHz
INTER-CHANNEL CHARACTERISTICS
Channel—Channel Offset Match
±0.3
%FS
Channel—Channel Gain Match
±4
%FS
85
dBc
Crosstalk (between any two channels)
(6)
(7)
10 MHz Tested, Channel;
20 MHz Other Channel
Optimum performance will be obtained by keeping the reference input in the 0.8V to 1V range. The LM4051CIM3-ADJ (SOT-23
package) is recommended for external reference applications.
This parameter is specified in dBFS - indicating the value that would be attained with a full-scale input signal.
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DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 5 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all
other limits TJ = 25°C (1) (2) (3) (4)
Symbol
Parameter
Conditions
Typical (5)
Limits (5)
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
0.5
V (max)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
1
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−1
µA
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
PD Pin = DGND
PD Pin = VD
168
0.5
200
mA (max)
mA
ID
Digital Supply Current
PD Pin = DGND
PD Pin = VD
48
0.2
53
mA (max)
mA
IDR
LVDS Output Supply Current
PD Pin = DGND, fIN = 33 MHz
46
62
mA (max)
PWR
Total Power Consumption
(includes driver supply)
PD Pin = DGND, CL = 5 pF
PD Pin = VD
828
3
990
mW (max)
mW
Power Supply Rejection Ratio
Rejection of Full-Scale Error with
VA = 3.0V vs. 3.6V
53
PSRR
(1)
dB
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV.
As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
(5)
8
To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
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AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 5 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all
other limits TJ = 25°C (1) (2) (3) (4)
Symbol
Parameter
fCLK1
Maximum Clock Frequency
fCLK
Minimum Clock Frequency
2
Conditions
Typical (5)
Limits (5)
Units
(Limits)
65
MHz (min)
30
70
% min
% max
9
Clock Cycles
20
Clock Duty Cycle
50
Input Sample(N) to LSB of Sample(N)
Data valid
MHz
tCONV
Conversion Latency
tAD
Aperture Delay
2
ns
tAJ
Aperture Jitter
1
ps rms
tPD
Power Down Mode Exit Cycle
<5
ms
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV.
As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
(5)
To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
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LVDS Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 5 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all
other limits TJ = 25°C (1) (2) (3) (4)
Symbol
Parameter
Conditions
Typical (5)
Limits (5)
Units
(Limits)
LVDS DC CHARACTERISTICS
VOD
Output Differential Voltage
(DO+) - (DO-)
RL = 100Ω
290
230
450
mV (min)
mV (max)
delta
VOD
Output Differential Voltage Unbalance
RL = 100Ω
±1
±15
mV (max)
VOS
Offset Voltage
RL = 100Ω
1.25
1.125
1.375
V (min)
V (max)
delta VOS Offset Voltage Unbalance
RL = 100Ω
±7
±25
mV (max)
IOS
DO = 0V, VIN = 1.1V
-10
Output Short Circuit Current
mA (max)
LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS
tOCP
Output Clock Period
50% to 50%
2.56
ns
tOCDC
Output Clock Duty Cycle
See (6)
50
35
65
tH
Data Edge to Output Clock Edge Hold
Time
50% to 50% (6)
625
300
ps
tS
Data Edge to Output Clock Edge Set-Up
Time
50% to 50% (6)
600
300
ps
tFP
Frame Period
50% to 50%
50
45
55
% (min)
% (max)
15.38
% (min)
% (max)
ns
tFDC
Frame Clock Duty Cycle
See (6)
tDFS
Data Edge to Frame Edge Skew
50% to 50%
60
160
ps (max)
tR, tF
LVDS Rise/Fall Time
CL=5pF to GND, ROUT=100Ω
360
700
ps (max)
tPLD
Serializer PLL Lock Time
50
µs
tSD
Serializer Delay
RL=100Ω
2.76
ns
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV.
As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
(5)
(6)
10
To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
This parameter is guaranteed by design and/or qualification and is not tested in production.
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Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is
presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay
plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
CROSSTALK is coupling of energy from one channel into the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale Error
(1)
Gain Error can also be separated into Positive Gain Error and Negative Gain Error, which are:
PGE = Positive Full Scale Error − Offset Error
NGE = Offset Error − Negative Full Scale Error
(2)
(3)
GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average
gain of the converters.
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in
the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VREF/2n,
where “n” is the ADC resolution in bits, which is 12 in the case of the ADC12QS065.
LVDS Differential Output Voltage (VOD) is the absolute value of the difference between the differential output
pair voltages (VD+ and VD-), each measured with respect to ground.
VD+
VD VOD
VOS
GND
VOD = | VD+ - VD- |
(4)
LVDS Output Offset Voltage (VOS) is the midpoint between the differential output pair voltages.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12QS065 is
guaranteed not to have any missing codes.
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MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of
½ LSB above negative full scale.
OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN−)] required to cause a transition
from code 2047 to 2048.
OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the
output pins.
OVER RANGE RECOVERY TIME is the time required after VIN goes from a specified voltage out of the normal
input range to a specified voltage within the normal input range and the converter makes a conversion with its
rated accuracy.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.
POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of
1½ LSB below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC12QS065, PSRR is the ratio of the change in Full-Scale Error that results from a
change in the d.c. power supply voltage, expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is
any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
THD = 20 x log
A 2 +... +A 2
f2
f10
A f12
(5)
where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the
first 9 harmonic frequencies in the output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in
the input frequency at the output and the power in its 2nd harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in
the input frequency at the output and the power in its 3rd harmonic level at the output.
12
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Timing Diagram
CLK
tSD
FRAME +/tOCHL
80%
OUTCLK+/-
80%
20%
20%
tF
tR
tOCP
tOCHL
tS
tH
DATA+/-
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
(MSB)
B0
B11
(LSB)
(MSB)
Nth Sample
B10
VOD
Nth+1 Sample
Figure 2. LVDS Output Timing
Transfer Characteristic
Figure 3. Transfer Characteristic
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Typical Performance Characteristics DNL, INL
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 5 KHz, CL = 15 pF/pin.
14
DNL
INL
Figure 4.
Figure 5.
DNL vs. fCLK
INL vs. fCLK
Figure 6.
Figure 7.
DNL vs. Clock Duty Cycle
INL vs. Clock Duty Cycle
Figure 8.
Figure 9.
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Typical Performance Characteristics DNL, INL (continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = +3.3V, VDR=
+2.5V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 5 KHz, CL = 15 pF/pin.
DNL vs. Temperature
INL vs. Temperature
Figure 10.
Figure 11.
DNL vs. VDR, VA = VD = 3.6V
INL vs. VDR, VA = VD = 3.6V
Figure 12.
Figure 13.
DNL vs. VA
INL vs. VA
Figure 14.
Figure 15.
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Typical Performance Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 5 MHz, CL = 15 pF/pin. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
16
SNR, SINAD, SFDR vs. VA
Distortion vs. VA
Figure 16.
Figure 17.
SNR, SINAD, SFDR vs. VCM
Distortion vs. VCM
Figure 18.
Figure 19.
SNR, SINAD, SFDR vs. fCLK
Distortion vs. fCLK
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 5 MHz, CL = 15 pF/pin. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
SNR, SINAD, SFDR vs. Clock Duty Cycle
Distortion vs. Clock Duty Cycle
Figure 22.
Figure 23.
SNR, SINAD, SFDR vs. VREF
Distortion vs. VREF
Figure 24.
Figure 25.
SNR, SINAD, SFDR vs. fIN
Distortion vs. fIN
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 5 MHz, CL = 15 pF/pin. Units for SNR and SINAD are dBFS.
Units for SFDR and Distortion are dBc.
18
SNR, SINAD, SFDR vs. Temperature
Distortion vs. Temperature
Figure 28.
Figure 29.
Spectral Response @ 5 MHz Input
Spectral Response @ 33 MHz Input
Figure 30.
Figure 31.
Spectral Response @ 70 MHz Input
Intermodulation Distortion, fIN1= 19.6 MHz, fIN2 = 20.2 MHz
Figure 32.
Figure 33.
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Functional Description
Operating on a single +3.3V supply, the ADC12QS065 uses a pipeline architecture and has error correction
circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The
user has the choice of using an internal 1.0 Volt or 0.5 Volt stable reference, or using an external reference. Any
external reference is buffered on-chip to ease the task of driving that pin.
Sampled data is transformed into high speed serial output LVDS data streams. Clock and frame LVDS pairs aid
in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make
PCB design easier.
The output word rate is the same as the clock frequency, which can be between 20 MSPS and 65 MSPS
(typical) with fully specified performance at 65 MSPS. The analog input for all channels are acquired at the rising
edge of the clock and the digital data for a given sample is delayed by the pipeline for 9 clock cycles.
APPLICATIONS INFORMATION
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC12QS065:
3.0V ≤ VA ≤ 3.6V
VD = VA
VDR = 2.5V
20 MHz ≤ fCLK ≤ 65 MHz
0.8V ≤ VREF ≤ 1V (for an external reference)
0.5V ≤ VCM ≤ 2.0V
ANALOG INPUTS
There is one reference input pin, VREF, which is used to select an internal reference, or to supply an external
reference. The ADC12QS065 has four analog signal input pairs, VIN 1+ and VIN 1-, VIN 2+ and VIN 2- , VIN 3+ and
VIN 3-, VIN 4+ and VIN 4- . Each pair of pins forms a differential input pair. There is a VREG pin for decoupling the
internal 1.8V regulator.
Reference Pins
The ADC12QS065 is designed to operate with an internal 1.0V or 0.5V reference, or an external 1.0V reference,
but performs well with external reference voltages in the range of 0.8V to 1V. Lower reference voltages will
decrease the signal-to-noise ratio (SNR) of the ADC12QS065. Increasing the reference voltage (and the input
signal swing) beyond 1V may degrade THD for a full-scale input, especially at higher input frequencies.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The six Reference Bypass Pins (VREFT12, VREFB12, VCOM12, VREFT34, VREFB34 and VCOM34) are made
available for bypass purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10
µF capacitor should be placed between the VREFT12 and VREFB12 pins and between the VREFT34 and
VREFB34 pins, as shown in Figure 36. This configuration is necessary to avoid reference oscillation, which could
result in reduced SFDR and/or SNR.
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may
result in degraded noise performance.
The VCOM pins may be loaded to 1 mA. The remaining reference bypass pins should not be loaded.
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The nominal voltages for the reference bypass pins are as follows:
VCOM = 1.5 V
VREFT = VCOM + VREF / 2
VREFB = VCOM − VREF / 2
User choice of an on-chip or external reference voltage is provided. When INTREF is high, the VREF pin selects
the internal reference voltage. The internal 1.0 Volt reference is in use when the the VREF pin is connected to VA.
When the VREF pin is connected to AGND, the internal 0.5 Volt reference is in use. When INTREF is low, a
voltage in the range of 0.8V to 1V is applied to the VREF pin and that is used for the voltage reference. When an
external reference is used, the VREF pin should be bypassed to ground with a 0.1 µF capacitor close to the
reference input pin. There is no need to bypass the VREF pin when the internal reference is used.
Signal Inputs
The ADC12QS065 has 4 input channels. They are labelled VIN 1+ and VIN1− , VIN 2+ and VIN2− , VIN 3+ and
VIN3− , VIN 4+ and VIN4− . The input signal, VIN, is defined as
VIN = (VIN+) – (VIN−)
(6)
Figure 34 shows the expected input signal range. Note that the common mode input voltage, VCM, should be in
the range of 0.5V to 2.0V with a typical value of 1.5V.
The peaks of the individual input signals should each never exceed 2.6V to maintain THD and SINAD
performance.
The ADC12QS065 performs best with a differential input signal with each input centered around a common
mode voltage, VCM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the
reference voltage or the output data will be clipped.
The two input signals should be exactly 180° out of phase from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms,
however, angular errors will result in distortion.
VREF
VIN-
VREF/2
0V
VIN+
(a) Differential Input
2VREF
VIN+
VREF
0V
(b) Single-Ended Input
Figure 34. Expected Input Signal Range
For single frequency sine waves the full scale error in LSB can be described as approximately
EFS = 4096 ( 1 - sin (90° + dev))
where
•
dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to
each other (see Figure 35).
(7)
Drive the analog inputs with a source impedance less than 100Ω.
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Figure 35. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause
Distortion
For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage just
below the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM.
Single-Ended Operation
Performance with differential input signals is better than with single-ended signals. For this reason, single-ended
operation is not recommended. However, if single ended-operation is required and the resulting performance
degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the
driven input. The peak-to-peak differential input signal at the driven input pin should be twice the reference
voltage to maximize SNR and SINAD performance (Figure 34). For example, set VREF to 0.5V, bias VIN− to 1.0V
and drive VIN+ with a signal range of 0.5V to 1.5V.
Because very large input signal swings can degrade distortion performance, better performance with a singleended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and
Table 2 indicate the input to output relationship of the ADC12QS065.
Table 1. Input to Output Relationship – Differential Input
VIN+
VIN−
Binary Output
VCM − VREF / 2
VCM + VREF / 2
0000 0000 0000
VCM − VREF / 4
VCM + VREF / 4
0100 0000 0000
VCM
VCM
1000 0000 0000
VCM + VREF / 4
VCM − VREF / 4
1100 0000 0000
VCM + VREF / 2
VCM − VREF / 2
1111 1111 1111
Table 2. Input to Output Relationship – Single-Ended Input
VIN
VIN−
Binary Output
VCM − VREF
VCM
0000 0000 0000
VCM − VREF / 2
VCM
0100 0000 0000
VCM
VCM
1000 0000 0000
VCM + VREF / 2
VCM
1100 0000 0000
VCM + VREF
VCM
1111 1111 1111
+
Driving the Analog Inputs
The VIN+ and the VIN− inputs of the ADC12QS065 consist of an analog switch followed by a switched-capacitor
amplifier. As the internal sampling switch opens and closes, current pulses occur at the analog input pins,
resulting in voltage spikes at the signal input pins. As a driving source attempts to counteract these voltage
spikes, it may add noise to the signal at the ADC analog input. To help isolate the pulses at the ADC input from
the amplifier output, use RCs at the inputs, as can be seen in Figure 36 and Figure 37. These components
should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive part of the
system and this is the last opportunity to filter that input.
For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the
sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC
pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response.
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Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range of 0.5V to 2.0V and be a value such that the peak
excursions of the analog signal does not go more negative than ground or more positive than 2.6V. The nominal
VCM should generally be about 1.5V. VCOM12 or VCOM34 can be used as a VCM source.
Internal Regulator
The ADC12QS065 has an internal 1.8V regulator. The VREG pin (pin 29) should be bypassed to AGND with a
1.0 µF capacitor.
DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, PD, REFPD, and INTREF.
CLK
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock
signal in the range of 20 MHz to 65 MHz. The trace carrying the clock signal should be as short as possible and
should not cross any other signal line, analog or digital, not even at 90°.
The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the
charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This
is what limits the minimum sample rate.
The ADC12QS065 can operate with a CMOS or LVDS clock signal.
For a CMOS clock, connect CLKB (pin 48) to AGND and apply the clock signal to CLK (pin 47.) The clock line
should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant
clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on
setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin only drive that
pin. However, if that source is used to drive other things, each driven pin should be a.c. terminated with a series
RC to ground, such that the resistor value is equal to the characteristic impedance of the clock line and the
capacitor value is
where
•
•
•
tPD is the signal propagation rate down the clock line
"L" is the line length
ZO is the characteristic impedance of the clock line
(8)
This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock
source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be
the same (inches or centimeters).
For an LVDS clock, drive the CLK and CLKB pins with an ac-coupled differential clock signal. The pair should be
terminated with a 100Ω resistor near the pins.
PD
The PD pin, when high, holds the ADC12QS065 in a power-down mode to conserve power when the converter is
not being used. The power consumption in this state is 3 mW with a 65MHz clock.. The output data pins are
undefined and the data in the pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the value of the components on the reference bypass
pins 55-57, and 20-22, and is as listed in the Electrical Tables with the recommended components on the
VREFT, VREFB and VCOM reference bypass pins. These capacitors loose their charge in the Power Down
mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values
allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB
performance.
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REFPD
When high, the REFPD pin will power down the internal reference. With REFPD high, user must drive VREFT12,
VREFT34 and VREFB12 & VREFB34 externally. With REFPD low, VREFT12, VREFT34, VREFB12 and
VREFB34 are driven internally.
INTREF
When INTREF is connected to VD , two internal reference choices are selectable through the VREF pin (pin 23).
When INTREF is connected to DGND, an external reference must be applied to VREF. (See Reference Pins).
OUTPUTS
The ADC12QS065 has four Low Voltage Differential Signaling (LVDS) Data Output pairs. Valid data is present at
these outputs while the PD pin is low. The OUTCLK and FRAME pins aid in data capture.
LVDS signals provide a high level of immunity to common mode noise. The differential data signals consist of
two 350mVpp (typical) signals that are 180 degrees out of phase. The PCB traces for these signals should be
treated as transmission lines. Each signal pair should have closely coupled traces designed with 100Ω
differential impedance and should be terminated with a 100Ω resistor near the receiver.
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10 PF
VA
10 PF
10 PF
0.1 PF
x6
VD
VA
0.1 PF
1
3
ADT1-6T
6
5
4
50:
0.1 PF
x2
0.1 PF
x2
VDR pin with a 0.1 PF capacitor. See
pin description table for list of pins.
VDR
NOTE: Decouple each VA, VD, and
20:
3
4
0.1 PF 47 pF
20:
10 PF
VIN1+
DO1+
VIN1-
DO1-
56
VREFT12
57
VREFB12
55
DO2+
VCOM12
1 PF
0.1 PF
1
ADT1-6T
6
5
3
4
50:
20:
DO2-
1
3
ADT1-6T
6
5
4
50:
44
100:
LVDS
Output 1
100:
LVDS
Output 2
100:
LVDS
OUTCLK
100:
LVDS
FRAME
100:
LVDS
Output 3
100:
LVDS
Output 4
41
42
0.1 PF
(3 places)
0.1 PF 47 pF
20:
7
VIN2+
6
VIN2-
OUTCLK+
OUTCLK-
0.1 PF
43
20:
0.1 PF 47 pF
20:
10 PF
9
VIN3+
10
VIN3-
FRAME+
FRAME-
21
VREFT34
20
VREFB34
22
VCOM34
37
36
38
39
1 PF
0.1 PF
1
3
50:
ADT1-6T
6
5
4
ADC12QS065
20:
0.1 PF
(3 places)
DO3+
0.1 PF
20: 47 pF
13
VIN4+
12
VIN4-
DO3-
VA
ADC CLOCK
47
48
24
DO4+
31
DO4-
32
VREF
CLK
CLKB
VREG
29
1 PF
PD
REFPD
AGND
25
INTREF
34
DRGND
23
DGND
54
33
Figure 36. Application Circuit using Transformer Drive Circuit
24
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SNOSAD6H – JULY 2005 – REVISED MARCH 2007
511, 1%
VCOM from
ADC
20
To ADC
VIN-
255, 1%
50:
SIGNAL
INPUT
49.9,
1%
280, 1%
+
VCM
Amplifier:
LMH6650
47 pF
-
511, 1%
20
To ADC
VIN+
Figure 37. Differential Op-Amp Drive Circuit of Figure 36
POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC12QS065 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100 mVP-P.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be
especially careful of this during power turn on and turn off.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining
separate analog and digital areas of the board, with the ADC12QS065 between these areas, is required to
achieve specified performance.
The package of the ADC12QS065 has an exposed pad on its back that provides the primary heat removal path
as well as electrical grounding to the printed circuit board. The exposed pad must be attached to the board to
remove the maximum amount of heat from the package, as well as to ensure best product parametric
performance.
To maximize the removal of heat from the package, a thermal land pattern must be incorporated on the PC
board within the footprint of the package. The land pattern for this exposed pad should be at least as large as the
exposed pad of the package and be located such that the exposed pad of the device is entirely over that thermal
land pattern. This thermal land pattern should be electrically connected to ground.
To minimize junction temperature, it is recommended that a simple heat sink be built into the PCB. This is done
by including a copper area on the opposite side of the PCB. This copper area may be plated or solder coated to
prevent corrosion, but should not have a conformal coating, which could provide some thermal insulation.
Thermal vias should be used to connect these top and bottom copper areas. These thermal vias act as "heat
pipes" to carry the thermal energy from the device side of the board to the opposite side of the board where it
can be more effectively dissipated. The use of 9 to 16 thermal vias is recommended. The thermal vias should be
placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These vias should be barrel plated to
avoid solder wicking into the vias during the soldering process.
The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output
current can exhibit high transients that could add noise to the conversion process. To prevent this from
happening, the DRGND pins should NOT be connected to system ground in close proximity to any of the
ADC12QS065's other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the
clock line as short as possible.
The LVDS output pairs should be routed with a 100Ω differential impedance trace, and should be terminated at
the receiver with a 100Ω resistor.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane volume.
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ADC12QS065
SNOSAD6H – JULY 2005 – REVISED MARCH 2007
www.ti.com
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit
in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies
beside each other.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane. Traces for the
input channels should be routed away from each other as much as possible, with Ground plane between
channels, to help minimize crosstalk.
DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate
the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 38. The gates used in
the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be
prevented.
Best performance will be obtained with a differential input drive, compared with a single-ended drive, as
discussed in Single-Ended Operation and Driving the Analog Inputs.
As mentioned in the CLK section, it is good practice to keep the ADC clock line as short as possible and to keep
it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to
reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings
have capacitive coupling, so try to avoid even these 90° crossings of the clock line.
Figure 38. Isolating the ADC Clock from other Circuitry with a Clock Tree
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above
the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not
uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot
that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending
digital input, close to the signal source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12QS065 with a device that is powered from supplies outside
the range of the ADC12QS065 supply. Such practice may lead to conversion inaccuracies and even to device
damage.
26
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Using an inadequate amplifier to drive the analog input. As explained, the capacitance seen at the input
alternates between two values depending upon the phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade
performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in
Figure 36 and Figure 37) will improve performance. The LMH6550 is an example of an amplifier that may be
used to drive the analog inputs of the ADC12QS065.
Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of
phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will
affect the effective phase between these two signals. Remember that an operational amplifier operated in the
non-inverting configuration will exhibit more time delay than will the same device operating in the inverting
configuration.
Operating with the reference pins outside of the specified range. As mentioned, VREF should be in the range
of
0.8V ≤ VREF ≤ 1V
(9)
Operating outside of these limits could lead to performance degradation.
Inadequate network on Reference Bypass pins (VREFT12, VREFB12, VCOM12, VREFT34, VREFB34 and
VCOM34). These pins should be bypassed as mentioned in Reference Pins for best performance.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR and SINAD performance.
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27
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADC12QS065CISQ
ACTIVE
WQFN
NKA
60
250
TBD
Call TI
Call TI
-40 to 85
ADC12QS065CISQ/NOPB
ACTIVE
WQFN
NKA
60
250
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 85
12QS065
CISQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADC12QS065CISQ/NOPB WQFN
NKA
60
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
16.4
Pack Materials-Page 1
9.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.3
1.3
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC12QS065CISQ/NOPB
WQFN
NKA
60
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
NKA0060A
SQA60A (Rev A)
www.ti.com
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