Maxim MAX1446 10-bit, 60msps, 3.0v, low-power adc with internal reference Datasheet

19-1729; Rev 1; 7/03
KIT
ATION
EVALU
E
L
B
A
IL
AVA
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
________________________Applications
Features
♦ Single 3.0V Operation
♦ Excellent Dynamic Performance
59.5dB SNR at fIN = 20MHz
73dB SFDR at fIN = 20MHz
♦ Low Power:
30mA (Normal Operation)
5µA (Shutdown Mode)
♦ Fully Differential Analog Input
♦ Wide 2Vp-p Differential Input Voltage Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ CMOS-Compatible Three-State Outputs
♦ 32-Pin TQFP Package
Ordering Information
PART
MAX1446EHJ
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Functional Diagram
CLK
VDD
MAX1446
Ultrasound Imaging
GND
CONTROL
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
IN+
T/H
PIPELINE ADC
IN-
D
E
C
10
OUTPUT
DRIVERS
D9–D0
Video Digitizing Applications
PD
REF
OVDD
REF SYSTEM +
BIAS
REFOUT REFIN REFP COM REFN
OGND
OE
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1446
General Description
The MAX1446 10-bit, 3V analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and
wideband track and hold (T/H) incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in
imaging and digital communications. The MAX1446
operates from a single 2.7V to 3.6V supply, consuming
only 90mW while delivering a 59.5dB signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz, -3dB bandwidth and
may be operated with single-ended inputs. In addition
to low operating power, the MAX1446 features a 5µA
power-down mode for idle periods.
An internal 2.048V precision bandgap reference is used
to set the ADC full-scale range. A flexible reference
structure allows the user to supply a buffered, direct or
externally derived reference for applications requiring
increased accuracy or a different input voltage range.
Lower and higher speed, pin-compatible versions of
the MAX1446 are also available. Refer to the MAX1444
data sheet for a 40Msps version and the MAX1448 data
sheet for a 80Msps version.
The MAX1446 has parallel, offset binary, three-state
outputs that can be operated from 1.7V to 3.3V to allow
flexible interfacing. The device is available in a 5x5mm,
32-pin TQFP package and is specified over the extended
industrial (-40°C to +85°C) temperature range.
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to VDD
REFIN, REFOUT, REFP,
REFN, and COM to GND.........................-0.3V to (VDD + 0.3V)
OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V)
D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFP (derate 11.1mW/°C above +70°C)...........889mW
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization.Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
INL
fIN = 7.492MHz, TA ≥ +25°C
±0.6
±1.9
LSB
Differential Nonlinearity
DNL
No missing codes, fIN = 7.492MHz
±0.4
±1.0
LSB
<±0.1
±1.9
% FS
0
±2.0
% FS
Offset Error
-1.6
Gain Error
ANALOG INPUT
Input Differential Range
VDIFF
Common-Mode Voltage Range
VCOM
Input Resistance
RIN
Input Capacitance
CIN
Differential or single-ended inputs
Switched capacitor load
±1.0
V
VDD/2
± 0.5
V
33
kΩ
5
pF
CONVERSION RATE
Maximum Clock Frequency
fCLK
60
Data Latency
MHz
5.5
Cycles
DYNAMIC CHARACTERISTICS (fCLK = 62.5MHz, 4096-point FFT)
Signal-to-Noise Ratio
SNR
fIN = 7.492MHz
57
59.5
fIN = 19.943MHz
56.5
59.5
fIN = 39.9MHz (Note 1)
Signal-to-Noise Plus Distortion
(up to 5th Harmonic)
SINAD
fIN = 7.492MHz
56.6
fIN = 19.943MHz
56.2
fIN = 39.9MHz (Note 1)
Spurious-Free Dynamic
Range
SFDR
2
59.4
59
dB
58.5
fIN = 7.492MHz
65
74
fIN = 19.943MHz
63
73
fIN = 39.9MHz (Note 1)
dB
59
71
_______________________________________________________________________________________
dBc
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization.Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
fIN = 7.492MHz
Third-Harmonic Distortion
Two-Tone Intermodulation
Distortion
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
(First 5 Harmonics)
HD3
MAX
UNITS
-74
dBc
fIN = 19.943MHz
-73
fIN = 39.9MHz (Note 1)
-71
IMDTT
f1 = 19MHz at -6.5dBFS,
f2 = 21MHz at -6.5dBFS (Note 2)
-75
dBc
IM3
f1 = 19MHz at -6.5dBFS
f2 = 21MHz at -6.5dBFS (Note 2)
-75
dBc
fIN = 7.492MHz
-70
-64
fIN = 19.943MHz
-70
-63
fIN = 39.9MHz (Note 1)
-69
Input at -20dBFS, differential inputs
500
MHz
Input at -0.5dBFS, differential inputs
400
MHz
THD
Small-Signal Bandwidth
Full-Power Bandwidth
TYP
FPBW
dBc
Aperture Delay
tAD
1
ns
Aperture Jitter
tAJ
2
psrms
For 1.5 × full-scale input
Overdrive Recovery Time
2
ns
±1
%
±0.25
°
0.2
LSBrms
REFOUT
2.048
±1%
V
TCREF
60
ppm/°C
1.25
mV/mA
Differential Gain
Differential Phase
Output Noise
IN+ = IN- = COM
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
EXTERNAL REFERENCE
Positive Reference
REFP
VREFIN = 2.048V
2.012
V
Negative Reference
REFN
VREFIN = 2.048V
0.988
V
VREF
VREFP - VREFN, VREFIN = 2.048V, TA ≥ +25°C
Differential Reference Voltage
REFIN Resistance
0.98
RREFIN
1.024
>50
1.07
V
MΩ
DIGITAL INPUTS (CLK, PD, OE )
Input High Threshold
CLK
0.8 x
VDD
PD, OE
0.8 x
OVDD
VIH
V
_______________________________________________________________________________________
3
MAX1446
ELECTRICAL CHARACTERISTICS (continued)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization.Typical values are at TA = +25°C.)
PARAMETER
Input Low Threshold
Input Hysteresis
Input Leakage
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
CLK
0.2 x
VDD
PD, OE
0.2 x
OVDD
VIL
VHYST
0.1
V
V
IIH
VIH = VDD = OVDD
±5
IIL
VIL = 0
±5
CIN
UNITS
5
µA
pF
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
VOL
ISINK = 200µA
Output Voltage High
VOH
ISOURCE = 200µA
Three-State Leakage Current
ILEAK
OE = OVDD
Three-State Output Capacitance
COUT
OE = OVDD
0.2
OVDD 0.2
V
V
±10
5
µA
pF
POWER REQUIREMENTS
Analog Supply Voltage
VDD
Output Supply Voltage
OVDD
Analog Supply Current
IVDD
Output Supply Current
IOVDD
2.7
3.0
3.6
V
1.7
3.0
3.6
V
Operating, fIN = 19.943MHz at -0.5dBFS
30
37
mA
Shutdown, clock idle, PD = OE = OVDD
4
15
µA
Operating, CL = 15pF, fIN = 19.943MHz at
-0.5dBFS
7
CL = 10pF
Shutdown, clock idle, PD = OE = OVDD
Power-Supply Rejection
PSRR
1
mA
20
µA
Offset
± 0.1
mV/V
Gain
± 0.1
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Figure 5 (Note 3)
5
OE Fall to Output Enable
tENABLE
tDO
Figure 5
10
8
ns
ns
OE Rise to Output Disable
tDISABLE
Figure 5
1.5
ns
ns
CLK Pulse Width High
tCH
Figure 6, clock period 16ns
8.3
± 2.5
CLK Pulse Width Low
tCL
Figure 6, clock period 16ns
8.3
± 2.5
ns
1.5
µs
Wake-Up Time
tWAKE
(Note 4)
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to VIH, VIL.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
4 _______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
FFT PLOT
(fIN = 7.5MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
-50
-60
3RD HARMONIC
-50
-60
3RD HARMONIC
2ND HARMONIC
-70
2ND HARMONIC
-70
-40
-100
0
-40
-50
5
10
15
20
25
30
-80
-90
-100
0
FFT PLOT
(fIN = 26.8MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
SINAD = 59.0dB
SNR = 59.4dB
THD = -70.5dBc
SFDR = 72.9dBc
-20
-40
2ND HARMONIC
-50
3RD HARMONIC
-60
10
15
20
25
30
35
0
SFDR = 70dBc
SNR = 59.1dB
THD = -67.1dBc
SINAD = 58.5dB
-20
-30
-40
-50
3RD HARMONIC
2ND HARMONIC
-60
0
-20
-50
-90
-90
-100
-100
-100
10
15
20
25
30
35
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(fIN = 20MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
TWO-TONE INTERMODULATION
(8192-POINT IMD,
DIFFERENTIAL INPUT)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
-20
-40
3RD HARMONIC
2ND HARMONIC
-70
-30
-40
-50
-60
-80
-80
-90
-90
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
35
65
SINGLE ENDED
55
-100
5
35
70
60
-70
-100
DIFFERENTIAL
75
SINAD (dBc)
AMPLITUDE (dB)
-30
f1 = 19MHz AT -6.5dBFS
f2 = 21MHz AT -6.5dBFS
3RD IMD = -76dBc
-10
80
MAX1446 toc10
-20
0
MAX1446 toc07
SINAD = 59.2dB
SNR = 59.5dB
THD = -70.7dBc
SFDR = 71.1dBc
0
0
ANALOG INPUT FREQUENCY (MHz)
0
-60
5
2ND HARMONIC
ANALOG INPUT FREQUENCY (MHz)
-10
-50
0
35
3RD HARMONIC
-60
-90
30
35
-40
-80
25
30
-30
-70
20
25
SINAD = 59.5dB
SNR = 59.7dB
THD = -73.0dBc
SFDR = 73.6dBc
-10
-80
15
20
FFT PLOT
(fIN = 7.5MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
-70
10
15
FFT PLOT
(fIN = 50MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
-80
5
10
ANALOG INPUT FREQUENCY (MHz)
-70
0
5
ANALOG INPUT FREQUENCY (MHz)
-10
AMPLITUDE (dB)
-30
5
0
MAX1446 toc04
0
-10
2ND HARMONIC
-70
-100
35
3RD HARMONIC
-60
-90
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
-30
AMPLITUDE (dB)
-90
AMPLITUDE (dB)
-20
-80
-80
SINAD = 59.3dB
SNR = 59.6dB
THD = -70.7dBc
SFDR = 72.2dBc
MAX1446 toc06
-40
-30
MAX1446 toc05
AMPLITUDE (dB)
-30
-20
0
-10
MAX1446 toc11
-20
AMPLITUDE (dB)
-10
SFDR = 72.2dBc
SNR = 60.1dB
THD = -71.5dBc
SINAD = 59.8dB
-10
MAX1446 toc03
0
SFDR = 72.2dB
SNR = 60.1dB
THD = -71.5dB
SINAD = 59.8dB
AMPLITUDE (dB)
0
FFT PLOT
(fIN = 20MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
MAX1446 toc01
FFT PLOT
fIN = 7.5MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT
50
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
35
1
10
100
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
MAX1446
Typical Operating Characteristics
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L ≈ 10pF, T A = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L ≈ 10pF, T A = +25°C,
unless otherwise noted.)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SINGLE ENDED
-55
59
-60
SINAD (dB)
THD (dBc)
SNR (dB)
DIFFERENTIAL
59
58
DIFFERENTIAL
58
60
MAX1446 toc13
-50
MAX1446 toc12
60
MAX1446 toc14
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
SINGLE ENDED
-65
57
SINGLE ENDED
56
55
57
54
-70
53
DIFFERENTIAL
-75
10
100
52
1
ANALOG INPUT FREQUENCY (MHz)
1
100
66
MAX1446 toc15
fIN = 19.943MHz
75
fIN = 19.943MHz
60
70
-50
fIN = 19.943MHz
-55
-60
THD (dBc)
SNR (dB)
54
65
48
-65
60
42
-70
55
36
-75
50
-80
30
-20
-16
-12
-8
-4
0
100
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
80
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
-20
-16
-12
-8
-4
-20
0
-16
-12
-8
-4
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
fIN = 19.943MHz
60
fIN = 19.943MHz
70
76
0
MAX1446 toc20
80
MAX1446 toc18
65
MAX1446 toc19
SFDR (dBc)
10
MAX1446 toc16
1
MAX1446 toc17
56
fIN = 19.943MHz
66
50
45
72
SNR (dB)
SFDR (dBc)
55
SINAD (dB)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
62
68
58
64
54
40
35
30
-16
-12
-8
-4
ANALOG INPUT POWER (dBFS)
6
50
60
-20
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
fIN = 19.943MHz
66
INTEGRAL NONLINEARITY vs. DIGITAL
OUTPUT CODE (BEST STRAIGHT LINE)
MAX1446 toc22
-60
MAX1446 toc21
70
fIN = 19.943MHz
-64
0.5
fIN = 7.5MHz
0.4
MAX1446 toc23
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
58
-72
0.2
INL (LSB)
-68
0.1
0
54
-76
50
-80
-0.1
-0.2
10
35
60
85
-40
-15
TEMPERATURE (°C)
35
60
-0.3
85
0
10
8
6
GAIN ERROR (LSB)
0.1
0
-0.1
-0.2
2
0
-2
2
0
-2
-4
-6
-8
-8
-0.5
-10
-10
400
600
800
1000
-40
1200
-15
10
35
60
85
-40
-15
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
33
31
35
60
85
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
8
MAX1446 toc28
32
MAX1446 toc27
35
10
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
1200
4
-0.4
200
1000
6
4
-6
0
800
8
-4
-0.3
600
10
OFFSET ERROR (LSB)
0.2
400
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (VREFIN = 2.048V)
MAX1446 toc25
fIN = 7.5MHz
MAX1446 toc24
0.3
200
DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (VREFIN = 2.048V)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DNL (LSB)
10
TEMPERATURE (°C)
MAX1446 toc26
-15
MAX1446 toc29
-40
fIN = 7.5MHz
7
31
29
29
5
4
28
27
25
2.70
30
IOVDD (mA)
IVDD (mA)
6
IVDD (mA)
SINAD (dB)
0.3
62
3
27
2.85
3.00
3.15
VDD (V)
3.30
3.45
3.60
2
-40
-15
10
35
TEMPERATURE (°C)
60
85
1.2
1.8
2.4
3.0
3.6
OVDD (V)
_______________________________________________________________________________________
7
MAX1446
Typical Operating Characteristics (continued)
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L ≈ 10pF, T A = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(V DD = 3.0V, OV DD = 2.7V, internal reference, differential input at -0.5dBFS, f CLK = 62.35MHz, C L ≈ 10pF, T A = +25°C,
unless otherwise noted.)
7
OE = OVDD,
PD = VDD
4.5
10
MAX1446 toc31
fIN = 7.5MHz
PD = VDD,
OE = OVDD
8
5
IOVDD (µA)
4.0
6
IVDD (µA)
IOVDD (mA)
5.0
MAX1446 toc30
8
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL POWER SUPPLY
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
MAX1446 toc32
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
3.5
6
4
3.0
4
2
2.5
-40
-15
10
35
60
0
2.0
2.70
85
2.85
3.00
TEMPERATURE (°C)
SFDR, SNR, THD, SINAD
vs. CLOCK FREQUENCY
SNR
62
56
50
50
54
58
62
66
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.10
2.08
2.06
2.04
2.85
3.00
3.15 3.30
VDD (V)
3.45
2.06
2.04
2.00
-40
3.60
-15
10
35
TEMPERATURE (°C)
OUTPUT NOISE HISTOGRAM (DC INPUT)
140000
MAX1446 toc36
160000
129421
120000
COUNTS
3.6
2.02
CLOCK FREQUENCY (MHz)
100000
80000
60000
40000
20000
0
926
N-2
N-1
725
0
N+1
N+2
0
N
DIGITAL OUTPUT CODE
8
3.0
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
2.00
2.70
70
2.4
OVDD (V)
2.02
SINAD
1.8
VDD (V)
2.08
THD
68
1.2
3.60
2.10
VREFOUT (V)
74
3.45
VREFOUT (V)
fIN = 20MHz
3.30
MAX1446 toc34
SFDR
MAX1446 toc33
80
3.15
MAX1446 toc35
3
SFDR, SNR, THD, SINAD (dB)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________
60
85
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
PIN
NAME
FUNCTION
1
REFN
Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF
capacitor.
2
COM
Common-Mode Voltage Output. Bypass to GND with a >0.1µF capacitor.
3, 9, 10
VDD
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel
with 0.1µF.
4, 5, 8, 11, 14, 30
GND
Analog Ground
6
IN+
Positive Analog Input. For single-ended operation, connect signal source to IN+.
7
IN-
Negative Analog Input. For single-ended operation, connect IN- to COM.
12
CLK
Conversion Clock Input
13
PD
Power-Down Input
High: power-down mode
Low: normal operation
15
OE
Output Enable Input
High: digital outputs disabled
Low: digital outputs enabled
16–20
D9–D5
Three-State Digital Outputs D9–D5. D9 is the MSB.
21
OVDD
Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
22
T.P.
23
OGND
Output Driver Ground
24–28
D4–D0
Three-State Digital Outputs D4–D0. D0 is the LSB.
29
REFOUT
31
REFIN
Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a >0.01µF capacitor.
32
REFP
Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF
capacitor.
Test Point. Do not connect.
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.
_______________________________________________________________________________________
9
MAX1446
Pin Description
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
Detailed Description
The MAX1446 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input T/H circuit in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuit samples the
input signal onto the two capacitors (C2a and C2b).
S2a and S2b set the common mode for the amplifier
input. The resulting differential voltage is held on C2a
and C2b. S4a, S4b, S5a, S5b, S1, S2a, and S2b are
then opened before S3a, S3b and S4c are closed, connecting capacitors C1a and C1b to the amplifier output,
and S4c is closed. This charges C1a and C1b to the
same values originally held on C2a and C2b. This value
is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The
wide-input-bandwidth T/H amplifier allows the
MAX1446 to track and sample/hold analog inputs of
high frequencies beyond Nyquist. The analog inputs
(IN+ and IN-) can be driven either differentially or single
ended. It is recommended to match the impedance of
IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1446 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
ADC’s full-scale range is user adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
MDAC
VIN
Σ
T/H
x2
VOUT
S4a
IN+
FLASH
ADC
OUT
C2a
DAC
S4c
1.5 bits
S1
OUT
INS4b
C2b
C1b
VIN
STAGE 1
STAGE 2
S3b
STAGE 10
S2b
INTERNAL
BIAS
DIGITAL CORRECTION LOGIC
10
D9–D0
VIN = INPUT VOLTAGE BETWEEN
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
10
TRACK
HOLD
TRACK
CLK
INTERNAL
HOLD NON-OVERLAPPING
CLOCK SIGNALS
Figure 2. Internal T/H Circuit
______________________________________________________________________________________
S5b
COM
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider if an application
requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a
>10nF capacitor to GND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10kΩ resistor.
In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip
buffers of REFP, COM, and REFN. With their buffers
shut down, these pins become high impedance and
can be driven by external reference sources.
Clock Input (CLK)
The MAX1446 CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR performance of the ADC as follows:
SNR = 20log (1 / 2 π fINtAJ)
where fIN represents the analog input frequency, and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.
The MAX1446 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR),
signal-to-noise ratio (SNR), total harmonic distortion
(THD), or signal-to-noise plus distortion (SINAD) versus
duty cycle.
Output Enable (OE), Power-Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS-logic compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD (power-down) high, the digital output enters a high-impedance state. If OE is held
low with PD high, the outputs are latched at the last
value prior to the power-down.
The capacitive load on the digital outputs D0–D9
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the analog portion of the MAX1446, degrading its dynamic performance. The use of buffers on the ADC’s digital
outputs can further isolate the digital outputs from
heavy capacitive loads.
To further improve the dynamic performance of the
MAX1446 small series resistors (e.g. 100Ω) may be
added to the digital output paths, close to the ADC.
Figure 5 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid.
System Timing Requirements
Figure 6 shows the relationship between the clock
input, analog input, and data output. The MAX1446
samples at the falling edge of the input clock. Output
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Table 1. MAX1446 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET BINARY
VREF × 511/512
VREF × 510/512
VREF × 1/512
0
- V REF × 1/512
- V REF × 511/512
- V REF × 512/512
+Full Scale -1LSB
+Full Scale -2LSB
+1LSB
Bipolar Zero
-1LSB
Negative Full Scale + 1LSB
Negative Full Scale
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
*VREFIN = VREFP = VREFN
______________________________________________________________________________________
11
MAX1446
The MAX1446 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
-40
80
fIN = 12.5MHz AT -0.5dBFS
fIN = 12.5MHz AT -0.5dBFS
-50
THD (dBc)
SFDR (dBc)
70
60
-60
-70
50
-80
40
20
30
40
50
60
20
70
30
Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input)
50
60
70
Figure 4a. THD vs. Clock Duty Cycle (Differential Input)
70
70
fIN = 12.5MHz AT -0.5dBFS
fIN = 12.5MHz AT -0.5dBFS
65
65
60
60
SINAD (dB)
SNR (dB)
40
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
55
55
50
50
45
45
40
40
20
30
40
50
60
70
CLOCK DUTY CYCLE (%)
20
30
40
50
60
70
CLOCK DUTY CYCLE (%)
Figure 3b. SNR vs. Clock Duty Cycle (Differential Input)
Figure 4b. SINAD vs. Clock Duty Cycle (Differential Input)
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
RISO and CIN values to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF
CIN capacitor acts as a small bypassing capacitor.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting
purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the
12
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1446 for
optimum performance. Connecting the transformer’s
center tap to COM provides a VDD/2 DC level shift to
______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
Grounding, Bypassing,
__________________and Board Layout
The MAX1446 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes produce the highest level of signal integrity. Consider
using a split ground plane arranged to match the physi-
Single-Ended AC-Coupled
Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high
OE
tDISABLE
tENABLE
OUTPUT
DATA D9–D0
HIGH-Z
VALID DATA
HIGH-Z
Figure 5. Output Enable Timing
5.5 CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
ANALOG INPUT
CLOCK INPUT
tDO
DATA OUTPUT
tCH
N-6
N-5
N-4
tCL
N-3
N-2
N-1
N
N+1
Figure 6. System and Output Timing Diagram
______________________________________________________________________________________
13
MAX1446
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the overall distortion.
In general, the MAX1446 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
+5V
0.1µF
LOWPASS FILTER
IN-
MAX4108
RISO
50Ω
0.1µF
300Ω
CIN
22pF
0.1µF
-5V
MAX1446
600Ω
600Ω
300Ω
COM
0.1µF
+5V
+5V
0.1µF
600Ω
INPUT
0.1µF
LOWPASS FILTER
MAX4108
300Ω
-5V
0.1µF
IN+
MAX4108
RISO
50Ω
300Ω
-5V
CIN
22pF
0.1µF
300Ω
300Ω
600Ω
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
cal location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground
planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
14
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1446’s static linearity parameters are measured
using the best-straight-line fit method.
______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
25Ω
IN+
22pF
VIN
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (rms value) to the rms quantization error (residual error). The ideal, theoretical minimum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR(MAX) = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics,
and the DC offset.
MAX1446
0.1µF
1
6
T1
N.C. 2
5
3
4
COM
2.2µF
0.1µF
MINICIRCUITS
TT1–6
25Ω
IN22pF
Figure 8. Using a Transformer for AC-Coupling
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the rms signal
to all spectral components minus the fundamental and
the DC offset.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
ENOB = (SINAD - 1.76dB) / 6.02dB
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
REFP
1k
VIN
0.1µF
RISP
IN+
MAX4108
100Ω
CIN
1k
MAX1446
COM
REFN
0.1µF
RISO
100Ω
RISO = 50Ω
CIN = 22pF
INCIN
Figure 9. Single-Ended AC-Coupled Input
______________________________________________________________________________________
15
MAX1446
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
Pin Configurations (continued)
Figure 10. T/H Aperture Timing
Total Harmonic Distortion (THD)
THD is typically the ratio of the rms sum of the input
signal’s first four harmonics to the fundamental itself.
This is expressed as:
THD = 20 × log
(
)
GND
REFOUT
D0
D1
D2
D3
27
26
25
REFN
1
24 D4
COM
2
23 OGND
VDD
3
22 T.P.
GND
4
21 OVDD
MAX1446
GND
5
IN+
6
19 D6
IN-
7
18 D7
GND
8
17 D8
9
10
11
12
20 D5
13
14
15
16
D9
TRACK
28
OE
HOLD
TRACK
29
GND
T/H
30
CLK
SAMPLED
DATA (T/H)
31
VDD
tAJ
32
GND
tAD
REFIN
ANALOG
INPUT
REFP
TOP VIEW
PD
CLK
VDD
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
TQFP
V22 + V32 + V42 + V52 / V1
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the rms
amplitude of the fundamental (maximum signal component) to the rms value of the next largest spurious component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale, and their envelope is at -0.5dB
full scale.
Chip Information
TRANSISTOR COUNT: 5684
PROCESS: CMOS
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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