SEMICONDUCTOR TECHNICAL DATA The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than 150 ps1 the device meets the needs of the most demanding clock applications. The MPC9992 offers a differential PECL input and a crystal oscillator interface. All control signals are LVCMOS compatible. Order Number: MPC9992/D Rev 2, 04/2002 3.3V DIFFERENTIAL ECL/PECL PLL CLOCK GENERATOR Features • 7 differential outputs, PLL based clock generator • SiGe technology supports minimum output skew (max. 150 ps1) • Supports up to two generated output clock frequencies with a maximum clock frequency up to 400 MHz • Selectable crystal oscillator interface and PECL compatible clock input • SYNC pulse generation • PECL compatible differential clock inputs and outputs FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A • Single 3.3V (PECL) supply • Ambient temperature range 0°C to +70°C • Standard 32 lead LQFP package • Pin and function compatible to the MPC992 Functional Description The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range. The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC generator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies. The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted. Assertion of the reset signal forces all outputs to the logic low state. The MPC9992 is fully 3.3V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 transmission lines. The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package. 1. Final specification of this parameter is pending characterization. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Motorola, Inc. 2002 1 MPC9992 ( *&/ *&/!'& 086 77 58:>= ;2<5<=9;< 40?2 0 ?07>2 93 6Ω *& 1 0 " " $23 (! ÷4 ÷2 PLL # # ÷ ÷ ÷ 1 0 # # ÷ ÷ ÷ A ( # # ÷ ÷ 0 1 %@81 ">7<2 086 $/% ( (!/% "/ %- . # # # # # # # # ( 2 %@81 $%&!" #%+ #%+ # #%+ #%+ ( # # # ( Figure 1. MPC9992 Logic Diagram # # # # # # # (/" # MPC9992 # # $%&!" *&/!'& " " $/% % % (!/% *&/ ( "/ Figure 2. MPC9992 32–Lead Package Pinout (Top View) MOTOROLA 2 TIMING SOLUTIONS MPC9992 Table 1: MPC9992 PLL Configurations Frequency Ratio QA to QB Internal Feedback (M ⋅ VCO_SEL) VCO÷12 (4 ⋅ fREF) 3÷2 VCO÷48 VCO÷4 (8 ⋅ fREF) VCO÷8 (4 ⋅ fREF) 2÷1 VCO÷32 10–20 VCO÷8 (10 ⋅ fREF) VCO÷20 (4 ⋅ fREF) 5÷2 VCO÷80 1 16.6–33.3 VCO÷4 (12 ⋅ fREF) VCO÷12 (4 ⋅ fREF) 3÷1 VCO÷48 0 0 8.3–16.6 VCO÷16 (6 ⋅ fREF) VCO÷24 (4 ⋅ fREF) 3÷2 VCO÷96 1 0 1 12.5–25 VCO÷8 (8 ⋅ fREF) VCO÷16 (4 ⋅ fREF) 2÷1 VCO÷64 1 1 0 5–10 VCO÷16 (10 ⋅ fREF) VCO÷40 (4 ⋅ fREF) 5÷2 VCO÷160 1 1 1 8.3–16.6 VCO÷8 (12 ⋅ fREF) VCO÷24 (4 ⋅ fREF) 3÷1 VCO÷96 VCO_SEL FSEL_0 FSEL_1 fREF (MHz) QA[3:0] (NA) QB[2:0] (NB) 0 0 0 16.6–33.3 VCO÷8 (6 ⋅ fREF) 0 0 1 25–50 0 1 0 0 1 1 Table 2: FUNCTION TABLE (Configuration Controls) Control Default 0 1 REF_SEL 1 Selects PCLK, PCLK as PLL refererence signal input Selects the crystal oscillator as PLL reference signal input VCO_SEL 1 Selects VCO÷2. The VCO frequency is scaled by a factor of 2 (high input frequency range) Selects VCO÷4. The VCO frequency is scaled by a factor of 4 (low input frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9992 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Normal operation mode with PLL enabled. MR/STOP 0 Normal operation Reset of the device and output disable (output clock stop). The outputs are stopped in logic low state: Qx=L, Qx=H. The minimum reset period should be greater than one reference clock cycle. VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 1 for the device frequency configuration. Table 3: PIN CONFIGURATION Pin PCLK, PCLK I/O Input XTAL_IN, XTAL_OUT Type Function PECL Differential reference clock signal input Analog Crystal oscillator interface VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL Enable/Bypass mode select REF_SEL Input LVCMOS PLL reference signal input select MR/STOP Input LVCMOS Device reset and output clock disable (stop in logic low state) FSEL[1:0] Input LVCMOS Output and PLL feedback frequency divider select QA[0-3], QA[0-3] Output PECL Differential clock outputs (bank A) QB[0-2], QB[0-2] Output PECL Differential clock outputs (bank B) QSYNC, QSYNC Output PECL Differential clock outputs (bank C) GND Supply GND Negative power supply VCC Supply VCC Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details TIMING SOLUTIONS 3 MOTOROLA MPC9992 Table 4: ABSOLUTE MAXIMUM RATINGSa Symbol Min Max Unit VCC Supply Voltage -0.3 3.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA 125 °C VOUT IIN IOUT TS Characteristics Storage Temperature -65 Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5: GENERAL SPECIFICATIONS Symbol Characteristics Min Max VCC - 2 Unit VTT Output termination voltage MM ESD Protection (Machine model) 200 V HBM ESD Protection (Human body model) 4000 V CDM ESD Protection (Charged device model) 1500 V Latch-up immunity 200 mA CIN Input capacitance θJA Thermal resistance junction to ambient JESD 51-3, single layer test board θJC Thermal resistance junction to case TJ Operating junction temperaturea (continuous operation) MTBF = 9.1 years 4.0 0 Condition V LU JESD 51-6, 2S2P multilayer test board a. Typ pF Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 °C/W MIL-SPEC 883E Method 1012.1 110 °C Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MPC9992 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9992 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. MOTOROLA 4 TIMING SOLUTIONS MPC9992 Table 6: DC CHARACTERISTICS (VCC = 3.3V ± 5%, GND = 0V, TA = 0°C to 70°C)a Symbol Characteristics Min Typ Max Unit Condition 0.1 1.3 V Differential operation 1.0 VCC-0.3 V Differential operation ±200 µA VIN=VCC or GND VCC + 0.3 V LVCMOS 0.8 V LVCMOS ±200 µA VIN=VCC or GND Differential PECL clock inputs (PCLK, PCLK)b VPP AC differential input voltagec VCMR Differential cross point IIN Input Currente voltaged Single-ended PECL clock inputs (VCO_SEL, PLL_EN, MR/STOP, REF_SEL, FSEL[1:0]) VIH Input high voltage VIL Input low voltage IIN Input Currente 2.0 PECL clock outputs (QA[3:0], QA[3:0], QB[2:0], QB[2:0], QSYNC, QSYNC) VOH Output High Voltage TBD VCC-1.005 TBD V Termination 50 to VTT VOL Output Low Voltage TBD VCC-1.705 TBD V Termination 50 to VTT Supply Current a. b. c. d. e. f. ICC_PLL Maximum PLL Supply Current 20 mA VCC_PLL pin IGNDf Maximum Supply Current 150 mA VCC pins AC characteristics are design targets and pending characterization. Clock inputs driven by PECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristics. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Inputs have pull-down resistors affecting the input current. Does not include output drive current which is dependant on output termination methods. TIMING SOLUTIONS 5 MOTOROLA MPC9992 Table 7: AC CHARACTERISTICS (VCC = 3.3V ± 5%, GND = 0V, TA = 0°C to +70°C)a b Symbol fref Characteristics Input reference frequency Min ÷32 feedback ÷48 feedback ÷64 feedback ÷80 feedback ÷96 feedback ÷160 feedback Typ Max Unit Condition 50.0 33.3 25.0 20.0 16.67 10.0 MHz MHz MHz MHz MHz MHz PLL locked TBD MHz PLL bypass 20 MHz 800 1600 MHz 200.0 100.0 66.6 50.0 40.0 33.3 16.6 400.0 200.0 133.3 100.0 80.0 66.6 33.3 MHz MHz MHz MHz MHz MHz MHz 25.0 16.67 12.5 10.0 8.33 5.0 Input reference frequency in PLL bypass modec fXTAL Crystal interface frequency ranged fVCO VCO frequency rangee fMAX Output Frequency VPP Differential input voltagef (peak-to-peak) VCMR VO(P-P) frefDC t(∅) e. f. g. h. i. j. (PCLK) 0.8 40 Propagation Delay (static phase offset) (PCLK, PCLK to FB_IN) 1.3 V VCC-0.3 V TBD V 60 % ±150 Skewh Output duty cycle ps 100 45 50 55 ps Period Jitter RMS (1 σ) TBD ps I/O Phase Jitter RMS (1 σ) TBD tJIT(PER) PLL locked % TBD Cycle-to-cycle jitter PLL locked ps RMS (1 σ)i tJIT(CC) tr, tf 0.3 Reference Input Duty Cycle Output-to-output tLOCK a. b. c. d. Differential output voltage (peak-to-peak) DC BW ÷4 output ÷8 output ÷12 output ÷16 output ÷20 output ÷24 output ÷48 output Differential input crosspoint voltageg (PCLK) tsk(O) tJIT(∅) 10 ps PLL closed loop bandwidthj kHz Maximum PLL Lock Time 10 Output Rise/Fall Time 0.05 ms TBD ns 20% to 80% AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50Ω to VTT. In bypass mode, the MPC9992 divides the input reference clock. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max) ÷ (M ⋅ VCO_SEL) and 10 MHz ≤ fXTAL ≤ 20 MHz. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M ⋅ VCO_SEL) VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 σ. -3 dB point of PLL transfer characteristics. MOTOROLA 6 TIMING SOLUTIONS MPC9992 APPLICATIONS INFORMATION SYNC Output Description The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9992 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic high) one QA period in duration after the coincident rising edges of the QA and QB outputs. The placement of the pulse is dependent on the QA and QB output frequencies ratio. Table 2 shows the waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank B outputs. $"# # # #%+ ( $"# # # #%+ $"# # # #%+ $"# # # #%+ $"# # # #%+ Figure 3. QSYNC Timing Diagram TIMING SOLUTIONS 7 MOTOROLA MPC9992 $ Ω Power Supply Filtering The MPC9992 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the V CC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9992 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9992. Figure 4. illustrates a typical power supply filter scheme. The MPC9992 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 4. “VCC_PLL Power Supply Filter” must have a resistance of 9-10 (VCC=2.5V) to meet the voltage drop criteria. 5332;28=507 ">7<2 282;0=9; , ( µ (/" 8 ( 8 Figure 4. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 4. “VCC_PLL Power Supply Filter”, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9992 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. , Ω $& Ω $ , Ω " '& (&& $& Ω (&& Figure 5. MPC9992 AC test reference MOTOROLA 8 TIMING SOLUTIONS MPC9992 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 &' , –U– –T– B V AE P B1 DETAIL Y V1 AE DETAIL Y 4X –Z– 9 &' , S1 S DETAIL AD G –AB– BASE METAL ÉÉ ÉÉ ÉÉ N F 8X M R D J &' , –AC– !&% %! &!$ "$ % + ! &$! %! &$ &' " % !& & !&&! ! % ! & )& & )$ & *&% & "%& !+ & & !&&! ! & "$& &'% & ' , &! &$ & &' " %! % % ( &! &$ & %& " %! % ! !& ' ! "$!&$'%! !) "$!&$'%! % "$ % %! % ! ' ! %& $ &$ & &' " %! !% !& ' $ "$!&$'%! $ "$!&$'%! % !& '% & %! &! * ' %!$ "& & %% % *& %" ! !$ $ + ($+ $! "&! SECTION AE–AE W K X DETAIL AD Q H C E ! TIMING SOLUTIONS 9 ! % % % % % $ % % % % % $ $ ! % % % % % $ % % % % % $ $ MOTOROLA MPC9992 NOTES MOTOROLA 10 TIMING SOLUTIONS MPC9992 NOTES TIMING SOLUTIONS 11 MOTOROLA MPC9992 Motorola reserves the right to make changes without further notice to any products herein. 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Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ 12 MPC9992/D TIMING SOLUTIONS