TI LM3477 Lm3477 high efficiency high-side n-channel controller for switching regulator Datasheet

LM3477
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LM3477 High Efficiency High-Side N-Channel Controller for Switching Regulator
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FEATURES
DESCRIPTION
•
•
•
•
•
The LM3477/A is a high-side N-channel MOSFET
switching regulator controller. It can be used in
topologies requiring a high side MOSFET such as
buck, inverting (buck-boost) and zeta regulators. The
LM3477/A's internal push pull driver allows
compatibility with a wide range of MOSFETs. This,
the wide input voltage range, use of discrete power
components and adjustable current limit allows the
LM3477/A to be optimized for a wide variety of
applications.
1
2
•
•
•
•
500kHz Switching Frequency
Adjustable Current Limit
1.5% Reference
Thermal Shutdown
Frequency Compensation Optimized with a
Single Capacitor and Resistor
Internal Softstart
Current Mode Operation
Undervoltage Lockout with Hysteresis
8-lead (VSSOP-8) Package
APPLICATIONS
•
•
•
•
•
•
•
•
Local Voltage Regulation
Distributed Power
Notebook and Palmtop Computers
Internet Appliances
Printers and Office Automation
Battery operated Devices
Cable Modems
Battery Chargers
The LM3477/A uses a high switching frequency of
500kHz to reduce the overall solution size. Currentmode control requires only a single resistor and
capacitor for frequency compensation. The current
mode architecture also yields superior line and load
regulation and cycle-by-cycle current limiting. A 5µA
shutdown state can be used for power savings and
for power supply sequencing. Other features include
internal soft-start and output over voltage protection.
The internal soft-start reduces inrush current. Over
voltage protection is a safety feature to ensure that
the output voltage stays within regulation.
The LM3477A is similar to the LM3477. The primary
difference between the two is the point at which the
device transitions into hysteretic mode. The hysteretic
threshold of the LM3477A is one-third of the LM3477.
Hysteretic Threshold (1)
(1)
LM3477
≊ 36% of programmed current limit
LM3477A
≊ 12% of programmed current limit
See Hysteretic Threshold and PROGRAMMING THE
CURRENT LIMIT/HYSTERETIC THRESHOLD for more
information.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM3477
SNVS141K – OCTOBER 2000 – REVISED MARCH 2013
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Typical Application Circuit
L
3.3PH
Q1
FDC653N
RSN
0.02:
CSN
0.1PF
D
30BG100
6
1
VIN
4.5V - 5.5V
CBYP
0.1PF
CIN
120PF/20V
RFB1
20.5k
COUT
47PF
ceramic
FB
DR
VOUT
2.5V, 3A
RFB2
20.0k
3
7
CB
LM3477
2
8
VIN
COMP/SD
5
4
SW
GND
ISEN
CBOOT
0.1PF
RC
510
CC1
47nF
*
*RFB1 = RFB2 (Vout - 1.26)/1.26
Figure 1. Typical High Efficiency Step-Down (Buck) Converter
Connection Diagram
ISEN
COMP/SD
VIN
LM3477
CB
FB
DR
GND
SW
Figure 2. 8 Lead (VSSOP-8 Package)
PIN DESCRIPTION
Pin Name
Pin Number
ISEN
1
Current sense input pin. Voltage generated across an external sense resistor is fed into this
pin.
Description
COMP/SD
2
Compensation pin. A resistor-capacitor combination connected to this pin provides
compensation for the control loop. Pull this pin below 0.65V to shutdown.
FB
3
Feedback pin. The output voltage should be adjusted using a resistor divider to provide
1.270V at this pin.
GND
4
Ground pin.
SW
5
Switch Node. Source of the external MOSFET is connected to this node.
DR
6
Drive pin. The gate of the external MOSFET should be connected to this pin.
CB
7
Boot-strap pin. A capacitor must be connected between this pin and SW pin (pin 5) for proper
operation. The voltage developed across this capacitor provides the gate drive for the external
MOSFET.
VIN
8
Power Supply Input pin.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1) (2)
Input Voltage
36V
Peak Driver Output Current (<10µs)
1.0A
CB Pin Voltage
(3)
43V
ISEN Pin Voltage
500mV
Power Dissipation
Internally Limited
Storage Temperature Range
−65°C to +150°C
Junction Temperature
+150°C
(4)
ESD Susceptibilty
Human Body Model
Machine Model
2kV
200V
Lead Temperature for VSSOP Package
Vapor Phase (60 sec.)
Infared (15 sec.)
(1)
215°C
220°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
The CB pin must not be higher than 8V above the VSW.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is 200 pF capacitor
discharged directly into each pin.
(2)
(3)
(4)
Operating Ratings
(1)
2.97V ≤ VIN ≤ 35V
Supply Voltage
−40°C ≤ TJ ≤ +125°C
Junction Temperature Range
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics (1)
Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature
Range. Unless otherwise specified, VIN = 12V.
Symbol
VFB
Parameter
Conditions
Feedback Voltage
Typical
VCOMP = 1.4V,
2.97V ≤ VIN ≤ 36V
1.270
2.97V ≤ VIN ≤ 36V
Limit
Units
1.260/1.252
1.288/1.290
V
V(min)
V(max)
ΔVLINE
Feedback Voltage Line Regulation
0.001
%/V
ΔVLOAD
Output Voltage Load Regulation
±0.5
%/V (max)
VUVLO
Input Undervoltage Lock-out
2.87
VUV(HYS)
FSW
Input Undervoltage Lock-out Hysteresis
435
575
kHz
kHz(min)
kHz(max)
Ω
IDR = 0.2A
4
Ω
VIN < 7.2V
VIN
V
VIN ≥ 7.2V
7.2
Driver Switch On Resistance (top)
IDR = 0.2A, VIN= 5V
RDS2
(ON)
Driver Switch On Resistance (bottom)
Maximum Boot Voltage
(1)
mV
mV (min)
mV (max)
7
(ON)
Tmin (on)
130
225
500
RDS1
Dmax
V
V(max)
180
Switching Frequency
(VCB−VSW)max
2.97
Maximum Duty Cycle
93
Minimum On Time
88
%
%(min)
230
495
nsec
nsec(min)
nsec(max)
330
All limits are ensured at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature
limits are 100% tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics(1) (continued)
Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature
Range. Unless otherwise specified, VIN = 12V.
Symbol
ISUPPLY
Parameter
Conditions
(2)
Supply Current (switching)
IQ
(3)
Quiescent Current in Shutdown Mode
VCL(O)
, VIN = 5V
Current Limit Voltage at 0% Duty Cycle
LM3477
LM3477A
VCL(100)
Current Limit Voltage at 100% Duty
Cycle
LM3477
LM3477A
VSC
Short-Circuit Current Limit Sense
Voltage
VIN = 5V, LM3477
VIN = 5V, LM3477A
VSL
Typical
mV
mV (min)
mV (max)
140/135
195/200
mV
mV (min)
mV (max)
50/43
98/98
mV
mV (min)
mV (max)
41/25
89/98
mV
mV (min)
mV (max)
270
420
mV
mV (min)
mV (max)
260
380
mV
mV (min)
mV (max)
310
Output Over-voltage Protection (with
respect to feedback voltage) (4)
VCOMP = 1.4V
50
VOVP(HYS)
Output Over-Voltage Protection
Hysteresis (4)
VCOMP = 1.4V
60
Error Amplifier Transconductance
VCOMP = 1.4V
IEAO = 100µA (Source/Sink)
750
VCOMP = 1.4V
IEAO = 100µA (Source/Sink)
38
Source, VCOMP = 1.4V, VFB =
0V
100
Sink, VCOMP = 1.4V, VFB = 1.4V
−140
Error Amplifier Output Voltage Swing
130/125
185/190
350
VOVP
VEAO
µA
µA (max)
65
83
Error Amplifier Output Current (Source/
Sink)
8
74
103
IEAO
mA
mA (max)
165
VIN = 5V, LM3477A
Error Amplifier Voltage Gain
3.0
155
VIN = 5V, LM3477
AVOL
Units
5
Internal Compensation Ramp Voltage
Height
Gm
Limit
2.0
Upper Limit
VFB = 0V
COMP Pin = Floating
2.2
Lower Limit
VFB = 1.4V
0.75
mV
32/25
78/85
mV
mV(min)
mV(max)
20
110
mV
mV(min)
mV(max)
600/365
1000/1265
µmho
µmho (min)
µmho (max)
30
42
V/V
V/V (min)
V/V (max)
75/50
130/160
µA
µA (min)
µA (max)
−110/−95
−170/−180
µA
µA (min)
µA (max)
2.0
2.35
V
V(min)
V(max)
0.5
0.95
V
V(min)
V(max)
TSS
Internal Soft-Start Delay
VFB = 1.2V, VCOMP = Floating
5
msec
Tr
Drive Pin Rise Time
CGS = 3000pF, VDR = 0 to 3V
25
ns
Tf
Drive Pin Fall Time
CGS = 3000pF, VDR = 0 to 3V
25
ns
(2)
(3)
(4)
4
For this test, the COMP/SD pin must be left floating.
For this test, the COMP/SD pin must be pulled low.
The over-voltage protection is specified with respect to the feedback voltage. This is because the over-voltage protection tracks the
feedback voltage. The overvoltage protection threshold is given by adding the feedback voltage, VFB to the over-voltage protection
specification.
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Electrical Characteristics(1) (continued)
Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature
Range. Unless otherwise specified, VIN = 12V.
Symbol
VSD
Parameter
Shutdown Threshold
(5)
Conditions
Output = High
Output = Low
ISD
Shutdown Pin Current
Typical
Limit
Units
1.35
V
V (max)
0.3
V
V (min)
1.15
0.65
VSD = 5V
−1
VSD = 0V
+1
µA
TSD
Thermal Shutdown
165
°C
TSH
Thermal Shutdown Hysteresis
10
°C
θJA
Thermal Resistance
200
°C/W
(5)
MM Package
The COMP/SD pin should be pulled to ground to turn the regulator off. The voltage on the COMP/SD pin must be below the limit for
Output = Low to keep the regulator off.
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Typical Performance Characteristics
Unless otherwise specified, VIN = 12V, TJ = 25°C.
IQ (Shutdown) vs Temperature & Supply Voltage
ISupply vs Temperature & Supply Voltage (Non-Switching)
11
2.75
o
-40 C
10
25 C
9
ISUPPLY (mA)
85oC
IQ (PA)
-40oC
25oC
2.5
o
8
7
2.25
125oC
2
6
1.75
5
1.5
4
0
5
10
15
20
25
30
35
0
40
5
10
20
25
30
35
40
VIN (Volts)
VIN (Volts)
Figure 3.
Figure 4.
ISupply vs Temperature & Supply Voltage (Switching)
Frequency vs Temperature
3
600
-40oC
25oC
125oC
Frequency (kHz)
2.75
2.5
ISUPPLY (mA)
15
2.25
2
400
200
1.75
0
1.5
0
5
10
15
20
25
35
30
40
-40
0
80
40
120
o
Temperature C
VIN (Volts)
Figure 5.
Figure 6.
VCB−VSW vs Supply Voltage
COMP Pin Voltage vs Load Current
8
7
VCB-VSW (Volts)
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
VIN (Volts)
Figure 7.
6
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C.
Efficiency vs Load Current (VIN = 24V, VOUT = 12V)
Efficiency vs Load Current (VIN = 5V, OUT = 3.3V)
100
100
LM3477
90
90
LM3477A
70
60
50
40
70
60
50
40
30
30
20
20
10
10
0
0.01
0.1
LM3477
80
EFFICIENCY (%)
EFFICIENCY (%)
80
LM3477A
1
0
0.01
10
0.1
1
10
LOAD (A)
LOAD (A)
Figure 9.
Figure 10.
Efficiency vs Load Current (VIN = 12V, VOUT = 3.3V)
Error Amplifier Gain
100
90
LM3477
EFFICIENCY (%)
80
70
LM3477A
60
50
40
30
20
10
0
0.01
0.1
1
10
LOAD (A)
Figure 11.
Figure 12.
Error Amplifier Phase Shift
COMP Pin Source Current vs Temperature
150
ICOMP (PA)
140
130
120
-40
0
40
80
120
Temperature (RC)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C.
Slope Compensation Ramp vs Slope Compensation
Resistor
450
250
LM3477
400
200
350
300
LM3477A
'VSL(mV)
SHORT CIRCUIT SENSE VOLTAGE (mV)
Short Circuit vs Temperature
250
200
150
150
100
100
50
50
0
-50
0
50
100
0
150
0
1k
2k
TEMPERATURE (°C)
Figure 15.
4k
5k
Figure 16.
Shutdown Threshold Hysteresis vs Temperature
Current Sense Voltage vs Duty Cycle
400
1.4
Output = High
LM3477
CURRENT LIMIT VOLTAGE (mV)
1.2
SHUTDOWN THRESHOLD (V)
3k
RSL (:)
1
0.8
0.6
Output = Low
0.4
300
LM3477A
200
100
0.2
0
-40
0
40
80
120
TEMPERATURE (°C)
0 10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
Figure 17.
8
0
Figure 18.
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Functional Block Diagram
_
ISEN
Short-Circuit
Detect
+
_
PWM
Comparator
+
UnderVoltage
Lockout
One-Shot
500kHz
Oscillator
VIN
Slope
Compensation
7.2V
Set / Blankout
Shutdown
Detect
Bias Voltages
1.26V
Reference
Soft-Start
COMP
FB
CB
_
Switch
Logic
+
R
Q
Switch
Driver
Error
Amplifier
GND
_
+
DR
S
SW
Thermal
Shutdown
Cboot Voltage
Detect
Over-voltage
Detect
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FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTION
The LM3477/A is a switching regulator controller for topologies incorporating a high side switch. The most
common of these topologies is the step-down, or buck, converter. Other topologies such as the inverting (buckboost) and inverse SEPIC (zeta) converters can be realized. This datasheet will focus on buck converter
applications.
The LM3477/A employs current mode control architecture. Among the many benefits of this architecture are
superior line and load regulation, cycle-by-cycle current limiting, and simple loop compensation. The LM3477/A
features a patented adjustable slope compensation scheme to enable flexible inductor selection. The LM3477/A
has a combination of features that allow its use in a wide variety of applications. The input voltage can range
from 2.97V to 35V, with the output voltage being positive or negative depending on the topology. The current
limit can be scaled to safely drive a wide range of loads. An internal soft-start is provided to limit initial in-rush
current. Output over voltage and input under voltage protection ensure safe operation of the LM3477/A.
REGIONS OF OPERATION
Pulse width modulation (PWM) is the normal mode of operation. In PWM, the output voltage is well regulated
and has a ripple frequency equal to the switching frequency (500kHz). In low load conditions, the part operates in
hysteretic mode. In this mode, the output voltage is regulated between a high and low value that results in a
higher ripple magnitude and lower ripple frequency than in PWM mode (see OVER VOLTAGE PROTECTION).
VSC
LM3477
VSC
LM3477A
VCL0
PWM
Hysteretic
D(MIN)
LM3477A
PWM
Hysteretic
LM3477
VHYS
LM3477
(32mV)
VHYS
LM3477A
(11mV)
Hysteretic
Se
D(MAX)
Figure 19. Operating Regions of the LM3477/A
The important differences between the LM3477 and the LM3477A are summarized in Figure 19. The voltages in
Figure 19 can be referred to the switch current by dividing through by RSN. The LM3477A has a lower hysteretic
threshold voltage VHYS, and thus will operate in PWM mode for a larger load range than the LM3477. Typically,
VHYS = 32mV for the LM3477, while VHYS = 11mV for the LM3477A. The difference in area between the shaded
regions give a graphical representation of this. The lightly shaded region is the extra PWM operating area gained
by using the LM3477A. Thus the benefits of operating in PWM mode such as a well regulated output voltage with
low noise ripple are extended to a larger load range when the LM3477A is used. While less significant, the other
noteworthy difference between the two parts is in the short circuit current limit VSC.
VSC is a ceiling limit for the peak sense voltage VSNpk (see SHORT CIRCUIT PROTECTION). VSC is lower in the
LM3477A than in the LM3477 (see the Electrical Characteristics for limits).
OVER VOLTAGE PROTECTION
The LM3477/A has over voltage protection (OVP) for the output voltage. OVP is sensed at and is in respect to
the feedback pin (pin 3). If at anytime the voltage at the feedback pin rises to VFB + VOVP, OVP is triggered. See
Electrical Characteristics for limits on VFB and VOVP.
10
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OVP will cause the drive pin to go low, forcing the power MOSFET off. With the MOSFET off, the output voltage
will drop. The LM3477/A will begin switching again when the feedback voltage reaches VFB + (VOVP - VOVP(HYS)).
See Electrical Characteristics for limits on VOVP(HYS).
OVP can be triggered by any event that causes the output voltage to rise out of regulation. There are several
common circumstances in which this can happen, and it is beneficial for a designer to be aware of these for
debugging purposes, since the mode of operation changes from the normal Pulse Width Modulation (PWM)
mode to the hysteretic mode. In the hysteretic mode the output voltage is regulated between a high and low
value that results in a higher ripple magnitude and lower ripple frequency than in the PWM mode, see Figure 20.
Feedback Voltage
VOVP (HIGH)
VOVP(HYS)
VFB
t
VOVP (LOW)
PWM Mode:
- Normal
operation
Hysteretic Mode:
- Light load current
- D < DMIN
- Transient response
overshoot too high
See different Ripple Components in PWM and Hysteretic Modes.
Figure 20. The Feedback Voltage is related to the Output Voltage
If the load current becomes too low, the LM3477/A will increase the duty cycle, causing the voltage to rise and
trigger the OVP. The reasons for this involve the way the LM3477/A regulates the output voltage, using a control
waveform at the pulse width modulator. This control waveform has upper and lower bounds.
Another way OVP can be tripped is if the input voltage rises higher than the LM3477/A is able to regulate in
pulse width modulation (PWM) mode. The output voltage is related to the input voltage by the duty cycle as:
VOUT = VIN*D. The LM3477/A has a minimum duty cycle of 16.5% (typical), due to the blank-out timing, TMIN. If
the input voltage increases such that the duty cycle wants to be less than DMIN, the duty cycle will hold at DMIN
and the output voltage will increase with the input voltage until it trips OVP.
It is useful to plot the operational boundaries in order to illustrate the point at which the device switches into
hysteretic mode. In Figure 19, the limits shown are with respect to the peak voltage across the sense resistor
RSN, (VSNpk); they can be referred to the peak inductor current by dividing through by RSN. VSNpk is bound to the
shaded regions. In normal circumstances VSNpk is required to be in the shaded region, and the LM3477/A will
operate in the PWM mode. If operating conditions are chosen such that VSNpk would not normally fall in the
shaded regions, then the mode of operation is changed so that VSNpk will be in the shaded region, and the part
will operate in the hysteretic mode. What actually happens is that the LM3477/A will not allow VSNpk to be outside
of the shaded regions, so the duty cycle is adjusted.
The output voltage transient response overshoot can also trigger OVP. As discussed in Output Capacitor
Selection, if the capacitance is too low or ESR too high, the output voltage overshoot will rise high enough to
trigger OVP. However, as long as there is room for the duty cycle to adjust (the converter is not near DMIN or
DMAX), the LM3477/A will return to PWM mode after a few cycles of hysteretic mode operation.
There is one last way that OVP can be triggered. If the unregulated input voltage crosses 7.2V, the output
voltage will react as shown in Figure 21. The internal bias of the LM3477/A switches supplies at 7.2V. When this
happens, a sudden small change in bias voltage is seen by all the internal blocks of the LM3477/A. The control
voltage, VC, shifts because of the bias change, the PWM comparator tries to keep regulation. To the PWM
comparator, the scenario is identical to step change in the load current, so the response at the output voltage is
the same as would be observed in a step load change. Hence, the output voltage overshoot here can also trigger
OVP. The LM3477/A will regulate in hysteretic mode for several cycles, or may not recover and simply stay in
hysteretic mode until the load current drops. Note that the output voltage is still regulated in hysteric mode.
Predicting whether or not the LM3477/A will come out of hysteretic mode in this scenario is a difficult task,
however it is largely a function of the output current and the output capacitance. Triggering hysteretic mode in
this way is only possible at higher load currents. The method to avoid this is to increase the output capacitance.
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VIN (V)
xxxxx
7.2V
t
VFB (V)
OVP
(1.315V)
1.265V
t
The Feedback Voltage Experiences an Oscillation if the Input Voltage Crosses the 7.2V Internal Bias Threshold
Figure 21.
DEFAULT/ADJUSTABLE SLOPE COMPENSATION
The LM3477/A uses a current mode control scheme. There are many advantages in a current mode architecture
including inherent cycle-by-cycle current limiting and simple compensation of the control loop. However, there are
consequences to using current mode control that one must be aware of while selecting circuit components. One
of these consequences is the inherent possibility of subharmonic oscillations in the inductor current. This is a
form of instability and should be avoided.
RSL = 0 (nominal)
VIN
LM3477
RSN
PWM Comparator
+
ISEN
R
DR
VC
Voltage
S
Q
D
VOUT
COUT
PWM Comparator
Waveforms
VC
VSEN
Q L
Q
Se
I0
Sn
I2
Sf
I1
Time
Figure 22. The Current Sensing Loop and Corresponding Waveforms
As a brief explanation, consider Figure 22. A lot of information is shown here. The top portion shows a schematic
of the current sensing loop. The bottom portion shows the pulse width modulation (PWM) comparator waveforms
for two switching cycles. The two solid waveforms shown are the waveforms compared at the internal pulse width
modulator, used to generate the MOSFET drive signal. The top waveform with the slope Se is the internally
generated control waveform VC. The bottom waveform with slopes Sn and Sf is the sensed inductor current
waveform VSEN. These signals are compared at the PWM comparator. There is a feedback loop involved here.
The inductor current is sensed and fed back to the PWM comparator, where it is compared to VC. The output of
the comparator in combination with the R/S latch determine if the MOSFET is on or off, which effectively controls
the amount of current the inductor receives. While VC is higher than VSEN, the PWM comparator outputs a high
signal, driving the external power MOSFET on. When MOSFET is on, the inductor current rises at a constant
slope, generating the sensed voltage VSEN. When VSEN equals VC, the PWM comparator signals to drive the
MOSFET off, and the sensed inductor current decreases with a slope Sf. The process begins again when RS
latch is set by an internal oscillator.
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The subharmonic oscillation phenomenon is realized when a load excursion is experienced. The way it is
analyzed is to calculate how the inductor current settles after such an excursion. Take for example the case
when the inductor current experiences a step increase in its average current, shown as the dotted line in
Figure 22. In the switching period that the excursion occurs, the inductor current will change by ΔI0. In the
following switching period, the inductor current will have a difference ΔI1 from its original starting value. The
original excursion is being propagated each switching cycle. What is desired is to find out if this propagation is
converging or diverging. It is apparent that the difference in the inductor current from one cycle to the next is a
function of Sn, Sf, and Se, as follows:
'In=
S f - Se
'In-1
Sn + Se
(1)
Hence, if the quantity (Sf - Se)/(Sn + Se)is greater than 1, the inductor current diverges and subharmonic
oscillations result. Notice that as Se increases, the factor decreases. Also, when the duty cycle is greater than
50%, as the inductance become less, the factor increases.
The LM3477/A internally generates enough slope compensation Se to allow for the use of reasonable
inductances. The height of the compensation slope ramp VSL can be found in the Electrical Characteristics. The
LM3477/A incorporates a patented scheme to increase Se if there is need to use a smaller inductor. With the use
of a single resistor RSL, Se can be increased indefinitely. RSL increases the compensation slope Se by the
amount:
'Se = 50 x 10-6 x fS x RSL ( V )
Ps
(2)
Therefore,
V)
Se = fS(VSL + 50 x 10-6 x RSL) ( Ps
(3)
When excursions of the inductor current are divergent, the current sensing control loop is unstable and produces
a subharmonic oscillation in the inductor current. This oscillation is viewed as a resonance in the outer voltage
control loop at half the switching frequency. In POWER INDUCTOR SECTION, calculations for minimum
inductance and necessary slope resistance RSL are carried out based on this resonant peaking.
START-UP/SOFT-START
The LM3477/A incorporates an internal soft-start during start-up. The soft-start forces the inductor current to rise
slowly and smoothly as it increases towards the steady-state current. This technique is used to reduce the input
inrush current during soft-start. The soft-start functionality is effective for approximately the first 5ms of start-up.
NOTE
The LM3477/A will not start-up if the output voltage is biased by more than 200mV above
ground.
NOTE
If the slope resistor RSL is used, the hysteretic threshold will be lowered. Therefore, the
LM3477/A may require up to 100mA of pre-load to successfully start up.
SHORT CIRCUIT PROTECTION
When the voltage across the sense resistor (measured as the VIN − ISEN differential voltage) exceeds VSC, shortcircuit current limit gets activated. In the short-circuit protection mode, the external MOSFET is turned off. When
the short is removed, the external MOSFET is turned on after five cycles. The short circuit protection voltage VSC
is specified in the Electrical Characteristics. VSC is lower in the LM3477A than in the LM3477.
SHUTDOWN
The compensation pin (Pin 2) of LM3477/A also functions as a shutdown pin. If a low signal (refer to the
Electrical Characteristics for definition of low signal) appears on the COMP/SD pin, the LM3477/A stops
switching and goes into a low supply current mode. The total supply current of the IC reduces to less than 10µA
under these conditions. Figure 23 shows different implementations of the shutdown function.
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COMP/SD
LM3477
+5V
OFF
0
SHUTDOWN
INPUT
ON
Figure 23. Implementing Shutdown in LM3477
VCC
+5V
SHUTDOWN
INPUT
OFF
0
ON
COMP/SD
LM3477
Figure 24. Implementing Shutdown in LM3477
Design Section
GENERAL
Power supply design involves making tradeoffs. To achieve performance specifications, limitations will be set on
component selection. The LM3477/A provides many degrees of flexibility in choosing external components to
accommodate various performance/component selection optimizations. For example, the internal slope
compensation can be externally increased to allow smaller inductances to be used. The design procedures that
follow provide instruction on how to select the external components in a typical LM3477/A buck circuit in
continuous conduction mode, as well as aid in the optimization of performance and/or component selection. See
Figure 25 for component reference and typical circuit. The LM3477/A may also be designed to operate in
discontinuous conduction mode.
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POWER STAGE
RSN
VIN
Q1
L
VOUT
CIN
R
RESR
LOAD
COUT
D
RFB1
RFB2
RSL
6
1
VSEN
+
DR
FB
ISEN
CB
LM3477
8
4
SW
3
7
5
CBOOT
RDR
VIN
GND
2
COMP/SD
CBYP
RC
CC1
COMPENSATION NETWORK
Figure 25. LM3477 Buck Converter Reference Schematic
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage can be programmed using a resistor divider between the output and the feedback pins, as
shown in Figure 25. The resistors are selected such that the voltage at the feedback pin is 1.27V. RFB1 and RFB2
can be selected using the equation:
VOUT = 1.27*(1+ RFB1/RFB2)
(4)
CALCULATING THE DUTY CYCLE
In buck converter applications, the duty cycle of the LM3477/A may be calculated as:
D=
VOUT + VD
VIN + VD - VQ -VSEN
|
VOUT
VIN
(5)
Where
VD = forward drop of the power diode ≊ 0.5V
VQ = VDS of the MOSFET when it is conducting ≊ IOUT*RDSON
VSEN = Voltage across the sense resistor = IOUT x RSN
This is the fraction of the switching period that the switch is on. The switch is off for the remainder of the period.
This fraction is expressed as:
D' = 1 − D
(6)
The LM3477/A has limits for the maximum and minimum duty cycle (see Electrical Characteristics). The
maximum duty cycle of 93% (typical) will limit how low the input voltage may drop while maintaining a regulated
output voltage (the dropout voltage). In situations where a very low dropout voltage is required, it is necessary to
include VD, VQ and VSN losses in the maximum duty cycle calculation. Voltage drops in the inductor will lower the
dropout voltage as well.
The LM3487 provides the FET drive voltage through the voltage developed across Cboot, which is charged when
the SW pin goes low. If Cboot cannot fully recharge, the device will automatically restart when the Cboot voltage
falls below approximately 2V. Therefore, a Cboot value of at least 0.1uF is recommended to ensure normal
operation at high duty cycles.
The minimum duty cycle of the LM3477/A corresponds to the minimum on time, or blank out time (see Electrical
Characteristics).
DMIN = TMIN* fs
(7)
This will not limit how high the input voltage can rise, however the LM3477/A will operate in hysteretic mode once
the operating duty cycle decreases to the minimum duty cycle.
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PROGRAMMING THE CURRENT LIMIT/HYSTERETIC THRESHOLD
Definitions
Current Limit: The current limit is the point at which the LM3477/A begins to limit the peak switch current. The
current limit in the LM3477/A varies with duty cycle, which is a function of the VIN − VOUT differential.
Hysteric Threshold: Hysteretic threshold is the current at which the LM3477/A enters the hysteretic mode of
operation (see OVER VOLTAGE PROTECTION). The hysteretic threshold is with respect to the peak switch
current.
SETTING CURRENT LIMIT AND HYSTERETIC THRESHOLD
The adjustable current limit of the LM3477/A is set by the sense resistor RSN. The voltage across RSN is
compared to an internal control voltage VC. The onset of current limiting is when VSEN(peak) equals VC(max), or VCL.
VSEN is defined here as the differential voltage from the VIN pin to the ISEN pin. VCL decreases as the duty cycle
increases, as shown in Figure 26. Therefore, it is important to know both VSEN(peak) and VCL(min) at the maximum
operating duty cycle, or lowest VIN condition.
xx
xx
xx
xx
200
VCL(D)
100
32
11
0
0
20
VCL(100)
VSEN(PEAK)
VSEN
Blank-out
Time
CONTROL VOLTAGE (mV)
VCL(0)
VHYS(LM3477)
VHYS(LM3477A)
40
60
80
100
DUTY CYCLE (%)
Figure 26. Current Limit and Hysteretic Threshold vs Duty Cycle
VSEN(PEAK) = RSN(IOUT(MAX) +
VOUT(1-DMAX)
) (V), RSL = 0
2 x L x fS
| RSN x IOUT(MAX)(1+ 0.15) (V)
VCL(MIN) = VCL(0)(MIN) − D(MAX) (VCL(0)(MIN) − VCL(100)(MIN))
(8)
(9)
where DMAX is the duty cycle at the lowest VIN condition.
To avoid current limit,
VSEN(peak) < VCL(MIN)
(10)
Therefore,
VCL(0)(MIN) - DMAX (VCL(0)(MIN) - VCL(100)(MIN))
RSN(MAX) =
VOUT(1-DMAX)
IOUT(MAX) +
|
2 x L x fS
VCL(0)(MIN) - DMAX (VCL(0)(MIN) - VCL(100)(MIN))
1.15 x IOUT(MAX)
(11)
Example: VIN(MIN) = 4.5V, VOUT = 2.5V, IOUT(MAX) = 3A
RSN(MAX)=
16
0.135 - 0.6 (0.135 - .025)
= 0.02:
1.15 (3)
(12)
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The hysteretic threshold is derived in a similar manner, the only difference being that VSEN(peak) is compared
VC(min) (VHYS). Notice that VHYS does not vary with the duty cycle. The hysteretic threshold is predetermined by
the selection of RSN above. The hysteretic threshold is:
IHYS =
VHYS 0.032
(A), LM3477
=
RSN
RSN
0.011
= R (A), LM3477A
SN
(13)
Continuing with the example above,
0.032
= 1.6A, LM3477
0.02
0.011
=
0.55A, LM3477A
0.02 |
IHYS =
(14)
If the peak switch current decreases below this threshold, the LM3477/A will operate in hysteretic mode (see
OVER VOLTAGE PROTECTION). In some designs, it will be desired to use RSL so that lower valued inductors
can be used (see DEFAULT/ADJUSTABLE SLOPE COMPENSATION and POWER INDUCTOR SECTION).
Using RSL will lower the current limit and the hysteretic threshold. See Figure 27. RSL effectively adds an
additional slope to the existing slope of the VC waveform.
xx
xx
xx
xx
VCL(D)
VCL(0)
100
32
11
0
0
VCL(100)
VSEN(PEAK)
VSEN
Blank-out
Time
CONTROL VOLTAGE (mV)
200
20
'VSL
'VSL
40
60
80
100
DUTY CYCLE (%)
Figure 27. Current Limit and Hysteretic Threshold vs Duty Cycle with RSL
When RSL is used, the following equations apply:
RSN(MAX) =
VCL(0)(MIN) - DMAX (VCL(0)(MIN) - (VCL(100)(MIN) - 50 x 10-6 x RSL))
IOUT +
|
VOUT(1-DMAX)
2 x L x fS
VCL(0)(MIN) - DMAX (VCL(0)(MIN) - (VCL(100)(MIN) - 50 x 10-6 x RSL))
1.15 x IOUT
(15)
-6
IHYS =
MAX (VHYS - 50 x 10 x RSL x DMAX, 0)
(A)
RSN
(16)
-6
where MAX(VHYS − 50x10 x RSL x DMAX, 0) is the smaller of the two values in the parenthesis and VHYS is
0.032V and 0.011V for the LM3477 and LM3477A, respectively. RSL can be used creatively to intentionally lower
the hysteretic threshold, allowing for better performance at lower loads. However, when RSL is used, there may
be a minimum load requirement (see START-UP/SOFT-START).
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POWER INDUCTOR SECTION
The LM3477/A operates at a high switching frequency of 500kHz, which allows the use of small inductors. This is
made apparent in the following set of equations used to calculate the output voltage ripple.
ΔVOUT(Pk-Pk) ≊ ΔiL(Pk-Pk) x RESR (V)
'iL(Pk-Pk) =
VOUT (1-D)
L x fS
(17)
(A)
(18)
As the switching frequency fs increases, the inductance required for a given output voltage ripple decreases. The
equations above for ΔVOUT and ΔiL provide criteria for choosing the inductance. The maximum voltage ripple in
steady-state, PWM operation can be controlled by limiting ΔiL which in turn is set by the inductance value.
Alternatively, one can simply choose ΔiL as a percentage of the maximum output current. Clearly, the size of the
output capacitor ESR, RESR, will have an affect on which criteria is used to choose the inductance. When the
ESR is relatively low (less than 100mΩ), such as in ceramic, OSCON, and some low ESR tantalum capacitors, it
is convenient to choose the inductance based on setting ΔiL to 30% of Iout(max). If the ESR is high, then it may
be necessary to restrict ΔiL to a lower value so that the output voltage ripple is not too high. Generally speaking,
the former suggestion of setting ΔiL to 30% of IOUT(MAX) is recommended.
The inductance also affects the stability of the converter. The slopes Sn and Sf in Figure 22 are functions of the
inductance, while the compensation ramp, Se, is fixed by default. Therefore if the inductance is too small, the
converter may experience sub-harmonic oscillations. The LM3477/A provides sufficient internal slope
compensation to allow for inductances chosen according to the ΔiL = 0.3 x IOUT guideline in most cases. Still, one
should check to make sure the inductance is not too low before continuing the design process. If it is found that
the selected inductance is too low, a patented scheme to increase the compensation ramp, Se, is provided in the
LM3477/A (see DEFAULT/ADJUSTABLE SLOPE COMPENSATION). In the calculations that follow, if it is found
that the chosen inductance is too small, RSL can be used to increase Se so that the inductance can be used.
In a current mode control architecture, there is an inherent resonance at half the switching frequency (see
DEFAULT/ADJUSTABLE SLOPE COMPENSATION ). A convenient indicator of how much resonance exists is
the quality factor Q. If Q is too high, subharmonic oscillations could occur, if Q is too low, the current mode
architecture begins to act like a voltage mode architecture and the necessary compensation becomes more
complex. This is discussed in more detail in Compensation, but here it is important to calculate Q to be sure the
selected inductance will not cause problems to the stability of the converter. The calculations below call for an
inductance that results in Q between 0.15 and 2. See Compensation if the chosen inductance enforces Q to be
out of this range. By default, no extra slope compensation is needed, so RSL = 0. In general, a Q between 0.5
and 1 is optimal.
Q=
1
S mc x D' - 0.5)
(19)
Where,
D' = 1−D
D=
(20)
VOUT + VD
VIN + VD - VQ -VSEN
mc = 1+
Se
Sn
|
VOUT
VIN
(21)
-6
= 1+
fSL(VSL+ 50 x 10 x RSL)
1.8RSNVIN D' - VQ -VSEN
fSL(VSL+ 50 x 10-6 x RSL)
| 1+
1.8RSNVIN D'
(22)
VQ = VDS of the MOSFET when it is conducting IOUT*RDS(ON).
1.8 = voltage gain of the current sense amp.
VSEN = Voltage across the sense resistor ≊ IOUT x RSN
Back solving for L gives a range for acceptable inductances based on a range for Q:
VIN1.8RSN (
1
+ D-0.5)
SQMAX
fS (VSL + 50 x 10-6 x RSL)
18
dLd
1
VIN1.8RSN ( SQMIN + D-0.5)
fS (VSL + 50 x 10-6 x RSL)
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It is recommended that:
Q(max) = 2, and
Q(min) = 0.15
Values for VSL can be found in the Electrical Characteristics.
Note: Adding slope compensation with RSL will decrease the current limit. An iterative process may be needed to
meet current limit and stability requirements, see PROGRAMMING THE CURRENT LIMIT/HYSTERETIC
THRESHOLD.
Output Capacitor Selection
A capacitance between 47µF - 100µF is typically used. Skip to CALCULATIONS FOR THE OUTPUT
CAPACITOR for minimum capacitance calculations.
TYPE OF OUTPUT CAPACITORS
Different type of capacitors often have different combinations of capacitance, equivalent series resistance (ESR),
and voltage ratings. High-capacitance multi-layer ceramic capacitors (MLCCs) have a very low ESR, typically
12mΩ, but also relatively low capacitance and low voltage ratings. Tantalum capacitors can have fairly low ESR,
such as 18mΩ, and high capacitance (up to 1mF) at higher voltage ratings than MLCCs. Aluminum capacitors
offer high capacitance and relatively low ESR and are available in high voltage ratings. OSCON capacitors can
achieve ESR values that are even lower than those of MLCCs and with higher capacitance, but the voltage
ratings are low. Other tradeoffs in capacitor technology include temperature stability, surge current capability, and
capacitance density (physical size vs. capacitance).
OUTPUT CAPACITOR CONSIDERATIONS
Skip to CALCULATIONS FOR THE OUTPUT CAPACITOR if a quick design is desired. While it is generally
desired to use as little output capacitance as possible to keep costs down, the output capacitor should be chosen
with care as it directly affects the ripple component of the output voltage as well as other components in the
design. The output voltage ripple is directly proportional to the ESR of the output capacitor (see POWER
INDUCTOR SECTION). Therefore, designs requiring low output voltage ripple should have an output capacitor
with low ESR. Choosing a capacitor with low ESR has the additional benefit of requiring one less component in
the compensation network, as discussed in Compensation.
In addition to the output voltage ripple, the output capacitor directly affects the output voltage overshoot in a load
transient. Two transients are possible: an unloading transient and a loading transient. An unloading transient
occurs when the load current transitions to a higher current, and charge is unloaded from the output capacitor. A
loading transient is when the load transitions to a lower current, and charge is loaded to the output capacitor.
How the output voltage reacts during these transitions is known as the transient response. Both the capacitance
and the ESR of the output capacitor will affect the transient response.
Figure 28. A Loading Transient
The control loop of the LM3477/A can be made fast enough to saturate the duty cycle when the worst case lode
transient occurs. This means the duty cycle jumps to DMIN or DMAX, depending on the type of load transient. In a
loading transient, as shown in Figure 28, the duty cycle drops to DMIN while the inductor current falls to match the
load current. During this time, the regulator is heavily dependent on the output capacitors to handle the load
transient. The initial overshoot is caused by the ESR of the output capacitors. How the output voltage recovers
after that initial excursion depends on how fast the inductor current falls and how large the output capacitance is.
See Figure 29.
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Voltage
'Vc1
'Vc2
Upper Voltage
Limit
VOS (MAX)
ESR too large
capacitance too small
0
Time
Figure 29. Output Voltage Overshoot Violation
The ESR and the capacitance of the output capacitor must be carefully chosen so that the output voltage
overshoot is within the design's specification VOS(MAX). If the total combined ESR of the output capacitors is not
low enough, the initial output voltage excursion will violate the specification, see ΔVC1. If the ESR is low enough,
but there is not enough output capacitance, the output voltage will travel outside the specification window due to
the extra charge being dumped into the capacitor, see ΔVC2. The LM3477/A has output over voltage protection
(OVP) which could trigger if the transient overshoot is high enough. If this happens, the controller will operate in
hysteretic mode (see OVER VOLTAGE PROTECTION) for a few cycles before the output voltage settles to its
steady state. If this behavior is not desired, substitute VOVP (referred to the output) for VOS(MAX) (VOVP is found in
the Electrical Characteristics) to find the minimum capacitance and maximum ESR of the output capacitor.
CALCULATIONS FOR THE OUTPUT CAPACITOR
During a loading transient, the delta output voltage ΔVc has two changing components. One is the voltage
difference across the ESR (ΔVr), the other is the voltage difference caused by the gained charge (ΔVq). This
gives:
ΔVc = ΔVr + ΔVq
(24)
The design objective is to keep ΔVc lower than some maximum overshoot (VOS(MAX)). VOS(MAX) is chosen based
on the output load requirements.
Both voltages ΔVr and ΔVqwill change with time. For ΔVr the equation is:
'Vr = RESR('IOUT(MAX) -
VOUT - DMINVIN
L
t) (V)
(25)
where,
RESR = the output capacitor ESR
ΔIOUT = the difference between the load current change IOUT(MAX) − IOUT(MIN)
DMIN = Minimum duty cycle of device (0.165 typical)
Evaluating this equation at t = 0 gives ΔVr(max). Substituting VOS(MAX) for ΔVr(MAX) and solving for RESR gives:
RESR(MAX) =
VOS(MAX)
'IOUT(MAX) :
(26)
The expression for ΔVq is:
'Vq =
'IOUT(MAX)
COUT
t-
VOUT - DMINVIN
2 X L X COUT
t2 (V)
(27)
From Figure 30 it can be told that ΔVC will reach its peak value at some point in time and then decrease. The
larger the output capacitance is, the earlier the peak will occur. To find the peak position, let the derivative of ΔVC
go to zero, and the result is:
tpeak =
'IOUT(MAX) x L
VOUT-DMINVIN
20
- COUTRESR
(28)
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Voltage
'Vc
'Vr
'Vq
0
tpeak
Time
Figure 30. Output Voltage Overshoot Peak
The intention is to find the capacitance value that will yield, at tpeak, a ΔVC that equals VOS(max). Substituting tpeak
for t and equating ΔVC to VOS(max) gives the following solution for COUT(MIN):
VOS(MAX)2 - ('IOUT(MAX) x RESR)2
L VOS(MAX)COUT(MIN)=
(VOUT) RESR2
(F)
(29)
The chosen output capacitance should not be less than 47µF, even if the solution for COUT(MIN) is less than 47µF.
Notice it is already assumed that the total ESR is no greater than RESR(MAX), otherwise the term under the square
root will be a negative number.
Power Mosfet Selection
The drive pin of LM3477/A must be connected to the gate of an external MOSFET. In a buck topology, the drain
of the external N-Channel MOSFET is connected to the input and the source is connected to the inductor. The
CB pin voltage provides the gate drive needed for an external N-Channel MOSFET. The gate drive voltage
depends on the input voltage (see Typical Performance Characteristics). In most applications, a logic level
MOSFET can be used. For very low input voltages, a sub-logic level MOSFET should be used.
The selected MOSFET directly controls the efficiency. The critical parameters for selection of a MOSFET are:
1. Minimum threshold voltage, VTH(MIN)
2. On-resistance, RDS(ON)
3. Total gate charge, Qg
4. Reverse transfer capacitance, CRSS
5. Maximum drain to source voltage, VDS(MAX)
The off-state voltage of the MOSFET is approximately equal to the input voltage. VDS(MAX) of the MOSFET must
be greater than the input voltage. The power losses in the MOSFET can be categorized into conduction losses
and ac switching or transition losses. RDS(ON) is needed to estimate the conduction losses. The conduction loss,
PCOND, is the I2R loss across the MOSFET. The maximum conduction loss is given by:
>
PCOND(MAX) = I2DMAX 1+ 1
12
'i(PK-PK)
I
2
@R
DS(ON)
(30)
where DMAX is the maximum operating duty cycle:
Dmax |
VOUT
VIN(MIN)
(31)
The turn-on and turn-off transition times of a MOSFET from the MOSFET specifications require tens of nanoseconds. CRSS and Qg are needed from the MOSFET specifications to estimate the large instantaneous power
loss that occurs during these transitions.
The average amount of gate current required to turn the MOSFET on can be calculated using the formula:
IG = Qg.FS
(32)
The required gate drive power to turn the MOSFET on is equal to the switching frequency times the energy
required to deliver the charge to bring the gate charge voltage to VDR (see Electrical Characteristics and Typical
Performance Characteristics for the drive voltage specification).
PDrive = FS.Qg.VDR
(33)
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It is sometimes helpful or necessary to slow down the turn on transition of the FET so that less switching noise
appears at the ISEN pin. This can be done by inserting a drive resistor RDR in series with the boot-strap capacitor
(see Figure 25). This can help reduce sensing noise that may be preventing designs from operating at or near
the LM3477/A's minimum duty cycle limit. Gate drive resistors from 2.2Ω to 51Ω are recommended.
Power Diode Selection
The output current commutates through the diode when the external MOSFET turns off. The three most
important parameters for the diode are the peak current, peak inverse voltage, and average power dissipation.
Exceeding these ratings can cause damage to the diode. The average current through the diode is given by:
ID(AVG) = IOUT x (1-D)
(34)
where D is the duty cycle and IOUT is the output current. The diode must be rated to handle this current.
The off-state voltage across the diode in a buck converter is approximately equal to the input voltage. The peak
inverse voltage rating of the diode must be greater than the off-state voltage of the diode. To improve efficiency,
a low forward drop schottky diode is recommended.
Input Capacitor Selection
In a buck converter, the high side switch draws large ripple currents from the input capacitor. The input capacitor
must be rated to handle this RMS current.
IRMS_CIN = IOUT
VOUT(VIN-VOUT)
VIN
(35)
The power dissipated in the input capacitor is given by:
PD(CIN)=IRMS_CIN2RESR_CIN,
where RESR_CIN is the ESR of the input capacitor. The input capacitor must be selected to handle the rms current
and must be able to dissipate the power. PD(CIN) must be lower than the rated power dissipation of the selected
input capacitor. In many cases, several capacitors have to be paralleled to handle the rms current. In that case,
the power dissipated in each capacitor is given by:
PD(CIN) = (I2RMS_CINRESR_CIN)/n2, where n is the total number of capacitors paralled at the input.
A 0.1µF or 1µF ceramic bypass capacitor is also recommended on the VIN pin (pin 8) of the IC. This capacitor
must be connected very close to pin 8.
Compensation
VREF
VC
+
VO
+
-
Fc(s)
Compensator
Fp(s) x Fh(s)
Power Stage
Loop (T)
H
Feedback
Figure 31. Control Block Diagram of a Current Mode Controlled Buck Converter
The LM3477/A is a current mode controller, therefore the control block diagram representation involves 2
feedback loops (see Figure 31). The inner feedback loop derives its feedback from the sensed inductor current,
while the outer loop monitors the output voltage. This section will not give a rigorous analysis of current mode
control, but rather a simplified but accurate method to determine the compensation network. The first part reveals
the results of the model, giving expressions for solving for component values in the compensation network.
22
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The compensation network is designed around the power components, or the power stage. An isolated
schematic of the error amplifier and the various compensation components is shown in Figure 32. The error
amplifier in conjunction with the compensation network makes up the compensator block in Figure 31. The
purpose of the compensator block is to stabilize the control loop and achieve high performance in terms of the
transient response, audio susceptibility and output impedance.
VOUT
CFF
LM3477
RFB1
GM
+
FB
RFB2
RGM
BG
VC
RC
CC2
CC1
Figure 32. LM3477 Compensation Components
Figure 33 shows a bode plot of a typical current mode buck regulator. It is an estimate of the actual plot using the
asymptotic approach. The three plots shown are of the compensator, powerstage, and loop gain, which is the
product of the power stage, compensator, and feedback gain. The loop gain determines both static and dynamic
performance of the converter. The power stage response is fixed by the selection of the power components,
therefore the compensator is designed around the powerstage response to achieve a good loop response.
Specifically, the compensator is added to increase low frequency magnitude, extend the 0dB frequency
(crossover frequency), and improve the phase characteristic.
Open Loop (T)
Compensator
Power Stage
60
20
R
f n f ES
fC
0
f P1
-20
f Z1
f P2
-40
0
-60
-45
-90
-135
m
PHASE (º)
MAGNITUDE (dB)
40
-180
102
103
104
105
106
-225
107
FREQUENCY (Hz)
Poles, Zeros and Important Measurements are Labeled
Figure 33. Typical Open Loop, Compensator, and Power Stage Bode Plots for LM3477 Buck Circuits
There are several different types of compensation that can be used to improve the frequency response of the
control loop. To determine which compensation scheme to use, some information about the power stage is
needed.
Use VIN = VIN(MIN) and R = RMIN (IOUT(MAX)) when calculating compensation components.
H = feedback gain =
RFB2
RFB1 + RFB2
(36)
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LM3477
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ADC =
R
1.8RSN
www.ti.com
1
R
1+
fSL mc x D' - 0.5
(37)
Se
mc = 1+ S
n
(38)
(39)
Se = fS(VSL + 50x10−6 RSL)
Sn =
VIND' x 1.8RSN
L
(40)
1
1
1
(mc x D' - 0.5) (Hz)
+
fp1 =
2S COUTR fsLCOUT
fESR =
1
2SCOUTRESR
(41)
(Hz)
(42)
1
Q=
S mc x D' - 0.5)
(43)
With the power stage known, a compensator can be designed to achieve improved performance and stability.
The LM3477/A will typically require only a single resistor and capacitor for compensation, but depending on the
power stage it could require three or four external components.
It is a good idea to check that Q is between 0.15 and 2, if it was not already done when selecting the inductor. If
Q is less than 0.15 or greater than 2, skip to SAMPLING POLE QUALITY FACTOR before continuing with the
compensator design.
First, a target crossover frequency (fc) for the loop gain must be selected. The crossover frequency is the
bandwidth of the converter. A higher bandwidth generally corresponds to faster response times and lower
overshoots to load transients. However, the bandwidth should not be much higher than 1/10 the switching
frequency. The LM3477/A operates with a 500kHz switching frequency, so it is recommended to choose a
crossover frequency between 10kHz - 50kHz.
The schematic of the LM3477/A compensator is shown in Figure 32. The default design uses Rc and CC1 to form
a lag (type 2) compensator. The CC2 capacitor can be added to form an additional pole that is typically used to
cancel out the esr zero of the output capacitor. Finally, if extra phase margin is needed, the Cff capacitor can be
added (this does not help at low output voltages, see below).
The strategy taken here for choosing Rc and CC1 is to set the crossover frequency with Rc, and set the
compensator zero with CC1. Using the selected target crossover frequency, fC, set RC to:
RC =
fC x RGM
ADC x GM x RGM x H x fP1 - fC
:
(44)
fC = Crossover frequency in Hertz (20kHz - 50kHz is recommended)
RGM = 50x103Ω
GM = 1000x10−6 A/V
The compensator zero, fZ1, is set with CC1. When fast transient responses are desired, fZ1 should be placed as
high as possible, however it should not be higher than the selected crossover frequency fC. The guideline
proposed here is to choose CC1 such that fZ1 falls somewhere between the power pole fP1 and ½ decade before
the selected crossover frequency fc:
3.16 d
1
CC1d
2Sfp1RC
2SfCRC
(45)
In this compensation scheme, the pole created by CC2 is used to cancel out the zero created by the ESR of the
output capacitor. In other schemes such as the methods discussed in SAMPLING POLE QUALITY FACTOR, the
ESR zero is used. For the typical case, use CC2 if:
fESR < fS
2
24
(46)
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RGM + RC
CC2 =
SfESR RGMRC
(F)
(47)
PLOTTING THE OPEN LOOP RESPONSE
The open loop response is expressed as:
T = ADC x ACM x H x Fp(s) x Fc(s)
Where ADC and H are given above and
ACM = GM x RGM
1+
s
SfESR
1+
s
Sfp1
FP(S) =
Fh(s) =
FC(s) =
2
(48)
1
1
1
s2 Sf + s Sf Q + 1
s
s
(49)
(sCC1RC + 1)
sCC1RGM (RGM + RC) + 1
FC(s) =
, CC2 not used
(50)
(sCC1RC + 1)
s2CC1CC2RCRGM + s(CC2RGM + CC1(RGM + RC)) + 1
, CC2 used
(51)
One can plot the magnitude and phase of the open loop response to analyze the frequency response.
EXAMPLE: COMPENSATION DESIGN
4.5V ≤ VIN ≤ 5.5V
VOUT = 2.5V
IOUT = 3A (R = 0.83Ω)
RSN = 0.02Ω
L = 3.3µH
RSL = 0Ω
COUT = 100µF
RESR = 0.01Ω
First, calculate the power stage parameters using VIN(MIN) and R(MAX):
H = feedback gain =
0.83
ADC =
1.8 x 0.02
1.27
= 0.508
2.5
(52)
1
1+
0.83
(500 x 103)(3.3 x 10-6)
= 15.5
[(3.36(0.44) - 0.5]
(53)
1
1
1
fp1 =
2S (100 x 10-6)(0.83) + (500 x 103)(3.3 x 10-6)(100 x 10-6)
> (3.36)(0.44) - 0.5 @
= 2.86 kHz
(54)
1
fESR =
= 159kHz
2S(100 x 10-6)(0.01)
Q=
(55)
1
= 0.33
S[(3.36)(0.44) - 0.5]
(56)
In this example, a crossover frequency of 20kHz is chosen, so: fC = 20000. RC is now calculated using the power
stage information and the target crossover frequency fC:
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LM3477
SNVS141K – OCTOBER 2000 – REVISED MARCH 2013
RC =
www.ti.com
(20 x 103)(50 x 103)
(15.5)(0.001)(50 x 103)(0.508)(2.86 x 103) - (20 x 103)
= 904:
(57)
This sets the high frequency gain of the compensator such that a crossover frequency of fC is obtained. The
capacitor CC1 sets the compensator zero, fZ2. Set fZ2 between the power pole fP1 and the ½ decade before the
target crossover frequency fC:
3.16
1
d CC1 d
2S(2.86 x 103)(900)
2S(20 x 103)(900)
28 nF d CC1 d 62 nF
(58)
−9
Choosing CC1 = 62 x 10 F will set fZ2 = fP1, canceling out the power pole and insuring a −20dB/decade slope in
the low frequency magnitude response. In other words, the phase margin below the crossover frequency will
always be higher than the phase margin at the crossover frequency.
If better transient response times are desired, a second method is to set fZ2 between fP1 and ½ decade before fC,
the target crossover frequency. This trades more low frequency gain for less phase margin, which translates to
faster but more oscillatory step responses. We pick CC1 = 47nF.
If the esr zero of the output capacitor (fESR) is too low or if more phase margin is required, additional components
may be added to increase the flexibility of the compensator.
Use CC2 if fESR < ½ fS, that is if:
1
< 250kHz
2SCOUTRESR
(59)
For this example, fESR = 159 kHz, so use CC2.
CC2 =
50 x 103 + 900
2S (.159 x 103) (50 x 103) (900)
= 1.1 nF
(60)
The equations used here for RC, CC1, and CC2 are approximations valid when CC2 << CC1. For exact equations,
see PLOTTING THE OPEN LOOP RESPONSE. In some cases, the desired inductance is several times higher
than the optimal inductance set by the internal slope compensation. This results in a Q lower than 0.15, in which
case additional methods of compensating are presented (see SAMPLING POLE QUALITY FACTOR).
BW = 16.7 kHz
PM = 61 degrees
40
20
0
-20
-40
0
-60
-50
-100
-150
-180
-200
101
102
103
104
105
PHASE ( )
MAGNITUDE (dB)
60
-250
106
Frequency (Hz)
Figure 34. Open Loop Frequency Response for LM3477 Compensation Design Example
26
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SAMPLING POLE QUALITY FACTOR
In a current mode control architecture, there is an inherent resonace at half the switching frequency. The
LM3477/A internally compensates for this by adding a negative slope to the PWM control waveform (see
DEFAULT/ADJUSTABLE SLOPE COMPENSATION). The factor in the power stage equations above, Q,
describes how much resonance will be observed. Q is a function of duty cycle and mc. Figure 35 shows how the
power stage bode plot is affected as Q is varied from 0.01 to 10. The resonance is caused by two complex poles
at half the switching frequency. If mc is too low, the resonant peaking could become severe coinciding with
subharmonic oscillations in the inductor current. If mc is too high, the two complex poles split and the converter
begins to act like a voltage mode converter and the compensation scheme used above should be changed.
Plotted Q values: 0.01, 0.05, 0.1, 0.2, 0.5, 1, 2, 10
Q = 10
0
-40
-80
Q = 0.01
-120
0
Q = 10
-50
-100
-150
-200
Q = 0.01
PHASE (°)
MAGNITUDE (dB)
40
-250
102
103
104
105
106
-300
107
FREQUENCY (Hz)
The Quality Factor Q of the Two Complex Poles is used to qualify how much resonant peaking is observed in the
Power Stage Bode Plot
Figure 35.
If Q>2, the sampling poles are imaginary and are approaching the right half of the imaginary plane (the system is
becoming unstable). In this case, Q must be decreased by either increasing the inductance, or more preferably,
adding more slope compensation through the RSL resistor (see DEFAULT/ADJUSTABLE SLOPE
COMPENSATION).
If Q<0.15, it means that one of the sampling poles is decreasing in frequency towards the dominant power pole,
fp1. There are three ways to compensate for this. Decrease the crossover frequency, add a phase lead network,
or use the output capacitor's ESR to cancel out the low frequency sampling pole.
One option is to decrease the crossover frequency so that the phase margin is not as severely decreased by the
sampling pole. Decreasing the crossover frequency to between 1kHz to 10kHz is advisable here. As a result,
there will be a decrease in transient response performance.
Another option is the use of the feed-forward capacitor, Cff. This will provide a positive phase shift (lead) which
can be used to increase phase margin. However, it is important to note that the effectiveness of Cff decreases
with output voltage. This is due to the fact that the frequencies of the zero fzff and pole fpff get closer together as
the output voltage is reduced.
The frequency of the feed-forward zero and pole are:
fzff =
fpff =
1
(Hz)
2SRFB1Cff
1
2SRFB1Cff
RFB1 + RFB2
RFB2
(61)
= fzff
VOUT
VFB
(Hz)
(62)
A third option is to strategically place the ESR zero fESR of the output capacitor to cancel out the sampling pole.
In this case, the capacitor CC2 will not be used to cancel out fESR. fESR should be placed around the crossover
frequency fc, but this will depend on how low Q is.
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LM3477
SNVS141K – OCTOBER 2000 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision J (March 2013) to Revision K
•
28
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM3477AMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S13A
LM3477AMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S13A
LM3477MM
NRND
VSSOP
DGK
8
1000
TBD
Call TI
Call TI
-40 to 125
S13B
LM3477MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S13B
LM3477MMX
NRND
VSSOP
DGK
8
3500
TBD
Call TI
Call TI
-40 to 125
S13B
LM3477MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S13B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-Dec-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM3477AMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3477AMMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3477MM
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3477MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3477MMX
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3477MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3477AMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM3477AMMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LM3477MM
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM3477MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM3477MMX
VSSOP
DGK
8
3500
367.0
367.0
35.0
LM3477MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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