STMicroelectronics M95512-D-WCS3G/AB 512 kbit serial spi bus eeprom with high-speed clock Datasheet

M95512-DR
M95512-R M95512-W
512 Kbit serial SPI bus EEPROM
with high-speed clock
Features
■
Compatible with the Serial Peripheral Interface
(SPI) bus
■
Memory array
– 512 Kb (64 Kbytes) of EEPROM
– Page size: 128 bytes
■
Additional Write lockable Page (Identification
page)
■
Write
– Byte Write within 5 ms
– Page Write within 5 ms
■
Write Protect: quarter, half or whole memory
array
■
High-speed clock frequency (20 MHz)
■
Single supply voltage: 1.8 V to 5.5 V
■
More than 1 Million Write cycles
■
More than 40-year data retention
■
Enhanced ESD Protection
■
Packages
– ECOPACK2® (RoHS compliant and
Halogen-free)
SO8 (MN)
150 mils width
TSSOP8 (DW)
169 mils width
UFDFPN8 (MB)
2 × 3 mm (MLP)
WLCSP (CS)
September 2010
Doc ID 11124 Rev 13
1/48
www.st.com
1
Contents
M95512-W, M95512-R
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
4.1.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
2/48
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M95512-W, M95512-R
Contents
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7
Read Identification Page (available only in M95512-DR devices) . . . . . . 25
6.8
Write Identification Page (available only in M95512-DR devices) . . . . . . 26
6.9
Read Lock Status (available only in M95512-DR devices) . . . . . . . . . . . . 27
6.10
Lock ID (available only in M95512-DR devices) . . . . . . . . . . . . . . . . . . . . 27
7
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 29
8
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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List of tables
M95512-W, M95512-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
4/48
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
M95512-W and M95512-R instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M95512-DR instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating conditions (M95512-W device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating conditions (M95512-W device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating conditions (M95512-R and M95512-DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC characteristics (current M95512-W products). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC characteristics (new M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 33
AC characteristics (current M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC characteristics (New M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 36
SO8N – 8 lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 40
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3 .mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
WLCSP-R – 8-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . 42
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Available M95512 products (package, voltage range, temperature grade) . . . . . . . . . . . . 44
Available M95512-DR products (package, voltage range, temperature grade) . . . . . . . . . 44
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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M95512-W, M95512-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO8, TSSOP8 and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39
TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 40
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
WLCSP-R – 8-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . 42
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Description
1
M95512-W, M95512-R
Description
The M95512-W, M95512-R and M95512-DR are electrically erasable programmable
memory (EEPROM) devices accessed by a high-speed SPI-compatible bus. In the rest of
the document these devices are referred to as M95512, unless otherwise specified.
The M95512-DR also offers an additional page, named the Identification Page (128 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as it can be used to store
unique identification parameters and/or parameters specific to the production line.
Figure 1.
Logic diagram
6##
$
1
#
3
-
7
(/,$
633
AI
The memory array is organized as 65536 × 8 bit. The device is accessed by a simple serial
interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and
Figure 1.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
6/48
Doc ID 11124 Rev 13
M95512-W, M95512-R
Table 1.
Description
Signal names
Signal name
Caution:
Function
Direction
C
Serial Clock
Input
D
Serial Data Input
Input
Q
Serial Data Output
Output
S
Chip Select
Input
W
Write Protect
Input
HOLD
Hold
Input
VCC
Supply voltage
VSS
Ground
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
Figure 2.
SO8, TSSOP8 and UFDFPN8 connections
-
3
1
7
633
6##
(/,$
#
$
AI
1. See Section 11: Package mechanical data for package dimensions, not and how to identify pin-1.
Figure 3.
WLCSP connections (top view, marking side, with balls on the underside)
6##
$
#
7
(/,$
1
633
3
AI
Doc ID 11124 Rev 13
7/48
Signal description
2
M95512-W, M95512-R
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Table 13 and Table 15). These signals are described next.
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
8/48
Doc ID 11124 Rev 13
M95512-W, M95512-R
2.6
Signal description
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
Doc ID 11124 Rev 13
9/48
Connecting to the SPI bus
3
M95512-W, M95512-R
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI Bus Master
SPI Memory
Device
R
CS3
VCC
C Q D
VSS
C Q D
VCC
VSS
SPI Memory
Device
R
VSS
SPI Memory
Device
R
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one device is selected at a time, so only one device drives the Serial Data Output (Q)
line at a time, the other devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that no device is selected if the Bus
Master leaves the S line in the high impedance state.
In applications where the Bus Master might enter a state where all inputs/outputs SPI lines
are in high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high). This ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met.
The typical value of R is 100 k,.
10/48
Doc ID 11124 Rev 13
M95512-W, M95512-R
3.1
Connecting to the SPI bus
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
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Operating features
M95512-W, M95512-R
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8 and
Table 10.). This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
4.1.2
Device reset
In order to prevent inadvertent Write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC has
reached the POR threshold voltage (this threshold is lower than the minimum VCC operating
voltage defined in Table 8 and Table 10).
When VCC passes over the POR threshold, the device is reset and in the following state:
●
in the Standby Power mode
●
deselected (note that when the device is deselected it is necessary to apply a falling
edge on Chip Select (S) prior to issuing any new instruction, otherwise the instruction is
not executed)
●
Status register values:
–
the Write Enable Latch (WEL) bit is reset to 0
–
the Write In Progress (WIP) bit is reset to 0
–
the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode, however, the device must not be accessed until VCC reaches a valid and
stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8 and
Table 10.
4.1.3
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 8 and Table 10 and the rise time must not vary faster than 1 V/µs.
12/48
Doc ID 11124 Rev 13
M95512-W, M95512-R
4.1.4
Operating features
Power-down
During power-down (continuous decrease in VCC below the minimum VCC operating voltage
defined in Table 8 and Table 10), the device must be:
4.2
●
deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC)
●
in Standby Power mode (that is there should not be any internal write cycle in
progress).
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC, as specified in Table 15.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption
drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 6).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
Figure 6.
Hold condition activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
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Operating features
4.4
M95512-W, M95512-R
Status register
Figure 7 shows the position of the Status register in the control logic of the device. The
Status register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status register bits
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
●
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-protected block size
Status register bits
14/48
Protected block
Protected array
addresses
BP1
BP0
0
0
none
none
0
1
Upper quarter
C000h - FFFFh
1
0
Upper half
8000h - FFFFh
1
1
Whole memory
0000h - FFFFh
Doc ID 11124 Rev 13
M95512-W, M95512-R
Memory organization
The memory is organized as shown in Figure 7.
Figure 7.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
Y Decoder
5
Memory organization
1 Page
X Decoder
AI01272C
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Instructions
6
M95512-W, M95512-R
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
Table 3.
M95512-W and M95512-R instruction set
Instruction
Description
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Table 4.
M95512-DR instruction set
Instruction
Description
Instruction
format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Read Identification
Reads the page dedicated to identification.
Page
1000 0011(1)
Write Identification
Writes the page dedicated to identification.
Page
1000 0010(1)
Read Lock Status
Reads the lock status of the Identification Page.
1000 0011(2)
Lock ID
Locks the Identification page in read-only mode.
1000 0010(2)
1. Address bit A10 must be 0, all other address bits are Don't Care.
2. Address bit A10 must be 1, all other address bits are Don't Care.
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Instruction format
Doc ID 11124 Rev 13
M95512-W, M95512-R
6.1
Instructions
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 8.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
Figure 9.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
AI03750D
Q
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Instructions
6.3
M95512-W, M95512-R
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 10.
The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 5) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.
Status register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
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M95512-W, M95512-R
Instructions
Figure 10. Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
MSB
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
Doc ID 11124 Rev 13
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Instructions
6.4
M95512-W, M95512-R
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before a WRSR instruction can be accepted, a Write Enable (WREN) instruction
must have been executed.
The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low,
sending the instruction code and the data byte on Serial Data input (D) and driving Chip
Select (S) high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C)
that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock
(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write
cycle whose duration is tW (specified in Table 16 and Table 18). The instruction sequence is
shown in Figure 11.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset when the Write cycle tW is complete.
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 and SRWD bits:
●
The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only,
as defined in Table 6.
●
The SRWD bit (Status Register Write Disable bit), depending on the signal applied on
the Write Protect pin (W), allows the user to set or reset the write protection mode of
the Status Register. When the Status Register is in the Write-protected mode, the Write
Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR
instruction (after tW).
The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5,
b4, b1, b0. They are always read as 0.
Figure 11. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
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M95512-W, M95512-R
Instructions
Table 6.
Protection modes
W
SRWD
Signal
Bit
1
0
0
0
1
1
0
1
Mode
Write Protection of the
Status Register
Memory content
Protected area(1)
Unprotected area(1)
Status Register is Writable
Software (if the WREN instruction
Protected has set the WEL bit)
Write Protected
(SPM) The values in the BP1 and
BP0 bits can be changed
Ready to accept
Write instructions
Status Register is
Hardware Hardware write protected
Protected The values in the BP1 and Write Protected
(HPM) BP0 bits cannot be
changed
Ready to accept
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W) input pin:
●
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction.
●
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction (attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area that are software-protected (SPM) by the Block
Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against
data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered either:
●
by setting the SRWD bit after driving the Write Protect (W) input pin low
●
or by driving the Write Protect (W) input pin low after setting the SRWD bit
Once entered, the Hardware-protected mode (HPM) can only be exited by pulling Write
Protect (W) high.
If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can
never be activated, and only the Software-protected mode (SPM) using the Block Protect
(BP1, BP0) bits in the Status Register, can be used.
Doc ID 11124 Rev 13
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Instructions
6.5
M95512-W, M95512-R
Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 12. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
1
0
MSB
Data Out 1
High Impedance
7
Q
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI01793D
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M95512-W, M95512-R
6.6
Instructions
Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle triggered by the rising edge of Chip Select (S) continues for
a period tW (as specified in Table 16 and Table 18), at the end of which the Write in Progress
(WIP) bit is reset to 0.
In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in Figure 14., the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 128 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
Note:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 13. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI01795D
Doc ID 11124 Rev 13
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Instructions
M95512-W, M95512-R
Figure 14. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
AI01796D
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M95512-W, M95512-R
6.7
Instructions
Read Identification Page (available only in M95512-DR
devices)
The Identification Page (128 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see Table 4).
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits
[A15:A11] and [A9:A7] are Don't Care, and the data byte pointed to by [A6:A0] is shifted out
on Serial Data output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out. The number of bytes to
read in the ID page must not exceed the page boundary (e.g.: when reading the ID page
from location 90d, the number of bytes should be less than or equal to 38d, as the ID page
boundary is 128 bytes).
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 15. Read Identification Page sequence
3
#
)NSTRUCTION
BIT ADDRESS
$
-3"
$ATA /UT (IGH IMPEDANCE
1
$ATA /UT -3"
!I
Doc ID 11124 Rev 13
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Instructions
6.8
M95512-W, M95512-R
Write Identification Page (available only in M95512-DR
devices)
The Identification Page (128 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. Writing this page is achieved with the Write
Identification Page instruction (see Table 4), the Chip Select signal (S) is first driven low. The
bits of the instruction byte, address byte, and at least one data byte are then shifted in on
Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are
Don't Care, the [A6:A0] address bits define the byte address inside the identification page.
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed write cycle triggered by the rising edge of Chip Select (S) continues for
a period tW (as specified in Table 17 and Table 18), at the end of which the Write in Progress
(WIP) bit is reset to 0.
In the case of Figure 16, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 16, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle. Each time
a new data byte is shifted in, the least significant bits of the internal address counter are
incremented. If the number of data bytes sent to the device exceeds the page boundary, the
internal address counter rolls over to the beginning of the page, and the previous data there
are overwritten with the incoming data. (The page size of these devices is 128 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a
Write Enable instruction)
●
if Status register bits (BP1, BP0) = (1, 1)
●
if a write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that was latched in)
●
if the Identification page is locked by the Lock Status bit
Figure 16. Write Identification Page sequence
3
#
)NSTRUCTION
$
BIT ADDRESS
$ATA BYTE
(IGH IMPEDANCE
1
!I
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Doc ID 11124 Rev 13
M95512-W, M95512-R
6.9
Instructions
Read Lock Status (available only in M95512-DR devices)
The Read Lock Status instruction (see Table 4) allows to check if the Identification Page is
locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip
Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted
in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care.
The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is
at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S)
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by
driving Chip Select (S) high.
The instruction sequence is shown in Figure 17.
Figure 17. Read Lock Status sequence
3
#
)NSTRUCTION
BIT ADDRESS
$
-3"
$ATA /UT (IGH IMPEDANCE
1
$ATA /UT -3"
!I
6.10
Lock ID (available only in M95512-DR devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't
Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is tW (specified in Table 17 and Table 18). The instruction sequence is
shown in Figure 18.
Doc ID 11124 Rev 13
27/48
Instructions
M95512-W, M95512-R
The instruction is not accepted, and so not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a
Write Enable instruction)
●
if Status register bits (BP1,BP0) = (1,1)
●
if a write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that was latched in)
●
if the Identification page is locked by the Lock Status bit
Figure 18. Lock ID sequence
3
#
)NSTRUCTION
$
BIT ADDRESS
$ATA BYTE
(IGH IMPEDANCE
1
!I
28/48
Doc ID 11124 Rev 13
M95512-W, M95512-R
7
ECC (error correction code) and write cycling
ECC (error correction code) and write cycling
The M95512-W, M95512-R and M95512-DR devices offer an ECC (error correction code)
logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a
result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation,
the ECC detects it and replaces it by the correct value. The read reliability is therefore much
improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by words of 4 bytes in order to
benefit from the larger amount of Write cycles.
The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000)
Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.
8
Power-up and delivery state
8.1
Power-up state
After power-up, the device is in the following state:
●
Standby Power mode
●
Deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
●
Not in the Hold Condition
●
Write Enable Latch (WEL) is reset to 0
●
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
8.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Doc ID 11124 Rev 13
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Maximum rating
9
M95512-W, M95512-R
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Ambient temperature with power applied
–40
Storage temperature
–65
Lead temperature during soldering
see note
Min.
Max.
130
°C
150
°C
(1)
°C
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
6.5
V
IOL
DC output current (Q = 0)
-
5
mA
IOH
DC output current (Q = 1)
–5
-
mA
VCC
Supply voltage
–0.50
6.5
V
VESD
Electrostatic discharge voltage (human
body model)(2)
–3000
+3000
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100pF, R1=1500 , R2=500 )
30/48
Doc ID 11124 Rev 13
Unit
M95512-W, M95512-R
10
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (M95512-W device grade 6)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
125
°C
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Operating conditions (M95512-W device grade 3)
Symbol
VCC
TA
Table 10.
Parameter
Operating conditions (M95512-R and M95512-DR)
Symbol
VCC
TA
Table 11.
Parameter
AC measurement conditions
Symbol
CL
Parameter
Min.
Load capacitance
Max.
30
Input Rise and Fall times
Unit
pF
50
ns
Input Pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
Figure 19. AC measurement I/O waveform
Input Levels
0.8VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
0.2VCC
AI00825B
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DC and AC parameters
Table 12.
M95512-W, M95512-R
Capacitance(1)
Symbol
Parameter
COUT
Test condition
Max.
Unit
VOUT = 0 V
8
pF
Input capacitance (D)
VIN = 0 V
8
pF
Input capacitance (other pins)
VIN = 0 V
6
pF
Output capacitance (Q)
CIN
Min.
1. Not 100% tested.
Table 13.
Symbol
DC characteristics (current(1) M95512-W products)
Test conditions: VCC = 2.5 to 5.5 V at
TA = –40 to 85 °C (device grade 6)
or TA = –40 to 125 °C (device grade 3)
Parameter
ILI
Input leakage current
ILO
Output leakage current
ICC
Supply current (Read)
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
3
mA
C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5
V, Q = open
5
mA
ICC0(2)
Supply current (Write)
During tW, S = VCC,
2.5 V < VCC < 5.5 V
6
mA
ICC1
Supply current
(Standby Power mode)
S = VCC, VIN = VSS or VCC,
2.5 V < VCC < 5.5 V
5
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
VCC = 2.5 V and IOL = 1.5 mA or
VCC = 5 V and IOL = 2 mA
0.4
V
VOH
Output high voltage
VCC = 2.5 V and IOH = –0.4 mA or
VCC = 5 V and IOH = –2 mA
1. Current products are identified by AB process letters AB.
2. Characterized value, not tested in production.
32/48
Min.
Doc ID 11124 Rev 13
0.8 VCC
V
M95512-W, M95512-R
Table 14.
Symbol
DC characteristics (new(1) M95512-W products)
Parameter
ILI
Input leakage current
ILO
Output leakage current
ICC
DC and AC parameters
Supply current (Read)
Test conditions: VCC = 2.5 to 5.5 V,
TA = –40 to 85 °C
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 2.5 V, Q = open
4
mA
C = 0.1VCC/0.9VCC at 20 MHz, VCC = 5 V,
Q = open
8
mA
ICC0(2)
Supply current (Write)
During tW, S = VCC, 2.5 V < VCC < 5.5 V
6
mA
ICC1
Supply current
(Standby Power mode)
S = VCC, VIN = VSS or VCC,
2.5 V < VCC < 5.5 V
5
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
VCC = 2.5 V and IOL = 1.5 mA or
VCC = 5 V and IOL = 2 mA
0.4
V
VOH
Output high voltage
VCC = 2.5 V and IOH = –0.4 mA or
VCC = 5 V and IOH = –2 mA
0.8 VCC
V
1. New products are identified by process letter K.
2. Characterized value, not tested in production.
Table 15.
Symbol
DC characteristics (current and new M95512-R and M95512-DR products)
Parameter
ILI
Input leakage current
ILO
Output leakage current
ICC
ICC0(3)
Supply current (Read)
Supply current (Write)
Test conditions:
Max
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 2 MHz, VCC = 1.8 V,
Q = open(1)
1
mA
C = 0.1VCC/0.9VCC at 5 MHz, VCC = 1.8 V,
Q = open(2)
2.5
mA
During tW, S = VCC, 1.8 V < VCC < 2.5 V
3
mA
S = VCC, VIN = VSS or VCC,
1.8 V < VCC < 2.5 V
3
µA
VCC = 1.8 to 5.5 V, TA = –40 to 85 °C
Min
ICC1
Supply current (Standby
Power mode)
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
IOL = 0.15 mA, VCC = 1.8 V
0.3
V
VOH
Output high voltage
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
V
1. Current products are identified by process letters AB.
2. New products are identified by process letter K.
3. Characterized value, not tested in production.
Doc ID 11124 Rev 13
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DC and AC parameters
Table 16.
M95512-W, M95512-R
AC characteristics (current(1) M95512-W products)
Test conditions:
VCC = 2.5 to 5.5 V at TA = –40 to 85 °C (device grade 6) or TA = –40 to 125 °C (device grade 3)
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
ns
tSHCH
tCSS2
S not active setup time
90
ns
tSHSL
tCS
S deselect time
100
ns
tCHSH
tCSH
S active hold time
90
ns
S not active hold time
90
ns
tCHSL
Parameter
Max.
Unit
D.C.
5
MHz
tCH
(2)
tCLH
Clock high time
90
ns
tCL
(2)
tCLL
Clock low time
90
ns
tCLCH (3)
tRC
Clock rise time
1
µs
(3)
tFC
Clock fall time
1
µs
tCHCL
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
30
ns
tHHCH
Clock low hold time after HOLD not active
70
ns
tHLCH
Clock low hold time after HOLD active
40
ns
tCLHL
Clock low setup time before HOLD active
0
ns
tCLHH
Clock low setup time before HOLD not active
0
ns
tSHQZ (3)
tDIS
tCLQV
tV
tCLQX
Output disable time
100
ns
Clock low to output valid
60
ns
tHO
Output hold time
(3)
tRO
Output rise time
50
ns
tQHQL (3)
tFO
Output fall time
50
ns
tHHQV
tLZ
HOLD high to output valid
50
ns
tHZ
HOLD low to output High-Z
100
ns
tWC
Write time
5
ms
tQLQH
tHLQZ
tW
(3)
1. Current products are identified by process letters AB.
2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
3. Value guaranteed by characterization, not 100% tested in production.
34/48
Min.
Doc ID 11124 Rev 13
0
ns
M95512-W, M95512-R
Table 17.
DC and AC parameters
AC characteristics (New(1) M95512-W products)
Test conditions: VCC = 2.5 to 5.5 V, TA = –40 to 85 °C
Min.
Symbol
Alt.
Max.
Min.
Max.
Parameter
Unit
2.5 V to 5.5 V
4.5 V to 5.5 V
D.C.
D.C.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
30
15
ns
tSHCH
tCSS2
S not active setup time
30
15
ns
tSHSL
tCS
S deselect time
40
20
ns
tCHSH
tCSH
S active hold time
30
15
ns
S not active hold time
30
15
ns
tCHSL
10
20
MHz
tCH
(2)
tCLH
Clock high time
45
20
ns
tCL
(2)
45
20
ns
tCLL
Clock low time
(3)
tRC
Clock rise time
2
2
µs
tCHCL (3)
tFC
Clock fall time
2
2
µs
tDVCH
tDSU
Data in setup time
10
5
ns
tCHDX
tDH
Data in hold time
10
10
ns
tHHCH
Clock low hold time after HOLD not active
30
15
ns
tHLCH
Clock low hold time after HOLD active
30
15
ns
tCLHL
Clock low setup time before HOLD active
0
0
ns
tCLHH
Clock low setup time before HOLD not active
0
0
ns
tCLCH
tSHQZ
(3)
tDIS
tCLQV
tV
tCLQX
Output disable time
40
20
ns
Clock low to output valid
40
20
ns
tHO
Output hold time
tQLQH
(3)
tRO
Output rise time
40
20
ns
tQHQL
(3)
tFO
Output fall time
40
20
ns
tLZ
HOLD high to output valid
40
20
ns
tHZ
HOLD low to output High-Z
40
20
ns
tWC
Write time
5
5
ms
tHHQV
tHLQZ
tW
(3)
0
0
ns
1. New products are identified by process letter K.
2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
3. Value guaranteed by characterization, not 100% tested in production.
Doc ID 11124 Rev 13
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DC and AC parameters
Table 18.
M95512-W, M95512-R
AC characteristics (current and new M95512-R and M95512-DR products)
Test conditions: VCC = 1.8 to 5.5 V, TA = –40 to 85 °C
Min.
Min.
Max.
Alt.
fC
fSCK
Clock frequency
D.C.
tSLCH
tCSS1
S active setup time
200
60
ns
tSHCH
tCSS2
S not active setup time
200
60
ns
tSHSL
tCS
S deselect time
200
90
ns
tCHSH
tCSH
S active hold time
200
60
ns
S not active hold time
200
60
ns
tCHSL
Parameter
Max.
Symbol
Current(1) products New products(2)
2
D.C.
5
Unit
MHz
tCH
(3)
tCLH
Clock high time
200
80
ns
tCL
(3)
200
80
ns
tCLL
Clock low time
(4)
tRC
Clock rise time
1
2
µs
tCHCL (4)
tFC
Clock fall time
1
2
µs
tDVCH
tDSU
Data in setup time
40
20
ns
tCHDX
tDH
Data in hold time
50
20
ns
tHHCH
Clock low hold time after HOLD not active
140
60
ns
tHLCH
Clock low hold time after HOLD active
90
60
ns
tCLHL
Clock low setup time before HOLD active
0
0
ns
tCLHH
Clock low setup time before HOLD not active
0
0
ns
tCLCH
tSHQZ
(4)
tDIS
tCLQV
tV
tCLQX
Output disable time
250
80
ns
Clock low to output valid
150
80
ns
tHO
Output hold time
tQLQH
(4)
tRO
Output rise time
100
80
ns
tQHQL
(4)
tFO
Output fall time
100
80
ns
tLZ
HOLD high to output valid
100
80
ns
tHZ
HOLD low to output High-Z
250
80
ns
tWC
Write time
5
5
ms
tHHQV
tHLQZ
tW
(4)
0
0
ns
1. Current products are identified by process letters “AB”.
2. New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values
defined in this table (when VCC = 1.8 V) and the AC parameter values defined in Table 17 (when VCC= 2.5 V or VCC=
5.0 V).
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
4. Value guaranteed by characterization, not 100% tested in production.
36/48
Doc ID 11124 Rev 13
M95512-W, M95512-R
DC and AC parameters
Figure 20. Serial input timing
tSHSL
S
tCHSL
tCH
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCL
tCLCH
tCHDX
D
Q
LSB IN
MSB IN
High impedance
AI01447d
Figure 21. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQV
Q
HOLD
AI01448c
Doc ID 11124 Rev 13
37/48
DC and AC parameters
M95512-W, M95512-R
Figure 22. Serial output timing
S
tCH
tSHSL
C
tCLQV
tCLCH
tCHCL
tCL
tSHQZ
tCLQX
Q
tQLQH
tQHQL
ADDR
D LSB IN
AI01449f
38/48
Doc ID 11124 Rev 13
M95512-W, M95512-R
11
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 23. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 19.
SO8N – 8 lead plastic small outline, 150 mils body width, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.0689
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.10
0.0039
D
4.90
4.80
5.00
0.1929
0.189
0.1969
E
6.00
5.80
6.20
0.2362
0.2283
0.2441
E1
3.90
3.80
4.00
0.1535
0.1496
0.1575
e
1.27
–
–
0.05
-
-
h
0.25
0.50
0.0098
0.0197
k
0°
8°
0°
8°
L
0.40
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 11124 Rev 13
39/48
Package mechanical data
M95512-W, M95512-R
Figure 24. TSSOP8 – 8 lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 20.
TSSOP8 – 8 lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
0.050
0.150
0.800
1.050
b
0.190
c
0.090
1.000
CP
Max
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394

0°
N
8
8°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
40/48
Min
1.200
A1
A2
Typ
Doc ID 11124 Rev 13
8
M95512-W, M95512-R
Package mechanical data
Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3 mm, package outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 21.
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3 .mm, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.55
0.50
0.60
0.0217
0.0197
0.0236
A1
0.02
0.00
0.05
0.0008
0
0.0020
b
0.25
0.20
0.30
0.0098
0.0079
0.0118
D
2.00
1.90
2.10
0.0787
0.0748
0.0827
D2
1.60
1.50
1.70
0.0630
0.0591
0.0669
ddd
0.08
0.0031
E
3.00
2.90
3.10
0.1181
0.1142
0.1220
E2
0.20
0.10
0.30
0.0079
0.0039
0.0118
e
0.50
–
–
0.0197
–
–
L
0.45
0.40
0.50
0.0177
0.0157
0.0197
L1
L3
0.15
0.30
0.0059
0.0118
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95512-W, M95512-R
Figure 26. WLCSP-R – 8-bump wafer-length chip-scale package outline
e1
D
X
e3
Y
Orientation reference
Orientation reference
e2
A
B
C
D
E
Detail A
E
aaa
e
G
1
Wafer back side
A2
2
3
F
Bump side
A
Side view
Bump
A1
eee Z
Detail A
rotated by 90 °C
Z
b
Seating plane
ME_1Cc
1. Drawing is not to scale.
Table 22.
WLCSP-R – 8-bump wafer-length chip-scale package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.580
0.490
0.670
0.0228
0.0193
0.0264
A1
0.230
0.0091
A2
0.350
0.0138
b(2)
0.322
0.0127
D
1.433
1.548
0.0564
0.0609
E
1.901
2.016
0.0748
0.0794
e
1.000
0.0394
e1
0.866
0.0341
e2
0.500
0.0197
e3
0.433
0.0170
F
0.284
0.0112
G
0.453
0.0178
8
8
N (number of terminals)
aaa
0.110
0.0043
eee
0.060
0.0024
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Measured at the maximum bump diameter parallel to primary datum Z.
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M95512-W, M95512-R
12
Part numbering
Part numbering
Table 23.
Ordering information scheme
Example:
M95512
–
W MN
6
T
P /AB
Device type
M95 = SPI serial access EEPROM
Device function
512 = 512 Kbit (65536 × 8)
512-D = 512 Kbit (65536 × 8) plus Identification page
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB = UFDFPN8 (MLP8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with high reliability certified flow(1).
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(2)
/AB = F8L
/K = F8H
1. ST strongly recommends the use of the automotive grade devices for use in an automotive environment.
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
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Part numbering
M95512-W, M95512-R
2. The process letters only appear in the product ordering codes of device grade 3 devices. For other
devices, it is only given here as an indication of how to differentiate current from new products.
To identify current from new devices, please contact your nearest ST sales office.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 24.
Available M95512 products (package, voltage range, temperature grade)
M95512-W
2.5 V to 5.5 V
M95512-R
1.8 V to 5.5 V
Range 6, range 3
Range 6
Range 6
Range 6
UFDFPN8 (MB)
-
Range 6
WLCSP (CS)
-
Range 6
Package
SO8 (MN)
TSSOP (DW)
Table 25.
Available M95512-DR products (package, voltage range, temperature
grade)
M95512-DR
1.8 V to 5.5 V
Package
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SO8 (MN)
Range 6
TSSOP (DW)
Range 6
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13
Revision history
Revision history
Table 26.
Document revision history
Date
Revision
Jan-1999
1.0
Document written
13-Feb-2002
2.0
Document reformatted using the new template
Voltage range -S added, and -R removed
Instruction Sequence illustrations updated
Announcement made of planned upgrade to 10 MHz clock for the 5V, –40
to 85°C, range
05-Dec-2003
3.0
Table of contents, and Pb-free options added. VIL(min) improved to 0.45V. Voltage range -R added, and -S removed
02-Apr-2004
4.0
Old versions of document completely replaced by one rewritten from
M95256
5.0
AC and DC characteristics tables updated with the performance data of
the new device identified with the process letter “A”.
Table 1., Product List added. AEC-Q100-002 compliance. Device Grade
information clarified. tHHQX, tCHHL and tCHHH corrected to tHHQV, tCLHL and
tCLHH, respectively.
M95512 part number with 4.5V to 5.5V operating voltage range removed
(related tables removed). Document status changed to Preliminary Data.
6.0
Updated Figure 4: Bus master and memory devices on the SPI bus and
Figure 21: Hold timing. Power On Reset information clarified. Protected
Array Addresses modified in Table 2: Write-protected block size. Ambient
Operating Temperature value added in Table 7: Absolute maximum
ratings. Supply Current (ICC) value modified for 10 MHz in Table 13: DC
characteristics (current M95512-W products). All values modified in
Table 18: AC characteristics (current and new M95512-R and M95512-DR
products). Document status changed to Datasheet.
03-Jan-2005
30-Jun-2005
Changes
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Revision history
Table 26.
Date
Document revision history (continued)
Revision
Changes
06-Feb-2007
7
Document reformatted. Packages are ECOPACK® compliant.
10 MHz frequency removed. VCC supply voltage and VSS ground
descriptions added. Figure 4: Bus master and memory devices on the SPI
bus modified and explanatory paragraph added. Power-up and Power On
Reset paragraphs replaced by Section 4.1: Supply voltage (VCC).
Section 7: ECC (error correction code) and write cycling added.
TA max modified in Table 8: Operating conditions (M95512-W device
grade 6).
Note modified below Table 12: Capacitance.
CL modified in and Table 11: AC measurement conditions.
VIL max and ICC0 test conditions modified in Table 15: DC characteristics
(current and new M95512-R and M95512-DR products).
ICC modified in Table 13: DC characteristics (current M95512-W
products), ICC0 added to Table 13 and Table 15: DC characteristics
(current and new M95512-R and M95512-DR products) modified.
Table 18: AC characteristics (current and new M95512-R and M95512-DR
products) modified.
tSHQZ end timing line moved back in Figure 22: Serial output timing.
SO8N package specifications updated (see Figure 23 and Table 19).
Blank removed below Plating technology in Table 23: Ordering information
scheme.
05-Jun-2007
8
The device endurance is specified at more than 1 000 000 (1 million)
cycles (corrected on cover page).
9
M95512-W is now available in the device grade 3 (automotive temperature
range), see Table 8 on page 31).
Section 4.1: Supply voltage (VCC) on page 12 updated.
Section 6.4: Write Status Register (WRSR) on page 20 and Section 6.6:
Write to Memory Array (WRITE) on page 23 clarified.
ICC0 modified in Table 13: DC characteristics (current M95512-W
products).
Figure 20: Serial input timing, Figure 21: Hold timing and Figure 22: Serial
output timing updated.
Package mechanical data values in inches are calculated from the
millimeter values and rounded to four decimal digits (see Section 11:
Package mechanical data).
Table 24: Available M95512 products (package, voltage range,
temperature grade) added. Small text changes.
10
M95512-DR part number added (see Table 25: Available M95512-DR
products (package, voltage range, temperature grade)).
New M95512-W, M95512-R and M95512-DR products operating at up to
20 MHz added (preliminary data).
UFDFPN8 package added (see Section 11: Package mechanical data).
03-Jul-2008
14-Apr-2009
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M95512-W, M95512-R
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M95512-W, M95512-R
Table 26.
Date
Revision history
Document revision history (continued)
Revision
Changes
11-May-2009
11
VESD modified in Table 7: Absolute maximum ratings.
Updated:
– Section 6.7: Read Identification Page (available only in M95512-DR
devices)
– Section 6.8: Write Identification Page (available only in M95512-DR
devices)
– Section 6.9: Read Lock Status (available only in M95512-DR devices)
– Section 6.10: Lock ID (available only in M95512-DR devices)
28-Aug-2009
12
Data related to new products are no longer preliminary.
Note 2 updated in Table 18: AC characteristics (current and new M95512R and M95512-DR products).
13
WLCSP package added.
M95512-DR added.
Updated:
– Section 1: Description
– Section 6.7: Read Identification Page (available only in M95512-DR
devices)
– Section 6.8: Write Identification Page (available only in M95512-DR
devices)
– Section 6.9: Read Lock Status (available only in M95512-DR devices),
Table 7: Absolute maximum ratings
Inserted Caution under Table 1: Signal names
Added Note under Figure 24: TSSOP8 – 8 lead thin shrink small outline,
package outline
14-Sep-2010
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M95512-W, M95512-R
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