IDT IDT49FCT805BTP Fast cmos buffer/clock driver Datasheet

FAST CMOS
BUFFER/CLOCK DRIVER
IDT49FCT805BT/CT
IDT49FCT806BT/CT
Integrated Device Technology, Inc.
• Military product compliant to MIL-STD-883, Class B
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Guaranteed low skew < 500ps (max.)
Very low duty cycle distortion < 600ps (max.)
Low CMOS power levels
TTL compatible inputs and outputs
TTL level output voltage swings
High drive: -32mA IOH, 48mA IOL
Two independent output banks with 3-state control
1:5 fanout per bank
‘Heartbeat’ monitor output
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
DESCRIPTION:
The IDT49FCT805BT/CT and IDT49FCT806BT/CT are
clock drivers built using advanced dual metal CMOS technology. The IDT49FCT805BT/CT is a non-inverting clock driver
and the IDT49FCT806BT/CT is an inverting clock driver. Each
device consists of two banks of drivers. Each bank drives five
output buffers from a standard TTL compatible input. The
805BT/CT and 806BT/CT have extremely low output skew,
pulse skew, and package skew. The devices has a "heartbeat" monitor for diagnostics and PLL driving. The MON
output is identical to all other outputs and complies with the
output specifications in this document. The 805BT/CT and
806BT/CT offer low capacitance inputs with hysteresis.
FUNCTIONAL BLOCK DIAGRAMS
IDT49FCT805T
IDT49FCT806T
OEA
INA
INB
OEA
5
5
OA1-OA5
INA
OB1-OB5
INB
5
5
OA1-OA5
OB1-OB5
OEB
OEB
MON
MON
2920 drw 02
2920 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
9.2
OCTOBER 1995
DSC-2920/5
1
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OA2
3
18
OB2
OA3
4
17
4
OB3
GND
5
16
GND
OA4
6
15
OB4
OA5
7
GND
14
OB5
8
GND
5
OA4
6
OA5
7
GND
8
13
MON
OEA
9
12
OEB
INA
10
11
INB
3
2
20 19
1
L20-2
18
OB2
17
OB3
16
GND
15
OB4
14
OB5
9 10 11 12 13
OEA
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
OA3
OB1
OB1
MON
19
VCC
2
OEB
OA1
INDEX
VCC
VCC
INB
20
OA1
1
INA
VCC
OA2
IDT49FCT805T
LCC
TOP VIEW
2920 drw 04
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2920 drw 03
OA1
2
19
OB1
OA2
3
18
OB2
OA3
4
17
OB3
16
GND
15
OB4
5
OA4
6
4
GND
5
OA4
6
OA5
GND
3
2
20 19
1
18
OB2
17
OB3
16
GND
7
15
OB4
8
14
OB5
L20-2
MON
OEA
9
12
OEB
INA
10
11
INB
MON
13
GND
OEB
8
7
INB
OB5
OA5
INA
14
9 10 11 12 13
OEA
GND
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
OA3
OB1
VCC
VCC
20
VCC
1
OA1
INDEX
VCC
OA2
IDT49FCT806T
LCC
TOP VIEW
2920 drw 06
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2920 drw 05
FUNCTION TABLE(1)
PIN DESCRIPTION
Outputs
Pin Names
OEA, OEB
Description
3-State Output Enable Inputs (Active LOW)
INA, INB
Clock Inputs
MON
OAn, OBn
MON
OAn, OBn
Clock Outputs (FCT805T)
L
L
L
L
H
H
OAn, OBn
Clock Outputs (FCT806T)
L
H
H
H
L
L
MON
Monitor Output (FCT805T)
H
L
Z
L
Z
H
MON
Monitor Output (FCT806T)
H
H
Z
H
Z
L
Inputs
OEA, OEB
2920 tbl 01
49FCT805T
INA, INB OAn, OBn
NOTE:
1. H = HIGH, L = LOW, Z = High Impedance
9.2
49FCT806T
2920 tbl 02
2
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
I OUT
DC Output
Current
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to VCC
+0.5
–0.5 to VCC
+0.5
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
–60 to +120
–60 to +120
mA
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
4.5
VOUT = 0V
5.5
Max. Unit
6.0
pF
8.0
pF
2920 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
2920 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Input LOW Level
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic LOW Level
—
—
0.8
V
Input HIGH
Current (5)
VCC = Max.
VI = 2.7V
—
—
±1
µA
II L
Input LOW
Current (5)
VCC = Max.
VI = 0.5V
—
—
±1
µA
I OZH
High Impedance Output Current
VCC = Max.
VO = 2.7V
—
—
±1
µA
VO = 0.5V
—
—
±1
µA
II H
I OZL
(3-State Output
pins) (5)
Current (5)
II
Input HIGH
VIK
Clamp Diode Voltage
VCC = Max., VI = VCC (Max.)
—
—
±1
µA
VCC = Min., IIN= –18mA
—
–0.7
–1.2
V
–60
–120
–225
mA
2.4
3.3
—
V
2.0
3.0
—
—
0.3
0.55
V
—
—
±1
µA
—
150
—
mV
—
5
500
µA
Max.(3) ,
I OS
Short Circuit Current
VCC =
VOH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
VOL
Output LOW Voltage
IOFF
Input/Output Power Off Leakage(5)
VH
Input Hysteresis for all inputs
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = GND
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OH = –24mA MIL.
I OH = –32mA COM'L.(4)
VCC = Min.
I OL = 32mA MIL.
VIN = VIH or VIL
I OL = 48mA COM'L.
VCC = 0V, VIN or VO ≤ 4.5V
—
VCC = Max., VIN = GND or V CC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
9.2
2920 lnk 05
3
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
—
0.5
2.0
mA
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current (4)
VCC = Max.
Outputs Open
OEA = OEB = GND
50% Duty Cycle
VIN = VCC
VIN = GND
—
60
100
µA/
MHz/bit
IC
Total Power Supply Current (6)
VCC = Max.
Outputs Open
fo = 25MHz
50% Duty Cycle
OEA = OEB =VCC
Mon. Output Toggling
VIN = VCC
VIN = GND
—
1.5
3.0
mA
VIN = 3.4V
VIN = GND
—
1.8
4.0
VCC = Max.
Outputs Open
fo = 50MHz
50% Duty Cycle
OEA = OEB = GND
Eleven Outputs
Toggling
VIN = VCC
VIN = GND
—
33
55.5 (5)
VIN = 3.4V
VIN = GND
—
33.5
57.5 (5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO= Output Frequency
NO= Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
9.2
2920 tbl 06
4
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT49FCT805BT/806BT
Com'l.
Symbol
Parameter
tPLH
Propagation Delay
INA to OAn, INB to OBn
tPHL
tR
Output Rise Time
Condition(1)
CL = 50pF
RL = 500Ω
Min. (2)
1.5
Mil.
Max.
Min. (2)
5.0
1.5
IDT49FCT805CT/806CT
Com'l.
Max.
Min. (2)
5.7
1.5
Mil.
Max.
Min. (2)
Max.
4.5
1.5
5.2
Unit
ns
—
1.5
—
2.0
—
1.5
—
2.0
ns
tF
Output Fall Time
—
1.5
—
1.5
—
1.5
—
1.5
ns
tSK(o)
Output skew: skew between outputs of all
banks of same package (inputs tied together)
—
0.7
—
0.9
—
0.5
—
0.7
ns
tSK(p)
Pulse skew: skew between opposite
transitions of same output (|t PHL–t PLH|)
—
0.7
—
0.9
—
0.6
—
0.8
ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
—
1.2
—
1.5
—
1.0
—
1.2
ns
tPZL
tPZH
tPLZ
tPHZ
Output Enable Time
OEA to OAn, OEB to OBn
Output Disable Time
OEA to OAn, OEB to OBn
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns
2920 tbl 07
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.2
5
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
VCC
7.0V
ENABLE AND DISABLE TIME
SWITCH POSITION
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
CL
2920 drw 07
Switch
Closed
Open
2920 lnk 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
OUTPUT SKEW- tSK(o)
PACKAGE DELAY
3V
1.5V
INPUT
INPUT
0V
tPLH
tPLH1
3V
1.5V
0V
VOH
1.5V
VOL
tPHL1
tPHL
VOH
2.0V
0.8V
OUTPUT
OUTPUT 1
tSK(o)
1.5V
tSK(o)
VOL
OUTPUT 2
tF
tR
tPLH2
VOH
1.5V
VOL
tPHL2
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
2920 drw 08
2920 drw 09
PULSE SKEW - tSK(p)
PACKAGE SKEW - tSK(t)
3V
1.5V
0V
INPUT
tPHL
tPLH
OUTPUT
VOH
1.5V
VOL
INPUT
PACKAGE 1 OUTPUT
tSK(t)
PACKAGE 2 OUTPUT
tSK(p) = |tPHL - tPLH|
tPHL1
tPLH1
tPLH2
tSK(t)
tPHL2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
2920 drw 10
Package 1 and Package 2 are same device type and speed grade
ENABLE AND DISABLE TIMES
ENABLE
2920 drw 11
DISABLE
3V
1.5V
0V
CONTROL
INPUT
t
OUTPUT
NORMALLY
LOW
t PLZ
PZL
SWITCH
CLOSED
0.3V V OL
t
t PZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3.5V
3.5V
1.5V
PHZ
0.3V VOH
1.5V
0V
0V
2920 drw 12
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
9.2
6
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT49FCT
XXX
Device Type
XX
Package
X
Process/
Temperature Range
Blank
B
Commercial (0°C to +70°C)
MIL-STD-883, Class B (–55°C to +125°C)
P
D
E
L
SO
PY
Q
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline Package
805BT
806BT
805CT
806CT
Non-Inverting Buffer/Clock Driver
Inverting Buffer/Clock Driver
2920 drw 13
9.2
7
Similar pages