Sample & Buy Product Folder Support & Community Tools & Software Technical Documents OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 OPA4188 0.03-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers 1 Features • • • 1 • • • • • • • 3 Description The OPA4188 operational amplifier uses TI proprietary auto-zeroing techniques to provide low offset voltage (25 μV, maximum), and near zero-drift over time and temperature. These miniature, highprecision, low quiescent current amplifiers offer high input impedance and rail-to-rail output swing within 15 mV of the rails, making them ideal for industrial applications. The input common-mode range includes the negative rail. Either single or dual supplies can be used in the range of 4 V to 36 V (±2 V to ±18 V). Low Offset Voltage: 25 μV (Maximum) Zero-Drift: 0.03 μV/°C Low Noise: 8.8 nV/√Hz 0.1-Hz to 10-Hz Noise: 0.25 µVPP Excellent DC Precision: PSRR: 142 dB CMRR: 146 dB Open-Loop Gain: 136 dB Gain Bandwidth: 2 MHz Quiescent Current: 475 μA (Maximum) Wide Supply Range: ±2 V to ±18 V Rail-to-Rail Output: Input Includes Negative Rail RFI Filtered Inputs MicroSIZE Packages The quad version is available in 14-pin SOIC and 14pin TSSOP packages. All versions are specified for operation from –40°C to 125°C. Device Information(1) PART NUMBER OPA4188 2 Applications • • • • • • • • • PACKAGE BODY SIZE (NOM) SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Bridge Amplifiers Strain Gauges Test Equipment Transducer Applications Temperature Measurement Electronic Scales Medical Instrumentation Resistance Temperature Detectors Precision Active Filters Zero-Drift Architecture Improves Performance 145 Offset Voltage (mV) 125 105 85 65 OPA4188 Zero-Drift Architecture Precision Laser Trim Architecture 45 25 5 -55 -35 -15 5 25 45 65 85 105 125 150 Temperature (°C) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Zero-Drift Amplifier Portfolio ................................ Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 7.2 7.3 7.4 7.5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics: High-Voltage Operation, VS = ±4 V to ±18 V (VS = 8 V to 36 V)............................ 6 7.6 Electrical Characteristics: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V) ..................... 7 7.7 Typical Characteristics .............................................. 9 8 Detailed Description ............................................ 17 8.2 Functional Block Diagram ....................................... 17 8.3 Feature Description................................................. 17 8.4 Device Functional Modes........................................ 19 9 Applications and Implementation ...................... 20 9.1 Application Information............................................ 20 9.2 Typical Applications ................................................ 20 10 Power Supply Recommendations ..................... 23 11 Layout................................................................... 23 11.1 Layout Guidelines ................................................. 23 11.2 Layout Example .................................................... 24 12 Device and Documentation Support ................. 25 12.1 12.2 12.3 12.4 Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 25 25 26 26 13 Mechanical, Packaging, and Orderable Information ........................................................... 26 8.1 Overview ................................................................. 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2013) to Revision C • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Revision A (September 2012) to Revision B Page • Changed maximum specification of second Input Bias Current, IB parameter row in High-Voltage Electrical Characteristics table ............................................................................................................................................................... 6 • Changed maximum specification of second Input Bias Current, IB parameter row in Low-Voltage Electrical Characteristics table ............................................................................................................................................................... 7 • Changed Input Impedance, Input impedance (Common-mode) parameter typical specification in Low-Voltage Electrical Characteristics table ............................................................................................................................................... 7 Changes from Original (June2012) to Revision A • 2 Page Changed second to last Applications bullet............................................................................................................................ 1 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 5 Zero-Drift Amplifier Portfolio VERSION Single Dual Quad PRODUCT OFFSET VOLTAGE (µV) OFFSET VOLTAGE DRIFT (µV/°C) BANDWIDTH (MHz) OPA188 (4 V to 36 V) 25 0.085 2 OPA333 (5 V) 10 0.05 0.35 OPA378 (5 V) 50 0.25 0.9 OPA735 (12 V) 5 0.05 1.6 OPA2188 (4 V to 36 V) 25 0.085 2 OPA2333 (5 V) 10 0.05 0.35 OPA2378 (5 V) 50 0.25 0.9 OPA2735 (12 V) 5 0.05 1.6 OPA4188 (4 V to 36 V) 25 0.085 2 OPA4330 (5 V) 50 0.25 0.35 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 3 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com 6 Pin Configuration and Functions D or PW Packages 14-Pin SOIC or 14-Pin TSSOP Top View 14 OUT D OUT A 1 -IN A 2 +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 -IN B 6 OUT B 7 A D 13 -IN D 10 +IN C B C 9 -IN C 8 OUT C Pin Functions PIN I/O DESCRIPTION NO. NAME 1 OUT A O Output channel A 2 –IN A I Inverting input channel A 3 +IN A I Noninverting input channel A 4 V+ I Positive power supply 5 +IN B I Noninverting input channel B 6 –IN B I Inverting input channel B 7 OUT B O Output channel B 8 OUT C O Output channel C 9 –IN C I Inverting input channel C 10 +IN C I Noninverting input channel C 11 V– I Negative power supply 12 +IN D I Noninverting input channel D 13 –IN D I Inverting input channel D 14 OUT D O Output channel D 4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT ±20 40 (single supply) V (V–) – 0.5 (V+) + 0.5 V ±10 mA 150 °C 150 °C 150 °C Supply voltage Signal input terminals (2) Voltage Current Output short circuit (3) Continuous Operating, TA Temperature –55 Junction, TJ Storage, Tstg (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5-V beyond the supply rails should be current-limited to 10 mA or less. Short-circuit to ground, one amplifier per package. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Power supply voltage, (V+)-(V–) Ambient temperature, TA NOM MAX UNIT 4 (±2) 36 (±18) V –40 125 °C 7.4 Thermal Information OPA4188 THERMAL METRIC (1) D (SOIC) PW (TSSOP) UNIT 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.8 24.4 °C/W RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 5 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com 7.5 Electrical Characteristics: High-Voltage Operation, VS = ±4 V to ±18 V (VS = 8 V to 36 V) At TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS dVOS/dT TA = 25°C Input offset voltage TA = –40°C to 125°C VS = 4 V to 36 V, VCM = VS / 2 PSRR Power-supply rejection ratio 25 0.085 μV/°C 0.075 0.3 μV/V 0.3 μV/V VS = 4 V to 36 V, VCM = VS / 2, TA = –40°C to 125°C 4 (1) Long-term stability Channel separation, DC μV 6 0.03 μV μV/V 1 INPUT BIAS CURRENT IB Input bias current IOS Input offset current VCM = VS / 2 ±160 TA = –40°C to 125°C ±320 TA = –40°C to 125°C ±1400 pA ±8 nA ±2800 pA ±6 nA NOISE en Input voltage noise f = 0.1 Hz to 10 Hz 0.25 μVPP en Input voltage noise density f = 1 kHz 8.8 nV/Hz in Input current noise density f = 1 kHz 7 fA/Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio TA = –40°C to 125°C V– (V+) – 1.5 V (V–) < VCM < (V+) – 1.5 V 120 134 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±18 V 130 146 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±18 V, TA = –40°C to 125°C 120 126 dB INPUT IMPEDANCE Input impedance Differential 100 || 6 MΩ || pF Common-mode 6 || 9.5 1012 Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ 130 136 dB (V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ, TA = –40°C to 125°C 118 126 dB FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate ts Settling time THD+N (1) 6 2 MHz G=1 0.8 V/μs 0.1% VS = ±18 V, G = 1, 10-V step 20 μs 0.01% VS = ±18 V, G = 1, 10-V step 27 μs 1 μs Overload recovery time VIN × G = VS Total harmonic distortion + noise 1 kHz, G = 1, VOUT = 1 VRMS 0.0001% 1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 Electrical Characteristics: High-Voltage Operation, VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued) At TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT No load Voltage output swing from rail ISC Short circuit current RO Open-loop output resistance CLOAD Capacitive load drive 6 15 mV RL = 10 kΩ 220 250 mV RL = 10 kΩ, TA = –40°C to 125°C 310 350 mV ±18 f = 1 MHz, IO = 0 mA 120 Ω 1 nF POWER SUPPLY VS Operating voltage range IQ Quiescent current (per amplifier) 4 to 36 (±2 to ±18) VS = ±4 V to VS = ±18 V 415 IO = 0 mA, TA = –40°C to 125°C V 475 μA 525 μA TEMPERATURE RANGE Temperature range Specified –40 125 °C Operating –55 150 °C Storage –65 150 °C 7.6 Electrical Characteristics: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V) At TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS dVOS/dT TA = 25°C Input offset voltage TA = –40°C to 125°C VS = 4 V to 36 V, VCM = VS / 2 PSRR Power-supply rejection ratio 25 0.085 μV/°C 0.075 0.3 μV/V 0.3 μV/V VS = 4 V to 36 V, VCM = VS / 2, TA = –40°C to 125°C Long-term stability 4 Channel separation, DC μV 6 0.03 (1) μV 1 μV/V INPUT BIAS CURRENT IB VCM = VS / 2 Input bias current IOS ±160 TA = –40°C to 125°C ±320 Input offset current TA = –40°C to 125°C ±1400 pA ±8 nA ±2800 pA ±6 nA NOISE en Input voltage noise f = 0.1 Hz to 10 Hz 0.25 μVPP en Input voltage noise density f = 1 kHz 8.8 nV/Hz in Input current noise density f = 1 kHz 7 fA/Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio V– (V+) – 1.5 V (V–) < VCM < (V+) – 1.5 V 106 114 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±2 V 114 120 dB (V–) + 0.5 V < VCM < (V+) – 1.5 V, VS = ±2 V, TA = –40°C to 125°C 108 120 dB INPUT IMPEDANCE Input impedance (1) Differential 100 || 6 MΩ || pF Common-mode 6 || 9.5 1012 Ω || pF 1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 7 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com Electrical Characteristics: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V) (continued) At TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ 120 130 dB (V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ, TA = –40°C to 125°C 110 120 dB OPEN-LOOP GAIN AOL Open-loop voltage gain FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate G=1 Overload recovery time VIN × G = VS Total harmonic distortion + noise 1 kHz, G = 1, VOUT = 1 VRMS THD+N 2 MHz 0.8 V/μs μs 1 0.0001% OUTPUT No load Voltage output swing from rail ISC Short circuit current RO Open-loop output resistance CLOAD Capacitive load drive 6 15 mV RL = 10 kΩ 220 250 mV RL = 10 kΩ, TA = –40°C to 125°C 310 350 mV ±18 f = 1 MHz, IO = 0 mA 120 Ω 1 nF POWER SUPPLY VS IQ Operating voltage range Quiescent current (per amplifier) 4 to 36 (±2 to ±18) VS = ±2 V to VS = ±4 V 385 IO = 0 mA, TA = –40°C to 125°C V 440 μA 525 μA TEMPERATURE RANGE Temperature range 8 Specified –40 125 °C Operating –40 125 °C Storage –65 150 °C Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 7.7 Typical Characteristics Table 1. Characteristic Performance Measurements DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Distribution Figure 2 Offset Voltage vs Temperature Figure 3 Offset Voltage vs Common-Mode Voltage Figure 4, Figure 5 Offset Voltage vs Power Supply Figure 6 IB and IOS vs Common-Mode Voltage Figure 7 Input Bias Current vs Temperature Figure 8 Output Voltage Swing vs Output Current (Maximum Supply) Figure 9 CMRR and PSRR vs Frequency (Referred-to-Input) Figure 10 CMRR vs Temperature Figure 11, Figure 12 PSRR vs Temperature Figure 13 0.1-Hz to 10-Hz Noise Figure 14 Input Voltage Noise Spectral Density vs Frequency Figure 15 THD+N Ratio vs Frequency Figure 16 THD+N vs Output Amplitude Figure 17 Quiescent Current vs Supply Voltage Figure 18 Quiescent Current vs Temperature Figure 19 Open-Loop Gain and Phase vs Frequency Figure 20 Closed-Loop Gain vs Frequency Figure 21 Open-Loop Gain vs Temperature Figure 22 Open-Loop Output Impedance vs Frequency Figure 23 Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 24, Figure 25 No Phase Reversal Figure 26 Positive Overload Recovery Figure 27 Negative Overload Recovery Figure 28 Small-Signal Step Response (100 mV) Figure 29, Figure 30 Large-Signal Step Response Figure 31, Figure 32 Large-Signal Settling Time (10-V Positive Step) Figure 33 Large-Signal Settling Time (10-V Negative Step) Figure 34 Short Circuit Current vs Temperature Figure 35 Maximum Output Voltage vs Frequency Figure 36 Channel Separation vs Frequency Figure 37 EMIRR IN+ vs Frequency Figure 38 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 9 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 40 Distribution Taken From 1400 Amplifiers Percentage of Amplifiers (%) 16 14 12 10 8 6 4 Distribution Taken From 78 Amplifiers 35 30 25 20 15 10 5 2 15 5 Typical Units Shown VS = ±18 V VOS (mV) -5 -10 -10 -55 -35 -15 5 25 45 65 85 105 125 -15 -2.5 150 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 VCM (V) Temperature (°C) Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage 15 5 Typical Units Shown VS = ±18 V 5 Typical Units Shown VSUPPLY = ±2 V to ±18 V 10 5 VOS (mV) 5 VOS (mV) 0.09 0 -5 -15 0 0 -5 -5 -10 -10 -15 -15 -20 -15 -10 -5 0 5 10 15 20 0 VCM (V) 2 4 6 8 10 12 14 16 18 20 VSUPPLY (V) Figure 5. Offset Voltage vs Common-Mode Voltage 10 0.08 5 0 10 0.07 5 Typical Units Shown VS = ±2 V 10 5 15 0.06 Figure 2. Offset Voltage Drift Distribution 15 VOS (mV) 0.05 Offset Voltage Drift (mV/°C) Figure 1. Offset Voltage Production Distribution 10 0.04 0.01 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 Offset Voltage (mV) 0.1 0 0 0.03 Percentage of Amplifiers (%) 18 0.02 20 Submit Documentation Feedback Figure 6. Offset Voltage vs Power Supply Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 4000 500 IB+ +IB 400 IB and IOS (pA) IOS Input Bias Current (pA) IOS 300 IB- 3000 -IB 200 100 0 -100 2000 1000 0 -1000 -200 -300 -2000 -20 -15 -10 -5 0 10 5 15 20 5 -55 -35 -15 VCM (V) 20 19 18 17 16 15 14 -14 -15 -16 -17 -18 -19 -20 85 105 125 150 140 120 100 80 60 40 +PSRR -PSRR CMRR 20 0 2 4 6 8 10 12 14 16 18 20 22 1 24 10 100 1k 10k 100k 1M Frequency (Hz) Output Current (mA) Figure 9. Output Voltage Swing vs Output Current (Maximum Supply) 40 Figure 10. CMRR and PSRR vs Frequency (Referred-to-Input) Common-Mode Rejection Ratio (mV/V) Common-Mode Rejection Ratio (mV/V) 65 160 -40°C +85°C +125°C 0 (V-) < VCM < (V+) - 1.5 V 30 45 Figure 8. Input Bias Current vs Temperature Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) Output Voltage (V) Figure 7. IB and IOS vs Common-Mode Voltage 35 25 Temperature (°C) (V-) + 0.5 V < VCM < (V+) - 1.5 V VSUPPLY = ±2 V 25 20 15 10 5 0 8 (V-) < VCM < (V+) - 1.5 V 7 6 (V-) + 0.5 V < VCM < (V+) - 1.5 V VSUPPLY = ±18 V 5 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 150 -55 -35 -15 5 25 45 65 85 105 125 Temperature (°C) Temperature (°C) Figure 11. CMRR vs Temperature Figure 12. CMRR vs Temperature Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 150 11 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. Power-Supply Rejection Ratio (mV/V) 1 5 Typical Units Shown VSUPPLY = ±2 V to ±18 V 0.8 0.6 50 nV/div 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 Peak-to-Peak Noise = 250 nV -1 -55 -35 -15 5 25 45 65 85 105 125 Time (1 s/div) 150 Temperature (°C) Figure 14. 0.1-Hz to 10-Hz Noise Figure 13. PSRR vs Temperature Total Harmonic Distortion + Noise (%) Voltage Noise Density (nV/ÖHz) 0.01 10 -80 VOUT = 1 VRMS BW = 80 kHz 0.001 -100 0.0001 -120 G = +1, RL = 10 kW G = -1, RL = 10 kW 0.00001 1 0.1 1 10 100 1k 10k 10 100k 100 -80 0.001 -100 0.0001 -120 G = +1, RL = 10 kW G = -1, RL = 10 kW 0.00001 0.01 -140 0.1 1 10 Output Amplitude (VRMS) 0.46 0.44 0.42 0.4 0.38 0.36 0.34 0.32 Specified Supply-Voltage Range 0.3 0 4 8 12 16 20 24 28 32 36 Supply Voltage (V) Figure 17. THD+N vs Output Amplitude 12 20 0.5 0.48 IQ (mA) Total Harmonic Distortion + Noise (%) 0.01 Total Harmonic Distortion + Noise (dB) -60 -140 20k Figure 16. THD+N Ratio vs Frequency Figure 15. Input Voltage Noise Spectral Density vs Frequency BW = 80 kHz 10k Frequency (Hz) Frequency (Hz) 0.1 1k Total Harmonic Distortion + Noise (dB) 100 Figure 18. Quiescent Current vs Supply Voltage Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. Gain Phase 120 VS = ±2 V 0.46 135 100 Gain (dB) 0.44 0.42 0.4 0.38 80 90 60 40 45 20 0.36 0.34 0 0.32 −20 1 10 100 1k 10k 100k Frequency (Hz) 0.3 -55 -35 -15 5 25 45 65 85 105 125 Phase (°) VS = ±18 V 0.48 IQ (mA) 180 140 0.5 1M 10M 0 100M G001 150 Temperature (°C) Figure 20. Open-Loop Gain and Phase vs Frequency Figure 19. Quiescent Current vs Temperature 25 3 VSUPPLY = 4 V, RL = 10 kW 20 VSUPPLY = 36 V, RL = 10 kW 2.5 15 2 AOL (mV/V) Gain (dB) 10 5 0 1.5 1 -5 -10 G = 10 G = +1 G = -1 -15 0.5 0 -20 10k 100k 1M 10M -55 -35 -15 5 25 Frequency (Hz) 45 65 85 105 125 150 Temperature (°C) Figure 21. Closed-Loop Gain vs Frequency Figure 22. Open-Loop Gain vs Temperature 10k 40 RL = 10 kW 35 ROUT = 0 W 30 Overshoot (%) ZO (W) 1k 100 10 ROUT = 25 W 25 ROUT = 50 W 20 15 G = +1 +18 V ROUT 10 Device 1 -18 V 5 RL CL 0 1m 1 10 100 1k 10k 100k 1M 10M 0 Frequency (Hz) 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Figure 23. Open-Loop Output Impedance vs Frequency Figure 24. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 13 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 40 ROUT = 0 W 35 Device ROUT = 50 W 30 25 -18 V 37 VPP Sine Wave (±18.5 V) 5 V/div Overshoot (%) +18 V ROUT = 25 W 20 15 RI = 10 kW 10 RF = 10 kW G = -1 +18 V VIN VOUT ROUT Device 5 CL RL = 10 kW -18 V 0 0 Time (100 ms/div) 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Figure 26. No Phase Reversal Figure 25. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) VIN VOUT 20 kW 20 kW +18 V Device 5 V/div 5 V/div 2 kW VOUT VIN -18 V 2 kW +18 V VOUT Device VIN -18 V G = -10 G = -10 VOUT VIN Time (5 ms/div) Time (5 ms/div) Figure 27. Positive Overload Recovery Figure 28. Negative Overload Recovery +18 V RL = 10 kW CL = 10 pF 20 mV/div 20 mV/div RL = 10 kW CL = 10 pF G = +1 RI = 2 kW RF = 2 kW +18 V Device Device -18 V RL CL CL -18 V G = -1 Time (20 ms/div) Time (1 ms/div) Figure 29. Small-Signal Step Response (100 mV) 14 Figure 30. Small-Signal Step Response (100 mV) Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. G = +1 RL = 10 kW CL = 10 pF 5 V/div 5 V/div G = -1 RL = 10 kW CL = 10 pF Time (50 ms/div) Time (50 ms/div) Figure 31. Large-Signal Step Response 10 10 G = -1 6 4 12-Bit Settling 2 0 -2 (±1/2 LSB = ±0.024%) -4 -6 6 4 0 -2 -6 -8 -10 20 30 40 50 (±1/2 LSB = ±0.024%) -4 -10 10 12-Bit Settling 2 -8 0 G = -1 8 D From Final Value (mV) 8 D From Final Value (mV) Figure 32. Large-Signal Step Response 60 0 10 20 Time (ms) 30 40 50 60 Time (ms) Figure 33. Large-Signal Settling Time (10-V Positive Step) Figure 34. Large-Signal Settling Time (10-V Negative Step) 30 15 20 12.5 Output Voltage (VPP) VS = ±15 V ISC (mA) 10 ISC, Source 0 ISC, Sink -10 10 Maximum output voltage without slew-rate induced distortion. 7.5 VS = ±5 V 5 2.5 -20 VS = ±2.25 V 0 -30 -55 -35 -15 5 25 45 65 85 105 125 150 1k 10k 100k 1M 10M Frequency (Hz) Temperature (°C) Figure 35. Short Circuit Current vs Temperature Figure 36. Maximum Output Voltage vs Frequency Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 15 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 160 -60 Channel A to B Channel B to A 140 -80 120 EMIRR IN+ (dB) Channel Separation (dB) -70 -90 -100 -110 -120 100 80 60 40 -130 20 -140 -150 1 10 100 1k 10k 100k 1M 10M 100M 0 10M Frequency (Hz) 1G 10G Frequency (Hz) Figure 37. Channel Separation vs Frequency 16 100M Submit Documentation Feedback Figure 38. EMIRR IN+ vs Frequency Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 8 Detailed Description 8.1 Overview The OPA4188 operational amplifier combines precision offset and drift with excellent overall performance, making the device ideal for many precision applications. The precision offset drift of only 0.085 μV per degree Celsius provides stability over the entire temperature range. In addition, the device offers excellent overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-μF capacitors are adequate. The OPA4188 is developed using TI's proprietary auto-zero architecture shown in Functional Block Diagram. The internal synchronous notch filter removes switching noise from the CHOP1 and CHOP2 stages, resulting in a low noise density of 8.8 nV/Hz, low input offset voltage maximum of only 25 µV. Input offset drift maximum of only 0.085 µV/°C allows for calibration free system design. 8.2 Functional Block Diagram C2 CHOP1 GM1 CHOP2 Notch Filter GM2 GM3 +IN OUT -IN C1 GM_FF 8.3 Feature Description 8.3.1 Phase-Reversal Protection The OPA4188 has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPA4188 input prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 39. +18 V Device 5 V/div -18 V 37 VPP Sine Wave (±18.5 V) VIN VOUT Time (100 ms/div) Figure 39. No Phase Reversal Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 17 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) 8.3.2 Capacitive Load and Stability The OPA4188 dynamic characteristics have been optimized for a range of common operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the amplifier phase margin and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 40 and Figure 41 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. For details of analysis techniques and application circuits, see the applications report, Feedback Plots Define Op Amp AC Performance (SBOA015), available for download from www.ti.com. 40 40 RL = 10 kW ROUT = 0 W 35 35 ROUT = 0 W ROUT = 25 W 25 ROUT = 25 W ROUT = 50 W 30 Overshoot (%) Overshoot (%) 30 ROUT = 50 W 20 15 G = +1 +18 V ROUT 10 -18 V 20 15 RI = 10 kW 10 Device 5 25 RL RF = 10 kW G = -1 +18 V ROUT CL Device 5 CL RL = 10 kW -18 V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 40. Small-Signal Overshoot versus Capacitive Load (100-mV Output Step) Figure 41. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) 8.3.3 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Figure 42 shows how a series input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications. V+ IOVERLOAD 10 mA max VIN 5 kW VOUT Device Figure 42. Input Current Protection An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. 18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 Feature Description (continued) When the operational amplifier connects into a circuit, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through ESD cells and rarely involves the absorption device. If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be added to the supply pins. The Zener voltage must be selected such that the diode does not turn on during normal operation. However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. 8.3.4 EMI Rejection The OPA4188 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI interference from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPA4188 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 43 shows the results of this testing on the OPA4188. Detailed information can also be found in the application report, EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com. 160 140 EMIRR IN+ (dB) 120 100 80 60 40 20 0 10M 100M 1G 10G Frequency (Hz) Figure 43. EMIRR Testing 8.4 Device Functional Modes The OPA4188 has a single functional mode that is operational when the power-supply voltage is greater than 4 V (±2 V). The maximum power supply voltage for the OPA4188 is 36 V (±18 V). Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 19 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The OPA4188 operational amplifier combines precision offset and drift with excellent overall performance, making it ideal for many precision applications. The precision offset drift of only 0.085 µV per degree Celsius provides stability over the entire temperature range. In addition, the device offers excellent overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. The application examples of Figure 46 and Figure 47 highlight only a few of the circuits where the OPA4188 can be used. 9.1.1 Operating Characteristics The OPA4188 is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. 9.2 Typical Applications 9.2.1 Second Order Low Pass Filter Low pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing. The OPA4188 is ideally suited to construct a high precision active filter. Figure 44 illustrates a second order low pass filter commonly encountered in signal processing applications. R4 2.94 k C5 1 nF R1 590 R3 499 Input C2 39 nF ± Output + OPA627 Figure 44. 25-kHz Low Pass Filter 9.2.1.1 Design Requirements Use the following parameters for this design example: • Gain = 5 V/V (inverting gain) • Low-pass cutoff frequency = 25 kHz • Second order Chebyshev filter response with 3-dB gain peaking in the passband 9.2.1.2 Detailed Design Procedure The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 44. Use Equation 1 to calculate the voltage transfer function. 1 R1R3C2C5 Output s 2 Input s s C2 1 R1 1 R3 1 R4 1 R3R4C2C5 (1) 20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 Typical Applications (continued) This circuit produces a signal inversion. For this circuit, use Equation 2 to calculate the gain at DC and the lowpass cutoff frequency. R4 Gain R1 fC 1 2S 1 R3R 4 C2C5 (2) Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multi-stage active filter solutions within minutes. 9.2.1.3 Application Curve 20 Gain (db) 0 -20 -40 -60 100 1k 10k Frequency (Hz) 100k 1M Figure 45. Gain (dB) vs Frequency (Hz) 9.2.2 Discrete INA + Attenuation for ADC With a 3.3-V Supply Figure 46 illustrates a circuit with high input impedance that can accommodate ±2 V differential input signals. The output, VOUT, is scaled into the full scale input range of a 3.3 V analog to digital converter. Input common mode voltages as high as ±10 V can be present with no signal clipping. Input stage gain is determined by resistors R5, RG and R7 according to Equation 3 . R5 R7 Gain 0.2x RG (3) Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 21 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com Typical Applications (continued) 15 V U2 1/4 OPA4188 VOUTP 3.3 V VDIFF/2 -15 V R5 1 kW Ref 1 Ref 2 RG 500 W + VCM 10 R7 1 kW U1 INA159 VOUT Sense -15 V -VDIFF/2 U5 1/4 OPA4188 VOUTN 15 V Figure 46. Discrete INA + Attenuation for ADC With a 3.3-V Supply Circuit 9.2.3 RTD Amplifier With Linearization The OPA4188 with ultra-low input offset voltage and ultra-low input offset voltage drift is ideally suited for RTD signal conditioning. Figure 47 illustrates a Pt100 RTD with excitation provided by a voltage reference and resistor R1. Linearization is provided by R5. Gain is determined by R2, R3 and R4. The circuit is configured such that the output, VOUT, ranges from 0 V to 5 V over the temperature range from 0°C to 200°C. The OPA4188 requires split power supplies (±5.35 V to ±15 V) for proper operation in this configuration. +15 V (5 V) Out REF5050 In 1 mF 1 mF R2 49.1 kW R3 60.4 kW R1 4.99 kW 1/4 OPA4188 VOUT 0°C = 0 V 200°C = 5 V R5 (1) 105.8 kW RTD Pt100 R4 1 kW (1) R5 provides positive-varying excitation to linearize output. Figure 47. RTD Amplifier With Linearization Circuit 22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 10 Power Supply Recommendations The OPA4188 is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C to 125°C and –55°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply applications. 11 Layout 11.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. – The OPA6x7 is capable of high-output current (in excess of 45 mA). Applications with low impedance loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger bypass capacitors such as 1-µF solid tantalum capacitors may improve dynamic performance in these applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques (SLOA089). • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. As shown in Figure 48, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • The case (TO-99 metal package only) is internally connected to the negative power supply, as with most common operational amplifiers. • Pin 8 of the plastic PDIP, SOIC, and TO-99 packages has no internal connection. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 23 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com 11.2 Layout Example + VIN A + VIN B VOUT A RG VOUT B RG RF RF + VIN C + VIN D VOUT C RG VOUT D RG RF RF (Schematic Representation) Output A Output D -In A -In D RF GND RF RG GND RG VIN A +In A +In D VIN D GND V+ V- GND +In B +In C VIN B GND -In B GND -In C RF RF Output C Output B Place components close to device and to each other to reduce parasitic errors VIN C RG RG Use low-ESR, ceramic bypass capacitor. Place as close to the device as possible Keep input traces short and run the input traces as far away from the supply lines as possible Ground (GND) plane on another layer Figure 48. OPA4188 Layout Example 24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 OPA4188 www.ti.com SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Device Support 12.1.1.1 Development Support 12.1.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 12.1.1.1.2 TI Precision Designs The OPAx188 (or similar operational amplifiers) are featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 12.1.1.1.3 WEBENCH® Filter Designer WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes. 12.1.2 Related Documentation For related documentation see the following: • Circuit Board Layout Techniques, SLOA089. • Op Amps for Everyone, SLOD006. • Operational amplifier gain stability, Part 3: AC gain-error analysis, SLYT383. • Operational amplifier gain stability, Part 2: DC gain-error analysis, SLYT374. • Using infinite-gain, MFB filter topology in fully differential active filters, SLYT343. • Op Amp Performance Analysis, SBOS054. • Single-Supply Operation of Operational Amplifiers, SBOA059. • Tuning in Amplifiers, SBOA067. • Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046. 12.2 Trademarks TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 25 OPA4188 SBOS641C – JUNE 2012 – REVISED NOVEMBER 2015 www.ti.com 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: OPA4188 PACKAGE OPTION ADDENDUM www.ti.com 19-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA4188AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4188 OPA4188AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4188 OPA4188AIPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4188 OPA4188AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4188 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Apr-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OPA4188AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4188AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA4188AIDR SOIC D 14 2500 367.0 367.0 38.0 OPA4188AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated