AD MSS1048 6.5 v, 4 a, high efficiency Datasheet

FEATURES
APPLICATIONS
Point-of-load conversion
Communications and networking equipment
Industrial and instrumentation
Consumer electronics
TYPICAL APPLICATIONS CIRCUIT
R1
PGOOD VIN
VIN
CIN
C1
R2
PVIN
L
EN
SW
SYNC
ADP2164
TRK
COUT
FB
VOUT
PGND
GND
09944-001
RT
RT
Figure 1.
100
95
90
85
EFFICIENCY (%)
4 A continuous output current
43 mΩ and 29 mΩ integrated FET
±1.5% output accuracy
Input voltage range: 2.7 V to 6.5 V
Output voltage: 0.6 V to VIN
Switching frequency
Fixed frequency: 600 kHz or 1.2 MHz
Adjustable frequency: 500 kHz to 1.4 MHz
Synchronizable from 500 kHz to 1.4 MHz
Selectable synchronize phase shift: 0° or 180°
Current mode architecture
Precision enable input
Power-good output
Voltage tracking input
Integrated soft start
Internal compensation
Starts up into a precharged output
UVLO, OVP, OCP, and thermal shutdown
Available in 16-lead, 4 mm × 4 mm LFCSP package
80
75
70
65
60
VIN = 5V
fS = 600kHz
55
50
0
0.5
1.0
VOUT = 1.2V
VOUT = 3.3V
1.5
2.0
2.5
OUTPUT CURRENT (A)
3.0
3.5
4.0
09944-002
Data Sheet
6.5 V, 4 A, High Efficiency,
Step-Down DC-to-DC Regulator
ADP2164
Figure 2. Efficiency vs. Output Current
GENERAL DESCRIPTION
The ADP2164 is a 4 A, synchronous, step-down dc-to-dc regulator
in a compact 4 mm × 4 mm LFCSP package. The regulator uses a
current mode, constant frequency pulse-width modulation (PWM)
control scheme for excellent stability and transient response.
The ADP2164 integrates a pair of low on-resistance P-channel
and N-channel internal MOSFETs to maximize efficiency and
minimize external component count. The 100% duty cycle
operation allows low dropout voltage at 4 A output current.
The input voltage range of the ADP2164 is 2.7 V to 6.5 V. The
output voltage of the ADP2164 is adjustable from 0.6 V to the
input voltage (VIN). The ADP2164 is also available in six preset
output voltage options: 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.
The high, 1.2 MHz PWM switching frequency allows the use of
small external components, and the SYNC input enables multiple
ICs to synchronize out of phase to reduce ripple and eliminate
beat frequencies.
Other key features of the ADP2164 include undervoltage lockout
(UVLO), integrated soft start to limit inrush current at startup,
overvoltage protection (OVP), overcurrent protection (OCP),
and thermal shutdown.
Rev. 0
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Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADP2164
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Integrated Soft Start ................................................................... 14
Applications ....................................................................................... 1
Oscillator and Synchronization ................................................ 14
Typical Applications Circuit............................................................ 1
Power Good ................................................................................ 15
General Description ......................................................................... 1
Current Limit and Short-Circuit Protection ............................ 15
Revision History ............................................................................... 2
Overvoltage Protection (OVP) ................................................. 15
Specifications..................................................................................... 3
Undervoltage Lockout (UVLO) ............................................... 15
Absolute Maximum Ratings............................................................ 5
Thermal Shutdown .................................................................... 15
Thermal Resistance ...................................................................... 5
Applications Information .............................................................. 16
ESD Caution .................................................................................. 5
Output Voltage Selection........................................................... 16
Pin Configuration and Function Descriptions ............................. 6
Inductor Selection ...................................................................... 16
Typical Performance Characteristics ............................................. 7
Output Capacitor Selection....................................................... 16
Functional Block Diagram ............................................................ 13
Input Capacitor Selection .......................................................... 17
Theory of Operation ...................................................................... 14
Voltage Tracking ......................................................................... 17
Control Scheme .......................................................................... 14
Applications Circuits...................................................................... 18
Slope Compensation .................................................................. 14
Outline Dimensions ....................................................................... 19
Precision Enable/Shutdown ...................................................... 14
Ordering Guide .......................................................................... 19
REVISION HISTORY
12/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
ADP2164
SPECIFICATIONS
VIN = PVIN = 3.3 V, EN high, SYNC high, TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C.
Table 1.
Parameter
VIN AND PVIN PINS
VIN Voltage Range
PVIN Voltage Range
Quiescent Current
Shutdown Current
VIN Undervoltage Lockout Threshold
OUTPUT CHARACTERISTICS
Load Regulation
Line Regulation
FB PIN
FB Regulation Voltage
FB Bias Current
SW PIN
High-Side On Resistance 1
Symbol
VIN
PVIN
IVIN
ISHDN
UVLO
VFB
IFB
Low-Side On Resistance1
SW Peak Current Limit
SW Maximum Duty Cycle
SW Minimum On Time 2
TRK PIN
TRK Input Voltage Range
TRK to FB Offset Voltage
TRK Input Bias Current
FREQUENCY
Switching Frequency
Switching Frequency Range
RT Pin Input High Voltage
RT Pin Input Low Voltage
SYNC PIN
Synchronization Range
Minimum Pulse Width
Minimum Off Time
Input High Voltage
Input Low Voltage
PGOOD PIN
Power-Good Range
Test Conditions/Comments
Typ
2.7
2.7
Unit
6.5
6.5
1100
12
2.7
V
V
μA
μA
V
V
2.4
TJ = −40°C to +125°C
0.591
0.6
0.01
0.609
0.1
V
μA
VIN = PVIN = 3.3 V, ISW = 500 mA
VIN = PVIN = 5 V, ISW = 500 mA
VIN = PVIN = 3.3 V, ISW = 500 mA
VIN = PVIN = 5 V, ISW = 500 mA
High-side switch, PVIN = 3.3 V
Full frequency
Full frequency
35
30
24
20
5
52
43
32
29
6.2
70
55
40
35
7.4
100
mΩ
mΩ
mΩ
mΩ
A
%
ns
600
+15
100
mV
mV
nA
1.32
660
720
1400
MHz
kHz
kHz
kHz
V
V
RT = VIN
RT = GND
RT = 91 kΩ
895
9
2.6
2.5
Max
No switching
VIN = PVIN = 6.5 V, EN = GND
VIN rising
VIN falling
Specified by the circuit in Figure 42
IO = 0 A to 4 A
IO = 2 A
TRK = 0 mV to 500 mV
fS
Min
0.05
0.05
%/A
%/V
100
0
−15
1.08
540
480
500
1.2
1.2
600
600
0.45
0.5
100
100
1.2
1.4
0.4
Power-Good Deglitch Time
FB rising threshold
FB rising hysteresis
FB falling threshold
FB falling hysteresis
From FB to PGOOD
Power-Good Leakage Current
Power-Good Output Low Voltage
VPGOOD = 5 V
IPGOOD = 1 mA
Rev. 0 | Page 3 of 20
105
85
110
2.5
90
2.5
16
115
95
0.1
170
1
220
MHz
ns
ns
V
V
%
%
%
%
Clock
cycles
μA
mV
ADP2164
Parameter
INTEGRATED SOFT START
Soft Start Time
EN PIN
EN Input Rising Threshold
EN Input Hysteresis
EN Pull-Down Resistor
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
Data Sheet
Symbol
Test Conditions/Comments
Min
All switching frequencies
Pin-to-pin measurements.
Guaranteed by design.
Rev. 0 | Page 4 of 20
Max
2048
1.12
TJ increasing
Typ
1.2
100
1
140
15
Unit
Clock
cycles
1.28
V
mV
MΩ
°C
°C
Data Sheet
ADP2164
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
PVIN, VIN, SW
FB, SYNC, TRK, RT, EN, PGOOD
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
θJA is measured using natural convection on a JEDEC 4-layer
board. The exposed pad is soldered to the printed circuit board
with thermal vias.
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Table 3. Thermal Resistance
Package Type
16-Lead LFCSP
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 20
θJA
38.3
Unit
°C/W
ADP2164
Data Sheet
13 PVIN
14 VIN
15 EN
16 PGOOD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 PVIN
SYNC 1
TRK 3
ADP2164
11 SW
TOP VIEW
(Not to Scale)
10 SW
FB 4
SW
PGND 8
PGND 7
PGND 6
GND 5
9
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED
TO AN EXTERNAL GROUND PLANE UNDER
THE IC FOR THERMAL DISSIPATION.
09944-003
RT 2
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
SYNC
2
RT
3
TRK
4
FB
5
6, 7, 8
9, 10, 11
12, 13
GND
PGND
SW
PVIN
14
VIN
15
EN
16
17 (EPAD)
PGOOD
Exposed Pad
Description
Synchronization Input. To synchronize the switching frequency to an external clock, connect this pin to an
external clock with a frequency of 500 kHz to 1.4 MHz (see the Oscillator and Synchronization section for
more information).
Frequency Setting. To select a switching frequency of 600 kHz, connect this pin to GND; to select a switching
frequency of 1.2 MHz, connect this pin to VIN. To program the frequency from 500 kHz to 1.4 MHz, connect a
resistor from this pin to GND (see the Oscillator and Synchronization section for more information).
Tracking Input. To track a master voltage, connect the TRK pin to a voltage divider from the master voltage. If
the tracking function is not used, connect the TRK pin to VIN. For more information, see the Voltage Tracking
section.
Feedback Voltage Sense Input. Connect this pin to a resistor divider from VOUT. For the preset output version,
connect this pin directly to VOUT.
Analog Ground. Connect to the ground plane.
Power Ground. Connect to the ground plane and to the output return side of the output capacitor.
Switch Node Output. Connect to the output inductor.
Power Input Pin. Connect this pin to the input power source. Connect a bypass capacitor between this pin
and PGND.
Bias Voltage Input Pin. Connect a bypass capacitor between this pin and GND; connect a small (10 Ω) resistor
between this pin and PVIN.
Precision Enable Pin. The external resistor divider can be used to set the turn-on threshold. To enable the
part automatically, connect the EN pin to VIN. This pin has a 1 MΩ pull-down resistor to GND.
Power-Good Output (Open Drain). Connect this pin to a resistor from any pull-up voltage lower than 6.5 V.
The exposed pad should be soldered to an external ground plane under the IC for thermal dissipation.
Rev. 0 | Page 6 of 20
Data Sheet
ADP2164
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
90
80
80
EFFICIENCY (%)
100
60
INDUCTOR: COILCRAFT
MSS1038-152NLB
0
1
2
OUTPUT CURRENT (A)
40
4
3
30
100
90
90
80
80
EFFICIENCY (%)
100
70
60
0
1
2
OUTPUT CURRENT (A)
4
3
70
60
30
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
INDUCTOR: COILCRAFT
MSS1038-102NLB
0
1
2
OUTPUT CURRENT (A)
4
3
Figure 5. Efficiency vs. Output Current, VIN = 3.3 V, fS = 1.2 MHz
Figure 8. Efficiency vs. Output Current, VIN = 5 V, fS = 1.2 MHz
1050
11
10
SHUTDOWN CURRENT (µA)
1000
950
900
850
TJ = –40°C
TJ = +25°C
TJ = +125°C
800
750
2.7
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
5.9
6.3
9
8
7
6
TJ = –40°C
TJ = +25°C
TJ = +125°C
5
4
2.7
09944-006
QUIESCENT CURRENT (µA)
2
OUTPUT CURRENT (A)
40
4
3
1
Figure 6. Quiescent Current vs. VIN (No Switching)
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
Figure 9. Shutdown Current vs. VIN
Rev. 0 | Page 7 of 20
5.9
6.3
09944-009
30
INDUCTOR: COILCRAFT
MSS1038-102NLB
0
50
VOUT = 0.6V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
40
INDUCTOR: COILCRAFT
MSS1038-152NLB
Figure 7. Efficiency vs. Output Current, VIN = 5 V, fS = 600 kHz
09944-005
EFFICIENCY (%)
Figure 4. Efficiency vs. Output Current, VIN = 3.3 V, fS = 600 kHz
50
VOUT = 0.6V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
50
VOUT = 0.6V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
40
30
60
09944-008
50
70
09944-007
70
09944-004
EFFICIENCY (%)
TJ = 25°C, VIN = 5 V, VOUT = 1.2 V, L = 1 μH, CIN = 47 μF, COUT = 100 μF, unless otherwise noted.
ADP2164
Data Sheet
606
1.30
605
1.28
1.26
604
1.24
1.22
ENABLE THRESHOLD (V)
602
601
600
599
598
597
1.18
1.16
1.14
1.12
1.08
1.06
1.04
595
0
20
40
60
80
TEMPERATURE (°C)
100
120
1.00
–40
09944-010
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 13. EN Threshold vs. Temperature
80
60
70
NFET RESISTOR (mΩ)
50
60
50
40
30
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
5.9
6.3
40
30
20
TJ = –40°C
TJ = +25°C
TJ = +125°C
10
2.7
09944-011
PFET RESISTOR (mΩ)
–20
09944-013
1.02
Figure 10. Feedback Voltage vs. Temperature, VIN = 3.3 V
20
2.7
FALLING
1.10
596
594
–40
RISING
1.20
Figure 11. PFET Resistor vs. VIN (Pin-to-Pin Measurements)
TJ = –40°C
TJ = +25°C
TJ = +125°C
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
5.9
6.3
09944-014
FEEDBACK VOLTAGE (mV)
603
Figure 14. NFET Resistor vs. VIN (Pin-to-Pin Measurements)
1300
650
640
1275
630
FREQUENCY (kHz)
1225
1200
1175
620
610
600
590
580
1150
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
5.9
6.3
TJ = –40°C
TJ = +25°C
TJ = +125°C
560
550
2.7
Figure 12. Switching Frequency vs. VIN, fS = 1.2 MHz (RT = VIN)
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
5.9
6.3
Figure 15. Switching Frequency vs. VIN, fS = 600 kHz (RT = GND)
Rev. 0 | Page 8 of 20
09944-015
1100
2.7
570
TJ = –40°C
TJ = +25°C
TJ = +125°C
1125
09944-012
FREQUENCY (kHz)
1250
Data Sheet
ADP2164
650
2.70
2.68
640
2.66
2.64
UVLO THRESHOLD (V)
620
610
600
590
580
TJ = –40°C
TJ = +25°C
TJ = +125°C
2.60
2.58
2.56
2.54
2.52
FALLING
2.50
2.48
550
2.7
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
5.9
2.44
2.42
6.3
2.40
–40
Figure 16. Switching Frequency vs. VIN, fS = 600 kHz (RT = 91 kΩ)
–20
0
20
40
60
80
TEMPERATURE (°C)
100
09944-019
560
120
Figure 19. UVLO Threshold vs. Temperature, VIN = 3.3 V
6.8
7.0
6.6
6.8
6.4
6.6
PEAK CURRENT LIMIT (A)
6.2
6.0
5.8
5.6
5.4
6.4
6.2
6.0
5.8
5.6
–20
0
20
40
60
80
TEMPERATURE (°C)
100
5.4
2.7
09944-017
5.2
–40
120
Figure 17. Peak Current Limit vs. Temperature, VIN = 3.3 V
3.1
3.5
3.9
4.3
4.7
VIN (V)
5.1
5.5
5.9
09944-020
PEAK CURRENT LIMIT (A)
RISING
2.62
2.46
570
09944-016
FREQUENCY (kHz)
630
6.3
Figure 20. Peak Current Limit vs. VIN, TJ = 25°C
T
T
EN
EN
3
3
VOUT
VOUT
1
1
PGOOD
PGOOD
2
IL
4
CH1 500mV
CH3 5.00V
CH2 5.00V
CH4 2.00A Ω
M 1.00ms
T 20.20%
A CH3
2.50V
09944-018
4
IL
CH1 500mV
CH3 5.00V
Figure 18. Soft Start with Full Load, VIN = 5 V, VOUT = 1.2 V, fS = 1.2 MHz
CH2 5.00V
CH4 2.00A Ω
M 1.00ms
T 20.20%
A CH3
2.50V
09944-021
2
Figure 21. Soft Start with Precharged Output Voltage, VIN = 5 V, fS = 1.2 MHz
Rev. 0 | Page 9 of 20
ADP2164
Data Sheet
T
T
VOUT (AC)
VOUT (AC)
1
1
IO
IO
CH1 100mV
BW
CH4 2.00A Ω
M 200µs
A CH4
2.52A
T 20.20%
CH1 100mV
Figure 22. Load Transient, 0.5 A to 3.5 A Load Step,
VIN = 5 V, VOUT = 1.2 V, fS = 1.2 MHz
BW
CH4 2.00A Ω
A CH4
2.52A
T 20.20%
Figure 25. Load Transient, 0.5 A to 3.5 A Load Step,
VIN = 5 V, VOUT = 1.2 V, fS = 600 kHz
T
T
SYNC
SYNC
1
M 200µs
09944-025
4
09944-022
4
1
SW
SW
2
CH2 2.00V
M 400ns
A CH1
2.50V
T 60.40%
CH1 5.00V
CH2 2.00V
M 400ns
A CH1
2.50V
T 60.40%
Figure 23. ADP2164 Synchronized to 1 MHz, in Phase
09944-026
CH1 5.00V
09944-023
2
Figure 26. ADP2164 Synchronized to 1 MHz, 180° out of Phase
T
T
VOUT
VOUT
1
1
SW
SW
2
2
IL
IL
CH1 500mV BW CH2 5.00V
M 2.00ms
CH4 5.00A Ω BW
T 30.20%
A CH1
680mV
CH1 500mV BW CH2 5.00V
M 2.00ms
CH4 5.00 AΩ BW
T 60.60%
Figure 24. Output Short
A CH1
Figure 27. Output Short Recovery
Rev. 0 | Page 10 of 20
680mV
09944-027
4
09944-024
4
Data Sheet
ADP2164
T
T
VOUT
1
TRK
IL
FB
4
SW
4
A CH2
820mV
CH1 5.00mV
3.30V
60
200
160
48
120
36
120
24
80
24
80
–12
–40
–24
–80
–36
–60
1k
10k
1
100k
FREQUENCY (Hz)
2
–80
–60
–120
CROSS FREQUENCY: 61kHz
PHASE MARGIN: 69°
1k
10k
–160
1
100k
FREQUENCY (Hz)
2
–200
1M
Figure 32. Bode Plot at VIN = 5 V, VOUT = 1.2 V, IO = 4 A, fS = 1.2 MHz,
L = 0.68 μH, COUT = 47 μF + 100 μF
200
60
200
36
120
24
80
24
80
12
40
PHASE
0
0
–12
–40
–24
–80
–36
–48
–120
CROSS FREQUENCY: 52kHz
PHASE MARGIN: 69°
–60
1k
MAGNITUDE (dB)
48
120
MAGNITUDE
PHASE (Degrees)
160
36
10k
1
100k
FREQUENCY (Hz)
2
12
40
PHASE
0
0
–12
–40
–24
–80
–160
–48
–200
–60
1M
160
MAGNITUDE
–120
–36
09944-030
48
–40
–48
Figure 29. Bode Plot at VIN = 5 V, VOUT = 1.0 V, IO = 4 A, fS = 1.2 MHz,
L = 0.68 μH, COUT = 2 × 100 μF
60
0
–24
–200
1M
PHASE
–12
–160
09944-029
–48
0
–36
–120
CROSS FREQUENCY: 57kHz
PHASE MARGIN: 67°
40
12
Figure 30. Bode Plot at VIN = 5 V, VOUT = 1.5 V, IO = 4 A, fS = 1.2 MHz,
L = 1 μH, COUT = 47 μF + 100 μF
1k
CROSS FREQUENCY: 61kHz
PHASE MARGIN: 66°
10k
–160
1
100k
FREQUENCY (Hz)
2
–200
1M
Figure 33. Bode Plot at VIN = 5 V, VOUT = 1.8 V, IO = 4 A, fS = 1.2 MHz,
L = 1 μH, COUT = 100 μF
Rev. 0 | Page 11 of 20
PHASE (Degrees)
0
160
MAGNITUDE
09944-033
40
PHASE
0
MAGNITUDE (dB)
12
PHASE (Degrees)
MAGNITUDE
PHASE (Degrees)
200
36
48
MAGNITUDE (dB)
A CH2
T 30.60%
Figure 31. Steady Waveform, VIN = 5 V, VOUT = 1.2 V, fS = 1.2 MHz
60
MAGNITUDE (dB)
M 400ns
09944-032
Figure 28. Tracking Function
CH2 5.00V
CH4 2.00A Ω
09944-031
CH2 500mV BW M 2.00ms
CH4 500mV BW
T 40.40%
09944-028
2
ADP2164
Data Sheet
60
160
48
36
80
24
12
PHASE
40
0
0
–12
–40
–24
–80
–36
–120
–48
CROSS FREQUENCY: 83kHz
PHASE MARGIN: 60°
–60
1k
10k
1
100k
FREQUENCY (Hz)
2
MAGNITUDE (dB)
120
24
PHASE (Degrees)
36
120
80
PHASE
12
40
0
0
–12
–40
–24
–80
–160
–48
–200
–60
1M
160
MAGNITUDE
–36
09944-034
MAGNITUDE (dB)
MAGNITUDE
200
Figure 34. Bode Plot at VIN = 5 V, VOUT = 2.5 V, IO = 4 A, fS = 1.2 MHz,
L = 1 μH, COUT = 47 μF
1k
–120
CROSS FREQUENCY: 68kHz
PHASE MARGIN: 65°
10k
–160
1
100k
FREQUENCY (Hz)
2
–200
1M
Figure 35. Bode Plot at VIN = 5 V, VOUT = 3.3 V, IO = 4 A, fS = 1.2 MHz,
L = 1 μH, COUT = 47 μF
Rev. 0 | Page 12 of 20
PHASE (Degrees)
48
200
09944-035
60
Data Sheet
ADP2164
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
PVIN
UVLO
ADP2164
REGULATOR
0.6V
+
+
TRK
SOFT
START
+
PMOS
CURRENT
SENSE AMP
ERROR AMP
ZCOMP
SW
–
FB
0.66V
NFET
–
+
–
0.54V
PFET
LOGIC
CONTROL
GM
CLK
SLOPE
COMPENSATION
+
NMOS
CURRENT
SENSE AMP
OSCILLATOR
PGOOD
SYNC
RT
Figure 36. Functional Block Diagram
Rev. 0 | Page 13 of 20
PGND
09944-036
GND
ADP2164
Data Sheet
THEORY OF OPERATION
The ADP2164 operates with an input voltage from 2.7 V to 6.5 V
and regulates the output voltage down to 0.6 V. The ADP2164 is
also available with preset output voltage options of 3.3 V, 2.5 V,
1.8 V, 1.5 V, 1.2 V, and 1.0 V.
CONTROL SCHEME
The ADP2164 uses a fixed-frequency, peak current mode
PWM control architecture. At the start of each oscillator cycle,
the P-channel MOSFET switch is turned on, placing a positive
voltage across the inductor. Current in the inductor increases
until the current sense signal crosses the peak inductor current
level, turns off the P-channel MOSFET switch, and turns on the
N-channel MOSFET synchronous rectifier. This action places a
negative voltage across the inductor, causing the inductor current
to decrease. The synchronous rectifier stays on for the rest of
the cycle.
INTEGRATED SOFT START
The ADP2164 has integrated soft start circuitry to limit the
output voltage rise time and reduce inrush current at startup.
The soft start time is set at 2048 clock cycles.
If the output voltage is precharged before the part is turned
on, the ADP2164 prevents a reverse inductor current—which
would discharge the output capacitor—until the soft start
voltage exceeds the voltage on the FB pin.
OSCILLATOR AND SYNCHRONIZATION
The ADP2164 switching frequency is controlled by the RT pin.
If the RT pin is connected to GND, the switching frequency is
set to 600 kHz. If the RT pin is connected to VIN, the switching
frequency is set to 1.2 MHz.
Connecting a resistor from RT to GND allows programming
of the switching frequency from 500 kHz to 1.4 MHz. Use the
following equation to set the switching frequency:
RT (kΩ) =
Figure 37 shows the typical relationship between the switching
frequency and the RT resistor.
1600
The peak inductor current level is set by the compensation
(COMP) voltage. The COMP voltage is the output of a transconductance error amplifier that compares the feedback voltage
with an internal 0.6 V reference (see Figure 36).
1400
FREQUENCY (kHz)
1200
SLOPE COMPENSATION
To prevent subharmonic oscillations, slope compensation
stabilizes the internal current control loop of the ADP2164
when the part operates at or beyond a 50% duty cycle. Slope
compensation is implemented by summing an artificial voltage
ramp with the current sense signal during the on time of the
P-channel MOSFET switch. This voltage ramp depends on the
output voltage. When operating at high output voltages, slope
compensation increases. The slope compensation ramp value
determines the minimum inductor value that can be used to
prevent subharmonic oscillations.
PRECISION ENABLE/SHUTDOWN
54,000
f S (kHz)
1000
800
600
400
200
20
40
60
80
100
120
RT RESISTOR (kΩ)
140
160
180
09944-037
The ADP2164 is a step-down dc-to-dc regulator that uses
a fixed-frequency, peak current mode architecture with an
integrated high-side switch and low-side synchronous rectifier.
The high switching frequency and tiny, 16-lead, 4 mm × 4 mm
LFCSP package provide a small, step-down dc-to-dc regulator
solution. The integrated high-side switch (P-channel MOSFET)
and synchronous rectifier (N-channel MOSFET) yield high
efficiency.
Figure 37. Switching Frequency vs. RT Resistor
To synchronize the ADP2164, drive an external clock at the
SYNC pin. The frequency of the external clock can be in the
range of 500 kHz to 1.4 MHz.
The EN pin is a precision analog input that enables the device
when the voltage exceeds 1.2 V (typical); this pin has 100 mV
hysteresis. When the enable voltage falls below 1.1 V (typical),
the part turns off. To force the ADP2164 to start automatically
when input power is applied, connect the EN pin to the VIN pin.
When the SYNC pin is driven by an external clock, the user
can configure the switching frequency to be in phase with the
external clock or 180° out of phase with the external clock, as
follows:
When the ADP2164 is shut down, the soft start capacitor is
discharged. This causes a new soft start cycle to begin when
the part is reenabled.
•
•
An internal pull-down resistor (1 MΩ) prevents accidental
enabling of the part if the EN input is left floating.
Rev. 0 | Page 14 of 20
If the RT pin is connected to GND or to a resistor, the
switching frequency is in phase with the external clock.
If the RT pin is connected to VIN, the switching frequency
is 180° out of phase with the external clock.
Data Sheet
ADP2164
POWER GOOD
OVERVOLTAGE PROTECTION (OVP)
PGOOD is an active high, open-drain output and requires a
resistor to pull it up to the logic supply voltage. PGOOD high
indicates that the voltage on the FB pin (and, therefore, the
output voltage) is within 10% of the desired value. PGOOD low
indicates the opposite. There is a 16-cycle waiting period after
the FB voltage is detected as being out of bounds. If FB returns
to within the ±10% range, it is ignored by the PGOOD circuitry.
Overvoltage protection (OVP) circuitry is integrated in the
ADP2164. The output voltage is continuously monitored by
a comparator through the FB pin, which is at 0.6 V (typical)
under normal operation. The comparator is activated when the
FB voltage exceeds 0.66 V (typical), thus indicating an output
overvoltage condition. If the voltage remains above the OVP
threshold for 16 clock cycles, the high-side MOSFET turns off
and the low-side MOSFET turns on until the current through it
reaches the −1.3 A current limit. Both MOSFETs remain in the
off state until FB falls below 0.54 V (typical), after which the
part restarts. The behavior of PGOOD under this condition is
described in the Power Good section.
CURRENT LIMIT AND SHORT-CIRCUIT PROTECTION
The ADP2164 has a peak current limit protection circuit to
prevent current runaway. The peak current limit is 6.2 A. When
the inductor current reaches the peak current limit, the high-side
MOSFET turns off and the low-side MOSFET turns on until the
next cycle begins.
The overcurrent counter is incremented by 1 at each peak
current limit event. If the overcurrent counter exceeds 10, the
part enters hiccup mode, and the high-side FET and low-side
FET are both turned off. The part remains in this mode for
4096 clock cycles and then attempts to restart using soft start.
If the current limit fault has cleared, the part resumes normal
operation. If the current limit fault has not cleared, the part
reenters hiccup mode after first counting 10 current limit
violations.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout (UVLO) circuitry is integrated in the
ADP2164. If the input voltage falls below 2.5 V, the ADP2164
shuts down, and both the power switch and the synchronous
rectifier turn off. When the voltage rises above 2.6 V again,
the soft start is initiated, and the part is enabled.
THERMAL SHUTDOWN
If the ADP2164 junction temperature rises above 140°C, the
thermal shutdown circuit turns off the regulator. Extreme junction temperatures can be the result of high current operation,
poor circuit board design, and/or high ambient temperature.
When thermal shutdown occurs, a 15°C hysteresis ensures that
the ADP2164 does not return to operation until the on-chip
temperature falls below 125°C. Soft start is initiated when the
part comes out of thermal shutdown.
Rev. 0 | Page 15 of 20
ADP2164
Data Sheet
APPLICATIONS INFORMATION
The typical application circuit for the ADP2164 is shown in
Figure 38.
R1
10Ω
16
15 14
PGOOD EN VIN
1
2
3
4
ADP2164ACPZ
SW
TRK
SW
FB
SW
12
11
VIN
3.3V
The negative current limit (−1.3 A) also limits the minimum
inductor value. The inductor current ripple (ΔIL) calculated by
the selected inductor should not exceed 2.6 A.
L
0.8µH
10
9
COUT1
47µF
X5R
6.3V
COUT2
100µF
X5R
6.3V
VOUT
1.2V
4A
The peak inductor current should be kept below the peak current
limit threshold and is calculated using the following equation:
I PEAK = I O +
GND PGND PGND PGND
5
6
7
8
L: MSS1048-801NL COILCRAFT
CIN: C3225X5R1A476M TDK
COUT1: C3225X5R0J476M TDK
RTOP
COUT2: C3225X5R0J107M TDK
10kΩ
09944-042
RBOT
10kΩ
13
PVIN
PVIN
SYNC
RT
CIN
47µF
X5R
10V
C1
0.1µF
R2
10kΩ
The ADP2164 uses slope compensation in the current control
loop to prevent subharmonic oscillations when the duty cycle
is larger than 50%. The internal slope compensation limits the
minimum inductor value.
Figure 38. Typical Application Circuit
OUTPUT VOLTAGE SELECTION
The output voltage of the adjustable version of the ADP2164 is
set by an external resistive voltage divider using the following
equation:
⎛
R
VOUT = 0.6 × ⎜⎜1 + TOP
R BOT
⎝
⎞
⎟
⎟
⎠
INDUCTOR SELECTION
The inductor value is determined by the operating frequency,
input voltage, output voltage, and ripple current. A small inductor
value provides larger inductor current ripple and fast transient
response but degrades efficiency; a large inductor value provides
small inductor current ripple and good efficiency but slows
transient response. For a reasonable trade-off between transient
response and efficiency, the inductor current ripple, ΔIL, is typically
set to one-third the maximum load current. The inductor value
is calculated using the following equation:
(VIN − VOUT ) × D
ΔI L × f S
where:
VIN is the input voltage.
VOUT is the output voltage.
ΔIL is the inductor current ripple.
fS is the switching frequency.
D is the duty cycle (VOUT/VIN).
Ensure that the rms current of the selected inductor is greater
than the maximum load current and that its saturation current
is greater than the peak current limit of the converter.
OUTPUT CAPACITOR SELECTION
The output capacitor value is determined by the output voltage
ripple, load step transient, and loop stability. The output ripple
is determined by the ESR and the capacitance.
⎛
1
ΔVOUT = ΔI L × ⎜ ESR +
⎜
×
8 COUT × f S
⎝
⎞
⎟
⎟
⎠
The load step transient response depends on the inductor, the
output capacitor, and the current control loop.
To limit output voltage accuracy degradation due to FB bias
current (0.1 μA maximum) to less than 0.5% (maximum),
ensure that RBOT is less than 30 kΩ.
L=
ΔI L
2
The ADP2164 has integrated loop compensation for simple
power design. Table 5 and Table 6 show the recommended
values for inductors and capacitors for the ADP2164 based
on the input and output voltages for the part. X5R or X7R
dielectric ceramic capacitors are highly recommended.
Table 5. Recommended L and COUT Values at fS = 1.2 MHz
VIN (V)
3.3
3.3
3.3
3.3
3.3
5
5
5
5
5
5
Rev. 0 | Page 16 of 20
VOUT (V)
1.0
1.2
1.5
1.8
2.5
1.0
1.2
1.5
1.8
2.5
3.3
L (μH)
0.8
0.8
1
1
1
0.8
0.8
1
1
1
1
COUT (μF)
100 + 100
100 + 47
100 + 47
100
47
100 + 100
100 + 47
100 + 47
100
47
47
Data Sheet
ADP2164
VOLTAGE TRACKING
Table 6. Recommended L and COUT Values at fS = 600 kHz
VOUT (V)
1.0
1.2
1.5
1.8
2.5
1.0
1.2
1.5
1.8
2.5
3.3
L (μH)
1
1
1
1
1
1
1.5
1.5
1.5
1.5
1.5
The ADP2164 includes a tracking feature that allows the
ADP2164 output (slave voltage) to be configured to track
an external voltage (master voltage), as shown in Figure 39.
COUT (μF)
100 + 100
100 + 100
100 + 47
100 + 47
100
100 + 100
100 + 100
100 + 47
100 + 47
100
100
VMASTER
TRK
RTOP
RTRKB
FB
RBOT
Figure 39. Voltage Tracking
Higher or lower values of inductors and output capacitors can
be used in the regulator, but system stability and load transient
performance must be verified.
Table 7 and Table 8 list some recommended inductors and
capacitors for the ADP2164.
Table 7. Recommended Inductors
Manufacturer
Coilcraft®
Sumida
VSLAVE
ADP2164
RTRKT
09944-039
VIN (V)
3.3
3.3
3.3
3.3
3.3
5
5
5
5
5
5
Coincident Tracking
A common requirement is coincident tracking, as shown in
Figure 40. Coincident tracking limits the slave output voltage
to the same value as the master voltage until the slave output
voltage reaches regulation. Connect the TRK pin to a resistor
divider driven from the master voltage, as shown in Figure 39.
For coincident tracking, set RTRKT = RTOP and RTRKB = RBOT.
Part No.
MSS1038, MSS1048, MSS1260
CDRH103R, CDRH104R, CDRH105R
VMASTER
VSLAVE
VOLTAGE
Part No.
GRM32ER60J107ME20
GRM32ER60J476ME20
C3225X5R0J107M
C3225X5R0J476M
Description
100 μF, 6.3 V, X5R, 1210
47 μF, 6.3 V, X5R, 1210
100 μF, 6.3 V, X5R, 1210
47 μF, 6.3 V, X5R, 1210
INPUT CAPACITOR SELECTION
TIME
Figure 40. Coincident Tracking
Ratiometric Tracking
Ratiometric tracking is shown in Figure 41. The slave output is
limited to a fraction of the master voltage. In this application, the
slave and master voltages reach their final values at the same time.
The input capacitor reduces the input voltage ripple caused by
the switch current on PVIN. Place the input capacitor as close
as possible to the PVIN pins. A 22 μF or 47 μF ceramic capacitor
is recommended. The rms current rating of the input capacitor
should be larger than the value calculated using the following
equation:
VMASTER
VSLAVE
VOLTAGE
I RMS = I O × D × (1 − D )
where D is the duty cycle.
TIME
09944-041
Manufacturer
Murata
Murata
TDK
TDK
09944-040
Table 8. Recommended Capacitors
Figure 41. Ratiometric Tracking
The ratio of the slave output voltage to the master voltage is a
function of the two dividers.
VSLAVE
V MASTER
Rev. 0 | Page 17 of 20
RTOP
R BOT
=
RTRKT
1+
RTRKB
1+
ADP2164
Data Sheet
APPLICATIONS CIRCUITS
3
4
RT
ADP2164ACPZ
TRK
SW
SW
SW
FB
12
11
1
L
0.8µH
COUT1
47µF
X5R
6.3V
10
9
COUT2
100µF
X5R
6.3V
VOUT
1.2V
4A
2
RT
54kΩ
3
4
GND PGND PGND PGND
5
6
7
8
L: MSS1048-801NL COILCRAFT
CIN: C3225X5R1A476M TDK
COUT1: C3225X5R0J476M TDK
RTOP
C
10kΩ
OUT2: C3225X5R0J107M TDK
09944-042
RBOT
10kΩ
PVIN
SYNC
16
15 14
PGOOD EN VIN
RT
16
15 14
PGOOD EN VIN
1MHz
EXT
CLOCK
1
2
3
4
13
PVIN
PVIN
SYNC
RT
ADP2164ACPZ
SW
TRK
SW
FB
SW
12
TRK
SW
FB
SW
11
COUT
100µF
X5R
6.3V
10
9
16
15 14
PGOOD EN VIN
1
VOUT
1.8V
4A
2
3
4
09944-044
RBOT
10kΩ
2
3
4
SYNC
13
PVIN
PVIN
RT
SW
TRK
SW
FB
SW
ADP2164ACPZ-1.2
12
11
10
9
RT
ADP2164ACPZ
11
SW
TRK
SW
FB
SW
L
1µH
COUT1
47µF
X5R
6.3V
10
9
16
15 14
PGOOD EN VIN
1
GND PGND PGND PGND
5
6
7
8
L: MSS1048-801NL COILCRAFT
CIN: C3225X5R1A476M TDK
COUT1: C3225X5R0J476M TDK
COUT2: C3225X5R0J107M TDK
VOUT
1.2V
4A
RTRKT
10kΩ
VMASTER
RTRKB
2.21kΩ
2
3
4
SYNC
RT
CIN
47µF
X5R
10V
C1
0.1µF
R2
10kΩ
COUT2
100µF
X5R
6.3V
COUT2
100µF
X5R
6.3V
VOUT
1.5V
4A
L: MSS1038-102NL COILCRAFT
CIN: C3225X5R1A476M TDK
COUT1: C3225X5R0J476M TDK
COUT2: C3225X5R0J107M TDK
R1
10Ω
L
0.8µH
COUT1
47µF
X5R
6.3V
12
PVIN
RTOP
15kΩ
VIN
5V
09944-046
16
15 14
PGOOD EN VIN
1
CIN
47µF
X5R
10V
C1
0.1µF
SYNC
VIN
5V
Figure 46. 1.5 V, 4 A Step-Down Regulator, Synchronized to 1 MHz,
180° out of Phase with the External Clock
Figure 43. 1.8 V, 4 A Step-Down Regulator,
Synchronized to 1 MHz, in Phase with the External Clock
R2
10kΩ
CIN
47µF
X5R
10V
13
PVIN
GND PGND PGND PGND
5
6
7
8
R1
10Ω
9
C1
0.1µF
R2
10kΩ
L: MSS1038-102NL COILCRAFT
CIN: C3225X5R1A476M TDK
COUT: C3225X5R0J107M TDK
RTOP
20kΩ
10
R1
10Ω
GND PGND PGND PGND
5
6
7
8
RBOT
10kΩ
VOUT
3.3V
4A
COUT
47µF
X5R
6.3V
Figure 45. 3.3 V, 4 A, 1 MHz Step-Down Regulator
1MHz
EXT
CLOCK
L
1µH
SW
ADP2164ACPZ
L
1µH
11
GND PGND PGND PGND
5
6
7
8
L: MSS1038-102NL COILCRAFT
CIN: C3225X5R1A476M TDK
RBOT RTOP
COUT: C3225X5R0J476M TDK
2.21kΩ 10kΩ
VIN
5V
CIN
47µF
X5R
10V
C1
0.1µF
R2
10kΩ
12
PVIN
SYNC
Figure 42. 1.2 V, 4 A, 1.2 MHz Step-Down Regulator
R1
10Ω
13
PVIN
VIN
5V
09944-043
2
13
PVIN
CIN
47µF
X5R
10V
C1
0.1µF
R2
10kΩ
09944-045
16
15 14
PGOOD EN VIN
1
CIN
47µF
X5R
10V
C1
0.1µF
R2
10kΩ
R1
10Ω
VIN
3.3V
13
PVIN
PVIN
ADP2164ACPZ
SW
TRK
SW
FB
SW
12
11
10
9
VIN
5V
L
1µH
COUT
47µF
X5R
6.3V
GND PGND PGND PGND
5
6
7
8
L: MSS1038-102NL COILCRAFT
CIN: C3225X5R1A476M TDK
RBOT RTOP
COUT: C3225X5R0J476M TDK
2.21kΩ 10kΩ
Figure 47. 3.3 V, 4 A, 1.2 MHz Step-Down Regulator, Tracking Mode
Figure 44. Fixed 1.2 V, 4 A, 1.2 MHz Step-Down Regulator
Rev. 0 | Page 18 of 20
VOUT
3.3V
4A
09944-047
R1
10Ω
Data Sheet
ADP2164
OUTLINE DIMENSIONS
0.35
0.30
0.25
0.65
BSC
PIN 1
INDICATOR
16
13
1
12
EXPOSED
PAD
2.60
2.50 SQ
2.40
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
042709-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-26)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP2164ACPZ-R7
ADP2164ACPZ-1.0-R7
ADP2164ACPZ-1.2-R7
ADP2164ACPZ-1.5-R7
ADP2164ACPZ-1.8-R7
ADP2164ACPZ-2.5-R7
ADP2164ACPZ-3.3-R7
ADP2164-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage
Adjustable
1.0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
Package Option
CP-16-26
CP-16-26
CP-16-26
CP-16-26
CP-16-26
CP-16-26
CP-16-26
ADP2164
Data Sheet
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09944-0-12/11(0)
Rev. 0 | Page 20 of 20