ON NCL30083BDR2G Dimmable quasi-resonant primary side current-mode controller for led lighting with thermal fold-back Datasheet

NCL30083
Dimmable Quasi-Resonant
Primary Side Current-Mode
Controller for LED Lighting
with Thermal Fold-back
The NCL30083 is a PWM current mode controller targeting isolated
flyback and non−isolated constant current topologies. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to precisely regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, biasing and an optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs. It supports step dimming by monitoring the AC line
and detecting when the line has been toggled on−off−on by the user to
reduce the light intensity in 5 steps down to 5% dimming.
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8
8
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
AAx
AYWG
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
Micro8
DM SUFFIX
CASE 846A
Quasi−resonant Peak Current−mode Control Operation
1
Primary Side Sensing (no optocoupler needed)
AAx
= Specific Device Code
Wide VCC Range
x
= E or F
A
= Assembly Location
Source 300 mA/Sink 500 mA Totem Pole Driver with 12 V Gate Clamp
Y
= Year
Precise LED Constant Current Regulation ±1% Typical
W
= Work Week
G
= Pb−Free Package
Line Feed−forward for Enhanced Regulation Accuracy
(Note: Microdot may be in either location)
Low LED Current Ripple
8
250 mV ±2% Guaranteed Voltage Reference for Current Regulation
L30083x
~ 0.9 Power Factor with Valley Fill Input Stage
ALYW
Low Start−up Current (13 mA typ.)
G
1
5 State Quasi−log Dimmable
L30083x = Specific Device Code
Thermal Fold−back
x
=B
Programmable soft−start
A
= Assembly Location
Wide Temperature Range of −40 to +125°C
L
= Wafer Lot
Y
= Year
Pb−free, Halide−free MSL1 Product
W
= Work Week
Robust Protection Features
G
= Pb−Free Package
♦ Over Voltage / LED Open Circuit Protection
♦ Latched and Auto−recoverable Versions
♦ Over Temperature Protection
♦ Brown−out
PIN
CONNECTIONS
♦ Secondary Diode Short Protection
♦ VCC Under Voltage
Lockout
♦ Output Short Circuit Protection
♦ Thermal Shutdown 1
SD
SS
♦ Shorted Current Sense Pin Fault Detection
ZCD
CS
GND
Typical Applications
• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
VIN
VCC
DRV
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 35 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 2
1
Publication Order Number:
NCL30083/D
NCL30083
.
.
Aux
.
1
8
2
7
3
6
4
5
Figure 1. Typical Application Schematic for NCL30083
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
SD
Thermal Fold−back
and shutdown
Connecting an NTC to this pin allows reducing the output current down to 50%
of its fixed value before stopping the controller. A Zener diode can also be
used to pull−up the pin and stop the controller for adjustable OVP protection
2
ZCD
Zero Crossing Detection
3
CS
Current sense
4
GND
−
5
DRV
Driver output
6
VCC
Supplies the controller
This pin is connected to an external auxiliary voltage.
7
VIN
Brown−Out
Input voltage sensing
This pin observes the HV rail and is used in valley selection. This pin also
monitors and protects for low mains conditions.
8
SS
Soft−Start
Connected to the auxiliary winding, this pin detects the core reset event.
This pin monitors the primary peak current
The controller ground
The current capability of the totem pole gate drive (+0.3/−0.5 A) makes it suitable to effectively drive a broad range of power MOSFETs.
A capacitor connected to ground select the soft−start duration.
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2
NCL30083
CS_shorted Enable
Over Voltage
Protection
Aux_SCP
Over Temperature
Protection
SD
Thermal
Foldback
Internal
Thermal
Shutdown
VTF
VCC_max
WOD_SCP
BO_NOK
CS
VCC
Valley Selection
S
Aux_SCP
offset_OK
Leading
Edge
Blanking
Clamp
Circuit
offset_OK
Aux. Winding
Short Circuit Prot.
Line
Feedforward
VCC Over Voltage
Protection
VVIN VREF
Zero Crossing Detection
VVIN
VCC
VCC Management
Latch
Ipkmax
Qdrv
ZCD
OFF
UVLO
Fault
Management
VREF
VDD
STOP
Q
DRV
Qdrv
VVLY
R
VTF
STOP VREF
SS
CS_reset
Constant−Current
Control
VSST
Soft−Start
Ipkmax STOP
Enable VSST
Max. Peak
Current
Limit
VVIN
GND
Enable
STEP_DIM
VVIN
Ipkmax
STEP_DIM
CS Short
Protection
CS_shorted
Winding and
Output diode
Short Circuit
Protection
Step
Dimming
VIN
Brown−Out
BO_NOK
WOD_SCP
Figure 2. Internal Circuit Architecture
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NCL30083
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
VCC(MAX)
ICC(MAX)
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3, +35
Internally limited
V
mA
VDRV(MAX)
IDRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, VDRV (Note 1)
−500, +800
V
mA
VMAX
IMAX
Maximum voltage on low power pins (except pins ZCD, SS, DRV and VCC)
Current range for low power pins (except pins ZCD, DRV and VCC)
−0.3, +5.5
−2, +5
V
mA
VZCD(MAX)
IZCD(MAX)
Maximum voltage for ZCD pin
Maximum current for ZCD pin
−0.3, +10
−2, +5
V
mA
VSST(MAX)
Maximum voltage for SS pin
−0.3, +10
V
RθJ−A
Thermal Resistance, Junction−to−Air
289
°C/W
TJ(MAX)
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (Note 2)
4
kV
ESD Capability, MM model (Note 2)
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC JESD22−A114−F and
Machine Model Method 200 V per JEDEC JESD22−A115−A.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except for VIN pin which passes 60 mA.
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NCL30083
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VCC increasing
VCC decreasing
VCC decreasing
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
16
8.2
8
3.5
18
8.8
–
4.5
20
9.4
–
5.5
Over Voltage Protection
VCC OVP threshold
VCC(OVP)
26
28
30
V
VCC(off) noise filter
VCC(reset) noise filter−
tVCC(off)
tVCC(reset)
–
–
5
20
–
–
ms
ICC(start)
–
13
30
mA
ICC(sFault)
–
46
60
mA
ICC1
ICC2
ICC3
0.8
–
–
1.2
2.3
2.7
1.4
4.0
5.0
Maximum Internal current limit
VILIM
0.95
1
1.05
V
Leading Edge Blanking Duration for VILIM
(Tj = −25°C to 125°C)
tLEB
250
300
350
ns
Leading Edge Blanking Duration for VILIM
(Tj = −40°C to 125°C)
tLEB
240
300
350
ns
Ibias
–
0.02
–
mA
tILIM
–
50
150
ns
VCS(stop)
1.35
1.5
1.65
V
tBCS
–
120
–
ns
Blanking time for CS to GND short detection VpinVIN = 1 V
tCS(blank1)
6
–
12
ms
Blanking time for CS to GND short detection VpinVIN = 3.3 V
tCS(blank2)
2
–
4
ms
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
–
–
13
30
–
–
Drive current capability
DRV Sink (Note 4)
DRV Source (Note 4)
ISNK
ISRC
–
–
500
300
–
–
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset
V
Startup current
Startup current in fault mode
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 5
Device Switching (Fsw = 65 kHz)
mA
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF,
Fsw = 65 kHz
CURRENT SENSE
Input Bias Current
DRV high
Propagation delay from current detection to gate off−state
Threshold for immediate fault protection activation
Leading Edge Blanking Duration for VCS(stop)
GATE DRIVE
W
mA
Rise Time (10% to 90%)
CDRV = 470 pF
tr
–
40
–
ns
Fall Time (90% to 10%)
CDRV = 470 pF
tf
–
30
–
ns
DRV Low Voltage
VCC = VCC(off)+0.2 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(low)
8
–
–
V
DRV High Voltage
VCC = 30 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(high)
10
12
14
V
4. Guaranteed by design
5. OTP triggers when RNTC = 4.7 kW
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NCL30083
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
ZCD threshold voltage
VZCD increasing
VZCD(THI)
25
45
65
mV
ZCD threshold voltage (Note 4)
VZCD decreasing
VZCD(THD)
5
25
45
mV
ZCD hysteresis (Note 4)
VZCD increasing
VZCD(HYS)
10
–
–
mV
VZCD(short)
0.8
1
1.2
V
tOVLD
70
90
110
ms
trecovery
3
4
5
s
Ipin1 = 3.0 mA
Ipin1 = −2.0 mA
VCH
VCL
–
−0.9
9.5
−0.6
–
−0.3
VZCD decreasing
tDEM
–
–
150
ns
tPAR
–
20
–
ns
tBLANK
2.25
3
3.75
ms
tTIMO
5
6.5
8
ms
Reference Voltage at Tj = 25°C
VREF
245
250
255
mV
Reference Voltage Tj = −40°C to 125°C
VREF
242.5
250
257.5
mV
70% reference voltage
VREF70
–
175
–
mV
40% reference Voltage
VREF40
–
100
–
mV
25% reference Voltage
VREF25
–
62.5
–
mV
10% reference Voltage
VREF10
–
25
–
mV
5% reference Voltage
VREF05
–
12.5
–
mV
Current sense lower threshold for detection of the
leakage inductance reset time
VCS(low)
30
55
80
mV
KLFF
15
17
19
mA/V
VpinVIN = 4.5 V
Ioffset(MAX)
67.5
76.5
85.5
mA
VREF value below which the offset current source is turned off
VREF decreases
VREF(off)
–
37.5
–
mV
VREF value above which the offset current source is turned on
VREF increases
VREF(on)
–
50
–
mV
Threshold for line range detection Vin increasing
(1st to 2nd valley transition for VREF > 0.75 V)
VVIN increases
VHL
2.28
2.4
2.52
V
Threshold for line range detection Vin decreasing
(2nd to 1st valley transition for VREF > 0.75 V)
VVIN decreases
VLL
2.18
2.3
2.42
V
tHL(blank)
15
25
35
ms
ZERO VOLTAGE DETECTION CIRCUIT
Threshold voltage for output short circuit or aux. winding
short circuit detection
Short circuit detection Timer
VZCD < VZCD(short)
Auto−recovery timer duration
Input clamp voltage
High state
Low state
V
Propagation Delay from valley detection to DRV high
Equivalent time constant for ZCD input (Note 4)
Blanking delay after on−time
Timeout after last demag transition
CONSTANT CURRENT CONTROL
LINE FEED−FORWARD
VVIN to ICS(offset) conversion ratio
Offset current maximum value
VALLEY SELECTION
Blanking time for line range detection
4. Guaranteed by design
5. OTP triggers when RNTC = 4.7 kW
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NCL30083
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
Valley thresholds
1st to 2nd valley transition at LL and 2nd to 3rd valley HL
2nd to 1st valley transition at LL and 3rd to 2nd valley HL
2nd to 4th valley transition at LL and 3rd to 5th valley HL
4th to 2nd valley transition at LL and 5th to 3rd valley HL
4th to 7th valley transition at LL and 5th to 8th valley HL
7th to 4th valley transition at LL and 8th to 5th valley HL
7th to 11th valley transition at LL and 8th to 12th valley HL
11th to 7th valley transition at LL and 12th to 8th valley HL
11th to 13th valley transition at LL and 12th to 15th valley HL
13th to 11th valley transition at LL and 15th to 12th valley HL
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VVLY1−2/2−3
VVLY2−1/3−2
VVLY2−4/3−5
VVLY4−2/5−3
VVLY4−7/5−8
VVLY7−4/8−5
VVLY7−11/8−12
VVLY11−7/12−8
VVLY11−13/12−15
VVLY13−11/15−12
177.5
185.0
117.5
125.0
–
–
–
–
–
–
187.5
195.0
125.0
132.5
75.0
82.5
37.5
50.0
15.0
20.0
197.5
205.0
132.5
140.0
–
–
–
–
–
–
SS pin voltage for zero output current (enable)
VSST(EN)
0.66
0.7
0.74
V
SS pin voltage for 100% of output current
VSST100
2.25
2.45
2.65
V
VSST(CLP)
–
7.8
–
V
ISST
8.5
10
11.5
mA
ISST(pre)
–
100
–
mA
SD pin voltage at which thermal fold−back starts
VTF(start)
0.9
1
1.2
V
SD pin voltage at which thermal fold−back stops
(Iout = 50% Iout(nom))
VTF(stop)
0.64
0.68
0.72
V
Reference current for direct connection of an NTC (Note 5)
IOTP(REF)
80
85
90
mA
VALLEY SELECTION
mV
SOFT−STAT PIN
Clamping voltage for SS pin
Soft−start current source
Pre−charge current source
VSST < VSST(EN)
THERMAL FOLD−BACK AND OVP
Fault detection level for OTP (Note 5)
VSD decreasing
VOTP(off)
0.47
0.5
0.53
V
SD pin level at which controller re−start switching after OTP
detection
VSD increasing
VOTP(on)
0.64
0.68
0.72
V
tOTP(start)
180
–
300
ms
Timer duration after which the controller is allowed to start
pulsing (Note 5)
Clamped voltage (SD pin left open)
SD pin open
Clamp series resistor
SD pin detection level for OVP
VSD increasing
Delay before OVP or OTP confirmation (OVP and OTP)
VSD(clamp)
1.13
1.35
1.57
V
RSD(clamp)
–
1.6
–
kW
VOVP
2.35
2.5
2.65
V
TSD(delay)
15
30
45
ms
TSHDN
130
155
170
°C
TSHDN(HYS)
–
55
–
°C
VBO(on)
0.90
1
1.10
V
THERMAL SHUTDOWN
Thermal Shutdown (Note 4)
Device switching
(FSW around 65 kHz)
Thermal Shutdown Hysteresis (Note 4)
BROWN−OUT
Brown−Out ON level (IC start pulsing)
VSD increasing
Brown−Out OFF level (IC shuts down)
VSD decreasing
VBO(off)
0.85
0.9
0.95
V
BO comparators delay
tBO(delay)
–
30
–
ms
Brown−Out blanking time
tBO(blank)
35
50
65
ms
Brown−out pin bias current
IBO(bias)
−250
–
250
nA
4. Guaranteed by design
5. OTP triggers when RNTC = 4.7 kW
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NCL30083
TYPICAL CHARACTERISTICS
8.90
18.15
8.85
18.10
8.80
VCC(off) (V)
VCC(on) (V)
18.20
18.05
8.75
18.00
8.70
17.95
8.65
17.90
−40
−20
0
20
40
60
80
8.60
−40
120
100
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(off) vs. Junction Temperature
27.80
18
17
27.75
ICC(start) (mA)
VCC(OVP) (V)
16
27.70
27.65
27.60
15
14
13
12
27.55
11
27.50
−40
−20
0
20
40
60
80
100
10
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. VCC(OVP) vs. Junction Temperature
Figure 6. ICC(start) vs. Junction Temperature
1.30
52
1.28
50
1.24
48
ICC1 (mA)
ICC(sFault) (mA)
1.26
46
44
1.22
1.20
1.18
1.16
42
1.14
40
−40
−20
0
20
40
60
80
100
1.12
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. ICC(sFault) vs. Junction Temperature
Figure 8. ICC1 vs. Junction Temperature
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120
NCL30083
TYPICAL CHARACTERISTICS
2.40
2.85
2.80
2.35
2.75
ICC3 (mA)
ICC2 (mA)
2.30
2.25
2.20
2.70
2.65
2.60
2.55
2.15
−20
0
20
40
60
80
100
2.45
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. ICC2 vs. Junction Temperature
Figure 10. ICC3 vs. Junction Temperature
1.000
1.495
0.995
1.490
0.990
0.985
0.980
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
VCS(stop) (V)
VILIM (V)
2.10
−40
2.50
120
1.485
1.480
−20
0
20
40
60
80
100
1.475
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VILIM vs. Junction Temperature
Figure 12. VCS(stop) vs. Junction Temperature
305
1.010
303
1.005
301
VZCD(short) (V)
tLEB (ns)
299
297
295
293
291
289
287
285
−40
1.000
0.995
0.990
0.985
−20
0
20
40
60
80
100
0.980
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. tLEB vs. Junction Temperature
Figure 14. VZCD(short) vs. Junction
Temperature
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120
NCL30083
TYPICAL CHARACTERISTICS
3.20
7.1
7.0
6.9
tTIMO (ms)
tBLANK (ms)
3.15
3.10
6.8
6.7
3.05
6.6
3.00
−40
−20
0
20
40
60
80
6.5
−40
120
100
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. tBLANK vs. Junction Temperature
Figure 16. tTIMO vs. Junction Temperature
120
180
254
179
VREF70 (mV)
253
VREF (mV)
0
TJ, JUNCTION TEMPERATURE (°C)
255
252
251
178
177
176
250
249
−40
−20
0
20
40
60
80
100
175
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. VREF vs. Junction Temperature
Figure 18. VREF70 vs. Junction Temperature
105
67.0
66.5
VREF25 (mV)
104
VREF40 (mV)
−20
103
102
101
66.0
65.5
65.0
64.5
100
−40
−20
0
20
40
60
80
100
64.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. VREF40 vs. Junction Temperature
Figure 20. VREF25 vs. Junction Temperature
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NCL30083
30.0
18.0
29.5
17.5
29.0
17.0
VREF05 (mV)
VREF10 (mV)
TYPICAL CHARACTERISTICS
28.5
28.0
27.5
16.0
15.5
27.0
15.0
26.5
14.5
26.0
−40
−20
0
20
40
60
80
100
14.0
−40
120
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. VREF10 vs. Junction Temperature
Figure 22. VREF05 vs. Junction Temperature
55.0
16.60
54.5
16.55
54.0
16.50
53.5
16.45
53.0
16.40
52.5
16.35
52.0
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
KLFF (mA/V)
VCS(low) (mV)
16.5
−20
0
20
40
60
80
100
16.30
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. VCS(low) vs. Junction Temperature
Figure 24. KLFF vs. Junction Temperature
37.6
120
49.0
48.5
48.0
37.4
VREF(on) (mV)
VREF(off) (mV)
37.5
37.3
37.2
47.5
47.0
46.5
46.0
45.5
45.0
37.1
37.0
−40
−20
0
20
40
60
80
100
44.5
44.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. VREF(off) vs. Junction Temperature
Figure 26. VREF(on) vs. Junction Temperature
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11
NCL30083
TYPICAL CHARACTERISTICS
2.300
2.395
2.295
2.390
2.290
VLL (V)
VHL (V)
2.400
2.385
2.285
2.380
2.280
2.375
2.275
2.370
−40
−20
0
20
40
60
80
100
2.270
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. VHL vs. Junction Temperature
Figure 28. VLL vs. Junction Temperature
120
187.0
28.0
186.5
VVLY1−2/2−3 (mV)
tHL(BLANK) (ms)
27.5
27.0
186.0
185.5
185.0
26.5
184.5
−20
0
20
40
60
80
100
184.0
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. tHL(BLANK) vs. Junction Temperature
Figure 30. VVLY1−2/2−3 vs. Junction
Temperature
198
125.0
197
124.5
196
120
VVLY2−4/3−5 (mV)
VVLY2−1/3−2 (mV)
26.0
−40
124.0
195
123.5
194
123.0
193
122.5
192
191
−40
−20
0
20
40
60
80
100
122.0
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. VVLY2−1/3−2 vs. Junction
Temperature
Figure 32. VVLY2−4/3−5 vs. Junction
Temperature
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12
120
NCL30083
136
76.0
135
75.5
VVLY4−7/5−8 (mV)
VVLY4−2/5−3 (mV)
TYPICAL CHARACTERISTICS
134
133
132
0
20
40
60
80
100
74.0
73.0
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. VVLY4−2/5−3 vs. Junction
Temperature
Figure 34. VVLY4−7/5−8 vs. Junction
Temperature
87
37.7
86
37.6
85
37.5
84
83
82
80
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
VVLY7−11/8−12 (mV)
VVLY7−4/8−5 (mV)
−20
120
37.4
37.3
37.2
37.1
81
−20
0
20
40
60
80
100
37.0
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. VVLY7−4/8−5 vs. Junction
Temperature
Figure 36. VVLY7−11/8−12 vs. Junction
Temperature
50
15.10
49
15.05
120
15.00
VVLY11−13/12−15 (mV)
VVLY11−7/12−8 (mV)
74.5
73.5
131
130
−40
75.0
48
14.95
47
14.90
46
14.85
45
14.80
44
43
−40
14.75
−20
0
20
40
60
80
100
14.70
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 37. VVLY11−7/12−8 vs. Junction
Temperature
Figure 38. VVLY11−13/12−15 vs. Junction
Temperature
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13
120
NCL30083
TYPICAL CHARACTERISTICS
21.0
0.710
0.705
20.0
VSST(EN) (V)
VVLY13−11/15−12 (mV)
20.5
19.5
19.0
18.5
0.700
0.695
18.0
17.5
17.0
−40
−20
0
20
40
60
80
100
0.690
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 39. VVLY13−11/15−12 vs. Junction
Temperature
Figure 40. VSST(EN) vs. Junction Temperature
10.10
2.46
10.05
10.00
ISST (mA)
VSST(100) (V)
2.45
2.44
9.95
9.90
9.85
9.80
2.43
9.75
2.42
−40
−20
0
20
40
60
80
100
9.70
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 41. VSST(100) vs. Junction Temperature
Figure 42. ISST vs. Junction Temperature
120
88.0
100
87.5
99
tOVLD (ms)
ISST(pre) (mA)
87.0
98
97
96
86.5
86.0
85.5
85.0
95
84.5
94
−40
−20
0
20
40
60
80
100
84.0
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 43. ISST(pre) vs. Junction Temperature
Figure 44. tOVLD vs. Junction Temperature
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14
120
NCL30083
TYPICAL CHARACTERISTICS
4.55
2.500
2.495
2.490
4.45
VOVP (V)
trecovery (s)
4.50
4.40
2.485
2.480
4.35
2.475
4.30
−40
−20
0
20
40
60
80
100
2.470
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 45. trecovery vs. Junction Temperature
Figure 46. VOVP vs. Junction Temperature
86.5
120
0.690
86.0
VOTP(on), VTF(stop) (V)
0.688
IOTP(ref) (mA)
85.5
85.0
84.5
84.0
0.686
0.684
0.682
83.5
83.0
−40
−20
0
20
40
60
80
100
0.680
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 47. IOTP(ref) vs. Junction Temperature
Figure 48. VOTP(on), VTF(stop) vs. Junction
Temperature
120
0.994
0.997
0.992
VBO(on) (V)
VTF(start) (V)
0.995
0.993
0.991
0.990
0.988
0.989
0.986
0.987
0.984
0.985
−40
−20
0
20
40
60
80
100
0.982
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 49. VTF(start) vs. Junction Temperature
Figure 50. VBO(on) vs. Junction Temperature
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15
NCL30083
TYPICAL CHARACTERISTICS
0.906
56.0
55.5
tBO(BLANK) (ms)
VBO(off) (V)
0.904
0.902
0.900
55.0
54.5
54.0
53.5
0.898
53.0
0.896
−40
−20
0
20
40
60
80
100
52.5
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 51. VBO(off) vs. Junction Temperature
Figure 52. tBO(BLANK) vs. Junction
Temperature
120
APPLICATION INFORMATION
The NCL30083 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current of the flyback converter without
using any opto−coupler or measuring directly the secondary
side current.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30083 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to a smart control
algorithm, the controller locks−out in a selected valley
and remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to take into
account the effect of the leakage inductance of the
transformer and allow accurate control of the secondary
side current.
• Line Feed−forward: compensation for possible
variation of the output current caused by system slew
rate variation.
• Open LED protection: if the voltage on the VCC pin
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting pulsing.
• Thermal Fold−back / Over Temperature / Over
Voltage Protection: by combining a dual threshold on
the SD pin, the controller allows the direct connection
of an NTC to ground plus a Zener diode to a monitored
voltage. The temperature is monitored and the output
current is linearly reduced in the event that the
temperature exceeds a prescribed level. If the
•
•
•
•
•
•
temperature continues to increase, the current will be
further reduced until the controller is stopped. The
control will automatically restart if the temperature is
reduced. This pin can implement a programmable OVP
shutdown that can also auto−restart the device.
Brown−Out: the controller includes a brown−out
circuit which safely stops the controller in case the
input voltage is too low. The device will automatically
restart if the line recovers.
Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold VILIM, the
MOSFET is turned off for the rest of the switching
cycle.
Winding Short−Circuit Protection: an additional
comparator with a short LEB filter (tBCS) senses the CS
signal and stops the controller if VCS reaches 1.5 x
VILIM. For noise immunity reasons, this comparator is
enabled only during the main LEB duration tLEB.
Output Short−circuit protection: If a very low
voltage is applied on ZCD pin for 90 ms (nominal), the
controllers assume that the output or the ZCD pin is
shorted to ground and enters shutdown. The
auto−restart version (B suffix) waits 4 seconds, then the
controller restarts switching. In the latched version (A
suffix), the controller is latched as long as VCC stays
above the VCC(reset) threshold.
Soft−start: The soft−start pin can be used to slowly
increase the output current at startup and provide a
smooth turn−on of the LED light.
Step dimming: Each time the IC detects a brown−out
condition, the output current is decreased by discrete
steps.
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16
NCL30083
Constant Current Control
Figure 54 portrays the primary and secondary current of
a flyback converter in discontinuous conduction mode
(DCM). Figure 53 shows the basic circuit of a flyback
converter.
Transformer
Vbulk
Lleak
Cclp
Nsp
Rclp
Vout
.
Lp
.
Clamping
network
DRV
Clump
Rsense
Figure 53. Basic Flyback Converter Schematic
When the diode conducts, the secondary current decreases
linearly from ID,pk to zero. When the diode current has
turned off, the drain voltage begins to oscillate because of
the resonating network formed by the inductors (Lp+Lleak)
and the lump capacitor. This voltage is reflected on the
auxiliary winding wired in flyback mode. Thus, by looking
at the auxiliary winding voltage, we can detect the end of the
conduction time of secondary diode. The constant current
control block picks up the leakage inductor current, the end
of conduction of the output rectifier and controls the drain
current to maintain the output current constant.
We have:
During the on−time of the MOSFET, the bulk voltage
Vbulk is applied to the magnetizing and leakage inductors Lp
and Lleak and the current ramps up.
When the MOSFET is turned−off, the inductor current
first charges Clump. The output diode is off until the voltage
across Lp reverses and reaches:
N spǒV out ) V fǓ
(eq. 1)
The output diode current increase is limited by the leakage
inductor. As a consequence, the secondary peak current is
reduced:
I D,pk t
I L,pk
N sp
(eq. 2)
I out +
The diode current reaches its peak when the leakage inductor
is reset. Thus, in order to accurately regulate the output
current, we need to take into account the leakage inductor
current. This is accomplished by sensing the clamping
network current. Practically, a node of the clamp capacitor
is connected to Rsense instead of the bulk voltage Vbulk.
Then, by reading the voltage on the CS pin, we have an
image of the primary current (red curve in Figure 54).
V REF
2N spR sense
(eq. 3)
The output current value is set by choosing the sense
resistor:
R sense +
V ref
2N spI out
(eq. 4)
From Equation 3, the first key point is that the output
current is independent of the inductor value. Moreover, the
leakage inductance does not influence the output current
value as the reset time is taken into account by the controller.
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17
NCL30083
IL,pk
NspID,pk
Ipri(t)
Isec(t)
time
t1
t2
ton
tdemag
Vaux(t)
time
Figure 54. Flyback Currents and Auxiliary Winding Voltage in DCM
Internal Soft−Start
At startup or after recovering from a fault, there is a small
internal soft−start of 40 ms.
In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak current
towards its nominal value as the output voltage grows.
Figure 55 shows a soft−start simulation example for a 9 W
LED power supply.
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18
NCL30083
16.0
(V)
12.0
1
Vout
2
I out
4
VControl
3
VCS
8.00
4.00
0
800m
(A)
600m
400m
200m
0
800m
(V)
600m
400m
200m
0
604u
1.47m
2.34m
time in seconds
3.21m
4.07m
Figure 55. Startup Simulation Showing the Natural Soft−start
Cycle−by−Cycle Current Limit
Winding and Output Diode Short−Circuit Protection
When the current sense voltage exceeds the internal
threshold VILIM, the MOSFET is turned off for the rest of the
switching cycle (Figure 56).
In parallel with the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS) and a higher
threshold (1.5 V typical) is able to sense winding
short−circuit and immediately stops the DRV pulses. The
controller goes into auto−recovery mode in version B.
In version A, the controller is latched. In latch mode, the
DRV pulses stop and VCC ramps up and down. The circuit
un−latches when VCC pin voltage drops below VCC(reset)
threshold.
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19
NCL30083
S
DRV
Q
Q
aux
Vdd
latch
CS
R
LEB1
Rsense
+
Vcontrol
Vcc
management
PWMreset
VCC
−
+
VCCstop
UVLO
grand
8_HICC
reset
Ipkmax
−
VILIMIT
OVP
LEB2
+
STOP
OVP
WOD_SCP
latch
−
S
VCS(stop)
Q
Q
OFF WOD_SCP
S
Q
Q
R
8_HICC
R
grand
reset
from Fault Management Block
Figure 56. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
Thermal Fold−back and Over Voltage / Over
Temperature Protection
If VSD drops below VOTP, the controller enters into the
auto−recovery fault mode for version B, meaning that the
4−s timer is activated. The controller will re−start switching
after the 4−s timer has elapsed and when VSD > VOTP(on) to
provide some temperature hysteresis (around 10°C).
For version A, this protection is latched: reset occurs when
VCC < VCC(reset).
The thermal fold−back and OTP thresholds correspond
roughly to the following resistances:
• Thermal fold−back starts when RNTC ≤ 11.76 kW.
• Thermal fold−back stops when RNTC ≤ 8.24 kW.
• OTP triggers when RNTC ≤ 5.88 kW.
• OTP is removed when RNTC ≥ 8.24 kW.
The thermal fold−back circuit reduces the current in the
LED string when the ambient temperature exceeds a set
point. The current is gradually reduced to 50% of its nominal
value if the temperature continues to rise. (Figure 58). The
thermal foldback starting temperature depends on the
Negative Coefficient Temperature (NTC) resistor chosen by
the power supply designer.
Indeed, the SD pin allows the direct connection of an NTC
to sense the ambient temperature. When the SD pin voltage
VSD drops below VTF(start), the internal reference for the
constant current control VREF is decreased proportionally to
VSD. When VSD reaches VTF(stop), VREF is clamped to
VREF50, corresponding to 50% of the nominal output
current.
Temperature increases
Temperature decreases
Iout
Iout(nom)
Shutdown
50% Iout(nom)
VSD
VOTP(off)
VTF(stop)
VOTP(on)
VTF(start)
Figure 57. Output Current Reduction versus SD Pin Voltage
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20
NCL30083
At startup, when VCC reaches VCC(on), the controller is
not allowed to start pulsing for at least 180 ms in order to
allow the SD pin voltage to reach its nominal value if a
filtering capacitor is connected to the SD pin. This is to avoid
flickering of the LED light in case of over temperature.
VOVP
VCC
Vdd
noise delay
−
Dz
IOTP(REF)
OVP
+
S
Q
SD
OFF
Q
OTP_Timer end
Rclamp
Clamp
R
OTP
−
4−s Timer
+
NTC
noise delay
Vclamp
(OTP latched for version A)
VOTP
0.5 V if OTP low
0.7 V if OTP high
S
Q
Latch
Q
VTF
R
VCCreset
Figure 58. Thermal Fold−back and OVP/OTP Circuitry
In case of over voltage, the Zener diode starts to conduct
and inject current inside the internal clamp resistor Rclamp
thus causing the pin SD voltage to increase. When this
voltage reaches the OVP threshold (2.5 V typ.), the
controller shuts−down and waits for at least 4 seconds before
restarting switching.
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21
NCL30083
VCC
VCC(on)
VCC(off)
VCC > VCC(on):
DRV pulses restart
VCC(reset)
VDRV
4−s Timer
VSD
VSD > VOVP:
controller stops
switching
4−s timer has elapsed:
waiting for VCC > VCC(on)
to restart DRV pulses
VOVP
VSD(clamp)
Vout
Figure 59. OVP with SD Pin Chronograms
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22
NCL30083
VCC
VCC(on)
VCC(off)
VCC(reset)
VDRV
VSD > VTF(stop) and
VCC > VCC(on):
DRV pulses restart
4−s Timer
VSD < VOTP(off):
controller stops
switching
VSD
4−s timer has elapsed
but VSD < VTF(stop)
≥ no restart
VTF(start)
VTF(stop)
VOTP(off)
Iout
Figure 60. Thermal Fold−back / OTP Chronograms
Soft−Start
The NCL30083 provides a soft−start pin allowing
increasing slowly the LEDs light at startup. An internal
current source ISST charges the soft−start capacitor. The
generated voltage ramp directly controls the amount of
current flowing in the LEDs.
At startup, if there are no faults (except “Enable_b” high),
an internal pre−charging current source ISST(pre) connected
in parallel with ISST charges the soft−start capacitor until it
reaches the VSST(EN) threshold. After that, ISST(pre) is turned
off and the soft−start capacitor keep on charging with the
soft−start current source ISST.
When a fault is detected, the soft−start pin is discharged
down to VSST(EN) to provide a clean soft−start when the fault
is removed.
VCC
Clamp
Circuit
S
Vdd
Q
VSST
ISST
Q
ISST(pre)
SST
R
−
Enable_b
+
VSST(EN)
CS_reset
STOP
7.4V clamp
STOP
Figure 61. Soft−start Pin Bloc Diagram
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23
DRV
Qdrv
Output
Buffer 1
NCL30083
Step Dimming
Note:
The power supply designer must ensure that VCC stays
high enough when the light is turned−off to let the controller
memorize the dimming step state.
The power supply designer should use a split VCC circuit
for step dimming with a capacitor allowing providing
enough VCC for 1 s (47 mF to 100 mF capacitor).
The step dimming state is memorized by the controller
until VCC crosses VCC(reset).
The step dimming function decreases the output current
from 100% to 5% of its nominal value in discrete steps.
There are 5 steps in total. Table 4 shows the different steps
value and the corresponding output current set−point. Each
time a brown−out is detected, the output current is decreased
by decreasing the reference voltage VREF setting the output
current value.
When the 5% dimming step is reached, if a brown−out
event occurs, the controller restarts at 100% of the output
current.
Table 4. DIMMING STEPS
Dimming Step
Iout
Perceived Light
ON
100%
100%
1
70%
84%
2
40%
63%
3
25%
50%
4
10%
32%
5
5%
17%
VCC
4.7 mF
47 − 100 mF
Figure 62. Split VCC Supply
Vbulk
Vbulk(on)
Vbulk(off)
VCC
VCC(on)
VCC(off)
VCC(reset)
BO
comp
Iout
100%
70%
40%
25%
10%
Figure 63. Step Dimming Chronograms
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24
5%
NCL30083
VCC Over Voltage Protection (Open LED Protection)
In the NCL30083, when the VCC voltage reaches the
VCC(OVP) threshold, the controller stops the DRV pulses and
the 4−s timer starts counting. The IC re−start pulsing after
the 4−s timer has elapsed and when VCC ≥ VCC(on).
If no output load is connected to the LED power supply,
the controller must be able to safely limit the output voltage
excursion.
40.0
V CC(OVP)
(V)
30.0
1 V CC
V CC(on)
20.0
10.0
VCC(off)
0
40.0
(V)
30.0
2 Vout
20.0
10.0
0
800m
(A)
600m
400m
200m
3 I out
0
8.00
(V)
6.00
4 OVP
4.00
2.00
0
1.38
3.96
6.54
time in seconds
9.11
11.7
Figure 64. Open LED Protection Chronograms
Valley Lockout
voltage or the output current set−point varies significantly.
This avoids valley jumping and the inherent noise caused by
this phenomenon.
The input voltage is sensed by the VIN pin. The internal
logic selects the operating valley according to VIN pin
voltage (line range detector in Figure 65), SD pin voltage
and dimming state imposed by the Step Dimming circuit.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCL30083 changes valley as the input voltage
increases and as the output current set−point is varied
(thermal fold−back and step dimming). This limits the
switching frequency excursion. Once a valley is selected,
the controller stays locked in the valley until the input
www.onsemi.com
25
NCL30083
Vbulk
VIN
+
LLine
HLine
25−ms blanking time
−
2.4 V if LLine low
2.3 V if LLine high
Figure 65. Line Range Detector
Table 5. VALLEY SELECTION
VIN pin voltage for valley change
Iout value at which the
controller changes valley
(Iout decreasing)
0
100%
75%
50%
30%
15%
6%
0%
0
−LL−
2.3 V
−HL−
1st
2nd
2nd
3rd
4th
5th
7th
8th
11th
12th
13th
15th
−LL−
2.4 V
−HL−
VVIN increases
VIN pin voltage for valley change
www.onsemi.com
26
5V
100%
78%
53%
33%
20%
8%
0%
5V
Iout increases
Iout decreases
Iout value at which the
controller changes valley
(Iout increasing)
VVIN decreases
NCL30083
Zero Crossing Detection Block
the valleys. To avoid such a situation, the NCL30083
features a Time−Out circuit that generates pulses if the
voltage on ZCD pin stays below the VZCD(THD) threshold
for 6.5 ms.
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the voltage on pin 1 crosses
below the VZCD(THD) internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
V ZCD
3
4
V ZCD(THD)
The 3rd valley
is validated
high
14
2nd, 3rd
low
12
The 3rd valley is not detected
by the ZCD comp
The 2nd valley is detected
By the ZCD comparator
high
15 ZCD comp
low
high
low
16
TimeOut
17
Clk
Time−out circuit adds a pulse to
account for the missing 3rd valley
high
low
Figure 66. Time−out Chronograms
Line Feed−forward
Because of this time−out function, if the ZCD pin or the
auxiliary winding is shorted, the controller will continue
switching leading to improper regulation of the LED
current. Moreover during an output short circuit, the
controller will strive to maintain the constant current
operation.
In order to avoid these scenarios, a secondary timer starts
counting when the ZCD voltage is below the VZCD(short)
threshold. If this timer reaches 90 ms, the controller detects
a fault and enters the auto−recovery fault mode (controller
shuts−down and waits 4−s before re−starting switching).
Because of the propagation delays, the MOSFET is not
turned−off immediately when the current set−point is
reached. As a result, the primary peak current is higher than
expected and the output current increases. To compensate
the peak current increase brought by the propagation delay,
a positive voltage proportional to the line voltage is added
on the current sense signal. The amount of offset voltage can
be adjusted using the RLFF resistor as shown in Figure 67.
The offset voltage is applied only during the MOSFET
on−time.
This offset voltage is removed at light load during
dimming when the output current drops below 15% of the
programmed output current.
www.onsemi.com
27
NCL30083
Bulk rail
VDD
VIN
CS
ICS(offset)
RLFF
Rsense
Q_drv
Offset_OK
Figure 67. Line Feed−Forward Schematic
Brown−out
shuts−down if the VIN pin voltage decreases and stays
below 0.9 V for 50 ms nominal. Exiting a brown−out
condition overrides the hiccup on VCC (VCC does not wait
to reach VCC(off)) and the IC immediately goes into startup
mode (ICC = ICC(start)).
In order to protect the supply against a very low input
voltage, the NCL30083 features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than 1 V is applied to the VIN pin and
Vbulk
VIN
+
50−ms blanking time
−
1 V if BONOK high
0.9 V if BONOK low
Figure 68. Brown−out Circuit
www.onsemi.com
28
BO_NOK
NCL30083
160
(V)
120
VBulk
80.0
1
40.0
0
18.0
(V)
2
VCC(on)
16.0
14.0
VCC
12.0
VCC(off)
10.0
1.10
V BO(on)
(V)
900m
V BO(off)
700m
V pinVIN
500m
3
300m
8.00
50−ms Timer
(V)
6.00
BO_NOK low
=> Startup mode
4.00
2.00
BO_NOK
4
0
46.1m
138m
231m
time in seconds
323m
Figure 69. Brown−Out Chronograms (Valley Fill circuit is used)
www.onsemi.com
29
415m
NCL30083
CS Pin Short Circuit Protection
Normally, if the CS pin or the sense resistor is shorted to
ground, the Driver will not be able to turn off, leading to
potential damage of the power supply. To avoid this, the
NCL30083 features a circuit to protect the power supply
against a short circuit of the CS pin. When the MOSFET is
on, if the CS voltage stays below VCS(low) after the adaptive
blanking timer has elapsed, the controller shuts down and
will attempt to restart on the next VCC hiccup.
Adaptative
Blanking Time
VVIN
Q_drv
CS
−
+
S
VCS(low)
Q
CS_short
Q
R
UVLO
BO_NOK
Figure 70. CS Pin Short Circuit Protection Schematic
Fault Management
In this mode, the DRV pulses are stopped. The VCC
voltage decrease through the controller own consumption
(ICC1).
For the output diode short circuit protection, the CS pin
short circuit protection, the output / aux. winding short
circuit protection and the OVP2, the controller waits 4
seconds (auto−recovery timer) and then initiates a startup
sequence (VCC ≥ VCC(on)) before re−starting switching.
Latch Mode
This mode is activated by the output diode short−circuit
protection (WOD_SCP), the OTP and the Aux−SCP in
version A only.
In this mode, the DRV pulses are stopped and the
controller is latched. There are hiccups on VCC.
The circuit un−latches when VCC < VCC(reset).
OFF Mode
The circuit turns off whenever a major condition prevents
it from operating:
• Incorrect feeding of the circuit: “UVLO high”. The
UVLO signal becomes high when VCC drops below
VCC(off) and remains high until VCC exceeds VCC(on).
• OTP
• VCC OVP
• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD_SCP
high”
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
• Brown−Out: “BO_NOK” high
• Pin CS short circuited to GND: “CS_short high”
www.onsemi.com
30
NCL30083
Reset
Timer has
finished
counting
VCC > VCC(on)
OVP2 or
VCC_OVP
VCC < VCC(off)
or
BO_NOK ↓
BO_NOK high
or OTP
or TSD
or CS_Short
Stop
4−s
Timer
VCC
Disch.
BO_NOK high
or OTP
or TSD
or CS_Short
OVP2
or WOD_SCP
or Aux_SCP
or VCC_OVP
Run
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching, tOTP(start) has elapsed
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Figure 71. State Diagram for B Version Faults
www.onsemi.com
31
NCL30083
Reset
Timer has
finished
counting
VCC > VCC(on)
VCC < VCC(off)
or
BO_NOK ↓
VCC < VCC(reset)
4−s
Timer
OVP2 or
VCC_OVP
OVP2 or
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Stop
VCC
Disch.
OTP
BO_NOK high
or TSD
or CS_Short
Latch
Run
OTP or
WOD_SCP or
Aux_SCP
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
Latch
→
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching, tOTP(start) has elapsed
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Controller is latched off, VCC is ramping up and down between VCC(on) and VCC(off),
only VCC(reset) can release the latch.
Figure 72. State Diagram for A Version Faults
www.onsemi.com
32
NCL30083
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
D
HE
PIN 1 ID
E
e
b 8 PL
0.08 (0.003)
−T−
DIM
A
A1
b
c
D
E
e
L
HE
M
T B
S
A
S
SEATING
PLANE
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
A
0.038 (0.0015)
A1
L
c
RECOMMENDED
SOLDERING FOOTPRINT*
8X
8X
0.48
0.80
5.25
0.65
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
33
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
NCL30083
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
34
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCL30083
OPTIONS
Controller
Output SCP
Winding/Output Diode SCP
Over Temperature Protection
NCL30083A
Latched
Latched
Latched
NCL30083B
Auto−recovery
Auto−recovery
Auto−recovery
Device
Package Marking
Package Type
Shipping†
NCL30083ADMR2G
AAE
Micro8
(Pb−Free, Halide−Free)
4000 / Tape & Reel
NCL30083BDMR2G
AAF
Micro8
(Pb−Free, Halide−Free)
4000 / Tape & Reel
NCL30083BDR2G
L30083B
SOIC−8
(Pb−Free)
2500 / Tape & Reel
ORDERING INFORMATION
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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www.onsemi.com
35
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NCL30083/D