Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 LMV76x and LMV762Q-Q1 Low-Voltage, Precision Comparator With Push-Pull Output 1 Features 2 Applications • • • • • • • • • 1 • • • • • • • • • • • • • VS = 5 V, TA = 25°C, Typical Values Unless Specified Input Offset Voltage 0.2 mV Input Offset Voltage (Maximum Over Temp) 1 mV Input Bias Current 0.2 pA Propagation Delay (OD = 50 mV) 120 ns Low Supply Current 300 μA CMRR 100 dB PSRR 110 dB Extended Temperature Range −40°C to +125°C Push-Pull Output Ideal for 2.7-V and 5-V Single-Supply Applications Available in Space-Saving Packages: – 6-Pin SOT-23 (Single With Shutdown) – 8-Pin SOIC (Single With Shutdown) – 8-Pin SOIC and VSSOP (Dual Without Shutdown) LMV762Q-Q1 is Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 1C – Device CDM ESD Classification Level M2 Portable and Battery-Powered Systems Scanners Set-Top Boxes High-Speed Differential Line Receiver Window Comparators Zero-Crossing Detectors High-Speed Sampling Circuits Automotive 3 Description The LMV76x devices are precision comparators intended for applications requiring low noise and low input offset voltage. The LMV761 single has a shutdown pin that can be used to disable the device and reduce the supply current. The LMV761 is available in a space-saving 6-pin SOT-23 or 8-Pin SOIC package. The LMV762 dual is available in 8-pin SOIC or VSSOP package. The LMV762Q-Q1 is available VSSOP and SOIC packages. These devices feature a CMOS input and push-pull output stage. The push-pull output stage eliminates the need for an external pullup resistor. The LMV76x are designed to meet the demands of small size, low power and high performance required by portable and battery-operated electronics. The input offset voltage has a typical value of 200 μV at room temperature and a 1-mV limit over temperature. Device Information(1) PART NUMBER PACKAGE LMV761 LMV762 LMV762Q-Q1 BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm SOT-23 (6) 2.90 mm × 1.60 mm SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Threshold Detector VIN VOS vs VCC 0.2 VCC 125°C 0.18 0.16 + VOUT 85°C 0.12 0.1 0.08 -40°C 0.06 - R2 25°C 0.14 C1 = 0.1µF VOS (mV) R1 SD 0.04 0.02 0 VREF 2.5 3 3.5 4 4.5 5 VCC (V) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 4 5 5 5 5 5 6 7 7 8 Absolute Maximum Ratings ...................................... ESD Ratings: LMV761, LMV762............................... ESD Ratings: LMV762Q-Q1 ..................................... Recommended Operating Conditions....................... Thermal Information .................................................. 2.7-V Electrical Characteristics ................................ 5-V Electrical Characteristics ................................... 2-V Switching Characteristics ................................... 5-V Switching Characteristics ................................... Typical Characteristics ............................................ Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 15 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 15 11 Device and Documentation Support ................. 16 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 16 12 Mechanical, Packaging, and Orderable Information ........................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (March 2013) to Revision I • Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision G (March 2013) to Revision H • 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 15 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 5 Pin Configuration and Functions LMV761 (Single) DBV Package 6-Pin SOT-23 Top View 1 6 V +IN - V 2 + 5 SD 3 -IN 4 OUT Pin Functions for SOT-23 PIN NO. NAME TYPE DESCRIPTION 1 +IN I Noninverting input 2 V- P Negative power terminal 3 -IN I Inverting input 4 OUT O Output 5 SDB I Shutdown (active low) 6 V+ P Positive power terminal LMV761 (Single) D Package 8-Pin SOIC Top View N/C -IN +IN V - 1 8 2 7 3 6 4 5 N/C + V OUT SD Pin Functions for SOIC (Single) PIN NO. NAME TYPE DESCRIPTION 1 N/C — 2 -IN I Inverting Input 3 +IN I Noninverting Input 4 V- P Negative Power Terminal 5 SDB I Shutdown (active low) 6 OUT O Output + No Connect (not internally connected) 7 V P Positive Power Terminal 8 N/C — No Connect (not internally connected) Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 Submit Documentation Feedback 3 LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com LMV762, LMV762Q-Q1 (Dual) DBV or DGK Package 8-Pin SOIC or VSSOP Top View 1 8 2 7 3 6 OUT A -IN A +IN A V - + V OUT B -IN B 4 5 +IN B Pin Functions for SOIC and VSSOP (Dual) PIN TYPE DESCRIPTION NO. NAME 1 OUTA O Channel A Output 2 -INA I Channel A Inverting Input 3 +INA I Channel A Noninverting Input 4 V- P Negative Power Terminal 5 +INB I Channel B Noninverting Input 6 -INB I Channel B Inverting Input 7 OUTB O Channel B Output 8 V+ P Positive Power Terminal 6 Specifications 6.1 Absolute Maximum Ratings See (1) (2) MIN MAX UNIT 5.5 V ±5 mA Infrared or convection (20 sec.) 235 °C Wave soldering (10 sec.) (Lead temp) 260 °C 150 °C 150 °C Supply voltage (V+ – V−) Differential input voltage Supply Voltage Voltage between any two pins Output short circuit duration (3) Soldering information Supply Voltage Current at input pin Junction temperature Storage temperature, Tstg (1) (2) (3) 4 −65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output current in excess of ±25 mA over long term may adversely affect reliability. Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 6.2 ESD Ratings: LMV761, LMV762 VALUE V(ESD) (1) (2) Electrostatic discharge (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2) ± 2000 Machine model ± 200 UNIT V Unless otherwise specified human body model is 1.5 kΩ in series with 100 pF. Machine model 200 pF. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings: LMV762Q-Q1 VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ± 2000 Machine model ± 200 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.4 Recommended Operating Conditions MIN MAX Supply voltage (V – V ) 2.7 5.25 V Temperature range −40 125 °C + − UNIT 6.5 Thermal Information THERMAL METRIC (1) RθJA (1) (2) Junction-to-ambient thermal resistance LMV761 LMV762, LMV762Q-Q1 D (SOIC) DBV (SOT-23) DGK (VSSOP) (2) 8 PINS 6 PINS 8 PINS 190 265 235 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) RθJA. All numbers apply for packages soldered directly into a PCB. 6.6 2.7-V Electrical Characteristics Unless otherwise specified, all limited ensured for TJ = 25°C, VCM = V+ / 2, V+ = 2.7 V, V− = 0 V−. PARAMETER MIN (1) TEST CONDITIONS VOS Input offset voltage IB Input bias current (4) TYP (2) MAX (1) 0.2 apply at the temperature extremes (3) 1 (4) UNIT mV 0.2 50 pA 0.001 5 pA IOS Input offset current CMRR Common-mode rejection ratio 0 V < VCM < VCC – 1.3 V 80 100 dB PSRR Power supply rejection ratio V+ = 2.7 V to 5 V 80 110 dB CMVR Input common-mode voltage range CMRR > 50 dB VO ISC (1) (2) (3) (4) (5) apply at the temperature extremes (3) Output swing high IL = 2 mA, VID = 200 mV Output swing low IL = −2 mA, VID = –200 mV Output short circuit current (5) −0.3 + 1.5 + V – 0.35 V – 0.1 90 Sourcing, VO = 1.35 V, VID = 200 mV 6 20 Sinking, VO = 1.35 V, VID = –200 mV 6 15 V V 250 mV mA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Maximum temperature ensured range is −40°C to +125°C. Specified by design. Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Recommended Operating Conditions for information on temperature de-rating of this device. Absolute Maximum Rating indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 Submit Documentation Feedback 5 LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com 2.7-V Electrical Characteristics (continued) Unless otherwise specified, all limited ensured for TJ = 25°C, VCM = V+ / 2, V+ = 2.7 V, V− = 0 V−. PARAMETER MIN (1) TEST CONDITIONS Supply current LMV761 (single comparator) IS TYP (2) MAX (1) 275 700 LMV762, LMV762Q-Q1 (both comparators) apply at the temperature extremes (3) 550 IOUT LEAKAGE Output leakage I at shutdown SD = GND, VO = 2.7 V 0.2 IS Supply leakage I at shutdown 0.2 2 TYP (2) MAX (1) LEAKAGE 6.7 1400 SD = GND, VCC = 2.7 V UNIT μA μA μA μA 5-V Electrical Characteristics Unless otherwise specified, all limited ensured for TJ = 25°C, VCM = V+ / 2, V+ = 5 V, V− = 0 V−. PARAMETER VOS Input offset voltage IB Input bias current (4) IOS Input offset current (4) CMRR Common-mode rejection ratio 0.2 apply at the temperature extremes (3) + Power supply rejection ratio CMVR Input common-mode voltage range CMRR > 50 dB Output swing high IL = 4 mA, VID = 200 mV Output swing low IL = –4 mA, VID = –200 mV Output short circuit current (5) ISC 1 0 V < VCM < VCC – 1.3 V PSRR VO MIN (1) TEST CONDITIONS V = 2.7 V to 5 V apply at the temperature extremes (3) IS 0.2 50 pA 0.01 5 pA 100 dB 80 110 dB −0.3 120 Sourcing, VO = 2.5 V, VID = 200 mV 6 60 Sinking, VO = 2.5 V, VID = −200 mV 6 40 225 IOUT LEAKAGE Output leakage I at shutdown SD = GND, VO = 5 V 0.2 IS Supply leakage I at shutdown SD = GND, VCC = 5 V 0.2 6 V 250 mV V mA 700 450 apply at the temperature extremes (3) (1) (2) (3) (4) (5) 3.8 V+ – 0.1 LMV762, LMV762Q-Q1 (both comparators) LEAKAGE mV 80 V+ – 0.35 Supply current LMV761 (single comparator) UNIT 1400 μA μA μA 2 μA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Maximum temperature ensured range is −40°C to +125°C. Specified by design. Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Recommended Operating Conditions for information on temperature de-rating of this device. Absolute Maximum Rating indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 6.8 2-V Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER tPD TEST CONDITIONS Propagation delay RL = 5.1 kΩ CL = 50 pF tSKEW Propagation delay skew tr Output rise time tf Output fall time ton Turnon time from shutdown MIN TYP Overdrive = 5 mV 270 Overdrive = 10 mV 205 Overdrive = 50 mV 120 MAX UNIT ns 5 ns 10% to 90% 1.7 ns 90% to 10% 1.8 ns 6 μs 6.9 5-V Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER tPD TEST CONDITIONS Propagation delay RL = 5.1 kΩ CL = 50 pF MIN TYP Overdrive = 5 mV 225 Overdrive = 10 mV 190 Overdrive = 50 mV 120 MAX UNIT ns tSKEW Propagation delay skew 5 ns tr Output rise time 10% to 90% 1.7 ns tf Output fall time 90% to 10% 1.5 ns ton Turnon time from shutdown 4 μs Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 Submit Documentation Feedback 7 LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com 6.10 Typical Characteristics 0.5 125°C 0.45 0.4 SUPPLY CURRENT PER CH (mA) SUPPLY CURRENT PER CH (mA) 0.5 85°C 0.35 0.3 0.25 25°C 0.2 0.15 -40°C 0.1 0.05 0 1.5 2 2.5 3 3.5 4.5 4 5 5.5 125°C 0.45 0.4 85°C 0.35 0.3 0.25 25°C 0.2 0.15 -40°C 0.1 0.05 0 1.5 6 2 2.5 Figure 1. PSI vs VCC 5 5.5 6 Figure 2. PSI vs VCC 100 125°C 0.18 VS = +2.7 V 80 INPUT BIAS CURRENT (fA) 0.16 25°C 0.14 VOS (mV) 4.5 VO = Low 0.2 85°C 0.12 0.1 0.08 -40°C 0.06 0.04 0.02 60 40 20 0 -20 -40 -60 -80 0 -100 2.5 3 3.5 4.5 4 5 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 COMMON MODE VOLTAGE (V) VCC (V) Figure 4. Input Bias vs Common Mode at 25°C Figure 3. VOS vs VCC 0.4 100 IL = 4 mA 0.35 + OUTPUT VOLTAGE, REF TO V (V) VS = +5 V 80 INPUT BIAS CURRENT (fA) 4 VCC (V) VO = High 60 40 20 0 -20 -40 -60 -80 0.3 125°C 0.25 85°C 0.2 25°C 0.15 0.1 -40°C 0.5 0 -100 0 4 3 1 2 COMMON MODE VOLTAGE (V) 5 Figure 5. Input Bias vs Common Mode at 25°C 8 3.5 3 VCC (V) Submit Documentation Feedback 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 6. Output Voltage vs Supply Voltage Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 Typical Characteristics (continued) 0.4 OUTPUT VOLTAGE REF TO V (V) IL = 2 mA 0.14 + 125°C IL = -4 mA 0.35 125°C - OUTPUT VOLTAGE, REF TO V (V) 0.16 0.12 85°C 0.1 25°C 0.08 0.06 0.04 -40°C 0.02 0 0.3 85°C 0.25 25°C 0.2 0.15 0.1 -40°C 0.05 0 2 2.5 3 3.5 4 4.5 5.5 5 6 2 2.5 3 3.5 5.5 6 Figure 8. Output Voltage vs Supply Voltage 0.2 80 IL = -2 mA 0.18 VCC = 5 V -40°C 70 125°C 25°C 0.16 60 0.14 85°C ISINK (mA) 85°C 0.12 25°C 0.1 0.08 50 40 125°C 30 0.06 20 0.04 -40°C 10 0.02 0 0 2 2.5 3 3.5 4 4.5 5 5.5 0 6 0.5 1 VCC (V) Figure 9. Output Voltage vs Supply Voltage 2 1.5 VOUT (V) 2.5 Figure 10. ISOURCE vs VOUT 60 25 -40°C 50 25°C 20 ISOURCE (mA) 85°C 30 125°C 20 VCC = 2.7 V -40°C VCC = 5 V 40 ISINK (mA) 5 4.5 4 VCC (V) Figure 7. Output Voltage vs Supply Voltage - OUTPUT VOLTAGE, TO REF V (V) VCC (V) 25°C 85°C 15 125°C 10 5 10 0 0 0 0.5 1 1.5 2 2.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VOUT (V) VOUT (V) Figure 11. ISINK vs VOUT Figure 12. ISOURCE vs VOUT Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 Submit Documentation Feedback 9 LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) 20 500 -40°C 18 16 PROP DELAY (ns) 12 10 85°C 8 CL = 50 pF 400 25°C 14 ISINK (mA) RL = 5.1 k: 450 125°C 6 350 300 2.7 V 250 200 5V 150 4 100 VCC = 2.7 V 2 50 0 0 0 0.4 0.2 0.6 1 0.8 1.2 1 1.4 10 Figure 14. Prop Delay vs Overdrive VCC = 2.7 V TEMP = 25°C 2 LOAD = 5.1 k: 50 pF 10 mV 5 mV OVERDRIVE = 50 mV 0 | | OVERDRIVE 0 OUTPUT VOLTAGE (V) 3 INPUT VOLTAGE (mV) INPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) Figure 13. ISINK vs VOUT 1 6 VCC = 5 V TEMP = 25°C LOAD = 5.1 k: 50 pF 5 4 3 100 50 150 200 250 OVERDRIVE = 50 mV 1 0 | | OVERDRIVE 0 300 50 0 5 mV OVERDRIVE = 0 50 mV | | 150 0 OVERDRIVE 0 50 100 150 200 TIME (ns) 250 300 Figure 17. Response Time vs Input Overdrives Negative Transition Submit Documentation Feedback INPUT VOLTAGE (mV) 10 mV 200 250 Figure 16. Response Time vs Input Overdrives Positive Transition OUTPUT VOLTAGE (V) 3 VCC = 2.7 V 2 TEMP = 25°C LOAD = 5.1 k: 50 pF 1 150 100 TIME (ns) Figure 15. Response Time vs Input Overdrives Positive Transition OUTPUT VOLTAGE (V) 5 mV 2 TIME (ns) INPUT VOLTAGE (mV) 10 mV -150 -150 0 10 100 OVERDRIVE (mV) VOUT (V) 6 5 4 3 2 1 0 10 mV VCC = 5 V TEMP = 25°C LOAD = 5.1 k: 50 pF 5 mV OVERDRIVE = 50 mV | | 150 0 OVERDRIVE 0 50 100 150 200 250 TIME (ns) Figure 18. Response Time vs Input Overdrives Negative Transition Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 7 Detailed Description 7.1 Overview The LMV76x family of precision comparators is available in a variety of packages and is ideal for portable and battery-operated electronics. To minimize external components, the LMV76x family features a push-pull output stage where the output levels are power-supply determined. In addition, the LMV761 (single) features an active-low shutdown pin that can be used to disable the device and reduce the supply current. 7.2 Functional Block Diagram V VREF - VIN + + VO V - 7.3 Feature Description 7.3.1 Basic Comparator A basic comparator circuit is used to convert analog input signals to digital output signals. The comparator compares an input voltage (VIN) at the noninverting input to the reference voltage (VREF) at the inverting pin. If VIN is less than VREF the output (VO) is low (VOL). However, if VIN is greater than VREF, the output voltage (VO) is high (VOH). V VREF - VIN + + VO V - Figure 19. Basic Comparator Without Hysteresis Figure 20. Basic Comparator 7.3.2 Hysteresis The basic comparator configuration may oscillate or produce a noisy output if the applied differential input is near the input offset voltage of the comparator, which tends to occur when the voltage on one input is equal or very close to the other input voltage. Adding hysteresis can prevent this problem. Hysteresis creates two switching thresholds (one for the rising input voltage and the other for the falling input voltage). Hysteresis is the voltage difference between the two switching thresholds. When both inputs are nearly equal, hysteresis causes one input to effectively move quickly past the other. Thus, moving the input out of the region in which oscillation may occur. Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 Submit Documentation Feedback 11 LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com Feature Description (continued) Hysteresis can easily be added to a comparator in a noninverting configuration with two resistors and positive feedback Figure 22. The output will switch from low to high when VIN rises up to VIN1, where VIN1 is calculated by Equation 1: VIN1 = [VREF(R1 + R2)] / R2 (1) The output will switch from high to low when VIN falls to VIN2, where VIN2 is calculated by Equation 2: VIN2 = [VREF(R1 + R2) – (VCC R1)] / R2 (2) The Hysteresis is the difference between VIN1 and VIN2, as calculated by Equation 3: ΔVIN = VIN1 – VIN2 = [VREF(R1 + R2) / R2] – [VREF(R1 + R2)] – [(VCC R1) / R2] = VCC R1 / R2 (3) VCC VREF VO VIN + R1 R2 Figure 21. Basic Comparator With Hysteresis VO VIN2 0 VIN1 VIN Figure 22. Noninverting Comparator Configuration 7.3.3 Input The LMV76x devices have near-zero input bias current, which allows very high resistance circuits to be used without any concern for matching input resistances. This near-zero input bias also allows the use of very small capacitors in R-C type timing circuits. This reduces the cost of the capacitors and amount of board space used. 7.4 Device Functional Modes 7.4.1 Shutdown Mode The LMV761 features a low-power shutdown pin that is activated by driving SD low. In shutdown mode, the output is in a high-impedance state, supply current is reduced to 20 nA and the comparator is disabled. Driving SD high will turn the comparator on. The SD pin must not be left unconnected due to the fact that it is a highimpedance input. When left unconnected, the output will be at an unknown voltage. Do not three-state the SD pin. The maximum input voltage for SD is 5.5 V referred to ground and is not limited by VCC. This allows the use of 5-V logic to drive SD while VCC operates at a lower voltage, such as 3 V. The logic threshold limits for SD are proportional to VCC. 12 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMV76x are single-supply comparators with 120 ns of propagation delay and 300 µA of supply current. 8.2 Typical Application A typical application for a LMV76x comparator is a programmable square-wave oscillator. R4 C1 VC VO + R1 + VA R3 V + R2 V 0 Figure 23. Square-Wave Oscillator 8.2.1 Design Requirements The circuit in Figure 23 generates a square wave whose period is set by the RC time constant of the capacitor C1 and resistor R4. V+ = 5 V unless otherwise specified. 8.2.2 Detailed Design Procedure The maximum frequency is limited by the large signal propagation delay of the comparator and by the capacitive loading at the output, which limits the output slew rate. Figure 24. Square-Wave Oscillator Timing Thresholds Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 Submit Documentation Feedback 13 LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com Typical Application (continued) Consider the output of Figure 23 is high to analyze the circuit. That implies that the inverted input (VC) is lower than the noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is equal to the noninverting input. The value of VA at this point is calculated by Equation 4: VCC ˜ R2 VA1 R2 R1 R R3 (4) If R1 = R2 = R3, then VA1 = 2 VCC / 3 At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is calculated by Equation 5: VCC (R2 R R3 ) VA2 R1 (R2 R R3 ) (5) If R1 = R2 = R3, then VA2 = VCC / 3. The capacitor C1 now discharges through R4, and the voltage VC decreases until it is equal to VA2, at which point the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it takes to discharge C1 from 2 VCC / 3 to VCC / 3, which is given by R4C1 × ln2. Hence, the formula for the frequency is calculated by Equation 6: F = 1 / (2 × R4 × C1 × ln2) (6) 8.2.3 Application Curve Figure Figure 25 shows the simulated results of an oscillator using the following values: • • • • R1 = R2 = R3 = R4 = 100 kΩ C1 = 100 pF, CL = 20 pF V+ = 5 V, V– = GND CSTRAY (not shown) from Va to GND = 10 pF 6 VOUT 5 Va VOUT (V) 4 3 2 1 Vc 0 -1 0 10 20 30 40 TIME (µs) 50 C001 Figure 25. Square-Wave Oscillator Output Waveform 14 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 9 Power Supply Recommendations To minimize supply noise, power supplies must be decoupled by a 0.1-μF ceramic capacitor in parallel with a 10-μF capacitor. Due to the nanosecond edges on the output transition, peak supply currents will be drawn during output transitions. Peak current depends on the capacitive loading on the output. The output transition can cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power supply to ring due to trace inductance and low self-resonance frequency of high ESR bypass capacitors. Treat the LMV6x as a high-speed device. Keep the ground paths short and place small (low-ESR ceramic) bypass capacitors directly between the V+ and V– pins. Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent current. 10 Layout 10.1 Layout Guidelines The LMV76x is designed to be stable and oscillation free, but it is still important to include the proper bypass capacitors and ground pick-ups. Ceramic 0.1-μF capacitors must be placed at both supplies to provide clean switching. Minimize the length of signal traces to reduce stray capacitance. 10.2 Layout Example C1 GND R1 +IN V+ VIN SOT-23 GND SD OUT -IN VREF R2 Figure 26. Comparator With Hysteresis Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 Submit Documentation Feedback 15 LMV761, LMV762, LMV762Q-Q1 SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMV761 Click here Click here Click here Click here Click here LMV762 Click here Click here Click here Click here Click here LMV762Q-Q1 Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: LMV761 LMV762 LMV762Q-Q1 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMV761MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LMV76 1MA LMV761MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV76 1MA LMV761MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV76 1MA LMV761MF NRND SOT-23 DBV 6 1000 TBD Call TI Call TI -40 to 125 C22A LMV761MF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C22A LMV761MFX NRND SOT-23 DBV 6 3000 TBD Call TI Call TI -40 to 125 C22A LMV761MFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C22A LMV762MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LMV7 62MA LMV762MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV7 62MA LMV762MAX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 125 LMV7 62MA LMV762MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV7 62MA LMV762MM NRND VSSOP DGK 8 TBD Call TI Call TI -40 to 125 C23A LMV762MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C23A LMV762MMX NRND VSSOP DGK 8 3500 TBD Call TI Call TI -40 to 125 C23A LMV762MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C23A LMV762QMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV76 2QMA LMV762QMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV76 2QMA LMV762QMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C32A LMV762QMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C32A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMV761MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV761MF SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV761MF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV761MFX SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV761MFX/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV762MAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV762MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV762MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV762MMX VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV762MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV762QMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV762QMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV762QMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV761MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMV761MF SOT-23 DBV 6 1000 210.0 185.0 35.0 LMV761MF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LMV761MFX SOT-23 DBV 6 3000 210.0 185.0 35.0 LMV761MFX/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LMV762MAX SOIC D 8 2500 367.0 367.0 35.0 LMV762MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMV762MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMV762MMX VSSOP DGK 8 3500 367.0 367.0 35.0 LMV762MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMV762QMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMV762QMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMV762QMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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