MC1455, MC1455B, NCV1455B Timers The MC1455 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode, time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free−running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 mA or drive MTTL circuits. http://onsemi.com MARKING DIAGRAMS 8 Features 8 Direct Replacement for NE555 Timers Timing from Microseconds through Hours Operates in Both Astable and Monostable Modes Adjustable Duty Cycle High Current Output Can Source or Sink 200 mA Output Can Drive MTTL Temperature Stability of 0.005% per °C Normally ON or Normally OFF Output Pb−Free Packages are Available 1.0 k 3 4 2 0.1 mF 8 6 MC1455 5 0.01 mF R x yyy A L Y, YY W, WW G or G 3.5 k 250 V ORDERING INFORMATION − 10 mF + + 0.01 mF 8 + Comp A − Control Voltage 7 Q Trigger + Comp −B Output Discharge Flip R Flop 5k 2 S Inhibit/ Reset 3 Output 5k 1 4 GND Reset Figure 2. Representative Block Diagram © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 9 Control Voltage 3 5k 5 Reset 5 VO ISink ISource VCC ICC VR VCC Threshold = B or V = BP1 or P1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Figure 1. 22 Second Solid State Time Delay Relay Circuit 6 1 1N4003 −10 V 1N4740 MC1455yyy AWL YYWWG 1 C t = 1.1; R and C = 22 sec Time delay (t) is variable by changing R and C (see Figure 16). PDIP−8 P1 SUFFIX CASE 626 8 7 1.0 mF 1 8 MT1 G 20M 1455x ALYW G 1 Load MT2 10 k 1 117 Vac/60 Hz • • • • • • • • • SOIC−8 D SUFFIX CASE 751 4 8 VCC 700 7 Discharge MC1455 Threshold 6 GND Trigger 1 2 Ith 2.0 k VS Test circuit for measuring DC parameters (to set output and measure parameters): a) When VS w 2/3 VCC, VO is low. b) When VS v 1/3 VCC, VO is high. c) When VO is low, Pin 7 sinks current. To test for Reset, set VO c) high, apply Reset voltage, and test for current flowing into Pin 7. c) When Reset is not in use, it should be tied to VCC. Figure 3. General Test Circuit 1 Publication Order Number: MC1455/D MC1455, MC1455B, NCV1455B MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Rating Power Supply Voltage Discharge Current (Pin 7) Power Dissipation (Package Limitation) P1 Suffix, Plastic Package Derate above TA = +25°C D Suffix, Plastic Package Derate above TA = +25°C Symbol Value Unit VCC +18 Vdc I7 200 mA PD 625 5.0 625 160 mW mW/°C mW °C/W PD °C Operating Temperature Range (Ambient) MC1455B MC1455 NCV1455B TA Maximum Operating Die Junction Temperature TJ +150 °C Storage Temperature Range Tstg −65 to +150 °C −40 to +85 0 to +70 −40 to +125 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = +5.0 V to +15 V, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Operating Supply Voltage Range VCC 4.5 − 16 V Supply Current VCC = 5.0 V, RL = R VCC = 15 V, RL = R, Low State (Note 1) ICC − − 3.0 10 6.0 15 − − − 1.0 50 0.1 − − − − 2/3 − − − 5.0 1.67 − − Timing Error (R = 1.0 kW to 100 kW) (Note 2) Initial Accuracy C = 0.1 mF Drift with Temperature Drift with Supply Voltage Threshold Voltage/Supply Voltage Vth/VCC mA % PPM/°C %/V Trigger Voltage VCC = 15 V VCC = 5.0 V VT Trigger Current IT − 0.5 − Reset Voltage VR 0.4 0.7 1.0 V Reset Current IR − 0.1 − mA Threshold Current (Note 3) Ith − 0.1 0.25 mA Idischg − − 100 nA 9.0 2.6 10 3.33 11 4.0 − − − − − − 0.1 0.4 2.0 2.5 − 0.25 0.25 0.75 2.5 − − 0.35 − 12.75 2.75 12.5 13.3 3.3 − − − Discharge Leakage Current (Pin 7) Control Voltage Level VCC = 15 V VCC = 5.0 V VCL Output Voltage Low ISink = 10 mA (VCC = 15 V) ISink = 50 mA (VCC = 15 V) ISink = 100 mA (VCC = 15 V) ISink = 200 mA (VCC = 15 V) ISink = 8.0 mA (VCC = 5.0 V) ISink = 5.0 mA (VCC = 5.0 V) VOL Output Voltage High VCC = 15 V (ISource = 200 mA) VCC = 15 V (ISource = 100 mA) VCC = 5.0 V (ISource = 100 mA) VOH V mA V V V Rise Time Differential Output tr − 100 − ns Fall Time Differential Output tf − 100 − ns 1. 2. 3. 4. ‘Supply current when output is high is typically 1.0 mA less. Tested at VCC = 5.0 V and VCC = 15 V Monostable mode. This will determine the maximum value of RA + RB for 15 V operation. The maximum total R = 20 MW . Tlow = 0°C for MC1455, Tlow = −40°C for MC1455B, NCV1455B Thigh = +70°C for MC1455, Thigh = +85°C for MC1455B, Thigh = +125°C for NCV1455B 5. NCV prefix is for Automotive and other applications requiring site and change control. http://onsemi.com 2 MC1455, MC1455B, NCV1455B 10 125 ICC , SUPPLY CURRENT (mA) PW, PULSE WIDTH (ns min) 150 100 75 0°C 50 25°C 70°C 25 0 0 0.1 0.2 0.3 10 15 Figure 4. Trigger Pulse Width Figure 5. Supply Current 10 VOL, LOW OUTPUT VOLTAGE (Vdc) VCC −VOH (Vdc) 2.0 VCC, SUPPLY VOLTAGE (Vdc) 1.6 1.4 25°C 1.2 1.0 0.8 0.6 0.4 5.0 V ≤ VCC ≤ 15 V 2.0 5.0 10 20 50 25°C 1.0 0.1 0.01 1.0 100 2.0 5.0 10 20 ISource (mA) ISink (mA) Figure 6. High Output Voltage Figure 7. Low Output Voltage @ VCC = 5.0 Vdc 10 50 100 10 VOL, LOW OUTPUT VOLTAGE (Vdc) VOL, LOW OUTPUT VOLTAGE (Vdc) 4.0 VT(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc) 1.8 25°C 1.0 0.1 0.01 1.0 6.0 0 5.0 0.4 2.0 0.2 0 1.0 25°C 8.0 2.0 5.0 10 20 50 1.0 0.01 1.0 100 25°C 0.1 2.0 5.0 10 20 50 ISink (mA) ISink (mA) Figure 8. Low Output Voltage @ VCC = 10 Vdc Figure 9. Low Output Voltage @ VCC = 15 Vdc http://onsemi.com 3 100 MC1455, MC1455B, NCV1455B t d, DELAY TIME NORMALIZED 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0 5.0 10 15 1.010 1.005 1.000 0.995 0.990 0.985 − 75 20 − 50 − 25 0 25 50 75 100 VCC, SUPPLY VOLTAGE (Vdc) TA, AMBIENT TEMPERATURE (°C) Figure 10. Delay Time versus Supply Voltage Figure 11. Delay Time versus Temperature 300 t pd , PROPAGATION DELAY TIME (ns) t d, DELAY TIME NORMALIZED 1.015 250 200 150 0°C 100 70°C 25°C 50 0 0 0.1 0.2 0.3 VT(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc) Figure 12. Propagation Delay versus Trigger Voltage http://onsemi.com 4 0.4 125 MC1455, MC1455B, NCV1455B Control Voltage Threshold Comparator Trigger Comparator Flip−Flop Output VCC 4.7 k 830 4.7k 6.8 k 1.0 k 5.0 k Threshold 7.0 k 3.9 k 10 k Output cb e 5.0 k b c 4.7 k Trigger 220 Reset Reset Discharge GND 100 k 4.7 k 5.0 k Discharge 100 Figure 13. Representative Circuit Schematic GENERAL OPERATION The MC1455 is a monolithic timing circuit which uses an external resistor − capacitor network as its timing element. It can be used in both the monostable (one−shot) and astable modes with frequency and duty cycle controlled by the capacitor and resistor values. While the timing is dependent upon the external passive components, the monolithic circuit provides the starting circuit, voltage comparison and other functions needed for a complete timing circuit. Internal to the integrated circuit are two comparators, one for the input signal and the other for capacitor voltage; also a flip−flop and digital output are included. The comparator reference voltages are always a fixed ratio of the supply voltage thus providing output timing independent of supply voltage. has been triggered by an input signal, it cannot be retriggered until the present timing period has been completed. The time that the output is high is given by the equation t = 1.1 RA C. Various combinations of R and C and their associated times are shown in Figure 16. The trigger pulse width must be less than the timing period. A reset pin is provided to discharge the capacitor, thus interrupting the timing cycle. As long as the reset pin is low, the capacitor discharge transistor is turned “on” and prevents the capacitor from charging. While the reset voltage is applied the digital output will remain the same. The reset pin should be tied to the supply voltage when not in use. +VCC (5.0 V to 15 V) Monostable Mode In the monostable mode, a capacitor and a single resistor are used for the timing network. Both the threshold terminal and the discharge transistor terminal are connected together in this mode (refer to circuit in Figure 14). When the input voltage to the trigger comparator falls below 1/3 VCC, the comparator output triggers the flip−flop so that its output sets low. This turns the capacitor discharge transistor “off” and drives the digital output to the high state. This condition allows the capacitor to charge at an exponential rate which is set by the RC time constant. When the capacitor voltage reaches 2/3 VCC, the threshold comparator resets the flip−flop. This action discharges the timing capacitor and returns the digital output to the low state. Once the flip−flop Reset 4 RL VCC 8 Output 3 RL MC1455 RA Discharge 7 6 Threshold 5 2 Trigger 1 Control Voltage Figure 14. Monostable Circuit http://onsemi.com 5 C 0.01 mF MC1455, MC1455B, NCV1455B 100 C, CAPACITANCE ( μ F) 10 1.0 0.1 0.01 0.001 10 ms t = 50 ms/cm (RA = 10 kW, C = 0.01 mF, RL = 1.0 kW, VCC = 15 V) 100 ms 1.0 ms Figure 15. Monostable Waveforms 10 ms 100 ms td, TIME DELAY (s) 1.0 10 100 Figure 16. Time Delay +VCC (5.0 V to 15 V) Reset 4 RL RA VCC 8 Output 3 7Discharge 6Threshold MC1455 Trigger Control Voltage 2 RL RB 5 1 C t = 20 ms/cm (RA = 5.1 kW, C = 0.01 mF, RL = 1.0 kW; RB = 3.9 kW, VCC = 15 V) Figure 17. Astable Circuit Figure 18. Astable Waveforms Astable Mode In the astable mode the timer is connected so that it will retrigger itself and cause the capacitor voltage to oscillate between 1/3 VCC and 2/3 VCC. See Figure 17. The external capacitor changes to 2/3 VCC through RA and RB and discharges to 1/3 VCC through RB. By varying the ratio of these resistors the duty cycle can be varied. The charge and discharge times are independent of the supply voltage. The charge time (output high) is given by: To obtain the maximum duty cycle RA must be as small as possible; but it must also be large enough to limit the discharge current (Pin 7 current) within the maximum rating of the discharge transistor (200 mA). The minimum value of RA is given by: RA w VCC(Vdc) VCC(Vdc) w 0.2 I7 (A) 100 t1 + 0.695 (RA ) RB) C C, CAPACITANCE ( μ F) The discharge time (output low) is given by: t2 + 0.695 (RB) C Thus the total period is given by: T + t1 ) t2 + 0.695 (RA ) 2RB) C The frequency of oscillation is then: f+ 1 1.44 + 1 (RA ) 2RB)C 1.0 0.1 0.01 (RA + 2 RB) and may be easily found as shown in Figure 19. The duty cycle is given by: 10 0.001 0.1 RB DC + RA ) 2RB 1.0 10 100 1.0 k 10 k f, FREE RUNNING FREQUENCY (Hz) Figure 19. Free Running Frequency http://onsemi.com 6 100 MC1455, MC1455B, NCV1455B APPLICATIONS INFORMATION Linear Voltage Ramp Missing Pulse Detector In the monostable mode, the resistor can be replaced by a constant current source to provide a linear ramp voltage. The capacitor still charges from 0 VCC to 2/3 VCC. The linear ramp time is given by: The timer can be used to produce an output when an input pulse fails to occur within the delay of the timer. To accomplish this, set the time delay to be slightly longer than the time between successive input pulses. The timing cycle is then continuously reset by the input pulse train until a change in frequency or a missing pulse allows completion of the timing cycle, causing a change in the output level. t= 2 VCC , where I = 3 1 VCC − VB − VBE RE If VB is much larger than VBE, then t can be made independent of VCC. +VCC (5.0 V to 15 V) VCC Reset 4 8 VCC RE Digital 3 Output 7 MC1455 Trigger VE 6 2 5 1 0.01 mF Sweep Output Discharge Output MC1455 VB I Input 2 7 Threshold 6 Control 5 Voltage Trigger R2 C 0.01 mF 1 C RA 8 3 R1 2N4403 or Equiv VCC Reset 4 RL 2N4403 or Equiv Control Voltage Figure 20. Linear Voltage Sweep Circuit Figure 21. Missing Pulse Detector t = 100 ms/cm t = 500 ms/cm (RE = 10 kW, R2 = 100 kW, R1 = 39 kW, C = 0.01 mF, VCC = 15 V) (RA = 2.0 kW, RL = 1.0 kW, C = 0.01 mF, VCC = 15 V) Figure 22. Linear Voltage Ramp Waveforms Figure 23. Missing Pulse Detector Waveforms http://onsemi.com 7 MC1455, MC1455B, NCV1455B Pulse Width Modulation If the timer is triggered with a continuous pulse train in the monostable mode of operation, the charge time of the capacitor can be varied by changing the control voltage at Pin 5. In this manner, the output pulse width can be modulated by applying a modulating signal that controls the threshold voltage. +VCC (5.0 V to 15 V) RA RL 4 8 t = 0.5 ms/cm (RA = 10 kW, C = 0.02 mF, VCC = 15 V) 7 3 Figure 25. Pulse Width Modulation Waveforms C Output 6 MC1455 2 5 Clock Input Test Sequences Several timers can be connected to drive each other for sequential timing. An example is shown in Figure 26 where the sequence is started by triggering the first timer which runs for 10 ms. The output then switches low momentarily and starts the second timer which runs for 50 ms and so forth. Modulation Input 1 Figure 24. Pulse Width Modulator VCC (5.0 V to 15 V) 9.1 k 27 k 8 9.1 k 4 8 5 0.01 mF 6 7 3 1.0 mF 1 5.0 mF 4 5 0.01 mF 6 7 MC1455 0.001 mF 2 8 5 0.01 mF 2 3 18.2 k 4 6 MC1455 7 27 k MC1455 3 2 0.001 mF 5.0 mF 1 Load Load Figure 26. Sequential Timer http://onsemi.com 8 1 Load MC1455, MC1455B, NCV1455B ORDERING INFORMATION Device Operating Temperature Range MC1455P1 MC1455P1G MC1455D MC1455DG TA = 0°C to +70°C MC1455DR2 MC1455DR2G MC1455BD MC1455BDG MC1455BDR2 MC1455BDR2G TA = −40°C to +85°C MC1455BP1 MC1455BP1G NCV1455BDR2* NCV1455BDR2G* TA = −40°C to +125°C Package Shipping† PDIP−8 50 Units / Rail PDIP−8 (Pb−Free) 50 Units / Rail SOIC−8 98 Units / Rail SOIC−8 (Pb−Free) 98 Units / Rail SOIC−8 2500 Units / Tape & Reel SOIC−8 (Pb−Free) 2500 Units / Tape & Reel SOIC−8 98 Units / Rail SOIC−8 (Pb−Free) 98 Units / Rail SOIC−8 2500 Units / Tape & Reel SOIC−8 (Pb−Free) 2500 Units / Tape & Reel PDIP−8 50 Units / Rail PDIP−8 (Pb−Free) 50 Units / Rail SOIC−8 2500 Units / Tape & Reel SOIC−8 (Pb−Free) 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV prefix is for automotive and other applications requiring site and control changes. http://onsemi.com 9 MC1455, MC1455B, NCV1455B PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AG NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 mm Ǔ ǒinches INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC1455, MC1455B, NCV1455B PACKAGE DIMENSIONS PDIP−8 P1 SUFFIX CASE 626−05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 −B− 1 4 F −A− NOTE 2 L C J −T− MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 N SEATING PLANE D H DIM A B C D F G H J K L M N M K G 0.13 (0.005) M T A M B M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 11 For additional information, please contact your local Sales Representative. MC1455/D