CXA2174S
US Audio Multiplexing Decoder
Description
The CXA2174S is an IC designed as a decoder for
the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built-in this IC.
Adjustment, mode control and sound processor
control are all executed through I2C BUS.
30 pin SDIP (Plastic)
Features
• Alignment-free VCO and filter
• Audio multiplexing decoder
dbx noise reduction decoder
sound processor
— One external input
— Volume control
are all included in a single chip. Almost any sort of
signal processing is possible through this IC.
• Input level, separation adjustments and each mode
control are possible through I2C bus.
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C)
11
V
• Supply voltage
VCC
• Operating temperature
Topr
–20 to +75 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation
PD
1.35
W
Range of Operating Supply Voltage
9 ± 0.5
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
V
∗ A license of the dbx-TV noise reduction system is
required for the use of this device.
AUX-L
AUX-R
VCAWGT
VCATC
VCAIN
VEOUT
VETC
VEWGT
VE
SAPIN
SAPOUT
NOISETC
STIN
SUBOUT
VCC
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LSOUT-R
LSOUT-L
SDA
SCL
DGND
MAININ
MAINOUT
PCINT1
PCINT2
PLINT
COMPIN
VGR
IREF
GND
SAPTC
Pin Configuration (Top View)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00815-PS
27
28
26
25
24
23
22
18
21
20
3
4
5
DGND
IREF
VGR
RMSDET
SCL
SPECTRAL
SDA
13
SW
LPF
RMSDET
VCA
SAPOUT
12
"PONRES"
LPF
HPF
VE
SAPIN
I2C BUS I/F
AMP
(+4dB)
DeEm
LOGIC
NRSW/FOMO/SAPC
STIN
IREF
SAPIND
"SAP"
"NOISE"
LPF
WIDEBAND
EXTI/MI
VE
SAPTC 15
NOISE
DET
SAPVCO
(+6dB)
LPF
VCA
MATRIX
6
VEWGT
NOISETC 19
BPF
STIND
DeEm
LPF
1/2
7
VETC
GND 14
LPF
"STEREO"
1/4
17
SUBOUT
VEOUT
VCC 16
ATT
VCA
PCINT1
FLT
9
VCO
10
PCINT2
LFLT
PLINT
8
MAINOUT
VCAIN
COMPIN 11
STLPF
VOL-L
30
TVSW
29
AUX-L
VOL-L
MAININ
VCAWGT
–2–
VCATC
AUX-R
VOL-R
Block Diagram
LSOUT-R
LSOUT-L
1
2
CXA2174S
VOL-R
CXA2174S
Pin Description
Pin
No.
Symbol
(Ta = 25°C, VCC = 9V)
Pin
voltage
Equivalent circuit
Description
VCC
3k
1
LSOUT-R
LSOUT right channel output
pin.
4.0V
580
1
580
2
2
LSOUT-L
LSOUT left channel output
pin.
4.0V
VCC
7.5k
↓ 35µ
2.1V
4k
×2
3
SDA
—
7.5k
×5
4.5k
Serial data I/O pin.
VIH > 3.0V
VIL < 1.5V
3k
3
VCC
7.5k
↓ 35µ
2.1V
4
SCL
4k
—
10.5k
×4
3k
Serial clock input pin.
VIH > 3.0V
VIL < 1.5V
4
5
DGND
—
5
Digital block GND.
–3–
CXA2174S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
10k
VCC
6
MAININ
Input the (L + R) signal from
MAINOUT (Pin 7).
4.0V
147
6
53k
4V
VCC
15k
×4
VCC
7
MAINOUT
4.0V
147
(L + R) signal output pin.
7
↓
200µ
1k
VCC
147
8
8
PCINT1
30k
4.0V
22k
Stereo block PLL loop filter
integrating pin.
VCC
147
9
9
PCINT2
10k
4.0V
10k
2k
×2
4k
–4–
CXA2174S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
20k
20k
Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)
147
10
PLINT
10
5.1V
20k
↓
26µ
20k
20k ↓
50µ
10k
VCC
24k
24k
14k
147
11
11
COMPIN
Audio multiplexing signal
input pin.
4.0V
34k
4V
24k
3k
12
VGR
1.3V
9.7k
11k
19.4k
×4
147
VCC
11k
11k
Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)
12
2.06k
VCC
40k
40k
30k
30k
15k
×2
VCC
13
IREF
1.3V
30p 1.8k
13
147
6.3k
16k
–5–
30k
Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based on
the current which flows to this
pin.
(Connect a 62kΩ (±1%)
resistor between this pin and
GND.)
CXA2174S
Pin
No.
Symbol
Pin
voltage
14
GND
—
Equivalent circuit
Description
14
Analog block GND.
VCC
8k
10k
1k
3k
15
SAPTC
4.5V
Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
VCC
4k
↓ 50µ
15
16
VCC
—
Supply voltage pin.
16
Vcc
2k
2k
10P
4k
580
17
SUBOUT
4.0V
(L–R) signal output pin.
17
2k
2k
2k
14.4k
580 147
4k
1k
VCC
18
STIN
23k
4.0V
Input the (L-R) signal from
SUBOUT (Pin 17).
23k
11.7k
147
147
18
21
SAPIN
4.0V
21
18k
18k
4V
20k
–6–
4V
Input the (SAP) signal from
SAPOUT (Pin 20).
CXA2174S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
3.3k
8k
10k
1k
19
NOISETC
3.0V
2k
4k
×2
4V
Vcc
3k
3k
Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
200k
19
Vcc
5P
580
20
SAPOUT
580
4.0V
10k
SAP FM detector output pin.
20
147
24k
↓ 10µ
4k
↓ 50µ
VCC
7.5k
22
VE
Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3kΩ resistor in series
between this pin and GND.)
147
4.0V
22
Vcc
2.9V
580
23
VEWGT
4.0V
4V
23
147
580
36k
8k
–7–
30k
↓ 8µ
4k
↓ 50µ
Weight the variable
de-emphasis control effective
value detection circuit.
(Connect a 0.047µF capacitor
and a 3kΩ resistor in series
between this pin and GND.)
CXA2174S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
24
VETC
1.7V
×4
24
×4
20k
↓ 7.5µ
4k
↓ 50µ
Determine the restoration
time constant of the variable
de-rmphasis control effective
value detection circuit.
(the specified restoration time
constant can be obtained by
connecting a 3.3µF capacitor
between this pin and GND.)
Vcc
5P
Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 25
and 26.)
580
25
VEOUT
4.0V
25
10k
580
VCC
47k
26
VCAIN
20k
4.0V
47k
VCA input pin.
Input the variable
de-emphasis output signal
from Pin 25 via a coupling
capacitor.
VCC
26
VCC
×4
27
VCATC
27
×4
1.7V
↓
50µ
4k
↓
7.5µ
20k
–8–
Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(the specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)
CXA2174S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
40k
40k 3p
580
28
VCAWGT
4.0V
28
2.9V
580 147
36k
↓
50µ
4k↓
8µ
30k
Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)
8k
VCC
29
AUX-R
4.0V
Right channel external input
pin.
10k
29
23.5k
30
AUX-L
4.0V
23.5k
4V
–9–
30
Left channel external input
pin.
– 10 –
11
ST
ST
ST
ST
SNmain
Vsub
FCsub
THDsub
THDsmax
SNsub
CTst
CTsap
Main S/N
Sub output level
Sub LPF frequency
response
Sub distortion
Sub overload distortion
Sub S/N
Crosstalk
Stereo → SAP
Cross talk
SAP → Stereo
7
8
9
10
11
12
13
14
ST
SAP
ST
11
11
11
11
11
11
11
11
THDmmax MONO
Main overload distortion
6
MONO
11
11
MONO
MONO
FCmain
11
THDm
MONO
FCdeem
Main distortion
Main de-emphasis
frequency response
Main LPF frequency
response
5
4
3
11
Vmain
Main output level
2
MONO
—
Mode Input pin
Icc
Symbol
Current consumption
Item
Mono 1kHz 100% mod.
Pre-em. ON
Mono 5kHz 30% mod.
Pre-em. ON
Mono 12kHz 30% mod.
Pre-em. ON
Mono 1kHz 100% mod.
Pre-em. ON
Mono 1kHz 200% mod.
Pre-em. ON
Mono 1kHz,
Pre-em. ON
SUB (L-R) 1kHz,
100% mod., NR OFF
SUB (L-R) 12kHz,
30% mod., NR OFF
SUB (L-R) 1kHz,
100% mod., NR OFF
SUB (L-R) 1kHz,
200% mod., NR OFF
SUB (L-R) 1kHz,
NR OFF
ST-L (R) 1kHz,
100% mod., NR ON,
SAP Carrier (5fH)
SAP 1kHz 100% mod.
NR ON, PILOT (fH)
No signal
Input signal
Main (L + R) (Pre-Emphasis: OFF) = 245mVrms
SUB (L – R) (dbx-TV: OFF) = 490mVrms
Pilot = 49mVrms
SAP Carrier = 147mVrms
fH = 15.734kHz
1
No.
COMPIN input level
(100% modulation level)
Electrical Characteristics
20 log
('100%'/'0%')
20 log
('NRSW = 0'/
'NRSW = 1')
20 log ('NRSW
= 1'/'NRSW = 0')
20 log
('12k'/'1k')
20 log
('100%'/'0%')
20 log
('5k'/'1k')
20 log
('12k'/'1k')
Measurement
conditions
1kBPF
1kBPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
Filter
2
2
17
17
17
17
17
1/2
1/2
1/2
1/2
1/2
1/2
mA
60
60
70
70
—
—
—
2.0
0.2
—
64
1.0
0.1
—
56
1.0
–0.5
dB
dB
dB
%
%
dB
230 mVrms
190
150
–3.0
—
dB
%
69
0.5
0.15
—
%
dB
dB
61
0.5
0.1
1.0
–1.0
–3.0
—
1.0
540 mVrms
43
0
490
32
–1.2
440
23
Output pin Min. Typ. Max. Unit
(Ta = 25°C, Vcc = 9V)
CXA2174S
11
11
11
SAP
SAP
SAP
FCsap
THDsap
SNsap
THsap
HYsap
SAP LPF frequency
response
SAP distortion
SAP S/N
SAP ON level
SAP ON/OFF hysteresis
18
19
20
21
22
– 11 –
11
30/29
30/29
30/29
30/29
30/29
ST
EXT
EXT
EXT
EXT
EXT
STLsep2
STRsep2
Vls
THDlsmax
SNls
VOLmin
ST separation 2 R → L
LSOUT output level
LSOUT mute attenuation MUls
THDls
ST separation 2 L → R
LSOUT distortion
LSOUT overload
distortion
LSOUT S/N
LSOUT volume
maximum attenuation
25
26
27
28
29
30
31
32
EXT
ST
30/29
11
11
STRsep1
ST separation 1 R → L
24
ST
STLsep1
ST separation 1 L → R
11
11
23
ST
SAP
11
Vsap
SAP output level
17
SAP
HYst
Stereo ON/OFF
hysteresis
11
16
ST
Mode Input pin
THst
Symbol
Stereo ON level
Item
15
No.
Sine wave 1kHz
490mVrms
ST-L 300Hz 30% mod.
NR ON
ST-R 300Hz 30% mod.
NR ON
ST-L 3kHz 30% mod.
NR ON
ST-R 3kHz 30% mod.
NR ON
Sine wave 1kHz
490mVrms
Sine wave 1kHz
490mVrms
Sine wave 1kHz
490mVrms
Sine wave 1kHz
2Vrms
Sine wave 1kHz
490mVrms
Change
SAP Carrier (5fH)
Level
SAP 1kHz, NR OFF
SAP 1kHz 100% mod.
NR OFF
SAP 10kHz 30% mod.
NR OFF
SAP 1kHz 100% mod.
NR OFF
Change
PILOT (fH) Level
Input signal
15kLPF
1kBPF
EXT1 = '1'
VOL-L = '0'
VOL-R = '0'
15kLPF
15kLPF
EXT1 = '1'
EXT1 = '1'
EXT1 = '1'
1/2
1/2
1/2
1/2
1/2
EXT1 = '1'
M1 = '0'
1/2
1/2
1/2
1/2
BUS
RETURN
20
20
20
20
–90
88
80
—
0.03
0.01
—
—
–90
490
440
—
35
35
35
35
4.0
23
23
23
23
2.0
dB
dB
dB
dB
dB
–80
—
0.3
0.3
–80
dB
dB
%
%
dB
540 mVrms
—
—
—
—
6.0
dB
–12.0 –9.0 –6.5
%
dB
dB
6.0
2.5
190 mVrms
dB
dB
—
55
2.5
—
46
0
160
–3.0
130
–9.0 –6.0 –3.0
BUS
RETURN 2.0
6.0 10.0
Output pin Min. Typ. Max. Unit
1/2
1kBPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
Filter
EXT1 = '1'
20 log ('on level'
/'off level')
0dB = 147mVrms
20 log
('100%'/'0%')
20 log
('10k'/'1k')
20 log ('on level
'/'off level')
0dB = 49mVrms
Measurement
conditions
(Ta = 25°C, Vcc = 9V)
CXA2174S
R7
3.3k
C16
10µ
SDA
DGND
I2C BUS DATA
4
SCL
3
7
MAININ
6
C7
4.7µ
MAINOUT
DGND
5
R4
C11
100k 0.012µ
9
PCINT2
C10
5600p
R6
1MEG
PCINT1
8
PLINT
10
COMPIN
GND
METAL
± 1%
VGR
12
IREF
SIGNAL
GENERATOR
V1
AC
GND
11
R8
62k
1
C13
1µ
2
AUX-L
LSOUT-R
R3
220
AUX-R
LSOUT-L
R1
220
VCAWGT
C3
4.7µ
VCATC
C1
4.7µ
VCAIN
14
VEOUT
GND
– 12 –
13
16
17
18
19
20
21
22
C18
4.7µ
23
C15
4.7µ
C17
4.7µ
24
C14
4.7µ
VETC
C9
C12
0.047µ 2700P
R5
3k
VEWGT
25
C8
3.3µ
VE
26
C6
4.7µ
SAPIN
27
C5
10µ
SAPOUT
28
C4
1µ
R2
3.9k
NOISETC
29
C5
4.7µ
V4
AC
MEASURES
STIN
30
C2
4.7µ
V3
AC
15kHz LPF
fH BPF
1kHz BPF
FILTERS
SUBOUT
SIGNAL
GENERATOR
SIGNAL
GENERATOR
BUFF
VCC
TANTALUM
S4
S3
S2
S1
TANTALUM
Electrical Characteristics Measurement Circuit
SAPTC
15
C19
4.7µ
C20
100µ
GND
V2
9V
VCC
CXA2174S
CXA2174S
Adjustment Method
1. ATT adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LSOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the LSOUT-L output goes to the standard value
(490mVrms).
3) Adjustment range: ±20%
Adjustment bits:
4 bits
2. Separation adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz
NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce LSOUT-R output to
the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce LSOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
5) “WIDEBAND”
“SPECTRAL”
Adjustment range: ±30%
Adjustment range: ±15%
Adjustment bits:
6 bits
Adjustment bits: 6 bits
∗ Adjust this IC through Tuner and IF when this IC is mounted in the set.
– 13 –
CXA2174S
Register Specifications
Slave address
SLAVE RECEIVER
SLAVE TRANSMITTER
84H (1000 0100)
85H (1000 0101)
Register table
DATA
SUB ADDRESS
MSB
LSB
BIT7
BIT6
BIT5
BIT4
BIT3
TEST-DA
TEST1
BIT2
∗∗∗∗0000
∗
∗∗∗∗0001
∗
SPECTRAL
∗∗∗∗0010
∗
WIDEBAND
∗∗∗∗0011
∗
∗∗∗∗0100
∗
VOL-L
∗∗∗∗0101
∗
VOL-R
BIT0
SAPC
M1
ATT
∗
EXT1
BIT1
NRSW
FOMO
∗ : don't care
Status Registers
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SAP
NOISE
—
—
—
—
POWER
STEREO
ON RESET
Note) The micro computer reads both SAP and NOISE status and judges SAP discrimination.
– 14 –
CXA2174S
Description of Registers
Control registers
Number
of bits
Classification∗1
Standard
setting
ATT
4
A
9
SPECTRAL
6
A
1F
Adjustment of stereo separation (3kHz)
WIDEBAND
6
A
1F
Adjustment of stereo separation (300Hz)
TEST-DA
1
T
0
DAC test mode
TEST1
1
T
0
Test mode
EXT1
1
U
0
Selection of TV mode or external input mode
NRSW
1
U
0
Selection of the output signal (Stereo mode, SAP mode)
FOMO
1
U
0
Forced MONO
(Left channel only is MONO during SAP output.)
M1
1
U
1
Selection of LSOUT mute function ON/OFF
(0: mute ON, 1: mute OFF)
SAPC
1
S
0
Selection SAP mode or L + R mode according to the
presence of SAP brodecasting
VOL-L
1
U
3F
Left channel volume control
VOL-R
1
U
3F
Right channel volume control
Register
Contents
Input level adjustment
∗1 Classification U: User control
A: Adjustment
S: Proper to set
T: Test
Status registers
Register
Number of bits
Contents
PONRES
1
POWER ON RESET detection;
1: RESET
STEREO
1
Stereo discrimination of the COMPIN input signal;
1: Stereo
SAP
1
SAP discrimination of the COMPIN input signal;
1: SAP
NOISE
1
Noise level discrimination of the SAP signal;
1: Noise
– 15 –
CXA2174S
Description of Control Registers
ATT
(4):
Perform input level adjustment.
0 = Level min.
F = Level max.
SPECTRAL
(6):
Perform high frequency (fs = 3kHz) separation adjustment.
0 = Level max.
3F = Level min.
WIDEBAND
(6):
Perform low frequency (fs = 300Hz) separation adjustment.
0 = Level min.
3F = Level max.
TEST-DA
(1):
Set DAC output test mode.
0 = Normal mode
1 = DAC output test mode
In addition, the following output are present at Pin 2.
LSOUT-L (Pin 2): DA control DC level
TEST1
(1):
Monitor SAPBPF and NRBPF output
0 = Normal mode
1 = SAPBPF, NRBPF output
In addition, the following outputs are present at Pins 1 and 2.
LSOUT-L (Pin 2): SAP BPF OUT
LSOUT-R (Pin 1): NR BPF OUT
EXT1
(1):
Select TV mode or external input mode
0 = TV mode
1 = External input mode
NRSW
(1):
Select stereo mode or SAP mode
0 = Stereo mode
1 = SAP mode
FOMO
(1):
Select forced MONO mode
0 = Normal mode
1 = Forced MONO mode
M1
(1):
Mute the LSOUT-L and LSOUT-R output.
0 = Mute ON
1 = Mute OFF
– 16 –
CXA2174S
SAPC
(1):
Select the SAP signal output mode
When there is no SAP signal, the conditions for selecting SAP output are selected by
SAPC.
0 = L + R output is selected
1 = SAP output is selected
VOL-L
(6):
LSOUT-L output signal level control
0 = Volume min.
3F = Volume max.
–1.25dB/STEP
VOL-R
(6):
LSOUT-R output signal level control
0 = Volume min.
3F = Volume max.
–1.25dB/STEP
– 17 –
CXA2174S
Description of Mode Control
Mode control
NRSW
SAPC = 0
SAPC = 1
“Select dbx input and TV decoder output”
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
• During ST input: left channel: L,
right channel: R
• During other input: left channel: L + R,
right channel: L + R
NRSW = 0 (MONO or ST output)
As on the left
NRSW = 1 (SAP output)
• When there is “SAP” during SAP
discrimination
– left channel: SAP, right channel: SAP
• When there is “No SAP”, output is the
same as when NRSW = 0.
• Regardless of the presence of SAP
discrimination,
dbx input: “SAP”
left channel: SAP, right channel: SAP
However, when there is no SAP, SAPOUT
output is soft muted (–7dB)
NRSW = 1 (SAP output)
“Forced MONO”
FOMO
FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC
M1
SAPC = 0: Switch to SAP output when there is SAP discrimination.
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.
“MUTE”
M1 = 0: LSOUT output is muted.
– 18 –
CXA2174S
Decoder Output and Mode Control Table 1 (SAPC = 1)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
0
0
∗
1
MUTE
L+R
L+R
0
0
0
1
0
1
SAP
SAP
SAP
0
0
0
1
1
1
SAP
L+R
SAP
0
∗
1
0
∗
1
MUTE
L+R
L+R
0
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
0
∗
1
1
1
1
(SAP)
L+R
(SAP)
1
0
∗
0
0
1
L–R
L
R
1
0
∗
0
1
1
MUTE
L+R
L+R
1
1
1
0
0
1
L–R
L
R
1
1
1
0
1
1
MUTE
L+R
L+R
1
0
0
1
0
1
SAP
SAP
SAP
1
0
0
1
1
1
SAP
L+R
SAP
1
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
1
∗
1
1
1
1
(SAP)
L+R
(SAP)
0
1
∗
0
0
1
MUTE
L+R
L+R
0
1
∗
0
1
1
MUTE
L+R
L+R
0
1
0
1
0
1
SAP
SAP
SAP
0
1
0
1
1
1
SAP
L+R
SAP
0
1
1
1
0
1
(SAP)
(SAP)
(SAP)
0
1
1
1
1
1
(SAP)
L+R
(SAP)
1
1
∗
0
0
1
L–R
L
R
1
1
∗
0
1
1
MUTE
L+R
L+R
1
1
0
1
0
1
SAP
SAP
SAP
1
1
0
1
1
1
SAP
L+R
SAP
1
1
1
1
0
1
(SAP)
(SAP)
(SAP)
1
1
1
1
1
1
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 19 –
CXA2174S
Decoder Output and Mode Control Table 2 (SAPC = 0)
MONO ∗1
STEREO
∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
∗
∗
∗
0
MUTE
L+R
L+R
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
0
∗
0
0
0
L–R
L
R
1
0
∗
0
1
0
MUTE
L+R
L+R
1
0
∗
1
0
0
L–R
L
R
1
0
∗
1
1
0
MUTE
L+R
L+R
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
0
1
0
0
0
0
MUTE
L+R
L+R
0
1
0
0
1
0
MUTE
L+R
L+R
0
1
0
1
0
0
SAP
SAP
SAP
0
1
0
1
1
0
SAP
L+R
SAP
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
1
0
0
0
0
L–R
L
R
1
1
0
0
1
0
MUTE
L+R
L+R
1
1
0
1
0
0
SAP
SAP
SAP
1
1
0
1
1
0
SAP
L+R
SAP
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 20 –
CXA2174S
Description of Operation
The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz
50
AM-DSB-SC
50
L-R
dbx-TV
NR
25
PILOT
25
15
SAP
dbx-TV NR
FM 10kHz
50 – 10kHz
L+R
5
50 – 15kHz
fH
2fH
3fH
4fH
TELEMETRY
FM 3kHz
3
5fH
6fH
6.5fH
f
fH = 15.734kHz
Fig. 1. Base band spectrum
2
2fHL0°
fHL90°
fHL0°
PLL
(VCO 8fH)
STEREO LPF
(COMPIN)
11
I C BUS
DECODER
MODE
CONTROL
PILOT
DET
MAIN LPF DE.EM
(MAIN OUT)
PILOT
CANCEL
MVCA
(MAIN IN)
6
7
4.7µ
L+R
SUB LPF
L-R (DSB)
DET
WIDEBAND
(SUBOUT) (ST IN)
(Lch)
L – R 4.7µ
SAP BPF
MATRIX
18
17
SUBVCA
NR SW
A
SAP (FM)
DET
SAP LPF
(SAP OUT)
INJ.
LOCK
(SAP IN)
20
dbx-TV
BLOCK
B
21
4.7µ
NOISE
DET
I 2C BUS
DECODER
MODE
CONTROL
I 2C BUS
DECODER
MODE
CONTROL
SAP
DET
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(ST IN)
18
NR SW
A
FIXED
VARIABLE
DEEMPHASIS DEEMPHASIS
(VE OUT)
(VCA IN)
26
25
(SAP IN)
4.7µ
21
HPF
RMS
DET
LPF
LPF
RMS
DET
Fig 3. dbx-TV block
– 21 –
B
VCA
to
MATRIX
(Rch)
to
TVSW
CXA2174S
(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the
L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened
(de-emphasized) and input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 20 output is
soft muted.
(4) Mode discrimination
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.
(5) dbx-TV block
Either the L – R signal or SAP signal input respectively from ST IN (Pin 18) or SAP IN (Pin 21) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is detected
to provide the control signal.
(6) Matrix, TVSW
The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the mode control and whether there is ST / SAP discrimination.
“TVSW” switches the “MATRIX” output signal and external input signal.
(7) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 13) with GND become the reference current.
– 22 –
Application Circuit
– 23 –
2
LSOUT-R
4.7µ
3
µ-com
220
4
6
DGND
DGND
7
MAININ
5
4.7µ
MAINOUT
5600p
1MEG
9
100k 0.012µ
8
10
Composite
baseband
signal input
11
12
10µ
GND
62k
METAL
± 1%
15
4.7µ
100µ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
LS OUTPUT
LSOUT-L
1
4.7µ
AUX-L
14
AUX-R
13
16
17
18
19
20
21
22
23
4.7µ
24
4.7µ
4.7µ
25
1µ
4.7µ
VCAWGT
0.047µ 2700P
3.3k
26
3.3µ
3k
27
220
10µ
4.7µ
28
1µ
3.9k
VCATC
SDA
VCAIN
SCL
VEOUT
TANTALUM
VETC
29
4.7µ
TANTALUM
VEWGT
PCINT1
VE
PCINT2
SAPIN
PLINT
SAPOUT
COMPIN
NOISETC
VGR
STIN
IREF
SUBOUT
GND
VCC
SAPTC
30
4.7µ
AUX INPUT
+9V
CXA2174S
CXA2174S
I2C BUS block items (SDA, SCL)
No.
Item
Symbol
Min.
Typ.
Max.
Unit
1
High level input voltage
VIH
3.0
—
5.0
2
Low level input voltage
VIL
0
—
1.5
3
High level input current
IIH
—
—
10
4
Low level input current
IIL
—
—
10
5
Low level output voltage SDA (Pin 3) during 3mA inflow
VOL
0
—
0.4
V
6
Maximum inflow current
IOL
3
—
—
mA
7
Input capacitance
CI
—
—
10
pF
8
Maximum clock frequency
fSCL
0
—
100
kHz
9
Minimum waiting time for data change
tBUF
4.7
—
—
10
Minimum waiting time for start of data transfer
tHD: STA
4.0
—
—
11
Low level clock pulse width
tLOW
4.7
—
—
12
High level clock pulse width
tHIGH
4.0
—
—
13
Minimum waiting time for start preparation
tSU: STA
4.7
—
—
14
Minimum data hold time
tHD: DAT
0
—
—
15
Minimum data preparation time
tSU: DAT
250
—
—
ns
16
Rise time
tR
—
—
1
µs
17
Fall time
tF
—
—
300
ns
18
Minimum waiting time for stop preparation
tSU: STO
4.7
—
—
µs
V
µA
µs
I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V)
Load capacity 200pF (Connect to GND)
I2C BUS Control Signal
SDA
tBUF
tF
tR
tHD: STA
SCL
P
S tHD: STA
tLOW
tHD: DAT
tHIGH
tSU: STA
tSU: DAT
– 24 –
Sr
tSU: STO
P
CXA2174S
I2C BUS Signal
There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.
• Accordingly there are 3 values outputs, H, L and Hi-Z.
H
L
Hi-Z
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
– 25 –
CXA2174S
• I2C data Write (Write from I2C controller to the IC)
L during Write
MSB
MSB
LSB
Hi-Z
SDA
1
SCL
2
3
4
5
6
7
8
Hi-Z
9
1
8
9
S
ACK
Address
MSB
Sub Address
ACK
LSB
Hi-Z
1
8
Hi-Z
9
DATA (n)
1
ACK
8
DATA (n+1)
ACK
Hi-Z
8
9
DATA (n + 2)
Hi-Z
9
1
8
∗ Data can be transferred in 8-bit units to be
9
set as required.
Sub address is incremented automatically.
P
DATA
ACK
DATA
ACK
• I2C data Read (Read from the IC to I2C controller)
H during Read
Hi-Z
SDA
1
SCL
6
7
8
9
7
1
8
9
P
S
ACK
Address
DATA
ACK
• Read timing
LSB
MSB
IC output SDA
SCL
Read timing
9
1
2
3
ACK
4
DATA
∗ Data Read is performed during SCL rise.
– 26 –
5
6
7
8
9
ACK
CXA2174S
Input level vs. Distortion characteristics 2 (Stereo)
Input level vs. Distortion characteristics 1 (MONO)
10
Input signal: Stereo L = –R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF, ST mode
Measurement point: LSOUT-L/R
Distortion [%]
Distortion [%]
1.0
Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF
Measurement point: LSOUT-L/R
1.0
0.1
Standard level (100%)
–10
0
10
Standard level (100%)
Input level [dB]
–10
0
Input level [dB]
Input level vs. Distortion characteristics 3 (SAP)
Distortion [%]
10
Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: LSOUT-L/R
1.0
Standard level (100%)
–10
0
Input level [dB]
10
– 27 –
10
CXA2174S
Stereo LPF frequency characteristics
Main LPF and Sub LPF frequency characteristics
10
Gain (FC main and FC sub) [dB]
30
Gain [dB]
5
0
–5
20
10
0
–10
–20
–30
–40
–10
–50
0
20
40
60
80
1
100
2
Frequency [kHz]
7
10
20
50 70 100
Frequency [kHz]
SAP frequency characteristics and group delay
Volume charactiristics
100
20
0
90
5fH
–20
60
50
0
40
30
–10
20
Group delay
3.8fH
–20
20
40
60
80
6.2fH
100
LSOUT output level [dB]
70
Group delay [µs]
80
Gain
10
Gain [dB]
5
–40
–60
Input:
AUXIN (Pins 29, 30)
1kHz, 490mVrms
Output: LSOUT (Pins 1, 2)
–80
10
0
120
–100
0
Frequency [kHz]
– 28 –
1F
2F
F
Control data VOL-L, VOL-R
3F
CXA2174S
Package Outline
Unit: mm
+ 0.1
.05
0.25 – 0
30PIN SDIP (PLASTIC)
+ 0.4
26.9 – 0.1
30
+ 0.3
8.5 – 0.1
10.16
16
0˚ to 15˚
15
1
+ 0.4
3.7 – 0.1
0.5 MIN
1.778
0.5 ± 0.1
3.0 MIN
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
0.9 ± 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SONY CODE
SDIP-30P-01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
P-SDIP30-8.5x26.9-1.778
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
1.8g
JEDEC CODE
– 29 –
Sony Corporation