ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 ADC10080 10-Bit, 80 MSPS, 3V, 78.6 mW A/D Converter Check for Samples: ADC10080 FEATURES APPLICATIONS • • • • • • • • • 1 2 • • Single +3.0V operation Selectable full-scale input swing 400 MHz −3 dB input bandwidth Low power consumption Standby mode On-chip reference and sample-and-hold amplifier Offset binary or two’s complement data format Separate adjustable output driver supply • • • • • Ultrasound and Imaging Instrumentation Cellular Base Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends DESCRIPTION The ADC10080 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 80 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution and to minimize power consumption, while providing excellent dynamic performance. A unique sampleand-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 78.6 mW at 80 MSPS, including the reference current. The Standby feature reduces power consumption to just 15 mW. The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C. Table 1. Key Specifications VALUE UNIT Resolution 10 Bits Conversion Rate 80 MSPS Full Power Bandwidth 400 MHz DNL ±0.25 LSB (typ) SNR (fIN = 10 MHz) 59.5 dB (typ) SFDR (fIN = 10 MHz) −78.7 dB (typ) Power Consumption, 80 Msps 78.6 mW 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2008, Texas Instruments Incorporated ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com Connection Diagram Block Diagram Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 12 VIN− Inverting analog input signal. With a 1.2V reference the full-scale input signal level is a differential 1.0 VP-P. This pin may be tied to VCOM (pin 4) for single-ended operation. 13 VIN+ Non-inverting analog input signal. With a 1.2V reference the fullscale input signal level is a differential 1.0 VP-P. (1) 2 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 Pin No. Symbol 6 VREF Equivalent Circuit Description Reference input. This pin should be bypassed to VSSA with a 0.1 µF monolithic capacitor. VREF is 1.20V nominal. This pin may be driven by a 1.20V external reference if desired. Do not load this pin. (2) 7 VREFT 4 VCOM 8 VREFB These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to VSSA. These pins should not be loaded. VCOM may be used to set the input common input voltage, VCM. (3) DIGITAL I/O 1 CLK 15 DF 28 STBY 5 IRS (Input Range Select) 16–20, 23–27 D0–D9 Digital clock input. The range of frequencies for this input is 20 MHz to 80 MHz. The input is sampled on the rising edge of this input. DF = “1” Two’s Complement DF = “0” Offset Binary This is the standby pin. When high, this pin sets the converter into standby mode. When this pin is low, the converter is in active mode. IRS = “VDDA” 2.0 VP-P differential input range IRS = “VSSA” 1.5 VP-P differential input range IRS = “Floating” 1.0 VP-P differential input range If using both VIN+ and VIN- pins, (or differential mode), then the (4) peak-to-peak voltage refers to the differential voltage (VIN+ - VIN-). Digital output data. D0 is the LSB and D9 is the MSB of the binary output word. (5) ANALOG POWER 2, 9, 10 VDDA Positive analog supply pins. These pins should be connected to a quiet 3.0V source and bypassed to analog ground with a 0.1 µF monolithic capacitor located within 1 cm of these pins. A 4.7 µF capacitor should also be used in parallel. 3, 11, 14 VSSA Ground return for the analog supply. DIGITAL POWER Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 3 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 Pin No. Symbol www.ti.com Equivalent Circuit Description 22 VDDIO Positive digital supply pins for the ADC10080's output drivers. This pin should be bypassed to digital ground with a 0.1 µF monolithic capacitor located within 1 cm of this pin. A 4.7 µF capacitor should also be used in parallel. The voltage on this pin should never exceed the voltage on VDDA by more than 300 mV. 21 VSSIO The ground return for the digital supply for the output drivers. This pin should be connected to the ground plane, but not near the analog circuitry. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VDDA, VDDIO 3.9V −0.3V to VDDA or VDDIO +0.3V Voltage on Any Pin to GND Input Current on Any Pin ±25 mA (3) Package Input Current ±50 mA Package Dissipation at T = 25°C See (4) ESD Susceptibility Human Body Model Machine Model (5) 2500V (5) Soldering Temperature 250V Infrared, 10 sec. (6) 235°C −65°C to +150°C Storage Temperature (1) (2) (3) (4) (5) (6) All voltages are measured with respect to GND = VSSA = VSSIO = 0V, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. When the voltage at any pin exceeds the power supplies (VIN < VSSA or VIN > VDDA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. In the 28-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,302 mW at 25°C and 677 mW at the maximum operating ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 78.6 mW. The values for maximum power dissipation listed above will be reached only when the ADC10080 is operated in a severe fault condition. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top of the package body above 183°C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be generated if the input goes above VDDA or VDDIO and below VSSA or VSSIO. Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Operating Temperature Range VDDA (Supply Voltage) (1) (2) 4 +2.7V to +3.6V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = VSSA = VSSIO = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 Operating Ratings (1) (2) (continued) VDDIO (Output Driver Supply Voltage) +2.5V to VDDA VREF 1.20V ≤ 100 mV |VSSA–VSSIO| Clock Duty Cycle 30 to 70 % Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 5 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V (1) (1) (2), VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V (External), fCLK = 80 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. (3) (1) (2) Symbol Parameter Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS No Missing Codes Guaranteed 10 Bits INL Integral Non-Linearity (4) FIN = 500 kHz, 0 dB Full Scale −1.4 ±0.5 +1.6 DNL Differential Non-Linearity FIN = 500 kHz, 0 dB Full Scale −0.9 ±0.25 +1.0 LSB Positive Error −1.6 +0.5% +2.0 % FS Negative Error −1.6 −0.07% +2.0 % FS −1.4 0.11 1.7 % FS GE Gain Error OE Offset Error (VIN+ = VIN−) FPBW Under Range Output Code 0 Over Range Output Code 1023 Full Power Bandwidth 400 LSB MHz REFERENCE AND INPUT CHARACTERISTICS VCM Common Mode Input Voltage VCOM Output Voltage for use as an input common mode voltage (5) VREF Internal Reference Voltage 0.5 1.45 CIN 1.0 Internal Reference Voltage Temperature Coefficient VIN Input Capacitance (each pin to VSSA) 1.2 V V 1.2 External Reverence Voltage VREFTC 1.5 V 1.5 V ±80 ppm/°C 4 pF POWER SUPPLY CHARACTERISTICS IVDDA Analog Supply Current IVDDIO Digital Supply Current PWR (1) (2) (3) (4) (5) (6) (7) 6 Power Consumption (6) (7) STBY = 1 5 6.3 mA STBY 0 25 32 mA STBY = 1, fIN= 0 Hz 0 STBY 0, fIN = 0 Hz 1.2 1.4 mA mA STBY = 1 15 18.9 mW STBY = 0 78.6 100.2 mW With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. Typical figures are at TA = TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). To guarantee accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge. VCOM is typical value, measured at room temperature. It is not guaranteed by test. This pin should not be loaded. IVDDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDDIO, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR x (C0 x f0 + C1 x f1 + C2 + f2 +....C11 x f11) where VDR is the output driver supply voltage, Cn is the total load capacitance on the output pin, and fn is the average frequency at which the pin is toggling. Power consumption includes output driver power. (fIN = 0 MHz). Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V (External), fCLK = 80 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1) (2) (3) Symbol Parameter Conditions Min Typ Max Units CLK, DF, STBY, SENSE Logical “1” Input Voltage 2 V Logical “0” Input Voltage 0.8 V Logical “1” Input Current +10 µA −10 Logical “0” Input Current µA D0–D9 OUTPUT CHARACTERISTICS Logical “1” Output Voltage IOUT = −0.5 mA Logical “0” Output Voltage IOUT = 1.6 mA DYNAMIC CONVERTER CHARACTERISTICS ENOB SNR SINAD 2nd HD 3rd HD THD SFDR (1) (2) (3) (4) VDDIO−0.2 V 0.4 V (4) fIN = 10.0 MHz 9.3 9.1 9.5 Bits fIN = 39 MHz 9.3 8.9 9.5 Bits fIN = 10.0 MHz 58.5 57.7 59.5 dB fIN = 39 MHz 58.0 57.0 59.2 dB fIN = 10.0 MHz 58.0 56.3 59.2 fIN = 39 MHz 57.6 55.6 59.0 fIN = 10.0 MHz −74.1 −68.7 −87.0 dBc fIN = 39 MHz −69.5 −62.7 −82 dBc fIN = 10.0 MHz −65 −58.6 −72.3 dBc fIN = 39 MHz −64.7 −57.6 −74.5 dBc fIN = 10.0 MHz −65 −58.6 −72.3 dB fIN = 39 MHz −64.7 −57.6 −74.5 dB fIN = 10.0 MHz −70.8 −68.2 −78.7 dBc −72 −68 −78.8 dBc Effective Number of Bits Signal-to-Noise Ratio Signal-to-Noise Ratio + Distortion 2nd Harmonic 3rd Harmonic Total Harmonic Distortion (First 6 Harmonics) Spurious Free Dynamic Range (Excluding 2nd and 3rd Harmonic) fIN = 39 MHz dB dB To guarantee accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. Typical figures are at TA = TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Optimum dynamic performance will be obtained by keeping the reference input at +1.2V. Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 7 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com AC Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 80 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1) (2) (3) (4) Symbol Parameter Conditions Min (4) Typ (4) Max (4) Units 80 MHz (min) CLK, DF, STBY, SENSE fCLK1 Maximum Clock Frequency fCLK2 Minimum Clock Frequency tCH tCL 20 MHz Clock High Time 6.25 ns Clock Low Time 6.25 ns Conversion Latency T = 25°C 2 3.5 6 Cycles 5 ns 6 ns tOD Data Output Delay after a Rising Clock Edge tAD Aperture Delay 1 ns tAJ Aperture Jitter 2 ps (RMS) 1 Clock Cycle 20 Cycles Over Range Recovery Time tSTBY (1) (2) (3) (4) 1 Differential VIN step from ±3V to 0V to get accurate conversion Standby Mode Exit Cycle To guarantee accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. Typical figures are at TA = TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge. Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full-Scale Error − Negative Full-Scale Error (6) INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale through positive full scale. The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC10080 is guaranteed not to have any missing codes. 8 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 NEGATIVE FULL SCALE ERROR is the difference between the input voltage (VIN+ − VIN−) just causing a transition from negative full scale to the first code and its ideal value of 0.5 LSB. OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding DC. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as: (7) where f1 is the RMS power of the fundamental (output) frequency and f2 through f6 are the RMS power in the first 6 harmonic frequencies. Second Harmonic Distortion (2nd Harm) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. Timing Diagram Figure 1. Clock and Data Timing Diagram Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 9 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com Transfer Characteristics Figure 2. Input vs. Output Transfer Characteristic 10 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle. DNL DNL vs. fCLK DNL vs. Clock Duty Cycle (DC input) DNL vs. Temperature INL INL vs. fCLK INL vs. Clock Duty Cycle SNR vs. VDDIO Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 11 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle. 12 SNR vs. VDDA SNR vs. fCLK INL vs. Temperature SNR vs. Clock Duty Cycle SNR vs. Temperature THD vs. VDDA THD vs. VDDIO THD vs. fCLK Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle. SNR vs. IRS THD vs. IRS SINAD vs. VDDA SINAD vs. VDDIO THD vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle THD vs. Temperature SINAD vs. Temperature Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 13 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle. 14 SINAD vs. fCLK SFDR vs. VDDIO SINAD vs. IRS SFDR vs. fCLK SFDR vs. VDDA SFDR vs. IRS SFDR vs. Clock Duty Cycle Spectral Response @ 10 MHz Input Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle. SFDR vs. Temperature Spectral Response @ 39 MHz Input Power Consumption vs. fCLK Functional Description The ADC10080 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. In differential mode each analog input signal should have a peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depending on the state of the IRS pin (pin 5), and be centered around VCM and be 180° out of phase with each other. If single ended operation is desired, VIN- may be tied to the VCOM pin (pin 4). A single ended input signal may then be applied to VIN+, and should have a mid range value of VCOM. The signal amplitude should be 2.0V, 1.5V or 1.0V peak-to-peak, depending on the state or the IRS pin (pin 5). Applications Information 1.0 ANALOG INPUTS The ADC10080 has two analog signal inputs, VIN+ and VIN−. These two pins form a differential input pair. There is one common mode pin VCOM that may be used to set the common mode input voltage. 1.2 VCOM PIN This pin supplies a voltage for possible use to set the common mode input voltage. This pin may also be connected to VIN-, so that VIN+ may be used as a single ended input. This pin should be bypassed with at least a 0.1 uF capacitor. Do not load this pin. 1.3 SIGNAL INPUTS The signal inputs are VIN+ and VIN−. The input signal amplitude is defined as VIN+ − VIN− and is represented in Figure 3: Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 15 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com 2.5V Max VCM + 0.5V VCM VCM - 0.5V 0V Min Figure 3. Input Voltage Waveforms for a 2VP-P Differential Input A single ended input signal is shown in Figure 4. 2.5V Max VCM + 1V VCM VCM - 1V 0V Min Figure 4. Input Voltage Waveform for a 2VP-P Single Ended Input The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal. To prevent this, use 18Ω series resistors at each of the signal input pins with a 25 pF capacitor across the inputs, as shown in Figure 5. These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The two 18Ω resistors and the 25 pF capacitor form a low-pass filter with a -3 dB frequency of 177 MHz. 1.4 CLK PIN The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the frequency range indicated in the AC Electrical Characteristics Table with rise and fall times of less than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90°. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the lowest sample rate. The duty cycle of the clock 16 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 ADC10080 www.ti.com SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC10080 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained with minimum clock low and high times indicated in the AC Electrical Characteristics Table. Both minimum high and low times may not be held simultaneously. 1.5 STBY PIN The STBY pin, when high, holds the ADC10080 in a power-down mode to conserve power when the converter is not being used. The power consumption in this state is 15 mW. The output data pins are undefined in this mode. Power consumption during power-down is not affected by the clock frequency, or by whether there is a clock signal present. The data in the pipeline is corrupted while in power down. 1.6 DF PIN The DF (Data Format) pin, when high, forces the ADC10080 to output the 2’s complement data format. When DF is tied low, the output format is offset binary. 1.7 IRS PIN The IRS (Input Range Select) pin defines the input signal amplitude that will produce a full scale output. The table below describes the function of the IRS pin. Table 2. IRS Pin Functions IRS Pin Full-Scale Input VDDA 2.0VP-P VSSA 1.5VP-P Floating 1.0VP-P 1.8 OUTPUT PINS The ADC10080 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these outputs while the DF and STBY pins are low. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDDIO and VSSIO. These large charging current spikes can cause on-chip noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by minimizing load capacitance and by connecting buffers between the ADC outputs and any other circuitry, which will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. Only one driven input should be connected to the ADC output pins. 1.9 APPLICATION SCHEMATICS The following figures show simple examples of using the ADC10080. Figure 5 shows a typical differentially driven input. Figure 6 shows a single ended application circuit. Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 17 ADC10080 SNAS177G – MAY 2004 – REVISED FEBRUARY 2008 www.ti.com Figure 5. A Simple Application Using a Differential Driving Source Figure 6. A Simple Application Using a Single Ended Driving Source 18 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Links: ADC10080 PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) ADC10080CIMT/NOPB ACTIVE TSSOP PW 28 48 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR ADC10080CIMTX ACTIVE TSSOP PW 28 2500 TBD CU SNPB Level-3-235C-168 HR ADC10080CIMTX/NOPB ACTIVE TSSOP PW 28 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC10080CIMTX TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 ADC10080CIMTX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10080CIMTX TSSOP PW 28 2500 358.0 343.0 63.0 ADC10080CIMTX/NOPB TSSOP PW 28 2500 358.0 343.0 63.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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