HEF4066B Quad single-pole single-throw analog switch Rev. 7 — 16 November 2011 Product data sheet 1. General description The HEF4066B provides four single-pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4066BP 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 HEF4066BT 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 5. Functional diagram 1Y 1E 2Y 2E 3Y 3E 4Y 4E 1 2 1Z 13 nY 4 3 2Z nE 5 8 9 3Z VDD 11 10 4Z 12 VSS 001aag200 Fig 1. VDD 6 nZ 001aag201 Functional diagram Fig 2. Logic diagram (one switch) 6. Pinning information 6.1 Pinning 1Y 1 14 VDD 1Z 2 13 1E 2Z 3 12 4E 2Y 4 HEF4066B 11 4Y 2E 5 10 4Z 3E 6 9 3Z VSS 7 8 3Y 001aag202 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description 1Y, 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output 1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output 1E, 2E, 3E, 4E 13, 5, 6, 12 enable input (active HIGH) VSS 7 ground (0 V) VDD 14 supply voltage HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 7. Functional description Table 3. Function table[1] Input nE Switch H ON L OFF [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage Conditions VI < 0.5 V or VI > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V II/O input/output current - 10 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C Ptot total power dissipation P [1] power dissipation [1] Tamb = 40 C to +85 C DIP14 [2] - 750 mW SO14 [3] - 500 mW - 100 mW per switch To avoid drawing VDD current out of terminal nZ, when switch current flows into terminals nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VDD current will flow out of terminals nY, in this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed VDD or VSS. [2] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. [3] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage VI input voltage Tamb ambient temperature in free air t/V input transition rise and fall rate HEF4066B Product data sheet Conditions Min Typ Max Unit 3 - 15 V 0 - VDD V 40 - +125 C VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Min VIH VIL HIGH-level input voltage LOW-level input voltage IO < 1 A input leakage current IS(OFF) OFF-state leakage current IDD supply current all valid input combinations CI input capacitance per channel; see Figure 4 nE input Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 15 V - 0.1 - 0.1 - 1.0 - 1.0 A 15 V - - - 200 - - - - nA 5V - 1.0 - 1.0 - 7.5 - 7.5 A 10 V - 2.0 - 2.0 - 15.0 - 15.0 A 15 V - 4.0 - 4.0 - 30.0 - 30.0 A - - - - 7.5 - - - - pF IO < 1 A II Max Tamb = 85 C Tamb = 125 C Unit 10.1 Test circuit VDD nE VIL nZ VI nY IS VSS VO 001aak669 Fig 4. Test circuit for measuring OFF-state leakage current HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 10.2 ON resistance Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = 0 V. Symbol Parameter Conditions RON(peak) ON resistance (peak) VI = 0 V to VDD; see Figure 5 and Figure 6 RON(rail) ON resistance (rail) VDD Typ Max Unit 5V 350 2500 10 V 80 245 15 V 60 175 5V 115 340 10 V 50 160 15 V 40 115 5V 120 365 10 V 65 200 15 V 50 155 VI = 0 V; see Figure 5 and Figure 6 VI = VDD; see Figure 5 and Figure 6 RON ON resistance mismatch between channels 5V 25 - 10 V 10 - 15 V 5 - VI = 0 V to VDD; see Figure 5 10.2.1 ON resistance waveform and test circuit 001aak671 400 RON (Ω) (1) 300 VSW 200 VDD nE VIH 100 nY VI nZ (2) VSS (3) ISW 0 0 5 10 15 VI (V) 001aak670 ISW = 200 A. RON = VSW / ISW. (1) VDD = 5 V (2) VDD = 10 V (3) VDD = 15 V Fig 5. Test circuit for measuring RON HEF4066B Product data sheet Fig 6. Typical RON as a function of input voltage All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = 0 V; for test circuit see Figure 9. Symbol Parameter Conditions VDD tPHL HIGH to LOW propagation delay nY, nZ to nZ, nY; see Figure 7 nY, nZ to nZ, nY; see Figure 7 tPHZ tPZH tPLZ tPZL HIGH to OFF-state propagation delay nE to nY, nZ; see Figure 8 OFF-state to HIGH propagation delay nE to nY, nZ; see Figure 8 LOW to OFF-state propagation delay nE to nY, nZ; see Figure 8 OFF-state to LOW propagation delay nE to nY, nZ; see Figure 8 Typ Max Unit 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 80 160 ns 10 V 65 130 ns 15 V 60 120 ns 5V 40 80 ns 10 V 20 40 ns 15 V 15 30 ns 5V 80 160 ns 10 V 70 140 ns 15 V 70 140 ns 5V 45 90 ns 10 V 20 40 ns 15 V 15 30 ns Table 9. Dynamic power dissipation PD PD can be calculated from the formulas shown; VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V Typical formula for PD (W) where: PD = 2500 fi + (fo CL) VDD 2 fi = input frequency in MHz; 10 V PD = 11500 fi + (fo CL) VDD2 fo = output frequency in MHz; 15 V PD = 29000 fi + (fo CL) CL = output load capacitance in pF; VDD2 VDD = supply voltage in V; (CL fo) = sum of the outputs. HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 11.1 Waveforms and test circuit VI input nY or nZ VM VM tPLH tPHL 0V VO VM output nZ or nY VM 0V 001aak672 Measurement points are given in Table 10. Fig 7. nY or nZ to nZ or nY propagation delays VI VM VM input nE 0V tPLZ tPZL VDD 90 % output nY or nZ 10 % 0V tPHZ VDD tPZH 90 % output nY or nZ 10 % 0V switch ON switch OFF switch ON 001aak673 Measurement points are given in Table 10. Fig 8. Enable and disable times Table 10. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VDD VI VI VDD VO G RL S1 open DUT RT CL VSS 001aak674 Test data is given in Table 11. Definitions: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including test jig and probe. RL = Load resistance. Fig 9. Test circuit for measuring switching times Table 11. Test data Supply voltage Input Load S1 position VDD VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 5 V to 15 V 0 V or VDD 20 ns 50 pF 10 k VSS VSS VDD 11.2 Additional dynamic parameters Table 12. Additional dynamic characteristics VSS = 0 V; Tamb = 25 C. Symbol THD Vct Parameter total harmonic distortion crosstalk voltage HEF4066B Product data sheet Conditions VDD see Figure 10; RL = 10 k; CL = 15 pF; 5 V channel ON; VI = 0.5VDD (p-p); 10 V fi = 1 kHz 15 V nE input to switch; see Figure 11; RL = 10 k; CL = 15 pF; nE = VDD (square-wave) All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 10 V Typ Max Unit [1] 0.25 - % [1] 0.04 - % [1] 0.04 - % 50 - mV © NXP B.V. 2011. All rights reserved. 8 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch Table 12. Additional dynamic characteristics …continued VSS = 0 V; Tamb = 25 C. Symbol Parameter Conditions VDD Typ Max Unit 50 - dB Xtalk crosstalk between switches; see Figure 12; fi = 1 MHz; RL = 1 k; VI = 0.5VDD (p-p) 10 V [1] iso isolation (OFF-state) see Figure 13; fi = 1 MHz; RL = 1 k; CL = 5 pF; VI = 0.5VDD (p-p) 10 V [1] 50 - dB f(3dB) 3 dB frequency response see Figure 14; RL = 1 k; CL = 5 pF; VI = 0.5VDD (p-p) 10 V [1] 90 - MHz [1] fi is biased at 0.5VDD. 11.2.1 Test circuits VDD nE VIH nY nZ VSS fi RL CL D 001aak675 Fig 10. Test circuit for measuring total harmonic distortion 0.5VDD VDD RL nE nY nZ VSS G RL CL V VO 001aak676 a. Test circuit logic input nE off on off Vct VO 001aak677 b. Input and output pulse definitions Fig 11. Test circuit for measuring crosstalk voltage between digital input and switch HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch VDD 1E VIH 1Y or 1Z 1Z or 1Y CHANNEL ON VI RL V VO1 RL V VO2 nE VIL nY or nZ nZ or nY CHANNEL OFF RL VSS 001aak678 20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2). Fig 12. Test circuit for measuring crosstalk between switches VDD VDD nE VIL nY fi nE VIH nZ VSS nY RL CL dB fi 001aak679 Adjust fi voltage to obtain 0 dBm level at input. Fig 13. Test circuit for measuring isolation (OFF-state) HEF4066B Product data sheet nZ VSS RL CL dB 001aak680 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Fig 14. Test circuit for measuring frequency response All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 15. Package outline SOT27-1 (DIP14) HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT108-1 (SO14) HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 13. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4066B v.7 20111116 Product data sheet - HEF4066B v.6 Modifications: • • Legal pages updated. Changes in “General description”, “Features and benefits” and “Applications”. HEF4066B v.6 20100325 Product data sheet - HEF4066B v.5 HEF4066B v.5 20100225 Product data sheet - HEF4066B v.4 HEF4066B v.4 20091013 Product data sheet - HEF4066B_CNV v.3 HEF4066B_CNV v.3 19950101 Product specification - HEF4066B_CNV v.2 HEF4066B_CNV v.2 19950101 Product specification - - HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4066B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 16 HEF4066B NXP Semiconductors Quad single-pole single-throw analog switch 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 11 11.1 11.2 11.2.1 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance waveform and test circuit . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms and test circuit . . . . . . . . . . . . . . . . 7 Additional dynamic parameters . . . . . . . . . . . . 8 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 November 2011 Document identifier: HEF4066B