Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM DESCRIPTION The MH2S64CZTJ/CWZTJ is 2097152-word by 64-bit Synchronous DRAM module. This consists of eight industry standard 2Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules. FEATURES CLK Access Time 1pin 94pin 10pin 95pin 11pin 124pin 40pin 125pin 41pin 168pin 84pin (Component SDRAM) 83MHz 8ns(CL=3) -15 67MHz 9.5ns (CL=2) -1539 67MHz 9ns (CL=3) Utilizes industry standard 2M x 8 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP 168-pin (84-pin dual in-line package) Front side -12 Back side Frequency 85pin single 3.3V±0.3V power supply Clock frequency 83MHz/67MHz Fully synchronous operation referenced to clock rising edge Dual bank operation controlled by BA(Bank Address) /CAS latency- 1/2/3(programmable) Burst length- 1/2/4/8(programmable) Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycle /64ms LVTTL Interface APPLICATION main memory or graphic memory in computer systems SPD table Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 126 127 MH2S64CZTJ/CWZTJ-12 80 08 04 0C 09 01 40 00 01 C0 80 00 80 00 06 01 05 02 06 01 01 83 06 MH2S64CZTJ/CWZTJ-15 80 08 04 0C 09 01 40 00 01 F0 95 00 80 00 06 01 05 02 06 01 01 66 06 MH2S64CZTJ/CWZTJ-1539 80 MIT-DS-0019-0.4 08 04 0C 09 01 40 00 01 F0 90 00 80 00 04 01 05 02 04 01 01 66 04 MITSUBISHI ELECTRIC ( 1 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME 1 VSS 43 VSS 85 VSS 127 VSS CKE 2 DQ0 44 NC 86 DQ32 128 3 DQ1 45 /S2 87 DQ33 129 NC 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VDD 48 NC 90 VDD 132 7 DQ4 49 VDD 91 DQ36 133 NC VDD 8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC NC 10 DQ7 52 NC 94 DQ39 136 11 53 NC 95 DQ40 137 NC 12 DQ8 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VDD 101 DQ45 143 VDD 18 VDD 60 DQ20 102 VDD 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 NC 63 NC 105 NC 147 NC 22 NC 64 VSS 106 NC 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 109 NC 151 DQ55 26 68 110 VDD 152 VSS 27 VDD /WE0 DQ23 VSS 69 DQ24 111 /CAS 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 /S0 72 DQ27 114 DQ59 NC 73 VDD 115 NC /RAS 156 31 157 VDD 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 NC 121 A9 163 NC 38 A10 80 NC 122 BA 164 NC 39 NC 81 NC 123 NC 165 SA0 40 VDD 82 SDA 124 VDD 166 SA1 41 42 VDD CK0 83 84 SCL VDD 125 126 CK1 NC 167 168 SA2 VDD NC = No Connection MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 2 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM Block Diagram MH2S64CZTJ Address CKE /RAS /CAS /WE CK0 /S0 DQMB0 DQMB4 DQM /CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CK0 DQM /CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQMB1 CK0 D4 DQMB5 DQM /CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CK0 DQM /CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 CK0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 CK1 /S2 DQMB2 DQMB6 DQM /CS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM /CS CK0 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQMB3 CK0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQMB7 DQM /CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM /CS CK0 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 CK0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 SERIAL PD Vcc D0 - D7 Vss D0 - D7 SCL SDA A0 A1 A2 SA0 SA1 SA2 MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 3 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM Block Diagram MH2S64CWZTJ Address CKE /RAS /CAS /WE CK0 /S0 DQMB0 DQMB4 DQM /CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CK0 DQM /CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQMB1 CK0 D4 DQMB5 DQM /CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CK0 DQM /CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 CK0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 CK1 /S2 DQMB2 DQMB6 DQM /CS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM /CS CK0 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQMB3 CK0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQMB7 DQM /CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM /CS CK0 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 CK0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 SERIAL PD Vcc D0 - D7 SCL Vss D0 - D7 SDA A0 A1 A2 SA0 SA1 SA2 MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 4 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM PIN FUNCTION Input Master Clock:All other inputs are referenced to the rising edge of CK CKE Input Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. /S (/S0 & /S2) Input Chip Select: When /S is high,any command means No Operation. /RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands. A0-10 Input A0-10 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-10.The Column Address is specified by A0-8.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. BA Input Bank Address:BA is not simply BA.BA specifies the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands CK (CK0 & CK1) DQ0-63 DQMB0-7 Vdd,Vss Data In and Data out are referenced to the rising edge of Input/Output CK Input Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle. Power Supply Power Supply for the memory mounted module. SLA Input Serial clock for serial PD SDA Output Serial data for serial PD SA0-3 Input MIT-DS-0019-0.4 Address input for serial PD MITSUBISHI ELECTRIC ( 5 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM BASIC FUNCTIONS The MH2S64CZTJ/CWZTJ provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table. CK /S Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Refresh Option @refresh command Precharge Option @precharge or read/write command A10 define basic commands Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 6 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM COMMAND TRUTH TABLE COMMAND MNEMONIC CK n-1 CK n /S Deselect No Operation DESEL NOP H H X X H L X H Row Adress Entry & Bank Activate ACT H X L Single Bank Precharge Precharge All Bank PRE PREA H H X X Column Address Entry & Write WRITE H Column Address Entry & Write with AutoPrecharge WRITEA Column Address Entry & Read /RAS /CAS /WE BA A10 A0-9 X H X H X X X X X X L H H V V V L L L L H H L L V V L H X X X L LH H L V L V H X L H L L V H V READ H X L H L H V L V Column Address Entry & Read with Auto Precharge READA H X L H L H V H V Auto-Refresh Self-Refresh Entry Self-Refresh Exit REFA REFS REFSX Burst Terminate Mode Register Set TERM MRS H H L L H H H L H H X X L L H L L L HL L LX H H L L L X H H L H H X H L L X X X X X L X X X X X L X X X X X V*1 H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 7 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE /S IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT L L H L L L L H BA,A10 X PRE/PREA REFA ROW ACTIVE READ /RAS /CAS /WE Address Command Current State Op-Code, Action READ/WRITE ILLEGAL*2 NOP*4 Auto-Refresh*5 L L L L H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST NOP L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X Mode-Add Op-Code, L L L L H X X X X L H H H L H H L Mode-Add MRS Bank Active,Latch RA READ/READA Mode Register Set*5 Begin Read,Latch CA, Determine Auto-Precharge WRITE/ Begin Write,Latch CA, WRITEA Determine Auto-Precharge REFA ILLEGAL MRS ILLEGAL DESEL NOP(Continue Burst to END) X NOP NOP(Continue Burst to END) BA TBST Terminate Burst Terminate Burst,Latch CA, L H L H BA,CA,A10 READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L H L L BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 MIT-DS-0019-0.4 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L Op-Code, Mode-Add Bank Active/ILLEGAL*2 Terminate Burst,Precharge REFA ILLEGAL MRS ILLEGAL MITSUBISHI ELECTRIC ( 8 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE(continued) Current State WRITE READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE MIT-DS-0019-0.4 /S H /RAS /CAS X X /WE Address X X L L H H H H H L X BA L H L H BA,CA,A10 Command DESEL Action NOP(Continue Burst to END) NOP TBST NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin Read,Determine Auto- WRITE/ L H L L BA,CA,A10 L L H H BA,RA ACT L L L L H L L H BA,A10 X PRE/PREA REFA L L L L H L L L X H H H X H H L X H L H Op-Code, Mode-Add X X BA BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA WRITEA ACT L L H L BA,A10 PRE/PREA L L L H L L L L H L L L X H H H X H H L X H L H X Op-Code, Mode-Add X X L H L L BA,CA,A10 L L L L L L H H L H L H BA,RA L L L L BA BA,CA,A10 BA,A10 X Op-Code, Mode-Add WRITEA MRS DESEL NOP TBST READ/READA WRITE/ Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 REFA ILLEGAL MRS ILLEGAL DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS MITSUBISHI ELECTRIC ( 9 / 45 ) NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE(continued) /S PRE - H X X X X DESEL NOP(Idle after tRP) CHARGING L H H H X NOP NOP(Idle after tRP) L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L ROW H X X X X DESEL NOP(Row Active after tRCD ACTIVATING L H H H X NOP NOP(Row Active after tRCD L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L WRITE RE- H X X X X DESEL NOP COVERING L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L MIT-DS-0019-0.4 /RAS /CAS /WE Address Command Current State Action READ/WRITE ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) REFA ILLEGAL MRS ILLEGAL Op-Code, Mode-Add READ/WRITE ILLEGAL*2 REFA ILLEGAL MRS ILLEGAL Op-Code, Mode-Add READ/WRITE ILLEGAL*2 REFA ILLEGAL MRS ILLEGAL Op-Code, Mode-Add MITSUBISHI ELECTRIC ( 10 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE(continued) Current State /S /RAS /CAS /WE Address RE- H X X X X DESEL NOP(Idle after tRC) FRESHING L H H H X NOP NOP(Idle after tRC) L H H L BA TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL MODE H X X X X DESEL NOP(Idle after tRSC) REGISTER L H H H X NOP NOP(Idle after tRSC) SETTING L H H L BA TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL Op-Code, Mode-Add Op-Code, Mode-Add Command Action READ/WRITE ILLEGAL READ/WRITE ILLEGAL ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed. MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 11 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE FOR CKE Current State CK n-1 CK n /S SELF - H X X X REFRESH*1 L H H L H L /RAS /CAS Action /WE Add X X X INVALID X X X X Exit Self-Refresh(Idle after tRC) L H H H X Exit Self-Refresh(Idle after tRC) H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh) POWER H X X X X X X INVALID DOWN L H X X X X X Exit Power Down to Idle L L X X X X X NOP(Maintain Self-Refresh) ALL BANKS H H X X X X X Refer to Function Truth Table IDLE*2 H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State = Power Down ANY STATE H H X X X X X Refer to Function Truth Table other than H L X X X X X Begin CK0 Suspend at Next Cycle*3 listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3 L L X X X X X Maintain CK0 Suspend ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only form the All banks idle State. 3. Must be legal command. MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 12 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM SIMPLIFIED STATE DIAGRAM SELF REFRESH REFS REFSX MRS MODE REGISTER SET REFA AUTO REFRESH IDLE CKEL CKEH CLK SUSPEND ACT POWER DOWN CKEL CKEH ROW ACTIVE WRITE READA WRITEA CKEL WRITE SUSPEND READ READ WRITE WRITE CKEL READ CKEH CKEH WRITEA READA WRITEA READA CKEL WRITEA SUSPEND POWER APPLIED READ SUSPEND CKEL PRE WRITEA CKEH POWER ON PRE PRE READA PRE CKEH READA SUSPEND PRE CHARGE Automatic Sequence Command Sequence MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 13 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs. 2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. CK /S BA A10 A9 A8 A7 0 0 0 A6 A5 A4 A3 A2 A1 A0 /RAS /CAS 0 0 LTMODE BT BL /WE BA, A10 -A0 LATENCY MODE CL 000 001 010 011 100 101 110 111 /CAS LATENCY R 1 2 3 4 R R R BURST LENGTH BURST TYPE BL 000 001 010 011 100 101 110 111 0 1 V BT= 0 1 2 4 8 R R R R BT= 1 1 2 4 8 R R R R SEQUENTIAL INTERLEAVED R:Reserved for Future Use MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 14 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM CK Command Read Write Y Y Address Q0 DQ CL= 3 BL= 4 /CAS Latency Q1 Q2 Q3 D0 Burst Length D1 D2 D3 Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 Sequential Interleaved 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 2 - - 1 MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 15 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM OPERATION DESCRIPTION BANK ACTIVATE The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank address(BA). A row is indicated by the row address A10-0. The minimum activation interval between one bank and the other bank is tRRD. PRECHARGE The PRE command deactivates indicated by BA. When both banks are active, the precharge all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued. Bank Activation and Precharge All (BL=4, CL=3) CK Command ACT ACT READ tRRD A0-9 Xa PRE ACT tRAS Xb Y tRP Xb tRCD A10 Xa Xb 0 BA 0 1 0 DQ 1 Xb 1 Qa0 Qa1 Qa2 Qa3 Precharge all READ After tRCD from the bank activation, a READ command can be issued. 1st output date is available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when the Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8) by interleaving the dual banks. When A10 is high at a READ command, the auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge start timing depends on /CAD Latency. The next ACT command can be issued after tRP from the internal precharge timing. MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 16 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM Dual Bank Interleaving READ (BL=4, CL=3) CK Command ACT A0-9 Xa Y Xb Y A10 Xa 0 Xb 0 0 BA 0 0 1 1 0 Qa1 Qa2 READ ACT READ PRE tRCD DQ Qa0 /CAS latency Qa3 Qb0 Qb1 Qb2 Burst Length READ with Auto-Precharge (BL=4, CL=3) CK Command ACT A0-9 Xa Y Xa A10 Xa 1 Xa BA 0 0 0 READ ACT tRCD tRP DQ Qa0 Qa1 Qa2 Qa3 Internal precharge begins READ Auto-Precharge Timing (BL=4) CK Command CL=4 DQ CL=3 DQ CL=2 DQ ACT READ Qa0 Qa0 Qa1 Qa2 Qa0 Qa1 Qa2 Qa3 Qa1 Qa2 Qa3 Qa3 Internal Precharge Start Timing MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 17 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous input data (in case of BL=8) by interleaving the dual banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. Dual Bank Interleaving WRITE (BL=4) CK Command ACT A0-9 Xa Write ACT tRCD Write PRE tRCD Y Y Xb tWR A10 Xa 0 Xb 0 0 BA 0 0 1 1 0 Da0 Da1 Db0 Db1 DQ Da2 Da3 Db2 Db3 Burst Length WRITE with Auto-Precharge (BL=4) CK Command ACT A0-9 Xa Y Xa A10 Xa 1 Xa BA 0 0 Write ACT tRCD tRP 0 tWR DQ Da0 Da1 Da2 Da3 Internal precharge begins MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 18 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM BURST INTERRUPTION [ Read Interrupted by Read ] Burst read option can be interrupted by new read of the same or the other bank. MH4S64CTJ allows random column access. READ to READ interval is minimum 1 CK Read Interrupted by Read (BL=4, CL=3) CK Command READ READ READ READ A0-9 Yi Yj Yk Yl A10 0 0 0 0 BA 0 0 1 0 DQ Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of the same or the other bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3) CK Command READ Write A0-9 Yi Yj A10 0 0 BA 0 0 DQMB0-7 Q D Qai0 Daj0 Daj1 Daj2 DQM control MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 19 / 45 ) Daj3 Write control Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same or the other bank. Read to PRE interval is minimum 1 CK. A PRE command disables the data output, depending on the /CAS Latency. The figure below shows examples, when the dataout is terminated. Read Interrupted by Precharge (BL=4) CK Command READ PRE DQ Q0 Q1 Q0 Q1 Q2 Q3 CL=4 Command READ PRE DQ Command READ PRE DQ Q0 Q1 Q0 Q1 Q2 Q3 CL=3 Command READ PRE DQ Command PRE READ DQ Q0 Q1 Q2 Q3 CL=2 Command READ PRE DQ Comman d Q0 REA D DQ CL= 1 Comman d DQ MIT-DS-0019-0.4 Q1 PRE Q 0 REA D Q 1 Q 2 Q 3 PR E Q 0 Q 1 MITSUBISHI ELECTRIC ( 20 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM [ Read Interrupted by Burst Terminate ] Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. READ to TERM interval is minimum 1 CK. The figure below shows examples, when the dataout is terminated. Read Interrupted by Burst Terminate (BL=4) CK Command READ TERM DQ Command Q0 READ Q1 Q2 Q1 Q2 Q3 TERM CL=3 DQ Command Q0 READ TERM DQ Command Q0 TERM READ DQ Command Q0 READ Q1 Q2 Q3 TERM CL=2 DQ Command Q0 Q0 REA D DQ CL= 1 Comman d DQ MIT-DS-0019-0.4 Q2 READ TERM DQ Comman d Q1 TERM Q 0 REA D Q 1 Q 2 Q 3 TERM Q 0 MITSUBISHI ELECTRIC ( 21 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CK. Write Interrupted by Write (BL=4) CK Command Write Write Write Write A0-9 Yi Yj Yk Yl A10 0 0 0 0 BA 0 0 1 0 DQ Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3) CK Command Write READ Write READ A0-9 Yi Yj Yk Yl A10 0 0 0 0 BA 0 0 0 1 DQMB0-7 DQ MIT-DS-0019-0.4 Dai0 Qaj0 Qaj1 MITSUBISHI ELECTRIC ( 22 / 45 ) Dak0 Dak1 Qbl0 Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Because the write recovery time(tWR) is required between the last input data and the next PRE, 3rd data should be masked with DQMB0-7 shown as below. Write Interrupted by Precharge (BL=4) CK Command Write PRE tWR ACT tRP A0-9 Yi A10 0 0 Xb BA 0 0 0 Xb DQMB0-7 DQ Dai0 Dai1 This data should be masked to satisfy tWR requirement. [ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. The figure below shows the case 3 words of data are written. Random column access is allowed. WRITE to TERM interval is minimum 1 CK. Write Interrupted by Burst Terminate (BL=4) CK Command Write A0-9 Yi A10 0 BA 0 TERM DQMB0-7 DQ MIT-DS-0019-0.4 Dai0 Dai1 Dai2 MITSUBISHI ELECTRIC ( 23 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L, /WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA cycle within 64ms refresh 16Mbit memory cells. The auto-refresh is performed on each bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks must be in the idle state. Additional commands must not be supplied to the device before tRC from the REFA command. Auto-Refresh CK /S NOP or DESLECT /RAS /CAS /WE CKE minimum tRC A0-10 BA Auto Refresh on Bank 0 MIT-DS-0019-0.4 Auto Refresh on Bank 1 MITSUBISHI ELECTRIC ( 24 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L, /WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is kept low.During the self-refresh mode, CKE is asynchronous and the only enabled input (but asynchronous), all other inputs including CK0 are disabled and ignored, and power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CK0 inputs, asserting DESEL or NOP command and then asserting CKE(REFSX). After tRC from REFSX both banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted till then. Self-Refresh CK Stable CK /S NOP /RAS /CAS /WE CKE new command A0-10 X BA 0 Self Refresh Entry MIT-DS-0019-0.4 Self Refresh Exit MITSUBISHI ELECTRIC ( 25 / 45 ) minimum tRC for recovery Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored. CK (ext.CLK) CKE int.CLK Power Down by CKE CK Standby Power Down CKE Command PRE NOP NOP NOP NOP NOP NOP NOP Active Power Down CKE Command NOP NOP NOP NOP NOP NOP NOP ACT DQ Suspend by CKE CK CKE Command DQ MIT-DS-0019-0.4 Write D0 READ D1 D2 D3 MITSUBISHI ELECTRIC ( 26 / 45 ) Q0 Q1 Q2 Q3 Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM DQM CONTROL DQMB0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7 to write mask latency is 0. During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z latency is 2. DQM Function CK Command READ Write DQMB0-7 DQ D0 D2 D3 Q0 masked by DQM=H MIT-DS-0019-0.4 Q1 Q3 disabled by DQM=H MITSUBISHI ELECTRIC ( 27 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Condition Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V VI Input Voltage with respect to Vss -0.5 ~ 4.6 V VO Output Voltage with respect to Vss -0.5 ~ 4.6 V IO Output Current 50 mA Pd Power Dissipation 8 W Topr Operating Temperature 0 ~ 70 °C Tstg Storage Temperature -40 ~ 100 °C Ta=25°C RECOMMENDED OPERATING CONDITION (Ta=0 ~ 70°C, unless otherwise noted) Limits Parameter Symbol Min. Typ. Max. Unit Vdd Supply Voltage 3.0 3.3 3.6 V Vss Supply Voltage 0 0 0 V VIH High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 2.0 Vdd+0.3 V -0.3 0.8 V VIL CAPACITANCE (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter Test Condition Limits(max.) Unit CI(A) Input Capacitance, address pin VI = Vss 65 pF CI(C) Input Capacitance, control pin 65 pF CI(K) Input Capacitance, CK0 pin 65 pF CI/O Input Capacitance, I/O pin 15 pF MIT-DS-0019-0.4 f=1MHz Vi=25mVrms MITSUBISHI ELECTRIC ( 28 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol Icc1s Icc1d Icc2h Icc2l Icc3 Icc4 Icc5 Icc6 Test Condition Parameter operating current, single bank operating current, dual bank standby current, CKE=H standby current, CKE=L active standby current burst current auto-refresh current self-refresh current tRC=min.tCLK=min, BL=1, CL=3 tRC=min.tCLK=min, BL=1, CL=3 both banks idle, tCLK=min, CKE=H both banks idle, tCLK=min, CKE=L both banks active, tCLK=min, CKE=H tCLK=min, BL=4, CL=3, 1 bank idle(discerte) tRC=min, tCLK=min CKE <0.2V Limits(max) Unit -15 -1539 mA 560 560 440 mA 800 800 640 mA 144 144 128 mA 16 16 16 mA 280 280 240 mA 480 480 400 mA 480 480 400 mA 8 8 8 -12 AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol VOH(DC) VOL(DC) VOH(AC IOZ )VOL(AC) Ii IOZ Ii MIT-DS-0019-0.4 Parameter Limits Min. Max. IOH=-2mA 2.4 IOL=2mA 0.4 CL=50pF, Q floating VO=0 ~ Vdd -10 2 10 IOH=-2mA -80 0.8 CL=50pF, VIH=0 ~ Vdd+0.3V IOL=2mA 80 -1 1 Q floating VO=0 Å` Vdd 0 0 VIH=0 Å` Vdd+0.3V -8 8 0 0 Test Condition High-Level Output Voltage(DC) Low-Level Output Voltage(DC) High-Level Off-stare Output Output Current Voltage(AC) Input Current Low-Level Output Voltage(AC) Off-stare Output Current Input Current MITSUBISHI ELECTRIC ( 29 / 45 ) Unit V V uA V uA V ÉA É A Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM AC TIMING REQUIREMENTS (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V Symbol Parameter CL=1 CL=2 CL=3 tCLK CK cycle time tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tRSC tPDE tREF CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Mode Register Set Cycle time Power Down Exit time Refresh Interval time CK Limits -12 -15 -1539 Unit Min. Max. Min. Max. Min. Max. ns 30 30 30 ns 15 15 20 ns 12 12 15 4 4 4 ns 4 4 4 ns 1 10 1 10 1 10 ns 3 3 3 ns 1 1 1.5 ns 100 100 120 ns 30 30 30 ns 70 10000 70 10000 80 10000 ns 30 30 40 ns 12 12 15 ns 24 24 30 ns 24 24 30 ns 12 12 15 ns 65.6 65.6 65.6 ms 1.4V Any AC timing is referenced to the input Signal 1.4V signal crossing through 1.4V. MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 30 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM SWITCHING CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter tAC tCAC tRAC tOH tOLZ tOHZ -12 Min. Max. 27 9.5 8 24.5 54.5 CL=1 CL=2 CL=3 Access time from CK Column Access Time Row Access Time Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK Output Load Condition Uni -1539 Min. Max. t 30 ns 12 ns ns 9 30 ns 60 ns 3 3 3 ns 0 0 0 ns 3 VTT=1.4V Limits -15 Min. Max. 27 9.5 8 24.5 54.5 8 3 8 CK 3 10 ns 1.4V 50Ω DQ 1.4V VOUT 50pF Output Timing Measurement Reference Point CK 1.4V DQ 1.4V tAC MIT-DS-0019-0.4 tOH tOHZ MITSUBISHI ELECTRIC ( 31 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM WRITE CYCLE (single bank) BL=4 CK tRC /S tRAS tRP /RAS tRCD /CAS /WE CKE DQMB 0-7 A0-9 X A10 X Y X X BA tWR DQ MIT-DS-0019-0.4 D D D D MITSUBISHI ELECTRIC ( 32 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM BL=4 WRITE CYCLE (dual bank) CK tRC /S tRAS tRP tRAS tRRD /RAS tRCD tRCD /CAS /WE CKE DQMB 0-7 A0-9 Xa A10 Xa Y Xb Y Xb BA tWR tWR DQ MIT-DS-0019-0.4 Da Da Da Da Db Db MITSUBISHI ELECTRIC ( 33 / 45 ) Db Db Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM READ CYCLE (single bank) BL=4, CL=3 CK tRC /S tRAS tRP /RAS tRCD /CAS /WE CKE DQMB 0-7 A0-9 X A10 X Y X X BA DQ tCAC Q Q Q Q tRAC MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 34 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM READ CYCLE (dual bank) BL=4, CL=3 CK tRC /S tRAS tRP tRRD tRAS /RAS tRCD tRCD /CAS /WE CKE DQMB 0-7 A0-9 Xa A10 Xa Y Xb Y Xa Xb Xa BA Qa DQ tRAC MIT-DS-0019-0.4 Qa Qa tCAC Qa Qb Qb Qb Qb tCAC tRAC MITSUBISHI ELECTRIC ( 35 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM BL=4, CL=3 WRITE to READ (single bank) CK /S tRAS /RAS tRCD /CAS /WE CKE DQMB 0-7 A0-9 X A10 X Y Y BA DQ D D D D Q Q Q Q tCAC MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 36 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM WRITE to READ (dual bank) BL=4, CL=3 CK tRC /S tRAS tRP tRRD tRAS /RAS tRCD tRCD /CAS /WE CKE DQMB 0-7 A0-9 Xa A10 Xa Y Y Xb Xa Xa Xb BA tWR DQ Da Da Da Qb Da Qb Qb Qb tCAC MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 37 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM BL=4, CL=3 READ to WRITE (single bank) CK /S tRAS /RAS tRCD /CAS /WE CKE for output diable DQMB 0-7 A0-9 X A10 X Y Y BA tWR Q DQ Q D D D D tCAC tRAC MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 38 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM BL=4, CL=3 READ to WRITE (dual bank) CK tRC /S tRAS tRP tRAS tRRD /RAS tRCD tRCD /CAS /WE CKE for output disable DQMB 0-7 A0-9 Xa A1 0 Xa Y Y Xb Xa Xb Xa BA tWR Qa DQ Qa Db Db Db Db tCAC tRAC MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 39 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM WRITE with AUTO-PRECHARGE BL=4 CK tRC /S tWR + tRP /RAS tRCD /CAS /WE CKE DQMB 0-7 A0-9 X A10 X Y X X BA DQ D D D D internal precharge starts this timing depends on BL MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 40 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM READ with AUTO-PRECHARGE BL=4, CL=3 CK tRC /S tRP /RAS tRCD /CAS /WE CKE DQMB 0-7 A0-9 X A10 X Y X X BA Q DQ Q Q Q tCAC tRAC internal precharge starts @CL=3, BL=4 this timing depends on CL and BL MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 41 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM AUTO-REFRESH CK tRC /S tRP /RAS /CAS /WE CKE DQMB 0-7 A0-9 A10 BA DQ if any bank is active, it must be precharged MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 42 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM SELF-REFRESH ENTRY CK /S tRP /RAS /CAS /WE CKE DQMB 0-7 A0-9 A10 BA DQ if any bank is active, it must be precharged MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 43 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM SELF-REFRESH EXIT CK /S NOP or DESEL /RAS /CAS /WE tRC CKE DQMB 0-7 A0-9 X A10 X BA DQ internal CLK re-start MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 44 / 45 ) Oct.28.1996 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH2S64CZTJ/CWZTJ-12,-15,-1539 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM MODE REGISTER SET BL=4, CL=3 CK /S tRSC tRP tRCD /RAS /CAS /WE CKE DQMB 0-7 A0-9 A10 mode X Y X BA Q DQ Q Q tCAC tRAC if any bank is active, it must be precharged MIT-DS-0019-0.4 MITSUBISHI ELECTRIC ( 45 / 45 ) Oct.28.1996