ICST ICS8442 700mhz, crystal oscillator-to-differential lvds frequency synthesizer Datasheet

ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8442 is a general purpose, dual output
Crystal-to-Differential LVDS High Frequency
HiPerClockS™
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8442 has a selectable TEST_CLK
or crystal input. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to LVDS levels. The
VCO operates at a frequency range of 250MHz to 700MHz. The
VCO frequency is programmed in steps equal to the value of
the input reference or crystal frequency. The VCO and output
frequency can be programmed using the serial or parallel interface to the configuration logic. The low phase noise characteristics of the ICS8442 makes it an ideal clock source for Gigabit
Ethernet and Sonet applications.
• Dual differential LVDS outputs
ICS
• Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
• Output frequency range: 31.25MHz to 700MHz
• Crystal input frequency range: 10MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 2.7ps (typical)
• Cycle-to-cycle jitter: 18ps (typical)
• 3.3V supply voltage
• 0°C to 85°C ambient operating temperature
• “Lead-Free” package available
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL2
nP_LOAD
M0
M1
M2
M3
M4
XTAL_SEL
TEST_CLK
VCO_SEL
VCO_SEL
0
32 31 30 29 28 27 26 25
XTAL1
OSC
1
M5
1
24
XTAL1
M6
2
23
TEST_CLK
M7
3
22
XTAL_SEL
M8
4
21
VDDA
N0
5
20
S_LOAD
N1
6
19
S_DATA
÷2
nc
7
18
S_CLOCK
÷4
GND
8
17
MR
XTAL2
PLL
÷1
PHASE DETECTOR
MR
VCO
÷M
1
GND
nFOUT0
FOUT0
VDD
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M0:M8
N0:N1
8442AY
nFOUT1
TEST
FOUT1
CONFIGURATION
INTERFACE
LOGIC
9 10 11 12 13 14 15 16
VDD
FOUT0
nFOUT0
FOUT1
nFOUT1
÷8
TEST
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
0
ICS8442
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1
REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
cific default state that will automatically occur during powerup. The TEST output is LOW when operating in the parallel
input mode. The relationship between the VCO frequency, the
crystal frequency and the M divider is defined as follows:
fVCO = fxtal x M
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8442 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10 ≤ M ≤ 28. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVDS output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8442 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a spe-
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS FOUT
SERIAL LOADING
S_CLOCK
T1
S_DATA
t
S
S_LOAD
t
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
Time
H
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8442AY
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REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
2, 3, 4,
28, 29,
30, 31, 32
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
Input
Type
Description
Input
M divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
Pulldown
7
nc
Unused
8, 16
GND
Power
9
TEST
Output
Pullup
Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
No connect.
10, 13
VDD
Power
Power supply ground.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
Core supply pins.
11, 12
FOUT1, nFOUT1
Output
Differential output for the synthesizer. LVDS interface levels.
14, 15
FOUT0, nFOUT0
Output
17
MR
Input
Pulldown
18
S_CLOCK
Input
Pulldown
19
S_DATA
Input
Pulldown
20
S_LOAD
Input
Pulldown
21
VDDA
Power
22
XTAL_SEL
Input
Pullup
Differential output for the synthesizer. LVDS interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inver ted
outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Asser tion of MR does not effect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between cr ystal oscillator or test inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects TEST_CLK when
LOW. LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Pulldown
24, 25
XTAL1, XTAL2
Input
26
nP_LOAD
Input
27
VCO_SEL
Input
Cr ystal oscillator interface. XTAL1 is the input XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
8442AY
Test Conditions
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3
Minimum
Typical
Maximum
Units
REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
TABLE 3A. PARALLEL
AND
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. When HIGH, forces the outputs to a differential
LOW state (FOUTx = LOW and nFOUTx = HIGH), but
does not effect loaded M, N, and T values.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
↑
Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
10
0
0
0
0
0
1
0
1
0
11
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
VCO Frequency
(MHz)
M Divide
250
275
•
•
•
•
•
•
•
•
•
•
•
•
650
26
0
0
0
0
1
1
0
1
0
675
27
0
0
0
0
1
1
0
1
700
28
0
0
0
0
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency
of 25MHz.
1
0
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N1
N0
N Divider Value
Output Frequency (MHz)
Minimum
Maximum
0
0
1
250
700
0
1
2
125
350
1
0
4
62.5
175
1
1
8
31.25
87.5
8442AY
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REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
155
mA
IDDA
Analog Supply Current
20
mA
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
VIH
VIL
IIH
IIL
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
Test Conditions
M0-M8, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD,
XTAL_SEL, VCO_SEL
TEST_CLK
M0-M8, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD,
XTAL_SEL, VCO_SEL
TEST_CLK
M0-M4, M6-M8, N0, N1, MR,
nP_LOAD, S_CLOCK, S_DATA,
S_LOAD,
M5, XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
nP_LOAD, S_CLOCK, S_DATA,
S_LOAD,
VDD = 3.465V,
VIN = 0V
VDD = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
Minimum Typical
-5
µA
-150
Output
TEST; NOTE 1
2.6
High Voltage
Output
TEST; NOTE 1
VOL
Low Voltage
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
V
VOH
8442AY
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5
0.5
V
REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Test Conditions
∆ VOD
VOD Magnitude Change
VOS
Offset Voltage
∆ VOS
VOS Magnitude Change
Minimum
Typical
Maximum
Units
250
450
600
mV
50
mV
1.125
1.4
1.6
V
50
mV
Maximum
Units
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
fIN
Test Conditions
Input Frequency
Minimum
Typical
TEST_CLK; NOTE 1
10
25
MHz
XTAL1, XTAL2; NOTE 1
10
25
MHz
S_CLOCK
50
MHz
NOTE 1: For the input cr ystal and TEST_CLK frequency range the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 10MHz valid values of M are 25 ≤ M ≤ 70. Using the
maximum frequency of 25MHz valid values of M are 10 ≤ M ≤ 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
10
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
TABLE 7. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
FOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
tjit(per)
Period Jitter, RMS; NOTE 1, 3
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
Setup Time
tH
Hold Time
Test Conditions
Minimum
Typical
31.25
Maximum
Units
700
MHz
ij 350MHz
18
28
ps
ƒ < 350MHz
27
45
ps
2.7
7
ps
15
ps
650
ps
20% to 80%
150
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
odc
Output Duty Cycle
N>1
48
52
tPW
Output Pulse Width
N=1
tPeriod/2 - 150
tPeriod/2 + 150
ps
1
ms
PLL Lock Time
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8442AY
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%
REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD
out
SCOPE
Qx
LVDS
➤
DC Input
3.3V±5%
Power Supply
Float GND
+
-
LVDS
➤
out
nQx
VOS/∆ VOS
➤
VOS / ∆VOS SETUP
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nFOUTx
LVDS
100
FOUTx
➤
VOD/∆ VOD
out
nFOUTy
➤
DC Input
➤
out
FOUTy
t sk(o)
VOD / ∆VOD SETUP
OUTPUT SKEW
VOH
nFOUT0,
nFOUT1
VREF
FOUT0,
FOUT1
n
➤
tcycle
➤
tcycle n+1
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
➤
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
Cycle-to-Cycle Jitter
Period Jitter
nFOUT0, nFOUT1
80%
FOUT0, FOUT1
80%
VSW I N G
Pulse Width
t
odc =
Clock
Outputs
PERIOD
20%
20%
t PW
tR
tF
t PERIOD
odc & tPERIOD
8442AY
OUTPUT RISE/FALL TIME
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REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below lists the common fre-
quencies used as well as the settings for the ICS8442 to generate the appropriate frequency.
Table 8. Common SANs Application Frequencies
Interconnect Technology
Reference Frequency to SERDES
(MHz)
Crystal Frequency
(MHz)
1.25 GHz
125, 250, 156.25
25, 19.53125
FC1 1.0625 GHz
FC2 2.1250 GHz
106.25, 53.125, 132.8125
16.6015625, 25
2.5 GHz
125, 250
25
Gigabit Ethernet
Fibre Channel
Clock Rate
Infiniband
Table 9. Configuration Details for SANs Applications
Interconnect
Technology
Crystal Frequency
(MHz)
ICS8442
Output Frequency
to SERDES
(MHz)
25
125
0
0
0
0
1
0
1
0
25
250
0
0
0
0
1
0
1
25
156.25
0
0
0
0
1
1
19.53125
156.25
0
0
0
1
0
25
53.125
0
0
0
0
25
106.25
0
0
0
16.6015625
132.8125
0
0
25
125
0
25
250
0
ICS8442
M & N Settings
M8 M7 M6 M5 M4 M3 M2
M1 M0
N1
N0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
1
Gigabit Ethernet
Fiber Channel 1
Fiber Channel 2
Infiniband
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8442 provides separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. V DD and V DDA , should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply
isolation is required. Figure 2 illustrates how a 10Ω along
|with a 10µF and a .01µF bypass capacitor should be
connected to each VDDA pin.
8442AY
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
FIGURE 2. POWER SUPPLY FILTERING
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REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS8442 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3. Typical results using parallel 18pF crystals are shown
in Table 10.
25
XTAL2
C1
18p
X1
18pF Parallel Crystal
24
XTAL1
C2
22p
ICS8442
Figure 3. CRYSTAL INPUt INTERFACE
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
3.3V
Zo = 50 Ohm
LVDS_DRIVER
CLK
R1
100
nCLK
Zo = 50 Ohm
HiPerClockS
Ω Differential Transmission Line
100Ω
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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REV. C JULY 8, 2004
ICS8442
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Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS8442 layout example used in this layout
guideline is shown in Figure 5A. The ICS8442 recommended PCB
board layout for this example is shown in Figure 5B. This layout
example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stack
up of the P.C. board.
C1
C2
M5
M6
M7
M8
N0
N1
nc
GND
VDD
ICS8442
C14
0.1u
XTAL1
T_CLK
nXTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
VDD
24
23
22
21
20
19
18
17
R7
10
VDDA
C11
C16
10u
0.01u
TEST
VDD
FOUT1
nFOUT1
VDD
FOUT0
nFOUT0
GND
1
2
3
4
5
6
7
8
9
10
11
12
VDD
13
FOUT0
14
nFOUT0 15
16
U1
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
XTAL2
32
31
30
29
28
27
26
25
X1
Zo = 50 Ohm
+
TL1
FOUT1
nFOUT1
C15
0.1u
R1
100
Zo = 50 Ohm
-
TL1N
Zo = 50 Ohm
+
TL2
R2
100
Zo = 50 Ohm
-
TL2N
FIGURE 5A. RECOMMENDED SCHEMATIC LAYOUT
8442AY
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10
REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER
AND
traces should be routed first and should be locked prior to routing
other signal traces.
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
If VDDA shares the same power supply with VDD, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VDDA as possible.
CLOCK TRACES
AND
• Make sure no other signal trace is routed between the
clock trace pair.
TERMINATION
The matching termination resistors R1 and R2 should be located
as close to the receiver input pins as possible. Other termination
scheme can also be used but is not shown in this example.
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location. While routing the traces, the clock signal
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
GND
C1
C2
VDD
X1
VIA
U1
PIN 1
C16
C11
VDDA
TL1N
R7
C14
TL1
Close to the input
pins of the
receiver
R1
Same requirement fo
FOUT1/nFOUT1
TL1
C15
TL1N
FIGURE 5B. PCB BOARD LAYOUT
8442AY
For FOUT0/n FOUT0
output TL1, TL1N are
50 Ohm traces and
equal length
FOR
ICS8442
www.icst.com/products/hiperclocks.html
11
REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 10. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8442 is: 3662
8442AY
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12
REV. C JULY 8, 2004
ICS8442
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
FOR
32 LEAD LQFP
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8442AY
www.icst.com/products/hiperclocks.html
13
REV. C JULY 8, 2004
Integrated
Circuit
Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
TABLE 12. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS8442AY
ICS8442AY
32 Lead LQFP
250 per tray
0°C to 85°C
ICS8442AYT
ICS8442AY
32 Lead LQFP on Tape and Reel
1000
0°C to 85°C
ICS8442AYLF
ICS8442AYLF
32 Lead "Lead-Free" LQFP
250 per tray
0°C to 85°C
ICS8442AYLFT
ICS8442AYLF
32 Lead "Lead-Free" LQFP on Tape and Reel
1000
0°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8442AY
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14
REV. C JULY 8, 2004
Integrated
Circuit
Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
Page
Corrected labels on the Parallel & Serial Load Operations diagram.
Revised MR pin description.
Power Supply table - changed IDD to 155mA max. from 130mA max.,
changed IDDA to 20mA max. from 15mA max.,
and changed IDDO to 55mA max. from 45mA max.
12/18/02
T1
T4A
2
3
5
9
1
Added LVDS Driver Termination Section.
General Description & Features - changed VCO min. from 200MHz to 250MHz
and replaced throughout the datasheet in: (Functional Description pg2,
T3C Program. Output Divider Func. Table pg4, and T5 Input Freq Charac. Table
pg6).
- Features - changed min. Output Frequency Range from 25MHz to 31.25MHz.
3/12/03
T1
3
Pin Descriptions Table - revised XTAL1,XTAL2 pin description.
T2
3
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
T3B
4
Prog. VCO Freq. Func. Table - deleted 200 and 225 rows, does not apply.
5
Power Supply DC Characteristics Table - deleted VDDO & IDDO rows,
does not apply.
A
B
B
C
T7
C
T6
C
T12
8442AY
Description of Change
Date
2/13/03
5/9/03
6
AC Characteristics Table - change FOUT 25MHz min. to 31.25MHz min.
2
6
9
5
14
Revised Parallel & Serial Load Operations diagram.
Crystal Characteristics Table - changed ESR from 70Ω max. to 50Ω max.
Deleted Table 10, Typical Results of Crystal Input Interface Frequency Fine Tuning
Absolute Maximum Ratings - updated Outputs rating.
Ordering Information table - added "Lead-Free" par t number.
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15
8/12/03
7/8/04
REV. C JULY 8, 2004