LF PA K 56D BUK9K32-100E Dual N-channel 100 V, 33 mΩ logic level MOSFET 10 December 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 2. Features and benefits • • • • • Dual MOSFET Q101 Compliant Repetitive avalanche rated Suitable for thermally demanding environments due to 175 °C rating True logic level gate with VGS(th) rating of greater than 0.5 V at 175 °C 3. Applications • • • • 12 V, 24 V and 48 V Automotive systems Motors, lamps and solenoid control Transmission control Ultra high performance power switching 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 1 - - 26 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 64 W VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 11 - 26.6 33 mΩ - 11 - nC Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QGD gate-drain charge ID = 5 A; VDS = 80 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 Scan or click this QR code to view the latest information for this product BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 drain1 Simplified outline 8 7 6 Graphic symbol 5 D1 D1 S1 D2 D2 G1 S2 G2 mbk725 1 2 3 4 LFPAK56D (SOT1205) 6. Ordering information Table 3. Ordering information Type number Package BUK9K32-100E Name Description Version LFPAK56D Plastic single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code BUK9K32-100E 93210E 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage RGS = 20 kΩ - 100 V VGS gate-source voltage Tj ≤ 175 °C; DC -10 10 V -15 15 V Tmb = 25 °C; VGS = 5 V; Fig. 1 - 26 A Tmb = 100 °C; VGS = 5 V; Fig. 1 - 19 A Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 106 A Tj ≤ 175 °C; Pulsed ID IDM drain current peak drain current BUK9K32-100E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 [1][2] © NXP N.V. 2013. All rights reserved 2 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET Symbol Parameter Conditions Min Max Unit Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 64 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 26 A - 106 A - 74 mJ Source-drain diode FET1 and FET2 IS source current ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C Avalanche Ruggedness FET1 and FET2 EDS(AL)S non-repetitive drain-source avalanche energy [1] [2] [3] [4] ID (A) ID = 26 A; Vsup ≤ 100 V; VGS = 10 V; [3][4] Tj(init) = 25 °C; Fig. 3 Accumulated Pulse duration up to 50 hours delivers zero defect ppm Significantly longer life times are achieved by lowering Tj and or VGS. Refer to application note AN10273 for further information Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 003aal002 30 03aa16 120 Pder (%) 25 20 80 15 10 40 5 0 Fig. 1. 0 30 60 90 120 150 Tj (°C) Continuous drain current as a function of mounting base temperature BUK9K32-100E Product data sheet 0 180 Fig. 2. 0 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 10 December 2013 50 © NXP N.V. 2013. All rights reserved 3 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET IAL (A) 003aal003 102 10 (1) (2) 1 (3) 10-1 10-3 Fig. 3. 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time ID (A) 003aal004 103 102 Limit RDSon = VDS / ID tp = 10 us 10 100 us 1 1 ms DC 10 ms 100 ms 10-1 10-2 Fig. 4. 1 102 10 VDS (V) 103 Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 2.36 K/W Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 95 - K/W BUK9K32-100E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 4 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET 003aal005 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 10-1 0.1 0.05 0.02 single shot P δ= 10-2 tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 tp T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 90 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.4 1.7 2.1 V 0.5 - - V - - 2.45 V VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 5 A; Tj = 175 °C; - 73.4 91 mΩ VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 11 - 25.6 31 mΩ VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 11 - 26.6 33 mΩ Static characteristics FET1 and FET2 V(BR)DSS VGS(th) Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 9; Fig. 10 IDSS IGSS RDSon RDSon drain leakage current gate leakage current drain-source on-state resistance drain-source on-state resistance Fig. 11; Fig. 12 Dynamic characteristics FET1 and FET2 QG(tot) QGS total gate charge ID = 5 A; VDS = 80 V; VGS = 5 V; - 27.3 - nC gate-source charge Tj = 25 °C; Fig. 13; Fig. 14 - 4.7 - nC BUK9K32-100E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 5 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET Symbol Parameter Conditions Min Typ Max Unit QGD gate-drain charge - 11 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 2377 3168 pF Tj = 25 °C; Fig. 15 Coss output capacitance - 153 184 pF Crss reverse transfer capacitance - 101 139 pF td(on) turn-on delay time VDS = 80 V; RL = 15 Ω; VGS = 5 V; - 12.6 - ns tr rise time RG(ext) = 5 Ω; ID = 5 A; Tj = 25 °C - 22 - ns td(off) turn-off delay time - 39.5 - ns tf fall time - 23.1 - ns Source-drain diode FET1 and FET2 VSD source-drain voltage IS = 5 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.78 1.2 V trr reverse recovery time IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V; - 35.6 - ns Qr recovered charge VDS = 50 V; Tj = 25 °C - 47.3 - nC 003aal007 50 RDSon ID (A) 003aal006 30 10 V 2.6 V VGS = 3 V 25 40 4.5 V 20 30 15 2.4 V 20 10 10 0 Fig. 6. 5 0 2 4 6 8 10 12 14 VGS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values BUK9K32-100E Product data sheet 0 16 2.2 2.2VV 0 0.5 1 1.5 2 2.5 VDS (V) 3 Tj = 25 °C; tp = 300 μs Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 6 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET ID (A) 003aal009 60 50 3 VGS(th) (V) 2.5 40 2 003aah025 max typ 30 1.5 20 1 10 min 0.5 175°C Tj = 25°C 0 Fig. 8. 0 0.8 1.6 2.4 3.2 VGS (V) 0 -60 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 9. 003aah026 10-1 60 120 003aal010 RDSon 10-2 180 Tj (° C) Gate-source threshold voltage as a function of junction temperature 50 ID (A) 10 0 2.4 V 2.6 V 40 min -3 typ max 2.8 V 3V 4.5 V 30 Vgs(V) = 10 V 10-4 20 10-5 10 10-6 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage BUK9K32-100E Product data sheet 0 5 10 15 20 25 ID (A) 30 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 7 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET 003aaj820 3 VDS a ID 2.4 VGS(pl) 1.8 VGS(th) VGS 1.2 QGS1 QGS2 QGS 0.6 QGD QG(tot) 003aaa508 0 -60 0 60 120 Tj ( °C) Fig. 13. Gate charge waveform definitions 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature VGS (V) 003aal011 10 003aal012 104 C (pF) 8 Ciss 103 6 VDS = 14 V 4 80 V Coss Crss 102 2 0 0 10 20 30 40 QG (nC) Fig. 14. Gate-source voltage as a function of gate charge; typical values BUK9K32-100E Product data sheet 10 10-1 50 1 10 VDS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 8 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET IS (A) 003aal013 30 25 20 15 10 175°C Tj = 25°C 5 0 0 0.2 0.4 0.6 0.8 1 VSD (V) 1.2 Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK9K32-100E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 9 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET 11. Package outline Plastic single ended surface mounted package (LFPAK56D); 8 leads E A SOT1205 A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 A max 1.05 nom min mm 5 mm scale Dimensions Unit y C c c1 D(1) D1(1) A1 b b1 0.1 0.50 4.4 0.25 0.30 4.70 0.0 0.35 4.1 0.19 0.24 4.45 4.8 D2 (ref) 3.5 E(1) E1(1) 5.30 1.8 4.95 1.6 E2 0.85 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA w y θ 0.25 0.1 8° 0° sot1205_po European projection Issue date 13-02-19 13-02-21 SOT1205 Fig. 17. Package outline LFPAK56D (SOT1205) BUK9K32-100E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 10 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 11 / 13 BUK9K32-100E NXP Semiconductors Dual N-channel 100 V, 33 mΩ logic level MOSFET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP N.V. 2013. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 December 2013 BUK9K32-100E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 13 / 13