SPANSION MB91F527Y This document states the current technical specifications regarding Datasheet

The following document contains information on Cypress products.
MB91520 Series
32-bit Microcontroller
FR Family FR81S
MB91F527R/U/M/Y *, MB91F528R/U/M/Y *
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.
Publication Number MB91F528_DS705-00016
CONFIDENTIAL
Revision 1.0
Issue Date March 28, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion
data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this
proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing
process that require maintaining efficiency and quality, this document may be revised by subsequent
versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB91F528_DS705-00016-1v0-E, March 28, 2014
CONFIDENTIAL
MB91520 Series
32-bit Microcontroller
FR Family FR81S
MB91F527R/U/M/Y *, MB91F528R/U/M/Y *
Data Sheet (Full Production)
 DESCRIPTION
The MB91520 series is a Spansion 32-bit microcontroller designed for automotive devices. This series
contains the FR81S CPU which is compatible with the FR family.
Note: FR is a line of products of Spansion Inc.
*:This series is a composition of the kind that adds HC/JC/KC/LC/SC/UC/WC/YC to the end of the
above-mentioned each name of articles of presence, According to Presence of sub-clock, CSV initial value and
LVD initial value.
Please see "■ORDERING INFORMATION" for details.
Spansion provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.spansion.com/Support/microcontrollers/Pages/default.aspx
Publication Number MB91F528_DS705-00016
Revision 1.0
Issue Date March 28, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product
qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this
document may be revised by subsequent versions or modifications due to changes in technical specifications.
CONFIDENTIAL
D a t a S h e e t
 FEATURES
 FR81S CPU Core
 32-bit RISC, load/store architecture, 5-stage pipeline
 Maximum operating frequency:
MB91F52xR/MB91F52xU(LQFP): 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied
(PLL clock multiplication system))
MB91F52xR/MB91F52xU(TEQFP): 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied
(PLL clock multiplication system))
MB91F52xM/ MB91F52xY: 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied
(PLL clock multiplication system))
 General-purpose register : 32-bit ×16 sets
 16-bit fixed length instructions (basic instruction), 1 instruction per cycle
 Instructions appropriate to embedded applications
 Memory-to-memory transfer instruction
 Bit processing instruction
 Barrel shift instruction etc.
 High-level language support instructions
 Function entry/exit instructions
 Register content multi-load and store instructions
 Bit search instructions
 Logical 1 detection, 0 detection, and change-point detection
 Branch instructions with delay slot
 Decrease overhead during branch process
 Register interlock function
 Easy assembler writing
 Built-in multiplier and instruction level support
 Signed 32-bit multiplication : 5 cycles
 Signed 16-bit multiplication : 3 cycles
 Interrupt (PC/PS saving)
 6 cycles (16 priority levels)
 The Harvard architecture allows simultaneous execution of program and data access.
 Instruction compatibility with the FR family
 Built-in memory protection function (MPU)
 Eight protection areas can be specified commonly for instructions and the data.
 Control access privilege in both privilege mode and user mode.
 Built-in FPU (floating point arithmetic)
 IEEE754 compliant
 Floating-point register 32-bit × 16 sets
 Peripheral functions
 Clock generation (equipped with SSCG function)
 Main oscillation (4MHz to 16MHz)
 Sub oscillation (32kHz) or no sub oscillation
 PLL multiplication rate : 1 to 20 times for MB91F52xR/MB91F52xU(LQFP)
: 1 to 32 times for MB91F52xR/MB91F52xU(TEQFP)
: 1 to 32 times for MB91F52xM/MB91F52xY
 100 kHz CR oscillator mounted
 Maximum operating frequency:
Peripheral bus clock: 40MHz
External bus clock: 40MHz
 Built-in Program flash capacity
MB91F527 : 1536KB + 64KB
MB91F528 : 2048KB + 64KB
 Built-in Data flash (WorkFlash) 64KB
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 Built-in RAM capacity
 Main RAM
MB91F527 : 192KB
MB91F528 : 192KB + 128KB (128KB located in the AHB area, a penalty given at access)
 Backup RAM 16KB
 General-purpose ports :
MB91F527R/MB91F528R :
115 (none sub oscillation), 113 (with sub oscillation)
MB91F527U/MB91F528U :
147 (none sub oscillation), 145 (with sub oscillation)
MB91F527M/MB91F528M :
177 (none sub oscillation), 175 (with sub oscillation)
MB91F527Y/MB91F528Y
219 (none sub oscillation), 217 (with sub oscillation)
Included I2C pseudo open drain ports : Max. 30
 External bus interface
 22-bit address, 8/16-bit data
 DMA Controller
 Up to 16 channels can be started simultaneously.
 2 transfer factors (Internal peripheral request and software)
 A/D converter (successive approximation type)
 12-bit resolution : Max. 64 channels (32 channels +32 channels)
 Conversion time : 1μs
 D/A converter (R-2R type)
 8-bit resolution : 2 channels
 External interrupt input: Max. 24 channels
 Level ("H" / "L"), or edge detection (rising or falling) supported
 Multi-function serial communication (built-in transmission/reception FIFO memory) : Max. 20 channels
5V tolerant input 8 channels (ch.6, ch.8, ch.9, ch.11, ch.16 to ch.19) CMOS hysteresis input
< UART (Asynchronous serial interface) >
 Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
 Parity or no parity is selectable.
 Built-in dedicated baud rate generator
 The external clock can be used as the transfer clock
 Parity, frame, and overrun error detect functions provided
 DMA transfer support
<CSIO (Synchronous serial interface) >
 Full-duplex double buffering system, 64-byte transmission FIFO, memory, 64-byte reception FIFO
memory
 SPI supported; master and slave systems supported; 5-bit to 16-bit, 20-bit, 24-bit, 32-bit data length
can be set.
 Built-in dedicated baud rate generator (Master operation)
 The external clock can be entered. (Slave operation)
 Overrun error detection function is provided
 DMA transfer support
 Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
 Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
 LIN protocol revision 2.1 supported
 Master and slave systems supported
 Framing error and overrun error detection
 LIN synch break generation and detection; LIN synch delimiter generation
 Built-in dedicated baud rate generator
 The external clock can be adjusted by the reload counter
 DMA transfer support
 Hardware assist function
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
3
D a t a S h e e t



















< I 2C >
 10 channels (ch.3, ch.4, ch.12 to ch.19) Standard mode / High-speed mode supported
 5 channels (ch.5 to ch.8, ch.11) Standard mode supported
 Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
 Standard mode (Max. 100kbps) / High-speed mode (Max. 400kbps) supported
 DMA transfer supported (for transmission only)
CAN : 6 channels
 Transfer speed : Up to 1Mbps
 128-transmission/reception message buffering : 6 channels
FlexRay controller: 1 unit (ch.A/ch.B)
 FlexRay specification version 2.1 supported
 Max. 128-message buffer configuration
 8KB message RAM
 Variable-length message buffer configuration
 Each message buffer can be configured as a part of a reception buffer, transmission buffer, or
reception FIFO.
 Host access to message buffers through input and output buffers
 Filtering the slot counter, cycle counter, and channels
 Maskable interrupts
PPG : 16-bit × Max. 88 channels
 LED drive output 4 channels (ch.11 to ch.14)
Reload timer : 16-bit × 8 channels
Free-run timer :
16-bit × 3 channels
32-bit × Max. 8 channels
Input capture :
16-bit × 4 channels (linked to the free-run timer)
32-bit × Max. 8 channels (linked to the free-run timer)
Output compare :
16-bit × 6 channels (linked to the free-run timer)
32-bit × Max. 8 channels (linked to the free-run timer)
Wave generator : 6 channels
U/D counter:
 8/16-bit up/down counter × Max. 4 channels
Real-time clock (RTC) (for day, hours, minutes, seconds)
 Main oscillation / sub oscillation frequency can be selected for the operation clock.
Calibration: A real-time clock (RTC) of the sub clock drive.
 The main clock to sub clock ratio can be corrected by setting the real-time clock prescaler
Clock Supervisor
 Monitoring abnormality (damage of crystal etc.) of sub oscillation (32kHz) (dual clock products)
and main oscillation (4 MHz).
 When abnormality is detected, it switches to the CR clock.
 For some devices, ON/OFF can be selected as the initial value.
Base timer : 2 channels
 16-bit timer
 The timer mode is selected from PWM/PPG/PWC/reload.
 In the cascaded mode, a pair of 16-bit timers can be used as one 32-bit timer.
CRC generation
Watchdog timer
 Hardware watchdog
 Software watchdog (An effective range of a clear counter can be set.)
NMI
Interrupt controller
Interrupt request batch read
 Multiple interrupts from peripherals can be read by a series of registers.
I/O relocation
 Peripheral function pins can be reassigned.
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D a t a S h e e t
 Low-power consumption mode
 Sleep / Stop / Watch / Sub RUN mode
 Stop (power shutdown) / Watch (power shutdown) mode
 Power on reset
 Low-voltage detection reset (External power supply and Internal power supply are independently
observed.)
 For some devices, ON/OFF can be selected as the initial value for external power supply.
 Tuning RAM
 Capacity: 128 KB
 Can be used as RAM for data tuning.
 JTAG pins (TRST, TCK, TMS, TDI, TDO)
 Device Package : LQFP-144/176/208, TEQFP-144(planning)/176/208, BGA-416
 CMOS 90nm Technology
 Power supplies
 5V or 3V Power supply
 The internal 1.2V is generated from 5V with the voltage step-down regulator.
 Restriction on the power-on sequence (from VCC to VCCE)
 Applying a voltage higher than the power supply voltage to an analog signal input is prohibited.
 Operation guaranteed voltage range (recommended): 3.0V to 5.5V (within the range guaranteed by AC
and DC spec)
 Operation guaranteed voltage range: 2.7V to 5.5V
March 28, 2014, MB91F528_DS705-00016-1v0-E
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D a t a S h e e t
 PRODUCT LINEUP
 Product lineup comparison 144pins
MB91F527R
System Clock
Minimum instruction
execution time
FLASH Capacity
(Program)
On-chip PLL Clock multiple method
12.5ns(80MHz) (LQFP-144)
8.0ns(128MHz) (TEQFP-144)
1536KB + 64KB
FLASH Capacity (Data)
RAM Capacity
External Bus I/F
(22 address/16 data/4cs)
MB91F528R
2048KB + 64KB
64KB
192KB + 16KB
(192KB + 128KB) + 16KB
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 3 channels
Input capture
16-bit × 4 channels
32-bit × 6 channels
Output Compare
16-bit × 6 channels
32-bit × 6 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 44 channels *2
Up/down Counter
2 channels
Clock Supervisor
Yes
External interrupt
8 channels × 2 units
A/D
12-bit × 32 channels (1 unit)
12-bit × 16 channels (1 unit)
D/A (8-bit)
2 channels
Multi-Function Serial
12 channels
CAN
FlexRay
128msg × 6 channels
1 channel
Hardware watchdog
Yes
CRC generation
Yes
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D a t a S h e e t
MB91F527R
MB91F528R
Low-voltage detection
reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
115 ports (no sub clock) / 113 ports (with sub clock)
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection
Unit)
Yes
Key Code Register
Yes
Wave Generator
Tuning RAM
JTAG
Operation guaranteed
temperature (Ta)
Power supply
Package
6 channels
None
Yes
Yes
-40°C to +125°C *1
2.7 V to 5.5 V
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: 1-pin to 39-pin and 128-pin to 144-pin power supply)
(External bus I/F: 3.0 V to 3.6 V)
LQFP-144 / TEQFP-144 (planning) *3
*1: The limitation with the package has been described by the item of the power consumption of "Absolute
maximum ratings".
*2: PPG output pins on ch.38 and ch.39 do not exist. See "Pins of PPG (ch.0 to ch.87)."
*3: TEQFP-144pin is planning. Please contact sales representatives about details.
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
7
D a t a S h e e t
 Product lineup comparison 176pins
MB91F527U
System Clock
Minimum instruction
execution time
FLASH Capacity
(Program)
On-chip PLL Clock multiple method
12.5ns(80MHz) (LQFP-176)
8.0ns(128MHz) (TEQFP-176)
1536KB + 64KB
FLASH Capacity (Data)
RAM Capacity
External Bus I/F
(22 address/16 data/4cs)
MB91F528U
2048KB + 64KB
64KB
192KB + 16KB
(192KB + 128KB) + 16KB
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 3 channels
Input capture
16-bit × 4 channels
32-bit × 6 channels
Output Compare
16-bit × 6 channels
32-bit × 6 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 48 channels
Up/down Counter
2 channels
Clock Supervisor
Yes
External interrupt
8 channels × 2 units
A/D
12-bit × 32 channels (1 unit)
12-bit × 16 channels (1 unit)
D/A (8-bit)
2 channels
Multi-Function Serial
12 channels
CAN
FlexRay
128msg × 6 channels
1 channel
Hardware watchdog
Yes
CRC generation
Yes
Low-voltage detection
reset
Yes
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D a t a S h e e t
MB91F527U
MB91F528U
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
147 ports (no sub clock) / 145 ports (with sub clock)
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection Unit)
Yes
Key Code Register
Yes
6 channels
Wave Generator
Tuning RAM
JTAG
Operation guaranteed
temperature (Ta)
Power supply
Package
None
Yes
Yes
-40°C to +125°C *1
2.7 V to 5.5 V
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: 1-pin to 49-pin and 156-pin to 176-pin power supply)
(External bus I/F: 3.0 V to 3.6 V)
LQFP-176 / TEQFP- 176
*1: The limitation with the package has been described by the item of the power consumption of "Absolute
maximum ratings".
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
9
D a t a S h e e t
 Product lineup comparison 208pins
MB91F527M
System Clock
MB91F528M
On-chip PLL Clock multiple method
Minimum instruction
execution time
FLASH Capacity
(Program)
8.0ns (128MHz)
1536KB + 64KB
FLASH Capacity (Data)
RAM Capacity
External Bus I/F
(22 address/16 data/4cs)
2048KB + 64KB
64KB
192KB + 16KB
(192KB + 128KB) + 16KB
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 8 channels
Input capture
16-bit × 4 channels
32-bit × 8 channels
Output Compare
16-bit × 6 channels
32-bit × 8 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 64 channels
Up/down Counter
4 channels
Clock Supervisor
Yes
External interrupt
8 channels × 3 units
A/D
12-bit × 32 channels (2 units)
D/A (8-bit)
2 channels
Multi-Function Serial
20 channels
CAN
FlexRay
128msg × 6 channels
1 channel
Hardware watchdog
Yes
CRC generation
Yes
Low-voltage detection
reset
Yes
Flash Security
Yes
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MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
MB91F527M
MB91F528M
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
177 ports (no sub clock) / 175 ports (with sub clock)
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection Unit)
Yes
Key Code Register
Yes
6 channels
Wave Generator
Tuning RAM
JTAG
Operation guaranteed
temperature (Ta)
Power supply
Package
None
Yes
Yes
-40°C to +125°C *1
2.7 V to 5.5 V
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: 1-pin to 57-pin and 188-pin to 208-pin power supply)
(External bus I/F: 3.0 V to 3.6 V)
LQFP-208 / TEQFP- 208
*1: The limitation with the package has been described by the item of the power consumption of "Absolute
maximum ratings".
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
11
D a t a S h e e t
 Product lineup comparison 416pins
MB91F527Y
System Clock
MB91F528Y
On-chip PLL Clock multiple method
Minimum instruction
execution time
FLASH Capacity
(Program)
8.0ns (128MHz)
1536KB + 64KB
FLASH Capacity (Data)
RAM Capacity
External Bus I/F
(22 address/16 data/4cs)
2048KB + 64KB
64KB
192KB + 16KB
(192KB + 128KB) + 16KB
Yes
DMA Transfer
16 channels
16-bit Base Timer
2 channels
Free-run Timer
16-bit × 3 channels
32-bit × 8 channels
Input capture
16-bit × 4 channels
32-bit × 8 channels
Output Compare
16-bit × 6 channels
32-bit × 8 channels
16-bit Reload Timer
PPG
8 channels
16-bit × 88 channels
Up/down Counter
4 channels
Clock Supervisor
Yes
External interrupt
8 channels × 3 units
A/D
12-bit × 32 channels (2 units)
D/A (8-bit)
2 channels
Multi-Function Serial
20 channels
CAN
FlexRay
128msg × 6 channels
1 channel
Hardware watchdog
Yes
CRC generation
Yes
Low-voltage detection
reset
Yes
Flash Security
Yes
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MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
MB91F527Y
MB91F528Y
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection
Function (MPU)
Yes
Floating-point
arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port
(#GPIOs)
219 ports (no sub clock) / 217 ports (with sub clock)
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD(On Chip Debug)
Yes
TPU
(Timing Protection Unit)
Yes
Key Code Register
Yes
6 channels
Wave Generator
Tuning RAM
JTAG
Operation guaranteed
temperature (Ta)
Power supply
Package
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
None
Yes
Yes
-40°C to +125°C
2.7 V to 5.5 V
VCCE = 5.0 V±10% or VCCE = 3.0 V to 3.6 V
(VCCE: See pin assignment)
(External bus I/F: 3.0 V to 3.6 V)
BGA-416
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D a t a S h e e t
 Table for clock supervisor and external low voltage detection reset initial value ON/OFF
Clock
Initial value of clock supervisor
ON
Single
OFF
ON
Dual
OFF
Initial value of external
low-voltage detection reset
Function
ON
OFF
ON
OFF
ON
OFF
ON
OFF
S
U
H
K
W
Y
J
L
MB91F52Xxyz
→Revision: C
→Function: See Table 3-5
→PKG Type: R 144 pin
U 176 pin
M 208 pin
Y BGA 416 pin
→Memory Size: 7 1.5MB
8 2MB
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MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 PIN ASSIGNMENT
 MB91F52xR
MB91F527R, MB91F528R
VCCE
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P012/D26/TIOB0_0/STOPWT_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P010/D24/RXDB_0
P007/D23/TXDB_0
P006/D22/SCS2_0/ADTG1_1/INT2_1/TXENB_0
P005/D21/SCK2_0/ADTG0_1/INT7_1/RXDA_0
P004/D20/SOT2_0/TXDA_0
P003/D19/SIN2_0/TIOB1_1/INT3_0/TXENA_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
VCCE
P134/RX2(128)_0/SCS1_1/ICU7_0/INT7_0
P133/TX2(128)_0
VSS
VCC
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P130/SCK0_0/TCK
P127/SOT0_0/TDO
P126/SIN0_0/INT6_0/TDI
P125/OCU11_0/TMS
P124/OCU10_0/TRST
DEBUGIF
VCC
(TOP VIEW)
Power supply Gr.1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
Power supply Gr.2
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P017/D31/TRG2_0
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0/RDY_1
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P046/A16/ICU4_1/TRG4_1
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0/TX5(128)_0
P052/A20/PPG34_0/INT14_0/RX5(128)_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCCE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
●
TOP VIEW
LQFP-144
TEQFP-144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VSS
P123/OCU9_0/STOPWT_1
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0/TX4(128)_0
P120/AN30/OCU6_0/PPG22_0/INT9_0/RX4(128)_0
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1(128)_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0/RXDB_1
P113/AN25/PPG17_0/RTO1_0/TXDB_1
P112/AN24/PPG16_0/RTO0_0/TXENB_1
P111/RX1(128)_0/SCS62_0/AN23/INT1_0
P110/TX1(128)_0/SCS63_0/AN22
NMIX
P155/AN21/RXDA_1
P154/AN20/TXDA_1
P107/AN19/PPG15_0/TXENA_1
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0/RX3(128)_0
P101/SOT7_0/SDA7/AN13/PPG9_0/TX3(128)_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)_0/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)_0/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0(128)_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
VSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VCC
P087/DAO0/PPG7_0/INT8_0
P086/DAO1/PPG6_0
P085/PPG5_0
P084/SCS51_0/AN3/PPG4_0
P083/SCS50_0/AN2/PPG3_0
P082/SIN5_0/AN1/PPG2_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P080/SCS52_0/PPG0_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P152/SCS53_0
P077/SCK3_0/SCL3
P076/SOT3_0/SDA3/TX5(128)_1
P075/SIN3_0/INT4_0/RX5(128)_1
P074/SCK4_0/SCL4
P073/SOT4_0/SDA4/AN33/ICU3_2
P072/SIN4_0/AN34/ICU2_2/INT5_0
P071/SCK4_2/AN35/ICU1_2/MONCLK
P070/ICU0_2
P067/AN36/FRCK5_0/AIN0_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
VCC
VSS
AVSS1/AVRL1
AVRH1
P057/RDY_0/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVCC1
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
VSS
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
15
D a t a S h e e t
 MB91F52xU
MB91F527U, MB91F528U
VCCE
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P167/PPG35_1
P012/D26/TIOB0_0/STOPWT_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P010/D24/RXDB_0
P166/PPG34_1
P007/D23/TXDB_0
P006/D22/SCS2_0/ADTG1_1/INT2_1/TXENB_0
P165/PPG33_1
P005/D21/SCK2_0/ADTG0_1/INT7_1/RXDA_0
P164/PPG32_1
P004/D20/SOT2_0/TXDA_0
P003/D19/SIN2_0/TIOB1_1/INT3_0/TXENA_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
VCCE
P134/RX2(128)_0/SCS1_1/ICU7_0/INT7_0
P133/TX2(128)_0
VSS
VCC
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P163/TRG6_2
P162/TRG5_2
P130/SCK0_0/TCK
P127/SOT0_0/TDO
P126/SIN0_0/INT6_0/TDI
P125/OCU11_0/TMS
P124/OCU10_0/TRST
P161/PPG31_1
P160/PPG30_1
DEBUGIF
VCC
(TOP VIEW)
Power supply Gr.1
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
Power supply Gr.2
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P170/PPG36_1
P017/D31/TRG2_0
P171/PPG37_1
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P172/PPG38_1
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P173/PPG39_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0/RDY_1
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P174/TRG8_1
P175/TRG9_1
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P046/A16/ICU4_1/TRG4_1
P176/TRG10_0
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P177/TRG11_0
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0/TX5(128)_0
P052/A20/PPG34_0/INT14_0/RX5(128)_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCCE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
●
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
TOP VIEW
LQFP-176
TEQFP-176
VSS
P123/OCU9_0/STOPWT_1
P197/PPG29_1
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0/TX4(128)_0
P120/AN30/OCU6_0/PPG22_0/INT9_0/RX4(128)_0
P196/FRCK3_1/PPG28_1
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1(128)_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0/RXDB_1
P195/FRCK4_1/PPG27_1
P194/FRCK5_1/PPG26_1
P113/AN25/PPG17_0/RTO1_0/TXDB_1
P112/AN24/PPG16_0/RTO0_0/TXENB_1
P111/RX1(128)_0/SCS62_0/AN23/INT1_0
P110/TX1(128)_0/SCS63_0/AN22
NMIX
P155/AN21/RXDA_1
P154/AN20/TXDA_1
P193/PPG25_1
P107/AN19/PPG15_0/TXENA_1
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0/RX3(128)_0
P101/SOT7_0/SDA7/AN13/PPG9_0/TX3(128)_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)_0/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)_0/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0(128)_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P192/PPG24_1/TOT1_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
P191/TIN1_1
P190/TIN0_1
VSS
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
VCC
P087/DAO0/PPG7_0/INT8_0
P086/DAO1/PPG6_0
P085/PPG5_0
P084/SCS51_0/AN3/PPG4_0
P083/SCS50_0/AN2/PPG3_0
P082/SIN5_0/AN1/PPG2_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P080/SCS52_0/PPG0_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P152/SCS53_0
P077/SCK3_0/SCL3
P076/SOT3_0/SDA3/TX5(128)_1
P075/SIN3_0/INT4_0/RX5(128)_1
P074/SCK4_0/SCL4
P187/PPG47_0
P186/PPG46_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P072/SIN4_0/AN34/ICU2_2/INT5_0
P071/SCK4_2/AN35/ICU1_2/MONCLK
P070/ICU0_2
P067/AN36/FRCK5_0/AIN0_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P185/PPG45_0
P184/PPG44_0
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P183/PPG43_0
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P182/PPG42_0
VCC
VSS
AVSS1/AVRL1
AVRH1
P057/RDY_0/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVCC1
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
P181/PPG41_0
P180/PPG40_0
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
VSS
16
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 MB91F52xM
MB91F527M, MB91F528M
VCCE
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P167/PPG35_1
P012/D26/TIOB0_0/STOPWT_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P237/SCS19_0/TRG15_0/ZIN3_0
P236/SIN19_0/TRG14_0/BIN3_0/INT23_0
P235/SOT19_0/SDA19/PPG63_0/AIN3_0
P234/SCK19_0/SCL19/PPG62_0
P010/D24/RXDB_0
P166/PPG34_1
P007/D23/TXDB_0
P006/D22/SCS2_0/ADTG1_1/INT2_1/TXENB_0
P165/PPG33_1
P005/D21/SCK2_0/ADTG0_1/INT7_1/RXDA_0
P164/PPG32_1
P004/D20/SOT2_0/TXDA_0
P003/D19/SIN2_0/TIOB1_1/INT3_0/TXENA_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
VCCE
P134/RX2(128)_0/SCS1_1/ICU7_0/INT7_0
P133/TX2(128)_0
VSS
VCC
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P163/TRG6_2
P162/TRG5_2
P130/SCK0_0/TCK
P127/SOT0_0/TDO
P126/SIN0_0/INT6_0/TDI
P233/SCS18_0/PPG61_0/INT16_1
P232/SIN18_0/PPG60_0/INT22_0
P231/SOT18_0/SDA18/OCU13_0/PPG59_0
P230/SCK18_0/SCL18/OCU12_0/PPG58_0
P125/OCU11_0/TMS
P124/OCU10_0/TRST
P161/PPG31_1
P160/PPG30_1
DEBUGIF
VCC
(TOP VIEW)
Power supply Gr.1
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
Power supply Gr.2
VSS
P015/D29/TRG0_0
P016/D30/TRG1_0
P170/PPG36_1
P017/D31/TRG2_0
P171/PPG37_1
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0
P172/PPG38_1
P026/A00/SCK4_1/PPG26_0/TIN3_0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1
P173/PPG39_1
P030/A02/SCS41_1/PPG28_0/TOT1_0
P031/A03/SCS42_1/PPG29_0/TOT2_0
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1
P200/SCK12_0/SCL12/AN63/TRG12_0
P201/SOT12_0/SDA12/AN62/TRG13_0
P202/SIN12_0/AN61/INT16_0
P203/SCS12_0/AN60
P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0/RDY_1
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1
P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0
P037/A09/OCU6_1/TOT6_0/ZIN0_0
P174/TRG8_1
P175/TRG9_1
P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_1
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_0
P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0
P043/A13/ICU7_1/TRG1_1
P044/A14/SCS9_0/ICU6_1/TRG2_1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2
P204/SCK13_0/SCL13/AN59/PPG48_0
P205/SOT13_0/SDA13/AN58/PPG49_0/AIN2_0
P206/SIN13_0/AN57/BIN2_0/INT17_0
P207/SCS13_0/AN56/ZIN2_0
P046/A16/ICU4_1/TRG4_1
P176/TRG10_0
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_1
P177/TRG11_0
P050/A18/TRG5_1/PPG33_0
P051/A19/TRG9_0/TX5(128)_0
P052/A20/PPG34_0/INT14_0/RX5(128)_0
P053/A21/AN44/PPG35_0/INT14_1/SCK0_1
P054/SYSCLK/PPG36_0
VCCE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
●
TOP VIEW
LQFP-208
TEQFP-208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
P123/OCU9_0/STOPWT_1
P197/PPG29_1
P227/SIN17_0/PPG57_0/INT21_0
P226/SOT17_0/SDA17/PPG56_0
P225/SCK17_0/SCL17/PPG55_0
P122/SIN6_0/AN31/OCU8_0/INT9_1
P121/OCU7_0/PPG23_0/TX4(128)_0
P120/AN30/OCU6_0/PPG22_0/INT9_0/RX4(128)_0
P196/FRCK3_1/PPG28_1
P117/SCS60_0/AN29/PPG21_0/RTO5_0
P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P115/RX1(128)_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P114/SCS61_0/AN26/PPG18_0/RTO2_0/RXDB_1
P195/FRCK4_1/PPG27_1
P194/FRCK5_1/PPG26_1
P113/AN25/PPG17_0/RTO1_0/TXDB_1
P112/AN24/PPG16_0/RTO0_0/TXENB_1
P111/RX1(128)_0/SCS62_0/AN23/INT1_0
P110/TX1(128)_0/SCS63_0/AN22
NMIX
VSS
VCC
P155/AN21/RXDA_1
P154/AN20/TXDA_1
P193/PPG25_1
P107/AN19/PPG15_0/TXENA_1
P106/SCS70_0/AN18/PPG14_0
P105/SCS71_0/AN17/PPG13_0
P104/SCS72_0/AN16/PPG12_0
P103/SCS73_0/AN15/PPG11_0
P102/SIN7_0/AN14/PPG10_0/INT10_0/RX3(128)_0
P101/SOT7_0/SDA7/AN13/PPG9_0/TX3(128)_0
P100/SCK7_0/SCL7/AN12/PPG8_0
AVCC0
AVRH0
AVSS0/AVRL0
P222/SIN16_0/PPG54_0/INT20_0
P221/SOT16_0/SDA16/ICU11_0/PPG49_1
P220/SCK16_0/SCL16/ICU10_0/PPG48_1
P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P096/RX0(128)_0/SOT11_0/SDA11/AN10/INT0_0
P095/TX0(128)_0/SCS11_0/AN9
P094/AN8/ICU4_0/TOT3_1
P093/TX0(128)_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1
P192/PPG24_1/TOT1_1
P092/AN6/PPG40_1/ICU2_0/TOT0_1
P091/AN5/PPG41_1/ICU1_0/TIN3_1
P090/AN4/ICU0_0/TIN2_1
P191/TIN1_1
P190/TIN0_1
VSS
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VCC
P087/DAO0/PPG7_0/INT8_0
P086/DAO1/PPG6_0
P085/PPG5_0
P084/SCS51_0/AN3/PPG4_0
P083/SCS50_0/AN2/PPG3_0
P082/SIN5_0/AN1/PPG2_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P080/SCS52_0/PPG0_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P152/SCS53_0
P077/SCK3_0/SCL3
P076/SOT3_0/SDA3/TX5(128)_1
P075/SIN3_0/INT4_0/RX5(128)_1
P217/SCS15_0/AN48/FRCK10_0/TRG13_1
P216/SIN15_0/AN49/FRCK9_0/TRG12_1/INT19_0
P215/SOT15_0/SDA15/AN50/FRCK8_0/PPG53_0
P214/SCK15_0/SCL15/AN51/PPG52_0
P074/SCK4_0/SCL4
P187/PPG47_0
P186/PPG46_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P072/SIN4_0/AN34/ICU2_2/INT5_0
P071/SCK4_2/AN35/ICU1_2/MONCLK
P070/ICU0_2
P067/AN36/FRCK5_0/AIN0_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P185/PPG45_0
P184/PPG44_0
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P183/PPG43_0
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P213/SCS14_0/AN52/FRCK7_0/INT17_1
P212/SIN14_0/AN53/FRCK6_0/ZIN2_1/INT18_0
P211/SOT14_0/SDA14/AN54/PPG51_0/BIN2_1
P210/SCK14_0/SCL14/AN55/PPG50_0/AIN2_1
P182/PPG42_0
VCC
VSS
AVSS1/AVRL1
AVRH1
P057/RDY_0/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVCC1
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
P181/PPG41_0
P180/PPG40_0
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
VSS
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
17
D a t a S h e e t
 MB91F52xY
MB91F527Y, MB91F528Y
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
VSS
B1
VSS
B 100
VCCE
B 99
P014
B 98
P012
B 97
P010
B 96
P006
B 95
P004
B 94
P002
B 93
P000
B 92
VCCE
B 91
VSS
B 90
C
B 89
VCC
B 88
VSS
B 87
P136
B 86
P135
B 85
VSS
B 84
X1
B 83
X0
B 82
VSS
B 81
P125
B 80
MD1
B 79
VCC
B 78
VSS
B 77
VSS
B 76
A
B
VSS
B2
VSS
B 101
VCCE
B 192
VSS
B 191
P013
B 190
P011
B 189
P007
B 188
P005
B 187
P003
B 186
P001
B 185
VCCE
B 184
VSS
B 183
VSS
B 182
VCC
B 181
RSTX
B 180
VSS
B 179
VSS
B 178
P291
B 177
VSS
B 176
VSS
B 175
P230
B 174
P286
B 173
MD0
B 172
VCC
B 171
VSS
B 170
VSS
B 75
B
C
P015
B3
VSS
B 102
VSS
B 193
P296
B 276
P295
B 275
P294
B 274
VSS
B 273
VSS
B 272
P234
B 271
P293
B 270
P165
B 269
VSS
B 268
VSS
B 267
VSS
B 266
VSS
B 265
P162
B 264
P127
B 263
P126
B 262
P233
B 261
P231
B 260
P287
B 259
P160
B 258
VSS
B 257
VSS
B 256
P284
B 169
D
P016
B4
P017
B 103
P240
B 194
VSS
B 277
P297
B 352
P167
B 351
P237
B 350
P236
B 349
P235
B 348
P166
B 347
P292
B 346
P164
B 345
VSS
B 344
P134
B 343
P133
B 342
P163
B 341
P130
B 340
P290
B 339
P232
B 338
P124
B 337
P161
B 336
P285
B 335
VSS
B 334
VSS
B 255
P226
B 168
P121
B 73
D
E
P020
B5
P021
B 104
P170
B 195
P241
B 278
Index
P123
B 333
P227
B 254
P122
B 167
P282
B 72
E
F
P022
B6
P023
B 105
VSS
B 196
P171
B 279
P197
B 332
VSS
B 253
P283
B 166
P115
B 71
F
G
P024
B7
P025
B 106
VSS
B 197
P242
B 280
P225
B 331
VSS
B 252
P116
B 165
P280
B 70
G
H
P026
B8
VSS
B 107
VSS
B 198
P243
B 281
P120
B 330
P117
B 251
P281
B 164
P194
B 69
H
J
P027
B9
P030
B 108
P244
B 199
P245
B 282
P196
B 329
VSS
B 250
P195
B 163
P111
B 68
J
K
P031
B 10
P032
B 109
P172
B 200
P173
B 283
VSS
B 353
VSS
B 380
VSS
B 379
VSS
B 378
VSS
B 377
VSS
B 376
VSS
B 375
VSS
B 374
P114
B 328
VSS
B 249
P113
B 162
P112
B 67
K
L
P033
B 11
P034
B 110
P200
B 201
P201
B 284
VSS
B 354
VSS
B 381
VSS
B 400
VSS
B 399
VSS
B 398
VSS
B 397
VSS
B 396
VSS
B 373
P110
B 327
P277
B 248
NMIX
B 161
P155
B 66
L
M
VCCE
B 12
VCCE
B 111
P202
B 202
P203
B 285
VSS
B 355
VSS
B 382
VSS
B 401
VSS
B 412
VSS
B 411
VSS
B 410
VSS
B 395
VSS
B 372
VSS
B 326
VSS
B 247
VSS
B 160
VSS
B 65
M
N
VSS
B 13
VSS
B 112
VSS
B 203
VSS
B 286
VSS
B 356
VSS
B 383
VSS
B 402
VSS
B 413
VSS
B 416
VSS
B 409
VSS
B 394
VSS
B 371
P154
B 325
VSS
B 246
VCC
B 159
VCC
B 64
N
P
VSS
B 14
VSS
B 113
VSS
B 204
VSS
B 287
VSS
B 357
VSS
B 384
VSS
B 403
VSS
B 414
VSS
B 415
VSS
B 408
VSS
B 393
VSS
B 370
P107
B 324
P106
B 245
P105
B 158
P193
B 63
P
R
P035
B 15
P036
B 114
P150
B 205
P151
B 288
VSS
B 358
VSS
B 385
VSS
B 404
VSS
B 405
VSS
B 406
VSS
B 407
VSS
B 392
VSS
B 369
P104
B 323
VSS
B 244
P103
B 157
P102
B 62
R
T
P037
B 16
P040
B 115
VSS
B 206
P174
B 289
VSS
B 359
VSS
B 386
VSS
B 387
VSS
B 388
VSS
B 389
VSS
B 390
VSS
B 391
VSS
B 368
P101
B 322
VSS
B 243
P100
B 156
AVCC0
B 61
T
U
P041
B 17
P042
B 116
VSS
B 207
P175
B 290
VSS
B 360
VSS
B 361
VSS
B 362
VSS
B 363
VSS
B 364
VSS
B 365
VSS
B 366
VSS
B 367
P221
B 321
P275
B 242
P276
B 155
AVRH0
B 60
U
V
P043
B 18
P044
B 117
P204
B 208
P205
B 291
P096
B 320
VSS
B 241
P222
B 154
AVRL0
B 59
V
W
P045
B 19
P046
B 118
VSS
B 209
P206
B 292
P093
B 319
VSS
B 240
P220
B 153
AVSS0
W
B 58
Y
P047
B 20
P050
B 119
VSS
B 210
P207
B 293
P092
B 318
P273
B 239
P095
B 152
P097
B 57
Y
AA
P051
B 21
P052
B 120
P176
B 211
P177
B 294
P270
B 317
VSS
B 238
P272
B 151
P094
B 56
AA
AB
P053
B 22
P054
B 121
P250
B 212
P251
B 295
P267
B 316
P090
B 237
P091
B 150
P192
B 55
AB
AC
P252
B 23
P253
B 122
VSS
B 213
VSS
B 296
P180
B 297
P181
B 298
P182
B 299
P211
B 300
VSS
B 301
P061
B 302
P063
B 303
P065
B 304
P066
B 305
P072
B 306
P263
B 307
P074
B 308
P265
B 309
P080
B 310
P082
B 311
TCK
B 312
P083
B 313
P086
B 314
VSS
B 315
P266
B 236
P191
B 149
P271
B 54
AC
VCCE
AD
B 24
VCCE
B 123
VSS
B 214
VSS
B 215
P255
B 216
P256
B 217
VSS
B 218
P213
B 219
VSS
B 220
VSS
B 221
P062
B 222
VSS
B 223
VSS
B 224
P071
B 225
VSS
B 226
VSS
B 227
P076
B 228
VSS
B 229
VSS
B 230
TDI
B 231
VSS
B 232
VSS
B 233
P085
B 234
VSS
B 235
P087
B 148
P190
B 53
AD
Power supply Gr.2
Power supply Gr.1
DEBUGIF
C
B 74
AE
VSS
B 25
VSS
B 124
P056
B 125
P254
B 126
P057
B 127
P210
B 128
P212
B 129
P060
B 130
VSS
B 131
VCC
B 132
VCC
B 133
P064
B 134
P185
B 135
P070
B 136
P262
B 137
P187
B 138
P216
B 139
P075
B 140
P264
B 141
P153
B 142
TDO
B 143
TRST
B 144
TMS
B 145
VCC
B 146
VSS
B 147
VSS
B 52
AE
AF
VSS
B 26
VSS
B 27
P055
B 28
AVCC1
B 29
AVRH1
B 30
AVRL1
B 31
AVSS1
B 32
VSS
B 33
VSS
B 34
VCC
B 35
VCC
B 36
P183
B 37
P184
B 38
P067
B 39
P073
B 40
P186
B 41
P215
B 42
P214
B 43
P217
B 44
P077
B 45
P152
B 46
P081
B 47
P084
B 48
VCC
B 49
VSS
B 50
VSS
B 51
AF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
BGA-416
18
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 PIN DESCRIPTION
144
176
208
BGA
416
Polarity
Pin Number
I/O
circuit
1
type*
-
-
-
D3
P240
-
A
General-purpose I/O port
-
-
-
E4
P241
-
A
General-purpose I/O port
P015
-
2
2
2
C1
D29
-
TRG0_0
-
PPG trigger 0 input pin(0)
P016
-
General-purpose I/O port
3
3
3
D1
-
4
4
E3
4
5
5
D2
-
6
6
F4
-
-
-
G4
-
-
-
H4
5
6
7
8
-
7
8
9
10
-
7
8
9
10
-
Pin Name
E1
E2
F1
F2
J3
D30
-
TRG1_0
-
P170
-
PPG36_1
-
P017
-
D31
-
TRG2_0
-
P171
-
PPG37_1
-
P242
-
TRG16_0
-
General-purpose I/O port
R
R
External Bus data bit29 I/O pin
External Bus data bit30 I/O pin
PPG trigger 1 input pin(0)
A
General-purpose I/O port
PPG ch.36 output pin(1)
General-purpose I/O port
R
External Bus data bit31 I/O pin
PPG trigger 2 input pin(0)
A
A
General-purpose I/O port
PPG ch.37 output pin(1)
General-purpose I/O port
PPG trigger 16 input pin(0)
P243
-
TRG17_0
-
P020
-
General-purpose I/O port
ASX
-
SIN3_1
-
TRG3_0
-
External Bus address strobe output pin
Multi-function serial ch.3 serial data input
pin(1)
PPG trigger 3 input pin(0)
TIN0_2
-
Reload timer ch.0 event input pin(2)
RTO5_1
-
Waveform generator ch.5 output pin(1)
P021
-
General-purpose I/O port
CS0X
-
SOT3_1
-
TRG6_1
-
External Bus chip select 0 output pin
Multi-function serial ch.3 serial data output
pin(1)
PPG trigger 6 input pin(1)
TRG4_0
-
PPG trigger 4 input pin(0)
A
F
A
General-purpose I/O port
PPG trigger 17 input pin(0)
P022
-
General-purpose I/O port
CS1X
-
External Bus chip select 1 output pin
SCK3_1
-
TRG7_1
-
PPG trigger 7 input pin(1)
TRG5_0
-
PPG trigger 5 input pin(0)
P023
-
General-purpose I/O port
F
Multi-function serial ch.3 clock I/O pin(1)
RDX
-
SCS3_1
-
PPG32_0
-
PPG ch.32 output pin(0)
TIN0_0
-
Reload timer ch.0 event input pin(0)
P244
-
PPG64_0
-
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
2
Function*
External Bus read strobe output pin
A
A
Serial chip select 3 I/O pin(1)
General-purpose I/O port
PPG ch.64 output pin(0)
19
D a t a S h e e t
144
176
208
BGA
416
-
-
-
J4
9
10
-
11
12
-
13
14
11
12
13
14
15
16
17
18
20
CONFIDENTIAL
11
12
13
14
15
16
17
18
G1
G2
K3
H1
J1
K4
J2
K1
Pin Name
Polarity
Pin Number
P245
-
PPG65_0
-
I/O
circuit
1
type*
A
2
Function*
General-purpose I/O port
PPG ch.65 output pin(0)
P024
-
General-purpose I/O port
WR0X
-
SIN4_1
-
PPG24_0
-
External Bus write strobe 0 output pin
Multi-function serial ch.4 serial data input
pin(1)
PPG ch.24 output pin(0)
TIN1_0
-
Reload timer ch.1 event input pin(0)
F
RTO4_1
-
Waveform generator ch.4 output pin(1)
INT15_0
-
INT15 external interrupt input pin(0)
P025
-
General-purpose I/O port
WR1X
-
SOT4_1
-
PPG25_0
-
External Bus write strobe 1 output pin
Multi-function serial ch.4 serial data output
pin(1)
PPG ch.25 output pin(0)
TIN2_0
-
Reload timer ch.2 event input pin(0)
P172
-
PPG38_1
-
P026
-
A
A
General-purpose I/O port
PPG ch.38 output pin(1)
General-purpose I/O port
A00
-
SCK4_1
-
External Bus address bit0 output pin
PPG26_0
-
PPG ch.26 output pin(0)
TIN3_0
-
Reload timer ch.3 event input pin(0)
P027
-
General-purpose I/O port
A01
-
External Bus address bit1 output pin
F
Multi-function serial ch.4 clock I/O pin(1)
SCS40_1
-
PPG27_0
-
TOT0_0
-
Reload timer ch.0 output pin(0)
RTO3_1
-
Waveform generator ch.3 output pin(1)
P173
-
PPG39_1
-
P030
-
A
A
Serial chip select 40 I/O pin(1)
PPG ch.27 output pin(0)
General-purpose I/O port
PPG ch.39 output pin(1)
General-purpose I/O port
A02
-
SCS41_1
-
External Bus address bit2 output pin
PPG28_0
-
PPG ch.28 output pin(0)
TOT1_0
-
Reload timer ch.1 output pin(0)
P031
-
General-purpose I/O port
A03
-
External Bus address bit3 output pin
A
A
Serial chip select 41 output pin(1)
SCS42_1
-
PPG29_0
-
Serial chip select 42 output pin(1)
PPG ch.29 output pin(0)
TOT2_0
-
Reload timer ch.2 output pin(0)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
15
-
-
-
-
16
17
176
19
-
-
-
-
20
21
208
19
20
21
22
23
24
25
BGA
416
K2
L3
L4
M3
M4
L1
L2
Pin Name
Polarity
Pin Number
P032
-
General-purpose I/O port
A04
-
External Bus address bit4 output pin
2
Function*
SCS43_1
-
PPG30_0
-
TOT3_0
-
Reload timer ch.3 output pin(0)
RTO2_1
-
Waveform generator ch.2 output pin(1)
P200
-
SCK12_0/SCL12
-
AN63
-
General-purpose I/O port
Multi-function serial ch.12 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 63 input pin
TRG12_0
-
PPG trigger 12 input pin(0)
P201
-
SOT12_0/SDA12
-
AN62
-
General-purpose I/O port
Multi-function serial ch.12 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 62 input pin
TRG13_0
-
PPG trigger 13 input pin(0)
P202
-
SIN12_0
-
AN61
-
General-purpose I/O port
Multi-function serial ch.12 serial data input
pin(0)
ADC analog 61 input pin
INT16_0
-
INT16 external interrupt input pin(0)
A
Q
Q
G
Serial chip select 43 output pin(1)
PPG ch.30 output pin(0)
P203
-
SCS12_0
-
AN60
-
ADC analog 60 input pin
P033
-
General-purpose I/O port
A05
-
External Bus address bit5 output pin
PPG31_0
-
ICU3_3
-
General-purpose I/O port
B
Serial chip select 12 I/O pin(0)
PPG ch.31 output pin(0)
A
Input capture ch.3 input pin(3)
TIN4_0
-
Reload timer ch.4 event input pin(0)
RTO1_1
-
Waveform generator ch.1 output pin(1)
SCK3_2
-
Multi-function serial ch.3 clock I/O pin(2)
P034
-
General-purpose I/O port
A06
-
External Bus address bit6 output pin
OCU11_1
-
Output compare ch.11 output pin(1)
ICU2_3
-
TIN5_0
-
Reload timer ch.5 event input pin(0)
RTO0_1
-
SOT3_2
-
Waveform generator ch.0 output pin(1)
Multi-function serial ch.3 serial data output
pin(2)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
I/O
circuit
1
type*
A
Input capture ch.2 input pin(3)
21
D a t a S h e e t
144
18
19
20
21
22
-
176
22
23
24
25
26
27
28
22
CONFIDENTIAL
208
26
27
28
29
30
31
32
BGA
416
Pin Name
Polarity
Pin Number
R1
R2
T1
T4
U4
2
Function*
P150
-
General-purpose I/O port
RDY_1
-
External Bus RDY input pin (1)
SOT8_0/SDA8
-
Multi-function serial ch.8 serial data output
pin(0)/I2C bus serial data I/O pin
OCU10_1
-
Output compare ch.10 output pin(1)
TRG6_0
-
PPG trigger 6 input pin(0)
ICU1_3
-
Input capture ch.1 input pin(3)
TIN6_0
-
Reload timer ch.6 event input pin(0)
P151
-
SCK8_0/SCL8
-
OCU9_1
-
General-purpose I/O port
Multi-function serial ch.8 clock I/O pin(0)/
I2C bus serial clock I/O pin
Output compare ch.9 output pin(1)
TRG7_0
-
ICU0_3
-
Input capture ch.0 input pin(3)
TIN7_0
-
Reload timer ch.7 event input pin(0)
ZIN0_2
-
U/D counter ch.0 ZIN input pin(2)
DTTI_1
-
Waveform generator ch.0-ch.5 input pin(1)
P035
-
General-purpose I/O port
A07
-
SIN8_0
-
OCU8_1
-
External Bus address bit7 output pin
Multi-function serial ch.8 serial data input
pin(0)
Output compare ch.8 output pin(1)
TOT4_0
-
Reload timer ch.4 output pin(0)
R3
R4
I/O
circuit
1
type*
F
F
I
PPG trigger 7 input pin(0)
AIN0_0
-
U/D counter ch.0 AIN input pin(0)
INT11_0
-
INT11 external interrupt input pin(0)
P036
-
General-purpose I/O port
A08
-
External Bus address bit8 output pin
SCS8_0
-
OCU7_1
-
TOT5_0
-
Reload timer ch.5 output pin(0)
BIN0_0
-
U/D counter ch.0 BIN input pin(0)
P037
-
General-purpose I/O port
A09
-
External Bus address bit9 output pin
OCU6_1
-
TOT6_0
-
Reload timer ch.6 output pin(0)
ZIN0_0
-
U/D counter ch.0 ZIN input pin(0)
P174
-
TRG8_1
-
P175
-
TRG9_1
-
A
A
A
A
Serial chip select 8 I/O pin(0)
Output compare ch.7 output pin(1)
Output compare ch.6 output pin(1)
General-purpose I/O port
PPG trigger 8 input pin(1)
General-purpose I/O port
PPG trigger 9 input pin(1)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
23
24
25
26
27
28
-
176
29
30
31
32
33
34
-
208
33
34
35
36
37
38
39
BGA
416
T2
U1
Pin Name
Polarity
Pin Number
P040
-
General-purpose I/O port
A10
-
External Bus address bit10 output pin
PPG23_1
-
TOT7_0
-
AIN1_0
-
SIN0_1
-
P041
-
A11
-
SIN9_0
-
ICU9_1
-
External Bus address bit11 output pin
Multi-function serial ch.9 serial data input
pin(0)
Input capture ch.9 input pin(1)
BIN1_0
-
U/D counter ch.1 BIN input pin(0)
INT12_0
-
INT12 external interrupt input pin(0)
P042
-
General-purpose I/O port
A12
-
SOT9_0
-
AN47
-
External Bus address bit12 output pin
Multi-function serial ch.9 serial data output
pin(0)
ADC analog 47 input pin
U2
V1
V2
PPG ch.23 output pin(1)
A
Reload timer ch.7 output pin(0)
U/D counter ch.1 AIN input pin(0)
Multi-function serial ch.0 serial data input
pin(1)
General-purpose I/O port
I
B
ICU8_1
-
Input capture ch.8 input pin(1)
-
PPG trigger 0 input pin(1)
ZIN1_0
-
U/D counter ch.1 ZIN input pin(0)
P043
-
General-purpose I/O port
A13
-
ICU7_1
-
TRG1_1
-
PPG trigger 1 input pin(1)
P044
-
General-purpose I/O port
A14
-
External Bus address bit14 output pin
SCS9_0
-
ICU6_1
-
Input capture ch.6 input pin(1)
TRG2_1
-
PPG trigger 2 input pin(1)
P045
-
General-purpose I/O port
A
A
External Bus address bit13 output pin
Input capture ch.7 input pin(1)
Serial chip select 9 I/O pin(0)
A15
-
External Bus address bit15 output pin
SCK9_0
-
Multi-function serial ch.9 clock I/O pin(0)
AN46
-
ICU5_1
-
Input capture ch.5 input pin(1)
TRG3_1
-
PPG trigger 3 input pin(1)
TOT1_2
-
Reload timer ch.1 output pin(2)
P204
-
SCK13_0/SCL13
-
AN59
-
General-purpose I/O port
Multi-function serial ch.13 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 59 input pin
PPG48_0
-
PPG ch.48 output pin(0)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
2
Function*
TRG0_1
W1
V3
I/O
circuit
1
type*
G
Q
ADC analog 46 input pin
23
D a t a S h e e t
144
-
-
-
29
-
30
-
31
32
-
176
-
-
-
35
36
37
38
39
40
-
24
CONFIDENTIAL
208
40
41
42
43
44
45
46
47
48
-
BGA
416
V4
W4
Y4
W2
AA3
Y1
AA4
Y2
AA1
AB3
AB4
Pin Name
Polarity
Pin Number
P205
-
SOT13_0/SDA13
-
AN58
-
PPG49_0
-
PPG ch.49 output pin(0)
AIN2_0
-
U/D counter ch.2 AIN input pin(0)
P206
-
SIN13_0
-
AN57
-
General-purpose I/O port
Multi-function serial ch.13 serial data input
pin(0)
ADC analog 57 input pin
BIN2_0
-
U/D counter ch.2 BIN input pin(0)
INT17_0
-
INT17 external interrupt input pin(0)
P207
-
General-purpose I/O port
SCS13_0
-
AN56
-
ZIN2_0
-
U/D counter ch.2 ZIN input pin(0)
P046
-
General-purpose I/O port
I/O
circuit
1
type*
Q
G
B
2
Function*
General-purpose I/O port
Multi-function serial ch.13 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 58 input pin
Serial chip select 13 I/O pin(0)
ADC analog 56 input pin
A16
-
ICU4_1
-
TRG4_1
-
P176
-
TRG10_0
-
P047
-
General-purpose I/O port
A17
-
External Bus address bit17 output pin
AN45
-
TRG8_0
-
TIN3_2
-
SOT0_1
-
P177
-
TRG11_0
-
P050
-
A
External Bus address bit16 output pin
Input capture ch.4 input pin(1)
PPG trigger 4 input pin(1)
A
General-purpose I/O port
PPG trigger 10 input pin(0)
ADC analog 45 input pin
B
A
PPG trigger 8 input pin(0)
Reload timer ch.3 event input pin(2)
Multi-function serial ch.0 serial data output
pin(1)
General-purpose I/O port
PPG trigger 11 input pin(0)
General-purpose I/O port
A18
-
TRG5_1
-
PPG33_0
-
PPG ch.33 output pin(0)
P051
-
General-purpose I/O port
A19
-
TRG9_0
-
TX5(128)_0
-
P250
-
PPG66_0
-
P251
-
PPG67_0
-
A
A
External Bus address bit18 output pin
PPG trigger 5 input pin(1)
External Bus address bit19 output pin
PPG trigger 9 input pin(0)
CAN transmission data 5 output pin(0)
A
A
General-purpose I/O port
PPG ch.66 output pin(0)
General-purpose I/O port
PPG ch.67 output pin(0)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
176
208
BGA
416
Pin Name
Polarity
Pin Number
P052
-
I/O
circuit
1
type*
General-purpose I/O port
A20
33
34
35
41
42
43
49
50
51
AA2
AB1
AB2
2
Function*
External Bus address bit20 output pin
PPG34_0
-
INT14_0
-
R
PPG ch.34 output pin(0)
INT14 external interrupt input pin(0)
RX5(128)_0
-
CAN reception data 5 input pin(0)
P053
-
General-purpose I/O port
External Bus address bit21 output pin
A21
-
AN44
-
PPG35_0
-
INT14_1
-
INT14 external interrupt input pin(1)
SCK0_1
-
Multi-function serial ch.0 clock I/O pin(1)
P054
-
General-purpose I/O port
SYSCLK
-
PPG36_0
-
B
A
ADC analog 44 input pin
PPG ch.35 output pin(0)
External Bus system clock output pin
PPG ch.36 output pin(0)
-
-
-
AC1
P252
-
A
General-purpose I/O port
-
-
-
AC2
P253
-
A
General-purpose I/O port
P254
-
PPG68_0
-
P255
-
PPG69_0
-
P055
-
General-purpose I/O port
CS2X
-
SIN10_0
-
AN43
-
External Bus chip select 2 output pin
Multi-function serial ch.10 serial data input
pin(0)
ADC analog 43 input pin
PPG37_0
-
PPG ch.37 output pin(0)
TIN4_1
-
Reload timer ch.4 event input pin(1)
-
38
-
46
-
54
AE4
AD5
AF3
-
47
55
AC5
-
48
56
AC6
39
-
49
-
57
-
AE3
AD6
P180
-
PPG40_0
-
A
G
A
General-purpose I/O port
PPG ch.68 output pin(0)
General-purpose I/O port
PPG ch.69 output pin(0)
General-purpose I/O port
PPG ch.40 output pin(0)
P181
-
PPG41_0
-
P056
-
General-purpose I/O port
A
General-purpose I/O port
PPG ch.41 output pin(0)
CS3X
-
External Bus chip select 3 output pin
ICU9_0
-
Input capture ch.9 input pin(0)
PPG0_1
-
ICU0_1
-
Input capture ch.0 input pin(1)
TIN5_1
-
DTTI_2
-
P256
-
Reload timer ch.5 event input pin(1)
Waveform generator ch.0 to ch.5 input
pin(2)
General-purpose I/O port
PPG66_1
-
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
A
A
A
PPG ch.0 output pin(1)
PPG ch.66 output pin(1)
25
D a t a S h e e t
144
41
-
-
-
-
-
46
176
51
56
-
-
-
-
57
26
CONFIDENTIAL
208
59
64
65
66
67
68
69
BGA
416
AE5
AC7
AE6
AC8
AE7
AD8
AE8
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
2
Function*
P057
-
General-purpose I/O port
RDY_0
-
External Bus RDY input pin (0)
SCK10_1
-
Multi-function serial ch.10 clock I/O pin(1)
AN42
-
ADC analog 42 input pin
ICU8_0
-
TRG0_2
-
G
PPG trigger 0 input pin(2)
PPG1_1
-
PPG ch.1 output pin(1)
ICU1_1
-
Input capture ch.1 input pin(1)
TIN6_1
-
Reload timer ch.6 event input pin(1)
P182
-
PPG42_0
-
P210
-
SCK14_0/SCL14
-
AN55
-
PPG50_0
-
PPG ch.50 output pin(0)
AIN2_1
-
U/D counter ch.2 AIN input pin(1)
P211
-
SOT14_0/SDA14
-
AN54
-
General-purpose I/O port
Multi-function serial ch.14 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 54 input pin
PPG51_0
-
PPG ch.51 output pin(0)
BIN2_1
-
U/D counter ch.2 BIN input pin(1)
P212
-
SIN14_0
-
General-purpose I/O port
Multi-function serial ch.14 serial data input
pin(0)
ADC analog 53 input pin
A
Q
Q
Input capture ch.8 input pin(0)
General-purpose I/O port
PPG ch.42 output pin(0)
General-purpose I/O port
Multi-function serial ch.14 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 55 input pin
AN53
-
FRCK6_0
-
Free-run timer 6 clock input pin(0)
G
ZIN2_1
-
U/D counter ch.2 ZIN input pin(1)
INT18_0
-
INT18 external interrupt input pin(0)
P213
-
General-purpose I/O port
SCS14_0
-
Serial chip select 14 I/O pin(0)
AN52
-
FRCK7_0
-
B
Free-run timer 7 clock input pin(0)
INT17_1
-
INT17 external interrupt input pin(1)
P060
-
General-purpose I/O port
SCS10_0
-
Serial chip select 10 I/O pin(0)
PPG2_1
-
A
ADC analog 52 input pin
PPG ch.2 output pin(1)
ICU2_1
-
TOT5_1
-
Input capture ch.2 input pin(1)
Reload timer ch.5 output pin(1)
INT13_0
-
INT13 external interrupt input pin(0)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
47
48
49
-
50
51
176
58
59
60
61
62
63
208
70
71
72
73
74
75
BGA
416
AC10
AD11
AC11
AF12
AE12
AC12
-
64
76
AF13
-
65
77
AE13
52
66
78
AC13
Pin Name
Polarity
Pin Number
P061
-
SOT10_1
-
AN41
-
2
Function*
General-purpose I/O port
Multi-function serial ch.10 serial data output
pin(1)
ADC analog 41 input pin
ICU6_0
-
PPG3_1
-
PPG ch.3 output pin(1)
B
Input capture ch.6 input pin(0)
ICU3_1
-
Input capture ch.3 input pin(1)
TOT6_1
-
Reload timer ch.6 output pin(1)
INT13_1
-
INT13 external interrupt input pin(1)
P062
-
General-purpose I/O port
SCS10_1
-
Serial chip select 10 I/O pin(1)
SCS40_0
-
Serial chip select 40 I/O pin(0)
AN40
-
B
ADC analog 40 input pin
PPG4_1
-
FRCK0_0
-
Free-run timer 0 clock input pin(0)
TOT7_1
-
Reload timer ch.7 output pin(1)
ZIN1_1
-
U/D counter ch.1 ZIN input pin(1)
PPG ch.4 output pin(1)
P063
-
General-purpose I/O port
SCS41_0
-
Serial chip select 41 output pin(0)
AN39
-
PPG5_1
-
FRCK1_0
-
Free-run timer 1 clock input pin(0)
BIN1_1
-
U/D counter ch.1 BIN input pin(1)
P183
-
PPG43_0
-
B
A
ADC analog 39 input pin
PPG ch.5 output pin(1)
General-purpose I/O port
PPG ch.43 output pin(0)
P064
-
General-purpose I/O port
SCS42_0
-
Serial chip select 42 output pin(0)
AN38
-
FRCK2_0
-
B
ADC analog 38 input pin
Free-run timer 2 clock input pin(0)
AIN1_1
-
U/D counter ch.1 AIN input pin(1)
PPG43_1
-
PPG ch.43 output pin(1)
P065
-
General-purpose I/O port
SCS43_0
-
FRCK3_0
-
Serial chip select 43 output pin(0)
A
Free-run timer 3 clock input pin(0)
ZIN0_1
-
U/D counter ch.0 ZIN input pin(1)
PPG44_1
-
PPG ch.44 output pin(1)
P184
-
PPG44_0
-
A
General-purpose I/O port
PPG ch.44 output pin(0)
P185
-
PPG45_0
-
P066
-
SOT4_2
-
SCS3_0
-
AN37
-
ADC analog 37 input pin
FRCK4_0
-
Free-run timer 4 clock input pin(0)
BIN0_1
-
U/D counter ch.0 BIN input pin(1)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
I/O
circuit
1
type*
A
B
General-purpose I/O port
PPG ch.45 output pin(0)
General-purpose I/O port
Multi-function serial ch.4 serial data output
pin(2)
Serial chip select 3 I/O pin(0)
27
D a t a S h e e t
144
53
54
55
56
57
-
176
67
68
69
70
71
72
208
79
80
81
82
83
84
BGA
416
AF14
AE14
AD14
AC14
AF15
AE15
AC15
AF16
-
73
85
AE16
58
74
86
AC16
-
-
28
CONFIDENTIAL
87
AF18
Pin Name
Polarity
Pin Number
P067
-
AN36
-
FRCK5_0
-
AIN0_1
-
P070
-
ICU0_2
-
I/O
circuit
1
type*
2
Function*
General-purpose I/O port
B
ADC analog 36 input pin
Free-run timer 5 clock input pin(0)
U/D counter ch.0 AIN input pin(1)
A
General-purpose I/O port
Input capture ch.0 input pin(2)
P071
-
General-purpose I/O port
SCK4_2
-
Multi-function serial ch.4 clock I/O pin(2)
AN35
-
ICU1_2
-
G
Input capture ch.1 input pin(2)
MONCLK
-
Clock monitor output pin
P072
-
SIN4_0
-
AN34
-
General-purpose I/O port
Multi-function serial ch.4 serial data input
pin(0)
ADC analog 34 input pin
ICU2_2
-
Input capture ch.2 input pin(2)
INT5_0
-
INT5 external interrupt input pin(0)
P073
-
SOT4_0/SDA4
-
AN33
-
General-purpose I/O port
Multi-function serial ch.4 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 33 input pin
ICU3_2
-
Input capture ch.3 input pin(2)
P262
-
PPG70_0
-
P263
-
PPG71_0
-
P186
-
PPG46_0
-
P187
-
PPG47_0
-
P074
-
G
D
A
A
A
A
ADC analog 35 input pin
General-purpose I/O port
PPG ch.70 output pin(0)
General-purpose I/O port
PPG ch.71 output pin(0)
General-purpose I/O port
PPG ch.46 output pin(0)
General-purpose I/O port
PPG ch.47 output pin(0)
SCK4_0/SCL4
-
P214
-
SCK15_0/SCL15
-
AN51
-
General-purpose I/O port
Multi-function serial ch.4 clock I/O pin(0) /
I2C bus serial clock I/O pin
General-purpose I/O port
Multi-function serial ch.15 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 51 input pin
PPG52_0
-
PPG ch.52 output pin(0)
E
Q
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
-
-
-
59
60
176
-
-
-
75
76
208
88
89
90
91
92
BGA
416
SOT15_0/SDA15
-
AN50
-
FRCK8_0
-
Free-run timer 8 clock input pin(0)
PPG53_0
-
PPG ch.53 output pin(0)
P216
-
SIN15_0
-
AN49
-
General-purpose I/O port
Multi-function serial ch.15 serial data input
pin(0)
ADC analog 49 input pin
FRCK9_0
-
Free-run timer 9 clock input pin(0)
TRG12_1
-
PPG trigger 12 input pin(1)
INT19_0
-
INT19 external interrupt input pin(0)
AE18
AD17
AF20
-
-
-
AE19
-
-
-
AC17
62
78
94
AF21
Q
G
2
Function*
General-purpose I/O port
Multi-function serial ch.15 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 50 input pin
P217
-
General-purpose I/O port
-
Serial chip select 15 I/O pin(0)
AN48
-
FRCK10_0
-
Free-run timer 10 clock input pin(0)
TRG13_1
-
PPG trigger 13 input pin(1)
P075
-
SIN3_0
-
INT4_0
-
General-purpose I/O port
Multi-function serial ch.3 serial data input
pin(0)
INT4 external interrupt input pin(0)
RX5(128)_1
-
CAN reception data 5 input pin(1)
P076
-
SOT3_0/SDA3
-
TX5(128)_1
-
General-purpose I/O port
Multi-function serial ch.3 serial data output
pin(0)/I2C bus serial data I/O pin
CAN transmission data 5 output pin(1)
P077
-
SCK3_0/SCL3
-
P264
-
PPG72_0
-
P265
-
PPG73_0
-
B
F
P
E
A
A
ADC analog 48 input pin
General-purpose I/O port
Multi-function serial ch.3 clock I/O pin(0)/
I2C bus serial clock I/O pin
General-purpose I/O port
PPG ch.72 output pin(0)
General-purpose I/O port
PPG ch.73 output pin(0)
P152
-
SCS53_0
-
P153
-
SCK5_0/SCL5
-
AN32
-
FRCK1_1
-
Free-run timer 1 clock input pin(1)
INT4_1
-
INT4 external interrupt input pin(1)
AE20
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
I/O
circuit
1
type*
SCS15_0
AF19
93
95
-
AE17
77
79
P215
AF17
61
63
Pin Name
Polarity
Pin Number
A
G
General-purpose I/O port
Serial chip select 53 output pin(0)
General-purpose I/O port
Multi-function serial ch.5 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 32 input pin
29
D a t a S h e e t
144
176
208
BGA
416
64
80
96
AC18
65
81
97
AF22
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
2
Function*
P080
-
SCS52_0
-
General-purpose I/O port
PPG0_0
-
PPG ch.0 output pin(0)
P081
-
SOT5_0/SDA5
-
AN0
-
General-purpose I/O port
Multi-function serial ch.5 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 0 input pin
PPG1_0
-
PPG ch.1 output pin(0)
A
G
Serial chip select 52 output pin(0)
-
-
-
AE21
TDO
-
W
JTAG test data output
-
-
-
AD20
TDI
-
V
JTAG test data input
P082
-
SIN5_0
-
AN1
-
General-purpose I/O port
Multi-function serial ch.5 serial data input
pin(0)
ADC analog 1 input pin
PPG2_0
-
PPG ch.2 output pin(0)
66
82
98
AC19
G
-
-
-
AE22
TRST
-
V
JTAG test reset input
-
-
-
AC20
TCK
-
V
JTAG test clock input
-
-
-
AE23
TMS
-
V
JTAG test mode state input
P083
-
SCS50_0
-
AN2
-
PPG3_0
-
PPG ch.3 output pin(0)
P084
-
General-purpose I/O port
SCS51_0
-
AN3
-
PPG4_0
-
P085
-
PPG5_0
-
P086
-
DAO1
-
PPG6_0
-
PPG ch.6 output pin(0)
P087
-
General-purpose I/O port
67
68
69
70
71
-
83
84
85
86
87
90
91
30
CONFIDENTIAL
99
100
101
102
103
106
107
AC21
AF23
AD23
AC22
AD25
AC24
AB23
AD26
AC25
DAO0
-
PPG7_0
-
INT8_0
-
P266
-
PPG74_0
-
P267
-
PPG75_0
-
P190
-
TIN0_1
-
P191
-
TIN1_1
-
General-purpose I/O port
B
B
Serial chip select 50 I/O pin(0)
ADC analog 2 input pin
Serial chip select 51 output pin(0)
ADC analog 3 input pin
PPG ch.4 output pin(0)
A
General-purpose I/O port
PPG ch.5 output pin(0)
General-purpose I/O port
C
C
DAC analog 1 output pin
DAC analog 0 output pin
PPG ch.7 output pin(0)
INT8 external interrupt input pin(0)
A
A
A
A
General-purpose I/O port
PPG ch.74 output pin(0)
General-purpose I/O port
PPG ch.75 output pin(0)
General-purpose I/O port
Reload timer ch.0 event input pin(1)
General-purpose I/O port
Reload timer ch.1 event input pin(1)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
74
176
92
208
108
BGA
416
AB24
-
-
-
AA23
-
-
-
AC26
75
76
-
93
94
95
109
110
111
AB25
Y23
AB26
-
-
-
AA25
-
-
-
Y24
77
78
79
96
97
98
112
113
114
Pin Name
Polarity
Pin Number
P090
-
AN4
-
ICU0_0
-
TIN2_1
-
P270
-
PPG76_0
-
Y25
General-purpose I/O port
B
ADC analog 4 input pin
Input capture ch.0 input pin(0)
Reload timer ch.2 event input pin(1)
A
General-purpose I/O port
PPG ch.76 output pin(0)
P271
-
P091
-
General-purpose I/O port
AN5
-
ADC analog 5 input pin
PPG41_1
-
ICU1_0
-
Input capture ch.1 input pin(0)
TIN3_1
-
Reload timer ch.3 event input pin(1)
P092
-
General-purpose I/O port
AN6
-
ADC analog 6 input pin
PPG40_1
-
ICU2_0
-
Input capture ch.2 input pin(0)
TOT0_1
-
Reload timer ch.0 output pin(1)
P192
-
General-purpose I/O port
PPG24_1
-
TOT1_1
-
P272
-
PPG78_0
-
P273
-
PPG79_0
-
A
B
B
A
General-purpose I/O port
PPG ch.77 output pin(0)
PPG ch.41 output pin(1)
PPG ch.40 output pin(1)
PPG ch.24 output pin(1)
Reload timer ch.1 output pin(1)
A
A
General-purpose I/O port
PPG ch.78 output pin(0)
General-purpose I/O port
PPG ch.79 output pin(0)
P093
-
General-purpose I/O port
TX0(128)_1
-
SIN11_0
-
CAN transmission data 0 output pin(1)
Multi-function serial ch.11 serial data input
pin(0)
ADC analog 7 input pin
AN7
-
ICU4_2
-
Input capture ch.4 input pin(2)
PPG16_1
-
PPG ch.16 output pin(1)
J
ICU3_0
-
Input capture ch.3 input pin(0)
TOT2_1
-
Reload timer ch.2 output pin(1)
P094
-
General-purpose I/O port
AN8
-
B
ADC analog 8 input pin
ICU4_0
-
TOT3_1
-
Reload timer ch.3 output pin(1)
General-purpose I/O port
P095
-
TX0(128)_0
-
SCS11_0
-
AN9
-
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
2
Function*
PPG77_0
W23
AA26
I/O
circuit
1
type*
B
Input capture ch.4 input pin(0)
CAN transmission data 0 output pin(0)
Serial chip select 11 I/O pin(0)
ADC analog 9 input pin
31
D a t a S h e e t
144
80
81
-
-
-
-
-
85
86
176
99
100
-
-
-
-
-
104
105
32
CONFIDENTIAL
208
115
116
117
118
119
-
-
123
124
BGA
416
V23
Y26
W25
U23
V25
U24
U25
T25
T23
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
2
Function*
P096
-
General-purpose I/O port
RX0(128)_0
-
SOT11_0/SDA11
-
AN10
-
CAN reception data 0 input pin(0)
Multi-function serial ch.11 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 10 input pin
INT0_0
-
INT0 external interrupt input pin(0)
P097
-
SCK11_0/SCL11
-
AN11
-
General-purpose I/O port
Multi-function serial ch.11 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 11 input pin
ICU5_0
-
Input capture ch.5 input pin(0)
PPG17_1
-
PPG ch.17 output pin(1)
P220
-
SCK16_0/SCL16
-
ICU10_0
-
General-purpose I/O port
Multi-function serial ch.16 clock I/O pin(0)/
I2C bus serial clock I/O pin
Input capture ch.10 input pin(0)
PPG48_1
-
PPG ch.48 output pin(1)
P221
-
SOT16_0/SDA16
-
ICU11_0
-
General-purpose I/O port
Multi-function serial ch.16 serial data output
pin(0)/I2C bus serial data I/O pin
Input capture ch.11 input pin(0)
PPG49_1
-
PPG ch.49 output pin(1)
P222
-
SIN16_0
-
PPG54_0
-
General-purpose I/O port
Multi-function serial ch.16 serial data input
pin(0)
PPG ch.54 output pin(0)
INT20_0
-
INT20 external interrupt input pin(0)
P275
-
PPG67_1
-
P276
-
TRG16_1
-
PPG86_1
-
PPG ch.86 output pin(1)
P100
-
SCK7_0/SCL7
-
AN12
-
General-purpose I/O port
Multi-function serial ch.7 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 12 input pin
PPG8_0
-
PPG ch.8 output pin(0)
P101
-
SOT7_0/SDA7
-
AN13
-
General-purpose I/O port
Multi-function serial ch.7 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 13 input pin
PPG9_0
-
PPG ch.9 output pin(0)
TX3(128)_0
-
CAN transmission data 3 output pin(0)
G
G
P
P
I
A
General-purpose I/O port
PPG ch.67 output pin(1)
General-purpose I/O port
A
G
G
PPG trigger 16 input pin(1)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
87
88
89
90
91
92
176
106
107
108
109
110
111
208
125
126
127
128
129
130
BGA
416
Pin Name
Polarity
Pin Number
P102
-
SIN7_0
-
AN14
-
PPG10_0
-
PPG ch.10 output pin(0)
INT10_0
-
INT10 external interrupt input pin(0)
RX3(128)_0
-
CAN reception data 3 input pin(0)
P103
-
General-purpose I/O port
SCS73_0
-
AN15
-
PPG11_0
-
PPG ch.11 output pin(0)
P104
-
General-purpose I/O port
SCS72_0
-
R26
R25
R23
P25
P24
P23
-
112
131
P26
93
113
132
N23
I/O
circuit
1
type*
G
H
H
2
Function*
General-purpose I/O port
Multi-function serial ch.7 serial data input
pin(0)
ADC analog 14 input pin
Serial chip select 73 output pin(0)
ADC analog 15 input pin
Serial chip select 72 output pin(0)
AN16
-
PPG12_0
-
PPG ch.12 output pin(0)
General-purpose I/O port
P105
-
SCS71_0
-
H
ADC analog 16 input pin
Serial chip select 71 output pin(0)
AN17
-
PPG13_0
-
PPG ch.13 output pin(0)
General-purpose I/O port
P106
-
SCS70_0
-
H
ADC analog 17 input pin
Serial chip select 70 I/O pin(0)
AN18
-
PPG14_0
-
PPG ch.14 output pin(0)
General-purpose I/O port
P107
-
AN19
-
PPG15_0
-
TXENA_1
-
P193
-
PPG25_1
-
P154
-
AN20
-
TXDA_1
-
P155
-
AN21
-
U
ADC analog 18 input pin
ADC analog 19 input pin
PPG ch.15 output pin(0)
FlexRay ch.A operation enable output(1)
A
General-purpose I/O port
PPG ch.25 output pin(1)
General-purpose I/O port
U
ADC analog 20 input pin
FlexRay ch.A data output(1)
General-purpose I/O port
94
114
133
L26
RXDA_1
-
95
115
136
L25
NMIX
N
P277
-
-
-
-
L24
TRG17_1
-
PPG87_1
-
PPG ch.87 output pin(1)
P110
-
General-purpose I/O port
TX1(128)_0
-
SCS63_0
-
AN22
-
96
116
137
L23
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
S
ADC analog 21 input pin
FlexRay ch.A data input(1)
M
Non-maskable interrupt input pin
General-purpose I/O port
A
B
PPG trigger 17 input pin(1)
CAN transmission data 1 output pin(0)
Serial chip select 63 output pin(0)
ADC analog 22 input pin
33
D a t a S h e e t
144
97
98
99
-
-
176
117
118
119
120
121
208
138
139
140
141
142
BGA
416
J26
K26
K25
H26
J25
-
-
-
G26
-
-
-
H25
100
101
102
122
123
124
34
CONFIDENTIAL
143
144
145
K23
F26
G25
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
2
Function*
P111
-
General-purpose I/O port
RX1(128)_0
-
CAN reception data 1 input pin(0)
SCS62_0
-
AN23
-
ADC analog 23 input pin
INT1_0
-
INT1 external interrupt input pin(0)
P112
-
General-purpose I/O port
AN24
-
PPG16_0
-
G
Serial chip select 62 output pin(0)
ADC analog 24 input pin
U
PPG ch.16 output pin(0)
RTO0_0
-
Waveform generator ch.0 output pin(0)
TXENB_1
-
FlexRay ch.B operation enable output(1)
P113
-
General-purpose I/O port
AN25
-
ADC analog 25 input pin
PPG17_0
-
RTO1_0
-
Waveform generator ch.1 output pin(0)
TXDB_1
-
FlexRay ch.B data output(1)
U
PPG ch.17 output pin(0)
P194
-
FRCK5_1
-
PPG26_1
-
PPG ch.26 output pin(1)
P195
-
General-purpose I/O port
FRCK4_1
-
PPG27_1
-
P280
-
PPG80_0
-
P281
-
PPG81_0
-
General-purpose I/O port
A
A
Free-run timer 5 clock input pin(1)
Free-run timer 4 clock input pin(1)
PPG ch.27 output pin(1)
A
A
General-purpose I/O port
PPG ch.80 output pin(0)
General-purpose I/O port
PPG ch.81 output pin(0)
P114
-
General-purpose I/O port
SCS61_0
-
Serial chip select 61 output pin(0)
AN26
-
PPG18_0
-
S
ADC analog 26 input pin
PPG ch.18 output pin(0)
RTO2_0
-
Waveform generator ch.2 output pin(0)
RXDB_1
-
FlexRay ch.B data input(1)
P115
-
General-purpose I/O port
RX1(128)_1
-
SOT6_0/SDA6
-
AN27
-
CAN reception data 1 input pin(1)
Multi-function serial ch.6 serial data output
pin(0)/I2C bus serial data I/O pin
ADC analog 27 input pin
PPG19_0
-
PPG ch.19 output pin(0)
RTO3_0
-
Waveform generator ch.3 output pin(0)
INT1_1
-
INT1 external interrupt input pin(1)
P116
-
SCK6_0/SCL6
-
AN28
-
General-purpose I/O port
Multi-function serial ch.6 clock I/O pin(0)/
I2C bus serial clock I/O pin
ADC analog 28 input pin
PPG20_0
-
PPG ch.20 output pin(0)
RTO4_0
-
Waveform generator ch.4 output pin(0)
G
G
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
103
-
176
125
126
208
146
147
BGA
416
Pin Name
Polarity
Pin Number
-
-
-
E26
-
-
-
F25
P117
-
General-purpose I/O port
-
Serial chip select 60 I/O pin(0)
AN29
-
PPG21_0
-
PPG ch.21 output pin(0)
RTO5_0
-
Waveform generator ch.5 output pin(0)
P196
-
General-purpose I/O port
FRCK3_1
-
PPG28_1
-
P282
-
PPG82_0
-
P283
-
PPG83_0
-
P120
-
B
A
105
106
-
-
-
-
127
128
129
-
-
-
130
148
149
150
151
152
153
154
H23
D26
D25
E24
F23
A
A
General-purpose I/O port
PPG ch.82 output pin(0)
General-purpose I/O port
PPG ch.83 output pin(0)
General-purpose I/O port
ADC analog 30 input pin
-
PPG22_0
-
INT9_0
-
INT9 external interrupt input pin(0)
RX4(128)_0
-
CAN reception data 4 input pin(0)
P121
-
General-purpose I/O port
S
Output compare ch.6 output pin(0)
PPG ch.22 output pin(0)
OCU7_0
-
PPG23_0
-
TX4(128)_0
-
CAN transmission data 4 output pin(0)
P122
-
SIN6_0
-
AN31
-
General-purpose I/O port
Multi-function serial ch.6 serial data input
pin(0)
ADC analog 31 input pin
OCU8_0
-
Output compare ch.8 output pin(0)
INT9_1
-
INT9 external interrupt input pin(1)
P225
-
SCK17_0/SCL17
-
P
PPG55_0
-
General-purpose I/O port
Multi-function serial ch.17 clock I/O pin(0)/
I2C bus serial clock I/O pin
PPG ch.55 output pin(0)
P226
-
SOT17_0/SDA17
-
P
PPG56_0
-
General-purpose I/O port
Multi-function serial ch.17 serial data output
pin(0)/I2C bus serial data I/O pin
PPG ch.56 output pin(0)
P227
-
SIN17_0
-
PPG57_0
-
General-purpose I/O port
Multi-function serial ch.17 serial data input
pin(0)
PPG ch.57 output pin(0)
INT21_0
-
INT21 external interrupt input pin(0)
P197
-
PPG29_1
-
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Free-run timer 3 clock input pin(1)
OCU6_0
E25
G23
ADC analog 29 input pin
PPG ch.28 output pin(1)
AN30
104
2
Function*
SCS60_0
H24
J23
I/O
circuit
1
type*
A
J
I
A
Output compare ch.7 output pin(0)
PPG ch.23 output pin(0)
General-purpose I/O port
PPG ch.29 output pin(1)
35
D a t a S h e e t
144
176
208
BGA
416
107
131
155
E23
110
134
158
C26
-
-
-
C25
-
-
-
D22
-
135
159
C22
-
136
160
D21
-
-
-
B22
-
-
-
C21
111
137
161
-
-
-
-
D20
112
138
162
-
-
-
-
-
-
-
-
-
-
-
36
CONFIDENTIAL
-
163
164
165
166
A22
B21
C20
D19
C19
Pin Name
Polarity
Pin Number
P123
-
OCU9_0
-
STOPWT_1
-
DEBUGIF
-
P284
-
PPG84_0
-
P285
-
PPG85_0
-
P160
-
PPG30_1
-
P161
-
PPG31_1
-
P286
-
TRG18_0
-
P287
-
TRG19_0
-
P124
-
OCU10_0
-
TRST
-
P124
-
OCU10_0
-
I/O
circuit
1
type*
2
Function*
General-purpose I/O port
R
Output compare ch.9 output pin(0)
FlexRay stopwatch input(1)
L
A
A
A
A
A
A
DEBUGIF I/O pin for debug (OCD)
General-purpose I/O port
PPG ch.84 output pin(0)
General-purpose I/O port
PPG ch.85 output pin(0)
General-purpose I/O port
PPG ch.30 output pin(1)
General-purpose I/O port
PPG ch.31 output pin(1)
General-purpose I/O port
PPG trigger 18 input pin(0)
General-purpose I/O port
PPG trigger 19 input pin(0)
General-purpose I/O port
A
Output compare ch.10 output pin(0)
JTAG test reset input
A
General-purpose I/O port
Output compare ch.10 output pin(0)
P125
-
OCU11_0
-
TMS
-
P125
-
OCU11_0
-
P230
-
SCK18_0/SCL18
-
OCU12_0
-
General-purpose I/O port
Multi-function serial ch.18 clock I/O pin(0)/
I2C bus serial clock I/O pin
Output compare ch.12 output pin(0)
PPG58_0
-
PPG ch.58 output pin(0)
P231
-
SOT18_0/SDA18
-
OCU13_0
-
General-purpose I/O port
Multi-function serial ch.18 serial data output
pin(0)/I2C bus serial data I/O pin
Output compare ch.13 output pin(0)
PPG59_0
-
PPG ch.59 output pin(0)
P232
-
SIN18_0
-
PPG60_0
-
General-purpose I/O port
Multi-function serial ch.18 serial data input
pin(0)
PPG ch.60 output pin(0)
INT22_0
-
INT22 external interrupt input pin(0)
P233
-
General-purpose I/O port
SCS18_0
-
PPG61_0
-
INT16_1
-
General-purpose I/O port
A
Output compare ch.11 output pin(0)
JTAG test mode state input
A
P
P
I
A
General-purpose I/O port
Output compare ch.11 output pin(0)
Serial chip select 18 I/O pin(0)
PPG ch.61 output pin(0)
INT16 external interrupt input pin(1)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
176
208
BGA
416
-
-
-
D18
-
113
-
114
-
115
-
-
139
-
140
-
141
142
-
167
-
168
-
169
170
B18
-
C18
-
C17
-
D17
C16
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
2
Function*
P290
-
TRG20_0
-
General-purpose I/O port
PPG64_1
-
PPG ch.64 output pin(1)
P291
-
General-purpose I/O port
TRG21_0
-
PPG65_1
-
PPG ch.65 output pin(1)
P126
-
SIN0_0
-
INT6_0
-
General-purpose I/O port
Multi-function serial ch.0 serial data input
pin(0)
INT6 external interrupt input pin(0)
A
A
F
PPG trigger 20 input pin(0)
PPG trigger 21 input pin(0)
TDI
-
JTAG test data input
P126
-
SIN0_0
-
F
INT6_0
-
General-purpose I/O port
Multi-function serial ch.0 serial data input
pin(0)
INT6 external interrupt input pin(0)
P127
-
SOT0_0
-
A
TDO
-
General-purpose I/O port
Multi-function serial ch.0 serial data output
pin(0)
JTAG test data output
P127
-
SOT0_0
-
P130
-
SCK0_0
-
TCK
-
P130
-
SCK0_0
-
P162
-
TRG5_2
-
P163
-
A
F
General-purpose I/O port
Multi-function serial ch.0 serial data output
pin(0)
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin(0)
JTAG test clock input
F
A
Multi-function serial ch.0 clock I/O pin(0)
General-purpose I/O port
PPG trigger 5 input pin(2)
General-purpose I/O port
-
143
171
D16
TRG6_2
-
116
144
172
B23
MD0
-
K
Mode pin 0
117
145
173
A23
MD1
-
K
Mode pin 1
118
146
174
A20
X0
-
N
Main clock oscillation input pin
119
147
175
A19
X1
-
N
Main clock oscillation output pin
P135
-
121
149
177
A17
122
150
178
A16
123
151
179
B15
126
154
182
D15
PPG trigger 6 input pin(2)
X1A
-
O
General-purpose I/O port
Waveform generator ch.0 to ch.5 input
pin(0)
Sub clock oscillation output pin
P136
-
A
General-purpose I/O port
X0A
-
O
Sub clock oscillation input pin
RSTX
N
M
External reset input pin
P133
-
TX2(128)_0
-
DTTI_0
-
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
A
General-purpose I/O port
A
A
General-purpose I/O port
CAN transmission data 2 output pin(0)
37
D a t a S h e e t
144
127
131
132
133
134
135
-
136
-
176
155
159
160
161
162
163
164
165
166
38
CONFIDENTIAL
208
183
187
188
189
190
191
192
193
194
BGA
416
D14
A10
B10
A9
B9
A8
D12
B8
C11
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
2
Function*
P134
-
General-purpose I/O port
RX2(128)_0
-
CAN reception data 2 input pin(0)
SCS1_1
-
ICU7_0
-
Input capture ch.7 input pin(0)
INT7_0
-
INT7 external interrupt input pin(0)
P000
-
General-purpose I/O port
D16
-
SIN1_0
-
TIOA0_1
-
External Bus data bit16 I/O pin
Multi-function serial ch.1 serial data input
pin(0)
Base timer ch.0 TIOA output pin(1)
INT2_0
-
INT2 external interrupt input pin(0)
P001
-
General-purpose I/O port
D17
-
F
F
Serial chip select 1 I/O pin(1)
SOT1_0
-
TIOA1_1
-
External Bus data bit17 I/O pin
Multi-function serial ch.1 serial data output
pin(0)
Base timer ch.1 TIOA I/O pin(1)
P002
-
General-purpose I/O port
R
D18
-
SCK1_0
-
TIOB0_1
-
Base timer ch.0 TIOB input pin(1)
P003
-
General-purpose I/O port
D19
-
SIN2_0
-
TIOB1_1
-
External Bus data bit19 I/O pin
Multi-function serial ch.2 serial data input
pin(0)
Base timer ch.1 TIOB input pin(1)
INT3_0
-
INT3 external interrupt input pin(0)
TXENA_0
-
FlexRay ch.A operation enable output(0)
P004
-
General-purpose I/O port
D20
-
SOT2_0
-
TXDA_0
-
F
T
R
External Bus data bit18 I/O pin
Multi-function serial ch.1 clock I/O pin(0)
External Bus data bit20 I/O pin
Multi-function serial ch.2 serial data output
pin(0)
FlexRay ch.A data output(0)
P164
-
PPG32_1
-
P005
-
General-purpose I/O port
D21
-
External Bus data bit21 I/O pin
SCK2_0
-
ADTG0_1
-
A
F
General-purpose I/O port
PPG ch.32 output pin(1)
Multi-function serial ch.2 clock I/O pin(0)
A/D converter external trigger input pin 0(1)
INT7_1
-
INT7 external interrupt input pin(1)
RXDA_0
-
FlexRay ch.A data input(0)
P165
-
PPG33_1
-
A
General-purpose I/O port
PPG ch.33 output pin(1)
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
137
176
167
208
195
BGA
416
A7
Pin Name
Polarity
Pin Number
P006
-
General-purpose I/O port
D22
-
External Bus data bit22 I/O pin
SCS2_0
-
ADTG1_1
-
I/O
circuit
1
type*
R
2
Function*
Serial chip select 2 I/O pin(0)
A/D converter external trigger input pin 1(1)
INT2_1
-
INT2 external interrupt input pin(1)
TXENB_0
-
FlexRay ch.B operation enable output(0)
P007
-
D23
-
General-purpose I/O port
138
168
196
B7
TXDB_0
-
-
-
-
D11
P292
-
A
General-purpose I/O port
-
-
-
C10
P293
-
A
General-purpose I/O port
P166
-
PPG34_1
-
P010
-
D24
-
RXDB_0
-
FlexRay ch.B data input(0)
P234
-
SCK19_0/SCL19
-
PPG62_0
-
General-purpose I/O port
Multi-function serial ch.19 clock I/O pin(0)/
I2C bus serial clock I/O pin
PPG ch.62 output pin(0)
P235
-
SOT19_0/SDA19
-
PPG63_0
-
General-purpose I/O port
Multi-function serial ch.19 serial data output
pin(0)/I2C bus serial data I/O pin
PPG ch.63 output pin(0)
AIN3_0
-
U/D counter ch.3 AIN input pin(0)
P236
-
SIN19_0
-
TRG14_0
-
General-purpose I/O port
Multi-function serial ch.19 serial data input
pin(0)
PPG trigger 14 input pin(0)
BIN3_0
-
U/D counter ch.3 BIN input pin(0)
INT23_0
-
INT23 external interrupt input pin(0)
P237
-
General-purpose I/O port
-
139
-
-
-
-
140
141
169
170
-
-
-
-
171
172
197
198
199
200
201
202
203
204
D10
A6
C9
D9
D8
D7
B6
A5
External Bus data bit23 I/O pin
FlexRay ch.B data output(0)
A
General-purpose I/O port
PPG ch.34 output pin(1)
General-purpose I/O port
R
P
P
I
External Bus data bit24 I/O pin
SCS19_0
-
TRG15_0
-
ZIN3_0
-
U/D counter ch.3 ZIN input pin(0)
P011
-
General-purpose I/O port
WOT
-
RTC output pin
D25
-
A
Serial chip select 19 I/O pin(0)
PPG trigger 15 input pin(0)
SOT2_1
-
TIOA0_0
-
External Bus data bit25 I/O pin
Multi-function serial ch.2 serial data output
pin(1)
Base timer ch.0 TIOA output pin(0)
INT3_1
-
INT3 external interrupt input pin(1)
P012
-
General-purpose I/O port
D26
-
TIOB0_0
-
STOPWT_0
-
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
R
R
R
External Bus data bit26 I/O pin
Base timer ch.0 TIOB input pin(0)
FlexRay stopwatch input(0)
39
D a t a S h e e t
144
176
208
BGA
416
-
-
-
C6
-
-
-
C5
-
173
205
D6
-
-
-
-
-
-
142
174
206
B5
143
175
207
Pin Name
Polarity
Pin Number
P294
-
PPG86_0
-
P295
-
PPG87_0
-
I/O
circuit
1
type*
A
A
2
Function*
General-purpose I/O port
PPG ch.86 output pin(0)
General-purpose I/O port
PPG ch.87 output pin(0)
P167
-
PPG35_1
-
C4
P296
-
A
General-purpose I/O port
D5
P297
-
A
General-purpose I/O port
P013
-
D27
-
TIOA1_0
-
Base timer ch.1 TIOA I/O pin(0)
P014
-
General-purpose I/O port
A4
D28
-
TIOB1_0
-
A
General-purpose I/O port
PPG ch.35 output pin(1)
General-purpose I/O port
R
R
External Bus data bit27 I/O pin
External Bus data bit28 I/O pin
40
50
58
AF4
AVCC1
-
-
84
103
122
T26
AVCC0
-
-
42
52
60
AF5
AVRH1
-
-
83
102
121
U26
AVRH0
-
-
43
53
61
-
AVSS1/AVRL1
-
-
-
-
-
AF7
AVSS1
-
-
-
-
-
AF6
AVRL1
-
-
82
101
120
-
AVSS0/AVRL0
-
-
-
-
-
W26
AVSS0
-
-
-
-
-
V26
AVRL0
-
-
130
158
186
A13
C
-
-
Base timer ch.1 TIOB input pin(0)
A/D, D/A converter unit1 analog power
supply pin
A/D, D/A converter unit0 analog power
supply pin
A/D converter unit1 upper limit reference
voltage pin
A/D converter unit0 upper limit reference
voltage pin
A/D, D/A converter unit1 GND/
A/D converter unit1 lower limit reference
voltage pin
A/D, D/A converter unit1 GND
A/D converter unit1 lower limit reference
voltage pin
A/D, D/A converter unit0 GND/
A/D converter unit0 lower limit reference
voltage pin
A/D, D/A converter unit0 GND
A/D converter unit0 lower limit reference
voltage pin
External capacity connection output pin
VCC
-
-
Power supply (1)
-
-
63
AF10
45
55
104
AF11
72
88
134
AE10
109
133
157
AE11
124
152
180
AE24
-
-
-
AF24
-
-
-
N25
-
-
-
N26
-
-
-
A24
-
-
-
B24
-
-
-
A14
-
40
CONFIDENTIAL
B14
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144
176
208
BGA
416
36
44
52
M1
128
156
184
M2
144
176
208
AD2
-
-
-
AD1
-
-
-
A11
-
-
-
B11
-
-
-
B3
-
-
-
A3
1
1
1
A1
37
45
53
B2
44
54
62
P1
73
89
105
P2
108
132
135
AF1
120
148
156
AE2
125
153
176
AF8
129
157
181
AF9
-
-
185
AE9
-
-
-
AD10
-
-
-
AF26
-
-
-
AE25
-
-
-
M26
-
-
-
M25
-
-
-
A26
-
-
-
B25
-
-
-
A21
-
-
-
A18
-
-
-
B16
-
-
-
A15
-
-
-
A12
-
-
-
B12
-
-
-
A2,A25
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
VCCE
-
-
Power supply (2)
VSS
-
-
GND
B1,B4
B13,B17
B19,B20
B26
C2,C3
C7,C8
C12,C13
C14,C15
C23,C24
D4,D13
D23,D24
F3,F24
G3,G24
H2,H3
J24
K10-K17
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
2
Function*
41
D a t a S h e e t
BGA
416
144
176
208
-
-
-
K24
-
-
-
L10-L17
-
-
-
M10-M17
-
-
-
M23,M24
-
-
-
N1-N4
-
-
-
N10-N17
-
-
-
N24
-
-
-
P3,P4
-
-
-
P10-P17
-
-
-
R10-R17
-
-
-
R24
-
-
-
T3
-
-
-
T10-T17
-
-
-
T24
-
-
-
U3
-
-
-
U10-U17
-
-
-
V24
-
-
-
W3,W24
-
-
-
Y3
-
-
-
AA24
-
-
-
AC3,AC4
-
-
-
AC9,AC23
AD12,AD13
-
-
-
AD15,AD16
-
-
-
AD18,AD19
-
-
-
AD21,AD22
-
-
-
AD24
-
-
-
AE1,AE26
-
-
-
AF2,AF25
Pin Name
Polarity
Pin Number
I/O
circuit
1
type*
VSS
-
-
2
Function*
GND
AD3,AD4
AD7,AD9
*1: For the I/O circuit types, see "I/O CIRCUIT TYPE".
*2: For switching, see "I/O Port" in HARDWARE MANUAL.
42
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 I/O CIRCUIT TYPE
Type
Circuit
A
Pull-up control
Digital output
Remarks
- General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- Automotive input
Digital output
Automotive input
Standby control
B
Pull-up control
Digital output
- Analog input, General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- Automotive input
Digital output
Automotive input
Standby control
Analog input
C
Pull-up control
Digital output
Digital output
- DAC output, General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- Automotive input
Automotive input
Standby control
DAC output
D
Pull-up control
Digital output
- I2C Analog input, General-purpose I/O port
- Output 3mA
- Pull-up resistor control 50kΩ
- I2C hysteresis input
Digital output
I2C input
Standby control
Analog input
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
43
D a t a S h e e t
Type
Circuit
E
Pull-up control
Digital output
Remarks
- I2C,General-purpose I/O port
- Output 3mA
- Pull-up resistor control 50kΩ
- I2C hysteresis input
Digital output
I2C input
Standby control
F
Pull-up control
Digital output
- General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
Digital output
CMOS-hys input
Standby control
G
Pull-up control
Digital output
- Analog input, General-purpose I/O port
- Output 4mA
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
Digital output
CMOS-hys input
Standby control
Analog input
H
Pull-up control
Digital output
- Analog input, General-purpose I/O port
- Output 12mA
- Pull-up resistor control 50kΩ
- Automotive input
Digital output
Automotive input
Standby control
Analog input
44
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Type
Circuit
Remarks
I
- General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
Digital output
Digital output
CMOS-hys input
Standby control
J
- Analog input, General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
Digital output
Digital output
CMOS-hys input
Standby control
Analog input
- Mode I/O
- CMOS hysteresis input
K
Mode input
Control
L
Digital output
- Open-drain I/O
- Output 25mA (Nch open drain)
- TTL input
TTL input
M
- Hysteresis input
- Pull-up resistor 50k
CMOS-hys input
March 28, 2014, MB91F528_DS705-00016-1v0-E
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D a t a S h e e t
Type
N
Circuit
Remarks
Input
- Main oscillation I/O
Standby control
O
Input
- Sub oscillation I/O
Standby control
P
Pull-up control
Digital output
Digital output
- General-purpose I/O port
- Output 4mA
- Output 3mA (Nch open drain)
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
CMOS-hys input
Standby control
Q
Pull-up control
Digital output
Digital output
- Analog input, General-purpose I/O port
- Output 4mA
- Output 3mA (Nch open drain)
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
CMOS-hys input
Standby control
Analog input
R
Pull-up control
Digital output
Digital output
- General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- Automotive input
- CMOS hysteresis input
Automotive input
Standby control
CMOS-hys input
Standby control
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Type
Circuit
S
Pull-up control
Digital output
Digital output
Remarks
- Analog input, General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- Automotive input
- CMOS hysteresis input
Automotive input
Standby control
CMOS-hys input
Standby control
Analog input
T
Pull-up control
Digital output
Digital output
- General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- CMOS hysteresis input
CMOS-hys input
Standby control
U
Pull-up control
Digital output
Digital output
- Analog input, General-purpose I/O port
- Output 4mA
- Output 4mA (FlexRay output)
- Pull-up resistor control 50kΩ
- Automotive input
Automotive input
Standby control
Analog input
V
- CMOS hysteresis input
CMOS-hys input
Standby control
W
- Output 4mA
Digital output
Digital output
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 HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-2Ea
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 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
 Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
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D a t a S h e e t
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
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3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
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D a t a S h e e t
 HANDLING DEVICES
This section explains the latch-up prevention and pin processing.
 For latch-up prevention
If a voltage higher than VCC (VCCE in case of terminal corresponding to VCCE power supply.) or a voltage
lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is applied between VCC and VSS
pins or VCCE and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply
current increases excessively and device elements may be damaged by heat. Take care to prevent any
voltage from exceeding the maximum ratings in device application.
Also, the analog power supply (AVCC, AVRH), analog input and digital power supply (VCCE) must not be
exceed the digital power supply (VCC) when the power supply to the analog system and digital power
supply (VCCE) are turned on or off.
In the correct power-on sequence of the microcontroller, turn on the digital power supply (VCC), analog
power supplies (AVCC, AVRH) and digital power supply (VCCE) simultaneously. Or, turn on the digital
power supply (VCC), and then turn on analog power supplies (AVCC, AVRH) and digital power supply
(VCCE).
 Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or
latch-up. Connect at least a 2kΩ resistor to each of the unused pins for pull-up or pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the
input state and treated in the same way as for the input pins.
 Power supply pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should be
at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these
pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from
malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown in
figure 1, all Vss power supply pins must be treated in the similar way. If multiple Vcc or Vss systems are
connected, the device cannot operate correctly even within the guaranteed operating range.
Figure 1 Power Supply Input Pins
Vcc
Vss
Vss
Vcc
Vss
Vcc
Vcc
Vss
Vss
Vcc
The power supply pins should be connected to VCC and VSS pins of this device at the low impedance from
the power supply source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin
is recommended to use as a bypass capacitor between VCC and VSS pins.
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 Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be
designed to lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be
grounded to the close position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
 Mode pins (MD1, MD0)
Connect the MD1and MD0 mode pins to the VCC or VSS pin directly. To prevent an erroneous selection of
test mode caused by the noise, reduce the pattern length between each mode pin and VCC or VSS pin on the
printed circuit board. Also, use the low-impedance pin connection.
 During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to
have 50μs or longer (between 0.2V and 2.7V) during power-on.
 Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock
may continue to operate at the free running frequency of the self-oscillator circuit built in the PLL clock.
This operation is not guaranteed.
 Treatment of A/D converter power supply pins
Connect the pins to have AVCC=AVRH=VCC and AVSS/AVRL=VSS even if the A/D converter is not used.
 Notes on using external clock
An external clock is not supported. None of the external direct clock input can be used for both main clock
and sub clock.
 Power-on sequence of A/D converter analog inputs
Be sure to turn on the digital power supply (VCC, VCCE) first, and then turn on the A/D converter power
supplies (AVcc, AVRH, AVRL) and analog inputs (AN0 to AN63). Also, turn off the A/D converter power
supplies and analog inputs first, and then turn off the digital power supply (VCC, VCCE). When the AVRH
pin voltage is turned on or off, it must not exceed AVCC. Even if a common analog input pin is used as an
input port, its input voltage must not exceed AVcc. (However, the analog power supply and digital power
supply can be turned on or off simultaneously.)
 Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to
assure the internal stabilization of the device. For the standard values, see the "Recommended Operating
Conditions" of the latest data sheet.
Note: Please see the latest data sheet for a detailed specification of the operation voltage.
 Function switching of a multiplexed port
To switch between the port function and the multiplexed pin function, use the PFR (port function register).
However, if a pin is also used for an external bus, its function is switched by the external bus setting. For
details, see " I/O PORTS" in the hardware manual.
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 Low-power consumption mode
To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off),
follow the procedure explained in "Activating the sleep mode, watch mode, or stop mode" or "Activating
the watch mode (power-off) or stop mode(power-off)" of " POWER CONSUMPTION CONTROL" in the
hardware manual.
Take the following notes when using a monitor debugger.
· Do not set a break point for the low-power consumption transition program.
· Do not execute an operation step for the low-power consumption transition program.
 Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control
function, taking care not to clear its status flag erroneously must be followed.
The program must be written not to clear the flag to the status bit, and then to set the control bits to have the
desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can
access to a single bit only.) By the Byte, Half-word, or Word access, data is written to the control bits and
status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of status
flag) erroneously.
Note: These points can be ignored because the bit instructions are already taken the points into consideration.
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 BLOCK DIAGRAM
 MB91F527R, MB91F528R
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 <-> PCLK2)
Flex Ray clock control
I/O port setting
32bit Free-run timer (3ch)
I / O Port
FRCK
32bit Input capture (6ch)
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 16ch)
Multi-function serial interface (12ch)
ICU
32bit Output compare (6ch)
OCU
DTTI,RTO
16bit Free-run timer (3ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
Base timer (2ch)
TIOA,TIOB
PPG(44ch)
U/D counter (2ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit <-> 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (16ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Watchdog timer (SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
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D a t a S h e e t
 MB91F527U, MB91F528U
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 <-> PCLK2)
Flex Ray clock control
Ｉ/Ｏ port setting
32bit Free-run timer (3ch)
I / O Port
FRCK
32bit Input capture (6ch)
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
FRCK
16bit Input capture (4ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 16ch)
Multi-function serial interface (12ch)
ICU
32bit Output compare (6ch)
OCU
DTTI,RTO
16bit Free-run timer (3ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
Base timer (2ch)
TIOA,TIOB
PPG (48ch)
U/D counter (2ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit <-> 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (16ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Watchdog timer (SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
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 MB91F527M, MB91F528M
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 <-> PCLK2)
Flex Ray clock control
Ｉ/Ｏ port setting
32bit Free-run timer (8ch)
I / O Port
FRCK
32bit Input capture (8ch)
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
Base timer (2ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 32ch)
Multi-function serial interface (20ch)
32bit Output compare (8ch)
TIOA,TIOB
FRCK
16bit Input capture (4ch)
ICU
OCU
DTTI,RTO
16bit Free-run timer (3ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
PPG (64ch)
U/D counter (4ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit <-> 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (24ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Watchdog timer (SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
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D a t a S h e e t
 MB91F527Y, MB91F528Y
Regulator
FR81s CPU core
Power-on reset
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
JTAG I/F
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 1600KB/2112KB
・Work Flash
64KB
On chip bus(AHB)
RAM
192KB/192KB
Flash
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
DMAC
(16 ch)
RAM ECC Control(XBS RAM)
CAN (6ch)
Peripheral Bus
Bridge
Flex Ray(1ch)
D,A,ASX,CS,
RDX,WRX,
SYSCLK,RDY
RX,TX
RXDA-B,TXDA-B,
TXENA-B, STOPWT
Clock / Bus Bridge
RAM ECC Control
(BackUp RAM)
16
32
BackUp RAM
16KB
Async Bus Bridge (PCLK1 <-> PCLK2)
Flex Ray clock control
Ｉ/Ｏ port setting
32bit Free-run timer (8ch)
I / O Port
FRCK
32bit Input capture (8ch)
16bit Peripheral Bus
CAN prescaler
RTC / WDT1 Calibration
Tuning RAM 0KB/128KB
AHB RAM 0KB/128KB
Bus
performance
counter
Operation mode
register
MD0,MD1,P006
32bit Peripheral Bus (APB)
External Bus
I/F
Async Bus Bridge (PCLK1 <-> PCLK2)
CRC
Wave generator (6ch)
Base timer (2ch)
ICU
16bit Output compare (6ch)
12bit AD converter (32ch + 32ch)
Multi-function serial interface (20ch)
32bit Output compare (8ch)
TIOA,TIOB
FRCK
16bit Input capture (4ch)
ICU
OCU
DTTI,RTO
16bit Free-run timer (3ch)
Bus Bridge (32bit <-> 16bit)
ADTG,AIN
ADC enable(ADER)
SOUT,
SIN,
SCK
PPG (88ch)
U/D counter (4ch)
TRG,PPG
Reload timer (8ch)
I / O Port
AIN,BIN,ZIN
Bus Bridge (32bit <-> 16bit)
TIN,TOT
8bit DA converter (2ch)
External interrupt input (24ch)
Clock monitor
Real time clock
INT
DAO
WOT
MONCLK
Watchdog timer (SW and HW)
Clock supervisor
NMI
NMIX
DMA transfer request generate/clear
Interrupt request batch read
Clock control (divide control)
RSTX
Reset control register
Low power consumption setting register
Delay interrupt
Low voltage detection
(External power supply low voltage detection)
Low voltage detection
(Internal power supply low voltage detection)
Clock control (Clock setting,
Main timer, Sub timer, PLL timer)
Interrupt controller
58
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 MEMORY MAP
 MB91F527, MB91F528
[ Tuning RAM function not used ]
[ Tuning RAM function used ]
MB91F528
MB91F528
MB91F527
0000 0000
H
I/O
0000 0000
H
I/O
0000 0000
H
I/O
0000 4000
H
BackUp RAM(16KB)
0000 4000
H
BackUp RAM(16KB)
0000 4000
H
BackUp RAM(16KB)
0000 8000
0001 0000
H
I/O
H
I/O
I/O
RAM(192KB)
H
RAM(192KB)
0000 8000
0001 0000
H
H
0000 8000
0001 0000
H
RAM(192KB)
0004 0000
H
Reserved
0004 0000
H
Reserved
0004 0000
H
Reserved
0007 0000
H
Flash Memory
(1536+64)KB
0007 0000
H
Flash Momory
(2048+64)KB
0007 0000
H
0008 0000
H
Flash Momory
(2048+64)KB
Tuning Area
(128KB)
000A 0000
H
000C 0000
H
000F FC00
H
0010 0000
H
0028 0000
H
000F FC00
H
0010 0000
H
0020 0000
H
Interrupt Vector
Reset Vector
Reserved
000F FC00
H
0010 0000
H
0028 0000
H
Interrupt Vector
Reset Vector
Reserved
Tuning Area
(128KB)
Interrupt Vector
Reset Vector
Reserved
Register
switching
0033 0000
H
0034 0000
H
Work Flash
(64KB)
0033 0000
H
0034 0000
H
Reserved
8000 0000
H
H
7FFE 0000
H
8000 0000
H
H
0034 0000
H
RAM
(128KB)
FFFF FFFF
H
Work Flash
(64KB)
Reserved
7FFE 0000
H
8000 0000
H
FFFF FFFF
H
External Area
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
0033 0000
Reserved
External Area
FFFF FFFF
Work Flash
(64KB)
Tuning RAM
(128KB)
Mirror region of Tuning Area
External Area
59
D a t a S h e e t
 I/O MAP
The following I/O map shows the relationship between memory space and registers for peripheral
resources.
Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
000090H
000094 H
000098 H
00009C H
0000A0 H
0000A4 H
0000A8 H
Address offset value/ register name
+1
+2
+0
+3
BT1TMR[R] H
BT1TMCR[R/W]B,H,W
0000000000000000
00000000 00000000
BT1STC[R/W] B
-
-
00000000
-
Base timer 1
BT1PCSR/BT1PRLL[R /W] H
BT1PDU T/BT1PRLH/BT1DTBF[R/W] H
0000000000000000
0000000000000000
BTSEL[R/W] B
BTSSSR[W] B,H
-
----000 0
Block
-------- ------11
ADERH [R/W]B, H, W
ADERL [R/W]B, H, W
00000000 00000000
00000000 00000000
ADCS1 [R/W] B, H,W
ADCS0 [R/W] B, H,W
ADCR1 [R] B, H,W
ADCR0 [R] B, H,W
00000000
00000000
------XX
XXXXX XXX
ADCT1 [R/W] B, H,W
ADCT0 [R/W] B, H,W
ADSCH [R/W] B, H,W
ADECH [R/W] B, H,W
00010000
00101100
---00000
---00000
A/D converter
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)The access by the data
access attribute not described
is disabled.
Initial register value after reset
The initial register value after reset indicates as follows:
· "1": Initial value "1"
· "0": Initial value "0"
· "X": Initial value undefined
· "-": Reserved bit/Undefined bit
· "*": Initial value "0" or "1" according to the setting
Note: The access to addresses not described is disabled.
60
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
000000H
000004H
000008H
00000CH
000010H
000014H
000018H
00001CH
000020H
000024H
000028H
00002CH
000030H
000034H
000038H
00003CH
000040H
000044H
000048H
to
00005CH
000060H
000064H
000068H
00006CH
000070H
000074H
+0
Address offset value / Register name
+1
+2
Block
PDR00 [R/W] B,H,W
XXXXXXXX
PDR04 [R/W] B,H,W
XXXXXXXX
PDR08 [R/W] B,H,W
XXXXXXXX
PDR12 [R/W] B,H,W
XXXXXXXX
PDR20 [R/W] B,H,W
XXXXXXXX
PDR24 [R/W] B,H,W
--XXXXXX
PDR16 [R/W] B,H,W
XXXXXXXX
PDR28 [R/W] B,H,W
XXXXXXXX
PDR01 [R/W] B,H,W PDR02 [R/W] B,H,W PDR03 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR05 [R/W] B,H,W PDR06 [R/W] B,H,W PDR07 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR09 [R/W] B,H,W PDR10 [R/W] B,H,W PDR11 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR13 [R/W] B,H,W PDR14 [R/W] B,H,W PDR15 [R/W] B,H,W
-XXX--XX
---------XXXXXX
Port Data Register
PDR21 [R/W] B,H,W PDR22 [R/W] B,H,W PDR23 [R/W] B,H,W
XXXXXXXX
XXX--XXX
XXXXXXXX
PDR25 [R/W] B,H,W PDR26 [R/W] B,H,W PDR27 [R/W] B,H,W
-XXXXXXX
XXXXXX-XXX-XXXX
PDR17 [R/W] B,H,W PDR18 [R/W] B,H,W PDR19 [R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR29 [R/W] B,H,W
―
―
XXXXXXXX
MSCY10 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY11 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCL1011 [R/W]
MSCH1011 [R] B,H,W
―
―
B,H,W
Input
00000000
------00
Capture 10,11
32-bit ICU
IPCP10 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP11 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS1011 [R/W] B,H,W
―
―
―
00000000
WDTECR0 [R/W]
B,H,W
―
―
―
---00000
Watchdog Timer
[S]
WDTCR0 [R/W]
WDTCPR0 [W]
WDTCR1 [R]
WDTCPR1 [W]
B,H,W
B,H,W
B,H,W
B,H,W
-0--0000
00000000
----0110
00000000
―
―
―
―
Reserved
DICR [R/W] B
―
―
―
Delayed Interrupt
-------0
―
―
―
―
TMRLRA0 [R/W] H
TMR0 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB0 [R/W] H
TMCSR0 [R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA7 [R/W] H
TMR7 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB7 [R/W] H
TMCSR7 [R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
FRS8 [R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
FRS9 [R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Reserved
Reload Timer 0
Reload Timer 7
Free-run timer
selection register 8
Free-run timer
selection register 9
61
D a t a S h e e t
Address
+0
Address offset value / Register name
+1
+2
000078H
―
―
00007CH
―
―
000080H
000084H
000088H
00008CH
000090H
000094H
000098H
00009CH
0000A0H
to
0000FCH
000100H
000104H
000108H
00010CH
000110H
000114H
BT0TMR [R] H
00000000 00000000
BT0TMCR2 [R/W] B BT0STC [R/W] B
-------0
-0-0-0-0
BT0PCSR/BT0PRLL [R/W] H
00000000 00000000
―
―
BT1TMR [R] H
00000000 00000000
BT1TMCR2 [R/W] B BT1STC [R/W] B
-------0
-0-0-0-0
BT1PCSR/BT1PRLL [R/W] H
00000000 00000000
BTSEL01 [R/W] B
―
----0000
―
TMRLRA1 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB1 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA2 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB2 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRA3 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB3 [R/W] H
XXXXXXXX XXXXXXXX
000118H
00011CH
000120H
000124H
000128H
―
00012CH
000130H
000134H
62
CONFIDENTIAL
―
―
+3
OCLS67 [R/W]
B,H,W
----0000
OCLS89 [R/W]
―
B,H,W
----0000
BT0TMCR [R/W] H
-000--00 -000-000
―
―
―
BT0PDUT/BT0PRLH/BT0DTBF [R/W] H
00000000 00000000
―
―
BT1TMCR [R/W] H
-000--00 -000-000
―
―
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
00000000 00000000
BTSSSR [W] B,H
-------- ------11
―
―
TMR1 [R] H
XXXXXXXX XXXXXXXX
TMCSR1 [R/W] B, H,W
00000000 0-000000
TMR2 [R] H
XXXXXXXX XXXXXXXX
TMCSR2 [R/W] B,H,W
00000000 0-000000
TMR3 [R] H
XXXXXXXX XXXXXXXX
TMCSR3 [R/W] B,H,W
00000000 0-000000
Block
OCU67 Output
level control
register
OCU89 Output
level control
register
Base Timer 0
Reserved
Base Timer 1
Base Timer 0,1
Reserved
Reload Timer 1
Reload Timer 2
Reload Timer 3
MSCY4 [R] H,W
Input Capture 4,5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Cycle measurement
MSCY5 [R] H,W
data register 45
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCCP6 [R/W] W
00000000 00000000 00000000 00000000
Output
OCCP7 [R/W] W
Compare 6,7
00000000 00000000 00000000 00000000
32-bit OCU
OCSH67 [R/W] B,H,W OCSL67 [R/W] B,H,W
―
---0--00
0000--00
OCCP8 [R/W] W
00000000 00000000 00000000 00000000
Output
OCCP9 [R/W] W
Compare 8,9
00000000 00000000 00000000 00000000
32-bit OCU
OCSH89 [R/W] B,H,W OCSL89 [R/W] B,H,W
―
---0--00
0000--00
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
+0
000138H
00013CH
000140H
―
000144H
to
0001B4H
―
0001B8H
0001BCH
0001C0H
0001C4H
0001C8H
0001CCH
0001D0H
0001D4H
0001D8H
0001DCH
0001E0H
0001E4H
0001E8H
0001ECH
0001F0H
0001F4H
Address offset value / Register name
+1
+2
OCCP12 [R/W] W
00000000 00000000 00000000 00000000
OCCP13 [R/W] W
00000000 00000000 00000000 00000000
OCSH1213 [R/W]
―
B,H,W
---0--00
EPFR64 [R/W]
EPFR65 [R/W]
B,H,W
B,H,W
-----000000-00EPFR68 [R/W]
EPFR69 [R/W]
B,H,W
B,H,W
----0000
----0000
EPFR72 [R/W]
EPFR73 [R/W]
B,H,W
B,H,W
000000-0
00000000
EPFR76 [R/W]
EPFR77 [R/W]
B,H,W
B,H,W
00000-0--000000
EPFR80 [R/W]
EPFR81 [R/W]
B,H,W
B,H,W
---00000
00000000
EPFR84 [R/W]
EPFR85 [R/W]
B,H,W
B,H,W
00000000
--000000
EPFR88 [R/W]
EPFR89 [R/W]
B,H,W
B,H,W
-------0
-0-00000
EPFR92 [R/W]
EPFR93 [R/W]
B,H,W
B,H,W
-0-0-0-0
00000000
TMRLRA4 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB4 [R/W] H
XXXXXXXX XXXXXXXX
EPFR96 [R/W]
EPFR97 [R/W]
B,H,W
B,H,W
-0-0-0-0
-0-0-0-0
EPFR100 [R/W]
EPFR101 [R/W]
B,H,W
B,H,W
-----00-----00EPFR104 [R/W]
EPFR105 [R/W]
B,H,W
B,H,W
-----00-----00EPFR108 [R/W]
EPFR109 [R/W]
B,H,W
B,H,W
---00000
--000000
TMRLRA5 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB5 [R/W] H
XXXXXXXX XXXXXXXX
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
―
―
+3
OCSL1213 [R/W]
B,H,W
0000--00
―
EPFR66 [R/W]
EPFR67 [R/W]
B,H,W
B,H,W
--000000
----0000
EPFR70 [R/W]
EPFR71 [R/W]
B,H,W
B,H,W
---00000
-0-0-0-0
EPFR74 [R/W]
EPFR75 [R/W]
B,H,W
B,H,W
00000000
00000000
EPFR78 [R/W]
EPFR79 [R/W]
B,H,W
B,H,W
------00
00000000
EPFR82 [R/W]
EPFR83 [R/W]
B,H,W
B,H,W
00000000
-0000000
EPFR86 [R/W]
EPFR87 [R/W]
B,H,W
B,H,W
---00000
-------EPFR90 [R/W]
EPFR91 [R/W]
B,H,W
B,H,W
-0-0-0-0
-0-0-0-0
EPFR94 [R/W]
EPFR95 [R/W]
B,H,W
B,H,W
-0-0-0-0
-0-0-0-0
TMR4 [R] H
XXXXXXXX XXXXXXXX
TMCSR4 [R/W] B, H,W
00000000 0-000000
EPFR98 [R/W]
EPFR99 [R/W]
B,H,W
B,H,W
0000-0-0
----0000
EPFR102 [R/W]
EPFR103 [R/W]
B,H,W
B,H,W
-----00-----00EPFR106 [R/W]
EPFR107 [R/W]
B,H,W
B,H,W
-----00-----00EPFR110 [R/W]
EPFR111 [R/W]
B,H,W
B,H,W
--000000
-------0
TMR5 [R] H
XXXXXXXX XXXXXXXX
TMCSR5 [R/W] B, H,W
00000000 0-000000
Block
Output
Compare 12,13
32-bit OCU
Reserved
Extended port
function register
Reload Timer 4
Extended port
function register
Reload Timer 5
63
D a t a S h e e t
Address
0001F8H
0001FCH
000200H
to
000238H
00023CH
000240H
000244H
000248H
00024CH
000250H
000254H
000258H
to
0002C0H
0002C4H
to
0002FCH
000300H
to
00030CH
+0
Address offset value / Register name
+1
+2
TMRLRA6 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB6 [R/W] H
XXXXXXXX XXXXXXXX
―
+3
TMR6 [R] H
XXXXXXXX XXXXXXXX
TMCSR6 [R/W] B, H,W
00000000 0-000000
―
―
―
Block
Reload Timer 6
Reserved
DACR0 [R/W] B,H,W DADR0 [R/W] B,H,W DACR1 [R/W] B,H,W DADR1 [R/W] B,H,W
DA Converter
-------0
XXXXXXXX
-------0
XXXXXXXX
CPCLR3 [R/W] W
11111111 11111111 11111111 11111111
TCDT3 [R/W] W
Free-run Timer 3
00000000 00000000 00000000 00000000
32-bit FRT
TCCSH3 [R/W]
TCCSL3 [R/W]
B,H,W
B,H,W
―
―
0-----00
-1-00000
CPCLR4 [R/W] W
11111111 11111111 11111111 11111111
TCDT4 [R/W] W
Free-run Timer 4
00000000 00000000 00000000 00000000
32-bit FRT
TCCSH4 [R/W]
TCCSL4 [R/W]
B,H,W
B,H,W
―
―
0-----00
-1-00000
―
―
―
―
Reserved
―
―
―
―
Reserved
―
―
―
―
Reserved
000310H
―
―
000314H
000318H
00031CH
―
―
―
―
―
MPU [S]
(Only CPU core
can access this
area)
000320H
64
CONFIDENTIAL
MPUCR [R/W] H
000000-0 ----0100
―
―
―
DPVAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
000324H
+0
―
000328H
00032CH
―
000330H
000334H
―
000338H
00033CH
―
000340H
000344H
―
000348H
00034CH
―
000350H
000354H
―
000358H
00035CH
―
000360H
000364H
―
000368H
00036CH
000370H
to
0003ACH
0003B0H
to
0003FCH
Address offset value / Register name
+1
+2
―
DEAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR [R/W] H
―
-------- 00000--0
PABR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0 [R/W] H
―
000000-0 00000--0
PABR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1 [R/W] H
―
000000-0 00000--0
PABR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2 [R/W] H
―
000000-0 00000--0
PABR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3 [R/W] H
―
000000-0 00000--0
PABR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4 [R/W] H
―
000000-0 00000--0
PABR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5 [R/W] H
―
000000-0 00000--0
PABR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR6 [R/W] H
―
000000-0 00000--0
PABR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR7 [R/W] H
―
000000-0 00000--0
MPU [S]
(Only CPU core
can access this
area)
MPU [S]
(Only CPU core
can access this
area)
―
―
―
Block
DPVSR [R/W] H
-------- 00000--0
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Reserved [S]
―
―
Reserved [S]
65
D a t a S h e e t
Address
000400H
000404H
000408H
00040CH
000410H
000414H
000418H
00041CH
000420H
000424H
000428H
00042CH
000430H
000434H
000438H
00043CH
66
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
+3
Block
ICSEL0 [R/W] B,H,W ICSEL1 [R/W] B,H,W ICSEL2 [R/W] B,H,W
-----000
----0000
-------0
ICSEL4 [R/W] B,H,W ICSEL5 [R/W] B,H,W ICSEL6 [R/W] B,H,W
-------0
-----000
----0000
ICSEL10 [R/W]
ICSEL8 [R/W] B,H,W ICSEL9 [R/W] B,H,W
B,H,W
------00
------00
------00
ICSEL12 [R/W]
ICSEL13 [R/W]
ICSEL14 [R/W]
B,H,W
B,H,W
B,H,W
-------0
------00
------00
ICSEL16 [R/W]
ICSEL17 [R/W]
ICSEL18 [R/W]
B,H,W
B,H,W
B,H,W
----0000
------00
--000000
ICSEL20 [R/W]
ICSEL21 [R/W]
ICSEL22 [R/W]
B,H,W
B,H,W
B,H,W
-----000
------00
------00
IRPR0H [R] B,H,W IRPR0L [R] B,H,W
IRPR1H [R] B,H,W
00-----00-----00-----IRPR3H [R] B,H,W
―
―
000000-IRPR4H [R] B,H,W IRPR4L [R] B,H,W
IRPR5H [R] B,H,W
0000---0000---0000---IRPR6H [R] B,H,W IRPR6L [R] B,H,W
IRPR7H [R] B,H,W
--00---0000----0-00--IRPR8H [R] B,H,W IRPR8L [R] B,H,W
IRPR9H [R] B,H,W
--0-----00-----0-----IRPR10H [R] B,H,W IRPR10L [R] B,H,W IRPR11H [R] B,H,W
-0------0-----0------IRPR12H [R] B,H,W IRPR12L [R] B,H,W IRPR13H [R] B,H,W
--0000-----00-00-----IRPR14H [R] B,H,W IRPR14L [R] B,H,W IRPR15H [R] B,H,W
00000000
00000000
000----ICSEL24 [R/W]
ICSEL25 [R/W]
ICSEL26 [R/W]
B,H,W
B,H,W
B,H,W
------00
---00000
-------0
IRPR16H [R] B,H,W IRPR16L [R] B,H,W
000----00000---
ICSEL3 [R/W] B,H,W
-------0
ICSEL7 [R/W] B,H,W
----0000
ICSEL11 [R/W]
B,H,W
-----000
DMA request
ICSEL15 [R/W]
generation and
B,H,W
clear
------00
ICSEL19 [R/W]
B,H,W
-----000
ICSEL23 [R/W]
B,H,W
------00
IRPR1L [R] B,H,W
00-----IRPR3L [R] B,H,W
000000-IRPR5L [R] B,H,W
Interrupt Request
0000000Batch Reading
IRPR7L [R] B,H,W
Register
------00
IRPR9L [R] B,H,W
-0-----IRPR11L [R] B,H,W
0------IRPR13L [R] B,H,W
Interrupt Request
00-----Batch Reading
IRPR15L [R] B,H,W
Register
00000000
ICSEL27 [R/W]
DMA request
B,H,W
generation and
-------0
clear
Interrupt Request
IRPR17H [R] B,H,W IRPR17L [R] B,H,W
Batch Reading
000----000----Register
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
+0
Address offset value / Register name
+1
+2
ICR00 [R/W] B,H,W
---11111
ICR04 [R/W] B,H,W
---11111
ICR08 [R/W] B,H,W
---11111
ICR12 [R/W] B,H,W
---11111
ICR16 [R/W] B,H,W
---11111
ICR20 [R/W] B,H,W
---11111
ICR24 [R/W] B,H,W
---11111
ICR28 [R/W] B,H,W
---11111
ICR32 [R/W] B,H,W
---11111
ICR36 [R/W] B,H,W
---11111
ICR40 [R/W] B,H,W
---11111
ICR44 [R/W] B,H,W
---11111
ICR01 [R/W] B,H,W
---11111
ICR05 [R/W] B,H,W
---11111
ICR09 [R/W] B,H,W
---11111
ICR13 [R/W] B,H,W
---11111
ICR17 [R/W] B,H,W
---11111
ICR21 [R/W] B,H,W
---11111
ICR25 [R/W] B,H,W
---11111
ICR29 [R/W] B,H,W
---11111
ICR33 [R/W] B,H,W
---11111
ICR37 [R/W] B,H,W
---11111
ICR41 [R/W] B,H,W
---11111
ICR45 [R/W] B,H,W
---11111
ICR02 [R/W] B,H,W
---11111
ICR06 [R/W] B,H,W
---11111
ICR10 [R/W] B,H,W
---11111
ICR14 [R/W] B,H,W
---11111
ICR18 [R/W] B,H,W
---11111
ICR22 [R/W] B,H,W
---11111
ICR26 [R/W] B,H,W
---11111
ICR30 [R/W] B,H,W
---11111
ICR34 [R/W] B,H,W
---11111
ICR38 [R/W] B,H,W
---11111
ICR42 [R/W] B,H,W
---11111
ICR46 [R/W] B,H,W
---11111
000470H
to
00047CH
―
―
―
000480H
RSTRR [R]
B,H,W
XXXX--XX
RSTCR [R/W]
B,H,W
111----0
STBCR [R/W]
B,H,W *
000---11
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
000484H
000488H
00048CH
000490H
000494H
000498H
00049CH
0004A0H
0004A4H
0004A8H
0004ACH
0004B0H
―
―
DIVR0 [R/W] B,H,W DIVR1 [R/W] B,H,W
000----0001---―
―
IORR0 [R/W] B,H,W IORR1 [R/W] B,H,W
-0000000
-0000000
IORR4 [R/W] B,H,W IORR5 [R/W] B,H,W
-0000000
-0000000
IORR8 [R/W] B,H,W IORR9 [R/W] B,H,W
-0000000
-0000000
IORR12 [R/W] B,H,W IORR13 [R/W] B,H,W
-0000000
-0000000
―
―
CANPRE [R/W]
B,H,W
―
---00000
―
―
ADERH0[R/W] B,H
11111111 11111111
ADERH1[R/W] B,H
11111111 11111111
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
―
DIVR2 [R/W] B,H,W
0011---―
IORR2 [R/W] B,H,W
-0000000
IORR6 [R/W] B,H,W
-0000000
IORR10 [R/W] B,H,W
-0000000
IORR14 [R/W] B,H,W
-0000000
―
―
+3
Block
ICR03 [R/W] B,H,W
---11111
ICR07 [R/W] B,H,W
---11111
ICR11 [R/W] B,H,W
---11111
ICR15 [R/W] B,H,W
---11111
ICR19 [R/W] B,H,W
---11111
ICR23 [R/W] B,H,W
---11111
Interrupt Controller
[S]
ICR27 [R/W] B,H,W
---11111
ICR31 [R/W] B,H,W
---11111
ICR35 [R/W] B,H,W
---11111
ICR39 [R/W] B,H,W
---11111
ICR43 [R/W] B,H,W
---11111
ICR47 [R/W] B,H,W
---11111
―
Reserved [S]
―
Reset Control [S]
Power Control [S]
*: Writing STBCR
by DMA is
forbidden
Reserved [S]
―
Clock Control [S]
―
―
Reserved [S]
IORR3 [R/W] B,H,W
-0000000
IORR7 [R/W] B,H,W
-0000000
DMA request by
IORR11 [R/W] B,H,W peripheral [S]
-0000000
IORR15 [R/W] B,H,W
-0000000
―
Reserved
―
CAN prescaler
CSCFG[R/W]B,H,W CMCFG[R/W]B,H,W Clock monitor
---0---00000000
control register
ADERL0[R/W] B,H
Analog input
11111111 11111111
control register 0
ADERL1[R/W] B,H
Analog input
11111111 11111111
control register 1
67
D a t a S h e e t
Address
0004B4H
0004B8H
0004BCH
0004C0H
0004C4H
0004C8H
0004CCH
0004D0H
0004D4H
0004D8H
0004DCH
0004E0H
to
00050CH
000510H
000514H
000518H
00051CH
000520H
000524H
000528H
00052CH
000530H
000534H
to
00053CH
68
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
―
―
CUCR0 [R/W] B,H,W
-------- ---0--00
+3
―
―
CUTD0 [R/W] B,H,W
10000000 00000000
CUTR0 [R] B,H,W
-------- 00000000 00000000 00000000
―
―
―
―
CUCR1 [R/W] B,H,W
CUTD1 [R/W] B,H,W
-------- ---0--00
11000011 01010000
CUTR1 [R] B,H,W
-------- 00000000 00000000 00000000
―
―
―
―
PLL2DIVM[R/W]
PLL2DIVN[R/W]
PLL2DIVG[R/W]
PLL2MULG[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
----0000
-0000000
----0000
00000000
PLL2CTRL[R/W]
PLL2DIVK[R/W]
CLKR2[R/W]
B,H,W
B,H,W
B,H,W
―
----0000
-------0
000--000
ICSEL28 [R/W]
ICSEL29 [R/W]
ICSEL30 [R/W]
ICSEL31 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
-------0
-------0
-------0
-------0
ICSEL32 [R/W]
ICSEL33 [R/W]
B,H,W
B,H,W
―
―
-------0
-------0
―
―
―
―
CSELR [R/W] B,H,W CMONR [R] B,H,W MTMCR [R/W] B,H,W STMCR [R/W] B,H,W
001---00
001---00
00001111
0000-111
PLLCR [R/W] B,H,W
CSTBR [R/W] B,H,W PTMCR [R/W] B,H,W
-------- 11110000
-0000000
00-----CPUAR [R/W] B,H,W
―
―
―
0----XXX
―
―
―
―
CCPSSELR [R/W]
CCPSDIVR [R/W]
B,H,W
―
―
B,H,W
-------0
-000-000
CCPLLFBR [R/W]
CCSSFBR0 [R/W]
CCSSFBR1 [R/W]
―
B,H,W
B,H,W
B,H,W
-0000000
--000000
---00000
CCSSCCR0 [R/W]
CCSSCCR1 [R/W] H,W
―
B,H,W
000----- -----------0000
CCCGRCR0 [R/W]
CCCGRCR1 [R/W]
CCCGRCR2 [R/W]
―
B,H,W
B,H,W
B,H,W
00----00
00000000
00000000
CCRTSELR [R/W]
CCPMUCR0 [R/W]
CCPMUCR1 [R/W]
B,H,W
―
B,H,W
B,H,W
0------0
0-----00
0--00000
―
―
―
―
Block
Reserved
RTC/WDT1
calibration
Reserved
Clock control for
FlexRay
DMA request
generation and
clear
Reserved
Clock Control [S]
Reset Control [S]
Reserved [S]
Clock Control 2
[S]
Clock Control 2
[S]
Reserved
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
000540H
000544H
to
00054CH
000550H
000554H
000558H
+0
Address offset value / Register name
+1
+2
EIRR2 [R/W] B,H,W ENIR2 [R/W] B,H,W
XXXXXXXX
00000000
―
―
EIRR0 [R/W] B,H,W ENIR0 [R/W] B,H,W
XXXXXXXX
00000000
EIRR1 [R/W] B,H,W ENIR1 [R/W] B,H,W
XXXXXXXX
00000000
―
―
00055CH
―
―
000560H
―
000564H
―
000568H
WTHR [R/W] B,H
---00000
00056CH
―
WTCRH [R/W] B
------00
WTBRH [R/W] B
--XXXXXX
WTMR [R/W] B,H
--000000
CSVCR [R/W] B
000111--
000570H
to
00057CH
―
000580H
000584H
000588H,
00058CH
000590H
000594H
000598H
00059CH
to
0005FCH
―
―
ELVR0 [R/W] B,H,W
00000000 00000000
ELVR1 [R/W] B,H,W
00000000 00000000
―
―
WTDR [R/W] H
00000000 00000000
WTCRM [R/W] B,H WTCRL [R/W] B,H
00000000
----00-0
WTBRM [R/W] B
WTBRL [R/W] B
XXXXXXXX
XXXXXXXX
WTSR [R/W] B
―
--000000
External Interrupt
(INT16 to 23)
Reserved
External Interrupt
(INT0 to 7)
External Interrupt
(INT8 to 15)
Reserved
Real Time Clock
(RTC)
―
―
Clock Supervisor
―
―
―
Reserved
―
―
―
LVD5F [R/W]
B,H,W
00000001
LVD [R/W]
B,H,W
01000--0
―
―
―
―
―
Reserved
PMUSTR [R/W]
B,H,W
0-----1X
PMUINTF0 [R/W]
B,H,W
00000000
―
PMUCTLR [R/W]
B,H,W
0-00---PMUINTF1 [R/W]
B,H,W
00000000
―
PWRTMCTL [R/W]
B,H,W
-----011
PMUINTF2 [R/W]
B,H,W
0000---―
―
PMU
PMUINTF3 [R/W]
B,H,W
00000000
―
PMU
―
―
―
―
Reserved
ASR0 [R/W] W
00000000 00000000 -------- 1111-001
ASR1 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
ASR2 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
ASR3 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000604H
000608H
00060CH
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
ELVR2 [R/W] B,H,W
00000000 00000000
Block
REGSEL [R/W]
B,H,W
0110011LVD5R [R/W]
B,H,W
-------1
000600H
000610H
to
00063CH
+3
―
―
Regulator Control /
Low Voltage
Detection
External Bus
Interface [S]
External Bus
Interface [S]
―
Reserved [S]
69
D a t a S h e e t
Address
Address offset value / Register name
+1
+2
+0
ACR0 [R/W] W
-------- -------- -------- 01--00-ACR1 [R/W] W
-------- -------- -------- XX--XX-ACR2 [R/W] W
-------- -------- -------- XX--XX-ACR3 [R/W] W
-------- -------- -------- XX--XX--
000640H
000644H
000648H
00064CH
000650H
to
00067CH
―
000684H
000688H
00068CH
000710H
―
Block
External Bus
Interface [S]
―
―
AWR0 [R/W] W
----1111 00000000 11110000 00000-0AWR1 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-XAWR2 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-XAWR3 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000680H
000690H
to
0006FCH
000700H
to
00070CH
+3
Reserved [S]
External Bus
Interface [S]
―
―
―
―
Reserved [S]
―
―
―
―
Reserved
BPCCRA [R/W] B
00000000
000714H
000718H
00071CH
BPCCRB [R/W] B
BPCCRC [R/W] B
00000000
00000000
BPCTRA [R/W] W
00000000 00000000 00000000 00000000
BPCTRB [R/W] W
00000000 00000000 00000000 00000000
BPCTRC [R/W] W
00000000 00000000 00000000 00000000
―
Bus Performance
Counter
000720H
to
0007F8H
―
―
―
0007FCH
BMODR [R] B, H, W
XXXXXXXX
―
―
000800H
to
00083CH
―
―
―
―
Reserved [S]
―
FSTR [R/W] B
-----001
Flash Memory
Register [S]
―
―
Reserved [S]
FCTLR [R/W] H
-0--1000 0--0----
000840H
000844H
to
000854H
―
―
000858H
―
―
00085CH
to
00087CH
―
―
70
CONFIDENTIAL
―
―
WREN [R/W] H
00000000 00000000
―
Reserved
Mode Register
Wild Register [S]
―
Reserved [S]
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
0008D0H
0008D4H
0008D8H
0008DCH
+0
Address offset value / Register name
+1
+2
WRAR00 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR04 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
Wild Register [S]
71
D a t a S h e e t
Address
+0
Address offset value / Register name
+1
+2
WRAR12 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR12 [R/W] W
0008E4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13 [R/W] W
0008E8H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13 [R/W] W
0008ECH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14 [R/W] W
0008F0H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14 [R/W] W
0008F4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15 [R/W] W
0008F8H
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15 [R/W] W
0008FCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
TPUUNLOCK [R/W] W
000900H
00000000 00000000 00000000 00000000
TPUVST [R/W]
TPULST [R] B,H,W
000904H
―
B,H,W
-------0
-----000
TPUCFG [R/W] B,H,W
000908H
-------0 0-000000 -------- -------0
TPUTIR [R] B,H,W
00090CH
―
―
00000000
TPUTST [R] B,H,W
000910H
―
―
00000000
TPUTIE [R/W] B,H,W
000914H
―
―
00000000
TPUTMID [R] B,H,W
000918H
00000000 00000000 00000000 00000000
00091CH
to
―
―
―
00092CH
TPUTCN00 [R/W] B,H,W
000930H
000000-- 00000000 00000000 00000000
TPUTCN01 [R/W] B,H,W
000934H
000000-- 00000000 00000000 00000000
TPUTCN02 [R/W] B,H,W
000938H
000000-- 00000000 00000000 00000000
TPUTCN03 [R/W] B,H,W
00093CH
000000-- 00000000 00000000 00000000
TPUTCN04 [R/W] B,H,W
000940H
000000-- 00000000 00000000 00000000
TPUTCN05 [R/W] B,H,W
000944H
000000-- 00000000 00000000 00000000
TPUTCN06 [R/W] B,H,W
000948H
000000-- 00000000 00000000 00000000
TPUTCN07 [R/W] B,H,W
00094CH
000000-- 00000000 00000000 00000000
+3
Block
0008E0H
72
CONFIDENTIAL
Wild Register [S]
―
―
―
―
―
Time Protection
Unit [S]
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
000950H
000954H
000958H
00095CH
000960H
000964H
000968H
00096CH
+0
TPUTCN10 [R/W]
B,H,W
---00000
TPUTCN11 [R/W]
B,H,W
---00000
TPUTCN12 [R/W]
B,H,W
---00000
TPUTCN13 [R/W]
B,H,W
---00000
TPUTCN14 [R/W]
B,H,W
---00000
TPUTCN15 [R/W]
B,H,W
---00000
TPUTCN16 [R/W]
B,H,W
---00000
TPUTCN17 [R/W]
B,H,W
---00000
000974H
000978H
00097CH
000980H
000984H
000988H
00098CH
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
000BF0H
000BF4H
―
000BF8H
―
000BFCH
―
HSCFR [R/W] B,H,W
-------- ------00 00000000 00000000
―
―
―
MBR [R/W] B,H,W
―
00------ XXXXXXXX
UER [W] B,H,W
―
-------- -------X
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
Time Protection
Unit [S]
TPUTCC0 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC1 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC2 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC3 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC4 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC5 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC6 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC7 [R] B,H,W
-------- 00000000 00000000 00000000
000970H
000990H
to
0009FCH
000A00H
to
000BECH
Address offset value / Register name
+1
+2
Reserved
OCDU
73
D a t a S h e e t
Address
000C00H
000C04H
000C08H
000C0CH
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
000C48H
000C4CH
000C50H
000C54H
000C58H
000C5CH
74
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
DCCR0 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR0 [R/W] H
DTCR0 [R/W] H
0------- -----000
00000000 00000000
DSAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCSR1 [R/W] H
DTCR1 [R/W] H
0------- -----000
00000000 00000000
DSAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR2 [R/W] H
DTCR2 [R/W] H
0------- -----000
00000000 00000000
DSAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR3 [R/W] H
DTCR3 [R/W] H
0------- -----000
00000000 00000000
DSAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR4 [R/W] H
DTCR4 [R/W] H
0------- -----000
00000000 00000000
DSAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR5 [R/W] H
DTCR5 [R/W] H
0------- -----000
00000000 00000000
DSAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
DMA
Controller
[S]
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
000C60H
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
000C80H
000C84H
000C88H
000C8CH
000C90H
000C94H
000C98H
000C9CH
000CA0H
000CA4H
000CA8H
000CACH
000CB0H
000CB4H
000CB8H
000CBCH
+0
Address offset value / Register name
+1
+2
DCCR6 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR6 [R/W] H
DTCR6 [R/W] H
0------- -----000
00000000 00000000
DSAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR7 [R/W] H
DTCR7 [R/W] H
0------- -----000
00000000 00000000
DSAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR8 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR8 [R/W] H
DTCR8 [R/W] H
0------- -----000
00000000 00000000
DSAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR9 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR9 [R/W] H
DTCR9 [R/W] H
0------- -----000
00000000 00000000
DSAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR10 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR10 [R/W] H
DTCR10 [R/W] H
0------- -----000
00000000 00000000
DSAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR11 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR11 [R/W] H
DTCR11 [R/W] H
0------- -----000
00000000 00000000
DSAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
DMA
Controller
[S]
75
D a t a S h e e t
Address
+0
000CC4H
000CC8H
000CCCH
000CD0H
000CD4H
000CD8H
000CDCH
000CE0H
000CE4H
000CE8H
000CECH
000CF0H
000CF4H
000CF8H
000CFCH
000D00H
to
000DF0H
―
000DF4H
―
000DF8H
76
CONFIDENTIAL
+3
DCCR12 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR12 [R/W] H
DTCR12 [R/W] H
0------- -----000
00000000 00000000
DSAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR13 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR13 [R/W] H
DTCR13 [R/W] H
0------- -----000
00000000 00000000
DSAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR14 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR14 [R/W] H
DTCR14 [R/W] H
0------- -----000
00000000 00000000
DSAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR15 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR15 [R/W] H
DTCR15 [R/W] H
0------- -----000
00000000 00000000
DSAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CC0H
000DFCH
Address offset value / Register name
+1
+2
―
―
―
DNMIR [R/W] B
0------0
DMACR[R/W] W
0------- -------- 0------- -------―
―
―
Block
DMA
Controller
[S]
―
DILVR [R/W] B
---11111
―
Reserved [S]
DMA
Controller
[S]
Reserved [S]
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
000E00H
000E04H
000E08H
000E0CH
000E10H
000E14H
000E18H
000E1CH
000E20H
000E24H
000E28H
000E2CH
000E30H
000E34H
000E38H
000E3CH
000E40H
000E44H
000E48H
000E4CH
000E50H
000E54H
000E58H
000E5CH
000E60H
000E64H
+0
Address offset value / Register name
+1
+2
DDR00 [R/W] B,H,W
00000000
DDR04 [R/W] B,H,W
00000000
DDR08 [R/W] B,H,W
00000000
DDR12 [R/W] B,H,W
00000000
DDR20 [R/W] B,H,W
00000000
DDR24 [R/W] B,H,W
--000000
DDR16 [R/W] B,H,W
00000000
DDR28 [R/W] B,H,W
00000000
PFR00 [R/W] B,H,W
00000000
PFR04 [R/W] B,H,W
00000000
PFR08 [R/W] B,H,W
00000000
PFR12 [R/W] B,H,W
00000000
PFR20 [R/W] B,H,W
00000000
PFR24 [R/W] B,H,W
--000000
PFR16 [R/W] B,H,W
00000000
PFR28 [R/W] B,H,W
00000000
PDDR00 [R] B,H,W
XXXXXXXX
PDDR04 [R] B,H,W
XXXXXXXX
PDDR08 [R] B,H,W
XXXXXXXX
PDDR12 [R] B,H,W
XXXXXXXX
PDDR20 [R] B,H,W
XXXXXXXX
PDDR24 [R] B,H,W
--XXXXXX
PDDR16 [R] B,H,W
XXXXXXXX
PDDR28 [R] B,H,W
XXXXXXXX
EPFR00 [R/W]
B,H,W
00000000
EPFR04 [R/W]
B,H,W
----00-0
DDR01 [R/W] B,H,W
00000000
DDR05 [R/W] B,H,W
00000000
DDR09 [R/W] B,H,W
00000000
DDR13 [R/W] B,H,W
-000--00
DDR21 [R/W] B,H,W
00000000
DDR25 [R/W] B,H,W
-0000000
DDR17 [R/W] B,H,W
00000000
DDR29 [R/W] B,H,W
00000000
PFR01 [R/W] B,H,W
00000000
PFR05 [R/W] B,H,W
00000000
PFR09 [R/W] B,H,W
00000000
PFR13 [R/W] B,H,W
-000--00
PFR21 [R/W] B,H,W
00000000
PFR25 [R/W] B,H,W
-0000000
PFR17 [R/W] B,H,W
00000000
PFR29 [R/W] B,H,W
00000000
PDDR01 [R] B,H,W
XXXXXXXX
PDDR05 [R] B,H,W
XXXXXXXX
PDDR09 [R] B,H,W
XXXXXXXX
PDDR13 [R] B,H,W
-XXX--XX
PDDR21 [R] B,H,W
XXXXXXXX
PDDR25 [R] B,H,W
-XXXXXXX
PDDR17 [R] B,H,W
XXXXXXXX
PDDR29 [R] B,H,W
XXXXXXXX
EPFR01 [R/W]
B,H,W
-0-0-000
EPFR05 [R/W]
B,H,W
----0000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
DDR02 [R/W] B,H,W
00000000
DDR06 [R/W] B,H,W
00000000
DDR10 [R/W] B,H,W
00000000
DDR14 [R/W] B,H,W
-------DDR22 [R/W] B,H,W
000--000
DDR26 [R/W] B,H,W
000000-DDR18 [R/W] B,H,W
00000000
DDR03 [R/W] B,H,W
00000000
DDR07 [R/W] B,H,W
00000000
DDR11 [R/W] B,H,W
00000000
DDR15 [R/W] B,H,W
--000000
DDR23 [R/W] B,H,W
00000000
DDR27 [R/W] B,H,W
000-0000
DDR19 [R/W] B,H,W
00000000
―
―
PFR02 [R/W] B,H,W
00000000
PFR06 [R/W] B,H,W
00000000
PFR10 [R/W] B,H,W
00000000
PFR14 [R/W] B,H,W
-------PFR22 [R/W] B,H,W
000--000
PFR26 [R/W] B,H,W
000000-PFR18 [R/W] B,H,W
00000000
PFR03 [R/W] B,H,W
00000000
PFR07 [R/W] B,H,W
00000000
PFR11 [R/W] B,H,W
00000000
PFR15 [R/W] B,H,W
--000000
PFR23 [R/W] B,H,W
00000000
PFR27 [R/W] B,H,W
000-0000
PFR19 [R/W] B,H,W
00000000
―
―
PDDR02 [R] B,H,W
XXXXXXXX
PDDR06 [R] B,H,W
XXXXXXXX
PDDR10 [R] B,H,W
XXXXXXXX
PDDR14 [R] B,H,W
-------PDDR22 [R] B,H,W
XXX--XXX
PDDR26 [R] B,H,W
XXXXXX-PDDR18 [R] B,H,W
XXXXXXXX
PDDR03 [R] B,H,W
XXXXXXXX
PDDR07 [R] B,H,W
XXXXXXXX
PDDR11 [R] B,H,W
XXXXXXXX
PDDR15 [R] B,H,W
--XXXXXX
PDDR23 [R] B,H,W
XXXXXXXX
PDDR27 [R] B,H,W
XXX-XXXX
PDDR19 [R] B,H,W
XXXXXXXX
―
―
EPFR02 [R/W]
B,H,W
----0000
EPFR06 [R/W]
B,H,W
----000-
EPFR03 [R/W]
B,H,W
---000-0
EPFR07 [R/W]
B,H,W
---00000
Block
Data Direction
Register
Port Function
Register
Port Direct
Read Register
Extended Port
Function Register
77
D a t a S h e e t
Address
+0
Address offset value / Register name
+1
+2
000E70H
000E74H
EPFR08 [R/W]
B,H,W
---00000
EPFR12 [R/W]
B,H,W
----0000
―
―
EPFR09 [R/W]
B,H,W
-----00EPFR13 [R/W]
B,H,W
------00
―
―
000E78H
―
―
000E7CH
EPFR28 [R/W]
B,H,W
--000-0-
000E80H
―
EPFR29 [R/W]
B,H,W
00000000
EPFR33 [R/W]
B,H,W
-----00-
000E84H
EPFR36 [R/W]
B,H,W
----0-0-
000E88H
000E68H
000E6CH
000E8CH
000E90H
000E94H
000E98H
000E9CH
000EA0H
to
000EB0H
000EB4H
000EB8H
EPFR10 [R/W]
B,H,W
----0000
EPFR14 [R/W]
B,H,W
------00
―
―
EPFR26 [R/W]
B,H,W
00000000
EPFR11 [R/W]
B,H,W
----0000
EPFR15 [R/W]
B,H,W
-----000
―
―
EPFR27 [R/W]
B,H,W
---0----
―
―
EPFR34 [R/W]
B,H,W
-----00-
EPFR35 [R/W]
B,H,W
---00000
―
―
―
―
―
EPFR42 [R/W]
B,H,W
------00
EPFR43 [R/W]
B,H,W
0--0000-
EPFR44 [R/W]
B,H,W
-00---0EPFR48 [R/W]
B,H,W
-----0-0
―
EPFR56 [R/W]
B,H,W
-----0-0
EPFR60 [R/W]
B,H,W
----00--
EPFR45 [R/W]
B,H,W
-0000000
EPFR49 [R/W]
B,H,W
-----000
―
EPFR57 [R/W]
B,H,W
-----0-0
EPFR61 [R/W]
B,H,W
-----00-
―
―
EPFR50 [R/W]
B,H,W
------00
―
EPFR58 [R/W]
B,H,W
----00-0
EPFR62 [R/W]
B,H,W
-----00-
EPFR51 [R/W]
B,H,W
---00000
―
EPFR59 [R/W]
B,H,W
----00-0
EPFR63 [R/W]
B,H,W
---0-0--
―
―
―
―
CPCLR9 [R/W] W
11111111 11111111 11111111 11111111
TCDT9 [R/W] W
00000000 00000000 00000000 00000000
TCCSH9 [R/W]
TCCSL9 [R/W] B,H,W
B,H,W
―
-1-00000
0-----00
PPER00 [R/W] B,H,W PPER01 [R/W] B,H,W PPER02 [R/W] B,H,W
000EC0H
00000000
00000000
00000000
PPER04 [R/W] B,H,W PPER05 [R/W] B,H,W PPER06 [R/W] B,H,W
000EC4H
00000000
00000000
00000000
PPER08 [R/W] B,H,W PPER09 [R/W] B,H,W PPER10 [R/W] B,H,W
000EC8H
00000000
00000000
00000000
PPER12 [R/W] B,H,W PPER13 [R/W] B,H,W PPER14 [R/W] B,H,W
000ECCH
00000000
-000--00
-------000EBCH
78
CONFIDENTIAL
+3
Block
Extended Port
Function Register
Reserved
Free-run Timer 9
32-bit FRT
―
PPER03 [R/W] B,H,W
00000000
PPER07 [R/W] B,H,W
00000000
Port Pull-up/down
PPER11 [R/W] B,H,W Enable Register
00000000
PPER15 [R/W] B,H,W
--000000
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
+0
Address offset value / Register name
+1
+2
+3
Block
PPER20 [R/W] B,H,W PPER21 [R/W] B,H,W PPER22 [R/W] B,H,W PPER23 [R/W] B,H,W
00000000
00000000
000--000
00000000
PPER24 [R/W] B,H,W PPER25 [R/W] B,H,W PPER26 [R/W] B,H,W PPER27 [R/W] B,H,W
000ED4H
--000000
-0000000
000000-000-0000
Port Pull-up/down
PPER16 [R/W] B,H,W PPER17 [R/W] B,H,W PPER18 [R/W] B,H,W PPER19 [R/W] B,H,W Enable Register
000ED8H
00000000
00000000
00000000
00000000
PPER28 [R/W] B,H,W PPER29 [R/W] B,H,W
000EDCH
―
―
00000000
00000000
PILR00[R/W] B,H,W PILR01[R/W] B,H,W
000EE0H
―
―
11-1--111111111
PILR05[R/W] B,H,W
000EE4H
―
―
―
-----1-Port Input
Level Register
PILR11[R/W] B,H,W
000EE8H
―
―
―
---1---PILR12[R/W] B,H,W
PILR15[R/W] B,H,W
000EECH
―
―
----1--1
--1----CPCLR10 [R/W] W
000EF0H
11111111 11111111 11111111 11111111
TCDT10 [R/W] W
000EF4H
Free-run Timer 10
00000000 00000000 00000000 00000000
32-bit FRT
TCCSH10 [R/W]
TCCSL10 [R/W]
000EF8H
B,H,W
B,H,W
―
―
0-----00
-1-00000
000EFCH
to
―
―
―
―
Reserved
000F0CH
UDCRL2 [R/W]
RCRH2 [R/W] H,W RCRL2 [R/W] B,H,W UDCRH2 [R/W] H,W
000F10H
B,H,W
XXXXXXXX
XXXXXXXX
00000000
00000000
UpDown Counter 2
CCR2 [R/W] B,H
CSR2 [R/W] B
000F14H
―
00000000 -0001000
00000000
UDCRL3 [R/W]
RCRH3 [R/W] H,W RCRL3 [R/W] B,H,W UDCRH3 [R/W] H,W
000F18H
B,H,W
XXXXXXXX
XXXXXXXX
00000000
00000000
UpDown Counter 3
CCR3 [R/W] B,H
CSR3 [R/W] B
000F1CH
―
00000000 -0001000
00000000
000F20H
to
―
―
―
―
Reserved
000F30H
000F34H,
―
―
―
―
Reserved
000F38H
OCLS1213 [R/W]
OCU12,13
000F3CH
―
―
―
B,H,W
Output level
----0000
control register
PORTEN [R/W]
Port Enable
000F40H
B,H,W
―
―
―
Register
-------0
KEYCDR [R/W] H
000F44H
―
―
KeyCodeRegister
00000000 00000000
000F48H
to
―
―
―
―
Reserved
000F64H
000ED0H
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
79
D a t a S h e e t
Address
000F68H
000F6CH
000F70H
000F74H
000F78H,
000F7CH
000F80H
000F84H
+0
Address offset value / Register name
+1
+2
―
―
RCRH1 [W] H,W
RCRL1 [W] B,H,W
XXXXXXXX
XXXXXXXX
CCR1 [R/W] B,H
00000000 -0001000
―
UDCRH1 [R] H,W
00000000
―
―
―
MSCH45 [R]
B,H,W
00000000
000F8CH
―
―
MSCH67 [R]
B,H,W
00000000
000F90H
000F94H
000F98H
―
000F9CH
―
000FA4H
TCCSH5
[R/W]B,H,W
0-----00
000FB0H
CONFIDENTIAL
―
―
TCCSL5 [R/W]B,H,W
-1-00000
―
TCCSH6
[R/W]B,H,W
0-----00
TCCSL6 [R/W]B,H,W
-1-00000
―
Reserved
UDCRL1 [R] B,H,W
00000000
UpDown Counter 1
CSR1 [R/W] B
00000000
Input Capture 4,5
MSCL45 [R/W]
32-bit ICU
B,H,W
Cycle and pulse
------00
width measurement
control 45
Input Capture 6,7
MSCL67 [R/W]
32-bit ICU
B,H,W
Cycle and pulse
------00
width measurement
control 67
OCSL1011 [R/W]
B,H,W
0000--00
OCLS1011 [R/W]
B,H,W
----0000
Output Compare
10,11
32-bit OCU
OCU10,11
Output level
control register
Free-run Timer 5
32-bit FRT
―
CPCLR6 [R/W] W
11111111 11111111 11111111 11111111
TCDT6 [R/W] W
00000000 00000000 00000000 00000000
000FACH
80
OCCP10 [R/W] W
00000000 00000000 00000000 00000000
OCCP11 [R/W] W
00000000 00000000 00000000 00000000
OCSH1011 [R/W]
―
B,H,W
---0--00
―
CPCLR5 [R/W] W
11111111 11111111 11111111 11111111
TCDT5 [R/W] W
00000000 00000000 00000000 00000000
000FA0H
000FB4H
Block
MSCY6 [R] H,W
Input
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Capture 6,7
Cycle measurement
MSCY7 [R] H,W
data register 67
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RCRH0 [W] H,W
RCRL0 [W] B,H,W
UDCRH0 [R] H,W
UDCRL0 [R] B,H,W
XXXXXXXX
XXXXXXXX
00000000
00000000
UpDown Counter 0
CCR0 [R/W] B,H
CSR0 [R/W] B
―
00000000 -0001000
00000000
000F88H
000FA8H
+3
Free-run Timer 6
32-bit FRT
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
+0
000FBCH
TCCSH7
[R/W]B,H,W
0-----00
000FC8H
000FD0H
000FD4H
000FD8H
000FDCH
000FE0H
000FE4H
000FE8H
000FECH
000FF0H
000FF4H
000FF8H
000FFCH
001000H
TCCSL7 [R/W]B,H,W
-1-00000
―
TCCSH8
[R/W]B,H,W
0-----00
TCCSL8 [R/W]B,H,W
-1-00000
―
―
Free-run Timer 8
32-bit FRT
―
IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
LSYNS2 [R/W] B,H,W LSYNS1 [R/W] B,H,W ICS45 [R/W] B,H,W
―
--000000
00000000
00000000
IPCP6 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS67 [R/W] B,H,W
―
―
―
00000000
IPCP8 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP9 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICS89 [R/W] B,H,W
―
―
―
00000000
MSCY8 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCY9 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MSCH89 [R] B,H,W MSCL89 [R/W] B,H,W
―
―
00000000
------00
SACR [R/W] B,H,W PICD [R/W] B,H,W
―
―
-------0
----0011
001004H
to
00112CH
―
―
―
―
001130H
―
―
―
CRCCR [R/W] B,H,W
-0000000
001134H
001138H
00113CH
CRCINIT [R/W] B,H,W
11111111 11111111 11111111 11111111
CRCIN [R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR [R] B,H,W
11111111 11111111 11111111 11111111
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Block
Free-run Timer 7
32-bit FRT
CPCLR8 [R/W] W
11111111 11111111 11111111 11111111
TCDT8 [R/W] W
00000000 00000000 00000000 00000000
000FC4H
000FCCH
+3
CPCLR7 [R/W] W
11111111 11111111 11111111 11111111
TCDT7 [R/W] W
00000000 00000000 00000000 00000000
000FB8H
000FC0H
Address offset value / Register name
+1
+2
Input
Capture 4,5
32-bit ICU
Input
Capture 6,7
32-bit ICU
Input
Capture 8,9
32-bit ICU
Clock Control
Reserved
CRC calculation
unit
81
D a t a S h e e t
Address
001140H
001144H
001148H
00114CH
Address offset value / Register name
+1
+2
+0
SCR16/(IBCR16)
SMR16
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR116/(TDR116))[R/W] B,H,W
-------- --------*3
SACSR16[R/W] B,H,W
0----000 00000000
STMCR16[R/W] B,H,W
00000000 00000000
001150H
― /(SCSTR316)/
(LAMSR16)
[R/W] B,H,W
--------*3
001154H
―
001158H
―/(TBYTE316)/
(LAMESR16)
[R/W] B,H,W
--------*3
00115CH
001160H
001164H
82
CONFIDENTIAL
― /(SCSTR216)/
(LAMCR16)
[R/W] B,H,W
--------*3
― /(SCSFR216)
[R/W] B,H,W
--------*3
―/(TBYTE216)/
(LAMERT16)
[R/W] B,H,W
--------*3
BGR16[R/W] H,W
00000000 00000000
FCR116
FCR016
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR16[R/W] B,H,W
00000000 00000000
+3
Block
SSR16
ESCR16/(IBSR16) Multi-UART16
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR016/(TDR016)[R/W] B,H,W
bits.
-------0 00000000*1
STMR16[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR16/SFUR16)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR116)/(SFLR11 /(SCSTR016)/(SFLR01 reset.
6)
6)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR116)
― /(SCSFR016)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE116)/
TBYTE016/(LAMRID
(LAMIER16)
16)/(LAMTID16) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK16)
― /(ISBA16)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE16[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001168H
00116CH
001170H
001174H
Address offset value / Register name
+1
+2
+0
SCR17/(IBCR17)
SMR17
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR117/(TDR117))[R/W] B,H,W
-------- --------*3
SACSR17[R/W] B,H,W
0----000 00000000
STMCR17[R/W] B,H,W
00000000 00000000
001178H
― /(SCSTR317)/
(LAMSR17)
[R/W] B,H,W
--------*3
00117CH
―
001180H
―/(TBYTE317)/
(LAMESR17)
[R/W] B,H,W
--------*3
001184H
001188H
00118CH
― /(SCSTR217)/
(LAMCR17)
[R/W] B,H,W
--------*3
― /(SCSFR217)
[R/W] B,H,W
--------*3
―/(TBYTE217)/
(LAMERT17)
[R/W] B,H,W
--------*3
BGR17[R/W] H,W
00000000 00000000
FCR117
FCR017
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR17[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
SSR17
ESCR17/(IBSR17) Multi-UART17
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR017/(TDR017)[R/W] B,H,W
bits.
-------0 00000000*1
STMR17[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR17/SFUR17)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR117)/(SFLR11 /(SCSTR017)/(SFLR01 reset.
7)
7)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR117)
― /(SCSFR017)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE117)/
TBYTE017/(LAMRID
(LAMIER17)
17)/(LAMTID17) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK17)
― /(ISBA17)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE17[R/W] B,H,W
00000000 00000000
―
―
83
D a t a S h e e t
Address
001190H
001194H
001198H
00119CH
Address offset value / Register name
+1
+2
+0
SCR18/(IBCR18)
SMR18
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR118/(TDR118))[R/W] B,H,W
-------- --------*3
SACSR18[R/W] B,H,W
0----000 00000000
STMCR18[R/W] B,H,W
00000000 00000000
0011A0H
― /(SCSTR318)/
(LAMSR18)
[R/W] B,H,W
--------*3
0011A4H
―
0011A8H
―/(TBYTE318)/
(LAMESR18)
[R/W] B,H,W
--------*3
0011ACH
0011B0H
0011B4H
84
CONFIDENTIAL
― /(SCSTR218)/
(LAMCR18)
[R/W] B,H,W
--------*3
― /(SCSFR218)
[R/W] B,H,W
--------*3
―/(TBYTE218)/
(LAMERT18)
[R/W] B,H,W
--------*3
BGR18[R/W] H,W
00000000 00000000
FCR118
FCR018
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR18[R/W] B,H,W
00000000 00000000
+3
Block
SSR18
ESCR18/(IBSR18) Multi-UART18
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR018/(TDR018)[R/W] B,H,W
bits.
-------0 00000000*1
STMR18[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR18/SFUR18)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR118)/(SFLR11 /(SCSTR018)/(SFLR01 reset.
8)
8)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR118)
― /(SCSFR018)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE118)/
TBYTE018/(LAMRID
(LAMIER18)
18)/(LAMTID18) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK18)
― /(ISBA18)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE18[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
0011B8H
0011BCH
0011C0H
0011C4H
Address offset value / Register name
+1
+2
+0
SCR19/(IBCR19)
SMR19
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR119/(TDR119))[R/W] B,H,W
-------- --------*3
SACSR19[R/W] B,H,W
0----000 00000000
STMCR19[R/W] B,H,W
00000000 00000000
0011C8H
― /(SCSTR319)/
(LAMSR19)
[R/W] B,H,W
--------*3
0011CCH
―
0011D0H
―/(TBYTE319)/
(LAMESR19)
[R/W] B,H,W
--------*3
0011DCH
― /(SCSFR219)
[R/W] B,H,W
--------*3
―/(TBYTE219)/
(LAMERT19)
[R/W] B,H,W
--------*3
BGR19[R/W] H,W
00000000 00000000
0011D4H
0011D8H
― /(SCSTR219)/
(LAMCR19)
[R/W] B,H,W
--------*3
FCR119
FCR019
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR19[R/W] B,H,W
00000000 00000000
FBYTE19[R/W] B,H,W
00000000 00000000
―
―
―
―
―
001200H
TCGS [R/W] B,H,W
------00
―
―
―
―
―
001204H
001208H
00120CH
001210H
001214H
001218H
00121CH
to
001230H
Reserved
16-bit Free-run
TCGSE [R/W] B,H,W
timer synchronous
-----000
activation
CPCLRB0/CPCLR0 [W] H,W
TCDT0 [R/W] H,W
11111111 11111111
00000000 00000000
16-bit Free-run
timer 0
TCCS0 [R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB1/CPCLR1 [W] H,W
TCDT1 [R/W] H,W
11111111 11111111
00000000 00000000
16-bit Free-run
timer 1
TCCS1 [R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB2/CPCLR2 [W] H,W
TCDT2 [R/W] H,W
11111111 11111111
00000000 00000000
16-bit Free-run
timer 2
TCCS2 [R/W] B,H,W
00000000 01000000 ----0000 --------
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Block
SSR19
ESCR19/(IBSR19) Multi-UART19
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR019/(TDR019)[R/W] B,H,W
bits.
-------0 00000000*1
STMR19[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR19/SFUR19)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR119)/(SFLR11 /(SCSTR019)/(SFLR01 reset.
9)
9)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR119)
― /(SCSFR019)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE119)/
TBYTE019/(LAMRID
(LAMIER19)
19)/(LAMTID19) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK19)
― /(ISBA19)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
0011E0H
to
0011FCH
―
+3
―
Reserved
85
D a t a S h e e t
Address
001234H
001238H
00123CH
001240H
001244H
001248H
00124CH
001250H
001254H
001258H
00125CH
001260H
001264H
to
001278H
+0
―
001284H
001288H
CONFIDENTIAL
―
IPCP0 [R] H,W
00000000 00000000
ICS01 [R/W] B,H,W
------00 00000000
IPCP2 [R] H,W
00000000 00000000
ICS23 [R/W] B,H,W
------00 00000000
001280H
86
+3
FRS0 [R/W] B,H,W
-------- --00--00 --00--00 --00--00
FRS1 [R/W] B,H,W
―
--00--00 --00--00
FRS2 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS3 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS4 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
―
―
―
―
OCCPB0/OCCP0 [R/W] H,W
OCCPB1/OCCP1 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD01 [R/W]
OCS01 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
OCCPB2/OCCP2 [R/W] H,W
OCCPB3/OCCP3 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD23 [R/W]
OCS23 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
OCCPB4/OCCP4 [R/W] H,W
OCCPB5/OCCP5 [R/W] H,W
00000000 00000000
00000000 00000000
OCMOD45 [R/W]
OCS45 [R/W] B,H,W
―
B,H,W
-110--00 00001100
------00
00127CH
00128CH
to
001298H
00129CH
Address offset value / Register name
+1
+2
―
―
IPCP1 [R] H,W
00000000 00000000
LSYNS [R/W] B,H,W
―
----0000
IPCP3 [R] H,W
00000000 00000000
―
―
Block
16-bit Free-run
timer selection
Reserved
16-bit Output
compare 0/1
16-bit Output
compare 2/3
16-bit Output
compare 4/5
Reserved
16-bit Input
capture 0/1
16-bit Input
capture 2/3
―
―
―
―
Reserved
―
―
―
―
Reserved
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
0012A0H
0012A4H
0012A8H
0012ACH
0012B0H
0012B4H
0012B8H
to
0012CCH
+0
―
―
―
―
FRS5 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS6 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS7 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS10 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
FRS11 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
0012D4H
0012D8H
0012DCH
0012E0H
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
TMRR0 [R/W] H,W
TMRR1 [R/W] H,W
00000000 00000001
00000000 00000001
TMRR2 [R/W] H,W
―
―
00000000 00000001
DTSCR0 [R/W]
DTSCR1 [R/W] B,H,W DTSCR2 [R/W] B,H,W
B,H,W
―
00000000
00000000
00000000
DTMNS0 [R/W]
DTIR0 [R/W] B,H,W
―
―
B,H,W
000000-00---000
SIGCR10 [R/W]
SIGCR20 [R/W]
―
B,H,W
―
B,H,W
00000000
000000-1
PICS0 [R/W] B,H,W
000000-- -------- -------- --------
0012D0H
0012E4H
to
0012FCH
001300H
Address offset value / Register name
+1
+2
―
―
―
Block
Waveform
generator
0/1/2
Reserved
16-bit Free-run
timer selection
A/D activation
compare
―
Reserved
Reserved
87
D a t a S h e e t
Address
001304H
001308H
00130CH
001310H
001314H
001318H
00131CH
001320H
001324H
001328H
00132CH
001330H
001334H
001338H
00133CH
001340H
001344H
001348H
00134CH
001350H
001354H
001358H
00135CH
001360H
001364H
001368H
88
CONFIDENTIAL
+0
ADTSS0[R/W]
B,H,W
-------0
Address offset value / Register name
+1
+2
―
―
+3
Block
―
ADTSE0[R/W] B,H,W
00000000 00000000 00000000 00000000
ADCOMP0/ADCOMPB0[R/W] H,W
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP2/ADCOMPB2[R/W] H,W
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP4/ADCOMPB4[R/W] H,W
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP6/ADCOMPB6[R/W] H,W
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP8/ADCOMPB8[R/W] H,W
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP10/ADCOMPB10[R/W] H,W
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP12/ADCOMPB12[R/W] H,W
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP14/ADCOMPB14[R/W] H,W
ADCOMP15/ADCOMPB15[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP16/ADCOMPB16[R/W] H,W
ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP18/ADCOMPB18[R/W] H,W
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP20/ADCOMPB20[R/W] H,W
ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP22/ADCOMPB22[R/W] H,W
ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP24/ADCOMPB24[R/W] H,W
ADCOMP25/ADCOMPB25[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP26/ADCOMPB26[R/W] H,W
ADCOMP27/ADCOMPB27[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP28/ADCOMPB28[R/W] H,W
ADCOMP29/ADCOMPB29[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP30/ADCOMPB30[R/W] H,W
ADCOMP31/ADCOMPB31[R/W] H,W
00000000 00000000
00000000 00000000
ADTCS0[R/W] B,H,W
ADTCS1[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS2[R/W] B,H,W
ADTCS3[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS4[R/W] B,H,W
ADTCS5[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS6[R/W] B,H,W
ADTCS7[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS8[R/W] B,H,W
ADTCS9[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS10[R/W] B,H,W
ADTCS11[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS12[R/W] B,H,W
ADTCS13[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS14[R/W] B,H,W
ADTCS15[R/W] B,H,W
00000000 0010---00000000 0010----
12-bit A/D
converter
1/2 unit
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
00136CH
001370H
001374H
001378H
00137CH
001380H
001384H
001388H
00138CH
001390H
001394H
001398H
00139CH
0013A0H
0013A4H
0013A8H
0013ACH
0013B0H
0013B4H
0013B8H
0013BCH
0013C0H
0013C4H
0013C8H
+0
Address offset value / Register name
+1
+2
ADTCS16[R/W] B,H,W
00000000 0010---ADTCS18[R/W] B,H,W
00000000 0010---ADTCS20[R/W] B,H,W
00000000 0010---ADTCS22[R/W] B,H,W
00000000 0010---ADTCS24[R/W] B,H,W
00000000 0010---ADTCS26[R/W] B,H,W
00000000 0010---ADTCS28[R/W] B,H,W
00000000 0010---ADTCS30[R/W] B,H,W
00000000 0010---ADTCD0[R] B,H,W
10--0000 00000000
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD8[R] B,H,W
10--0000 00000000
ADTCD10[R] B,H,W
10--0000 00000000
ADTCD12[R] B,H,W
10--0000 00000000
ADTCD14[R] B,H,W
10--0000 00000000
ADTCD16[R] B,H,W
10--0000 00000000
ADTCD18[R] B,H,W
10--0000 00000000
ADTCD20[R] B,H,W
10--0000 00000000
ADTCD22[R] B,H,W
10--0000 00000000
ADTCD24[R] B,H,W
10--0000 00000000
ADTCD26[R] B,H,W
10--0000 00000000
ADTCD28[R] B,H,W
10--0000 00000000
ADTCD30[R] B,H,W
10--0000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
ADTCS17[R/W] B,H,W
00000000 0010---ADTCS19[R/W] B,H,W
00000000 0010---ADTCS21[R/W] B,H,W
00000000 0010---ADTCS23[R/W] B,H,W
00000000 0010---ADTCS25[R/W] B,H,W
00000000 0010---ADTCS27[R/W] B,H,W
00000000 0010---ADTCS29[R/W] B,H,W
00000000 0010---ADTCS31[R/W] B,H,W
00000000 0010---ADTCD1[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
ADTCD9[R] B,H,W
10--0000 00000000
ADTCD11[R] B,H,W
10--0000 00000000
ADTCD13[R] B,H,W
10--0000 00000000
ADTCD15[R] B,H,W
10--0000 00000000
ADTCD17[R] B,H,W
10--0000 00000000
ADTCD19[R] B,H,W
10--0000 00000000
ADTCD21[R] B,H,W
10--0000 00000000
ADTCD23[R] B,H,W
10--0000 00000000
ADTCD25[R] B,H,W
10--0000 00000000
ADTCD27[R] B,H,W
10--0000 00000000
ADTCD29[R] B,H,W
10--0000 00000000
ADTCD31[R] B,H,W
10--0000 00000000
Block
12-bit A/D
converter
1/2 unit
89
D a t a S h e e t
Address
0013CCH
0013D0H
0013D4H
0013D8H
0013DCH
0013E0H
0013E4H
0013E8H
0013ECH
0013F0H
0013F4H
0013F8H
0013FCH
001400H
001404H
001408H
00140CH
001410H
001414H
001418H
90
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
ADTECS0[R/W] B,H,W
-------0 ---00000
ADTECS2[R/W] B,H,W
-------0 ---00000
ADTECS4[R/W] B,H,W
-------0 ---00000
ADTECS6[R/W] B,H,W
-------0 ---00000
ADTECS8[R/W] B,H,W
-------0 ---00000
ADTECS10[R/W] B,H,W
-------0 ---00000
ADTECS12[R/W] B,H,W
-------0 ---00000
ADTECS14[R/W] B,H,W
-------0 ---00000
ADTECS16[R/W] B,H,W
-------0 ---00000
ADTECS18[R/W] B,H,W
-------0 ---00000
ADTECS20[R/W] B,H,W
-------0 ---00000
ADTECS22[R/W] B,H,W
-------0 ---00000
ADTECS24[R/W] B,H,W
-------0 ---00000
ADTECS26[R/W] B,H,W
-------0 ---00000
ADTECS28[R/W] B,H,W
-------0 ---00000
ADTECS30[R/W] B,H,W
-------0 ---00000
ADRCUT0[R/W] B,H,W
----0000 00000000
ADRCUT1[R/W] B,H,W
----0000 00000000
ADRCUT2[R/W] B,H,W
----0000 00000000
ADRCUT3[R/W] B,H,W
----0000 00000000
+3
ADTECS1[R/W] B,H,W
-------0 ---00000
ADTECS3[R/W] B,H,W
-------0 ---00000
ADTECS5[R/W] B,H,W
-------0 ---00000
ADTECS7[R/W] B,H,W
-------0 ---00000
ADTECS9[R/W] B,H,W
-------0 ---00000
ADTECS11[R/W] B,H,W
-------0 ---00000
ADTECS13[R/W] B,H,W
-------0 ---00000
ADTECS15[R/W] B,H,W
-------0 ---00000
ADTECS17[R/W] B,H,W
-------0 ---00000
ADTECS19[R/W] B,H,W
-------0 ---00000
ADTECS21[R/W] B,H,W
-------0 ---00000
ADTECS23[R/W] B,H,W
-------0 ---00000
ADTECS25[R/W] B,H,W
-------0 ---00000
ADTECS27[R/W] B,H,W
-------0 ---00000
ADTECS29[R/W] B,H,W
-------0 ---00000
ADTECS31[R/W] B,H,W
-------0 ---00000
ADRCLT0[R/W] B,H,W
----0000 00000000
ADRCLT1[R/W] B,H,W
----0000 00000000
ADRCLT2[R/W] B,H,W
----0000 00000000
ADRCLT3[R/W] B,H,W
----0000 00000000
Block
12-bit A/D
converter
1/2 unit
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
00141CH
001420H
001424H
001428H
00142CH
001430H
001434H
001438H
00143CH
001440H
001444H
001448H
00144CH
001450H
001454H
001458H
00145CH
001460H
001464H
001468H
00146CH
+0
ADRCCS0[R/W]
B,H,W
00000000
ADRCCS4[R/W]
B,H,W
00000000
ADRCCS8[R/W]
B,H,W
00000000
ADRCCS12[R/W]
B,H,W
00000000
ADRCCS16[R/W]
B,H,W
00000000
ADRCCS20[R/W]
B,H,W
00000000
ADRCCS24[R/W]
B,H,W
00000000
ADRCCS28[R/W]
B,H,W
00000000
Address offset value / Register name
+1
+2
ADRCCS1[R/W]
ADRCCS2[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS5[R/W]
ADRCCS6[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS9[R/W]
ADRCCS10[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS13[R/W]
ADRCCS14[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS17[R/W]
ADRCCS18[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS21[R/W]
ADRCCS22[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS25[R/W]
ADRCCS26[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS29[R/W]
ADRCCS30[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCOT0[R] B,H,W
00000000 00000000 00000000 00000000
ADRCIF0[R,W] B,H,W
00000000 00000000 00000000 00000000
Block
ADRCCS3[R/W]
B,H,W
00000000
ADRCCS7[R/W]
B,H,W
00000000
ADRCCS11[R/W]
B,H,W
00000000
ADRCCS15[R/W]
B,H,W
00000000
ADRCCS19[R/W]
B,H,W
00000000
ADRCCS23[R/W]
B,H,W
00000000
ADRCCS27[R/W]
B,H,W
00000000
ADRCCS31[R/W]
B,H,W
00000000
ADSCANS0[R/W]
B,H,W
―
―
―
000----ADNCS0[R/W] B,H,W ADNCS1[R/W] B,H,W ADNCS2[R/W] B,H,W ADNCS3[R/W] B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS4[R/W] B,H,W ADNCS5[R/W] B,H,W ADNCS6[R/W] B,H,W ADNCS7[R/W] B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS10[R/W]
ADNCS11[R/W]
ADNCS8[R/W] B,H,W ADNCS9[R/W] B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADNCS12[R/W]
ADNCS13[R/W]
ADNCS14[R/W]
ADNCS15[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
0-000-00
ADPRTF0[R] B,H,W
00000000 00000000 00000000 00000000
ADEOCF0[R] B,H,W
11111111 11111111 11111111 11111111
ADCS0[R] B,H,W
ADCH0[R] B,H,W ADMD0[R/W] B,H,W
0------- ----------00000
0---0000
ADSTPCS0[R/W]
ADSTPCS1[R/W]
ADSTPCS2[R/W]
ADSTPCS3[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADSTPCS4[R/W]
ADSTPCS5[R/W]
ADSTPCS6[R/W]
ADSTPCS7[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
12-bit A/D
converter
1/2 unit
91
D a t a S h e e t
Address
001470H
001474H
001478H
00147CH
001480H
001484H
001488H
00148CH
001490H
001494H
001498H
00149CH
0014A0H
0014A4H
0014A8H
0014ACH
0014B0H
0014B4H
0014B8H
0014BCH
0014C0H
0014C4H
0014C8H
0014CCH
0014D0H
0014D4H
92
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
ADTSS1[R/W] B,H,W
-------0
―
―
+3
Block
―
ADTSE1[R/W] B,H,W
00000000 00000000 00000000 00000000
ADCOMP32/ADCOMPB32[R/W] H,W
ADCOMP33/ADCOMPB33[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP34/ADCOMPB34[R/W] H,W
ADCOMP35/ADCOMPB35[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP36/ADCOMPB36[R/W] H,W
ADCOMP37/ADCOMPB37[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP38/ADCOMPB38[R/W] H,W
ADCOMP39/ADCOMPB39[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP40/ADCOMPB40[R/W] H,W
ADCOMP41/ADCOMPB41[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP42/ADCOMPB42[R/W] H,W
ADCOMP43/ADCOMPB43[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP44/ADCOMPB44[R/W] H,W
ADCOMP45/ADCOMPB45[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP46/ADCOMPB46[R/W] H,W
ADCOMP47/ADCOMPB47[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP48/ADCOMPB48[R/W] H,W
ADCOMP49/ADCOMPB49[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP50/ADCOMPB50[R/W] H,W
ADCOMP51/ADCOMPB51[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP52/ADCOMPB52[R/W] H,W
ADCOMP53/ADCOMPB53[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP54/ADCOMPB54[R/W] H,W
ADCOMP55/ADCOMPB55[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP56/ADCOMPB56[R/W] H,W
ADCOMP57/ADCOMPB57[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP58/ADCOMPB58[R/W] H,W
ADCOMP59/ADCOMPB59[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP60/ADCOMPB60[R/W] H,W
ADCOMP61/ADCOMPB61[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP62/ADCOMPB62[R/W] H,W
ADCOMP63/ADCOMPB63[R/W] H,W
00000000 00000000
00000000 00000000
ADTCS32[R/W] B,H,W
ADTCS33[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS34[R/W] B,H,W
ADTCS35[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS36[R/W] B,H,W
ADTCS37[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS38[R/W] B,H,W
ADTCS39[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS40[R/W] B,H,W
ADTCS41[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS42[R/W] B,H,W
ADTCS43[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS44[R/W] B,H,W
ADTCS45[R/W] B,H,W
00000000 0010---00000000 0010---ADTCS46[R/W] B,H,W
ADTCS47[R/W] B,H,W
00000000 0010---00000000 0010----
12-bit A/D
converter
2/2 unit
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
0014D8H
0014DCH
0014E0H
0014E4H
0014E8H
0014ECH
0014F0H
0014F4H
0014F8H
0014FCH
001500H
001504H
001508H
00150CH
001510H
001514H
001518H
00151CH
001520H
001524H
001528H
00152CH
001530H
001534H
+0
Address offset value / Register name
+1
+2
ADTCS48[R/W] B,H,W
00000000 0010---ADTCS50[R/W] B,H,W
00000000 0010---ADTCS52[R/W] B,H,W
00000000 0010---ADTCS54[R/W] B,H,W
00000000 0010---ADTCS56[R/W] B,H,W
00000000 0010---ADTCS58[R/W] B,H,W
00000000 0010---ADTCS60[R/W] B,H,W
00000000 0010---ADTCS62[R/W] B,H,W
00000000 0010---ADTCD32[R] B,H,W
10--0000 00000000
ADTCD34[R] B,H,W
10--0000 00000000
ADTCD36[R] B,H,W
10--0000 00000000
ADTCD38[R] B,H,W
10--0000 00000000
ADTCD40[R] B,H,W
10--0000 00000000
ADTCD42[R] B,H,W
10--0000 00000000
ADTCD44[R] B,H,W
10--0000 00000000
ADTCD46[R] B,H,W
10--0000 00000000
ADTCD48[R] B,H,W
10--0000 00000000
ADTCD50[R] B,H,W
10--0000 00000000
ADTCD52[R] B,H,W
10--0000 00000000
ADTCD54[R] B,H,W
10--0000 00000000
ADTCD56[R] B,H,W
10--0000 00000000
ADTCD58[R] B,H,W
10--0000 00000000
ADTCD60[R] B,H,W
10--0000 00000000
ADTCD62[R] B,H,W
10--0000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
ADTCS49[R/W] B,H,W
00000000 0010---ADTCS51[R/W] B,H,W
00000000 0010---ADTCS53[R/W] B,H,W
00000000 0010---ADTCS55[R/W] B,H,W
00000000 0010---ADTCS57[R/W] B,H,W
00000000 0010---ADTCS59[R/W] B,H,W
00000000 0010---ADTCS61[R/W] B,H,W
00000000 0010---ADTCS63[R/W] B,H,W
00000000 0010---ADTCD33[R] B,H,W
10--0000 00000000
ADTCD35[R] B,H,W
10--0000 00000000
ADTCD37[R] B,H,W
10--0000 00000000
ADTCD39[R] B,H,W
10--0000 00000000
ADTCD41[R] B,H,W
10--0000 00000000
ADTCD43[R] B,H,W
10--0000 00000000
ADTCD45[R] B,H,W
10--0000 00000000
ADTCD47[R] B,H,W
10--0000 00000000
ADTCD49[R] B,H,W
10--0000 00000000
ADTCD51[R] B,H,W
10--0000 00000000
ADTCD53[R] B,H,W
10--0000 00000000
ADTCD55[R] B,H,W
10--0000 00000000
ADTCD57[R] B,H,W
10--0000 00000000
ADTCD59[R] B,H,W
10--0000 00000000
ADTCD61[R] B,H,W
10--0000 00000000
ADTCD63[R] B,H,W
10--0000 00000000
Block
12-bit A/D
converter
2/2 unit
93
D a t a S h e e t
Address
001538H
00153CH
001540H
001544H
001548H
00154CH
001550H
001554H
001558H
00155CH
001560H
001564H
001568H
00156CH
001570H
001574H
001578H
00157CH
001580H
001584H
94
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
ADTECS32[R/W] B,H,W
-------0 ---00000
ADTECS34[R/W] B,H,W
-------0 ---00000
ADTECS36[R/W] B,H,W
-------0 ---00000
ADTECS38[R/W] B,H,W
-------0 ---00000
ADTECS40[R/W] B,H,W
-------0 ---00000
ADTECS42[R/W] B,H,W
-------0 ---00000
ADTECS44[R/W] B,H,W
-------0 ---00000
ADTECS46[R/W] B,H,W
-------0 ---00000
ADTECS48[R/W] B,H,W
-------0 ---00000
ADTECS50[R/W] B,H,W
-------0 ---00000
ADTECS52[R/W] B,H,W
-------0 ---00000
ADTECS54[R/W] B,H,W
-------0 ---00000
ADTECS56[R/W] B,H,W
-------0 ---00000
ADTECS58[R/W] B,H,W
-------0 ---00000
ADTECS60[R/W] B,H,W
-------0 ---00000
ADTECS62[R/W] B,H,W
-------0 ---00000
ADRCUT4[R/W] B,H,W
----0000 00000000
ADRCUT5[R/W] B,H,W
----0000 00000000
ADRCUT6[R/W] B,H,W
----0000 00000000
ADRCUT7[R/W] B,H,W
----0000 00000000
+3
ADTECS33[R/W] B,H,W
-------0 ---00000
ADTECS35[R/W] B,H,W
-------0 ---00000
ADTECS37[R/W] B,H,W
-------0 ---00000
ADTECS39[R/W] B,H,W
-------0 ---00000
ADTECS41[R/W] B,H,W
-------0 ---00000
ADTECS43[R/W] B,H,W
-------0 ---00000
ADTECS45[R/W] B,H,W
-------0 ---00000
ADTECS47[R/W] B,H,W
-------0 ---00000
ADTECS49[R/W] B,H,W
-------0 ---00000
ADTECS51[R/W] B,H,W
-------0 ---00000
ADTECS53[R/W] B,H,W
-------0 ---00000
ADTECS55[R/W] B,H,W
-------0 ---00000
ADTECS57[R/W] B,H,W
-------0 ---00000
ADTECS59[R/W] B,H,W
-------0 ---00000
ADTECS61[R/W] B,H,W
-------0 ---00000
ADTECS63[R/W] B,H,W
-------0 ---00000
ADRCLT4[R/W] B,H,W
----0000 00000000
ADRCLT5[R/W] B,H,W
----0000 00000000
ADRCLT6[R/W] B,H,W
----0000 00000000
ADRCLT7[R/W] B,H,W
----0000 00000000
Block
12-bit A/D
converter
2/2 unit
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001588H
00158CH
001590H
001594H
001598H
00159CH
0015A0H
0015A4H
+0
ADRCCS32[R/W]
B,H,W
00000000
ADRCCS36[R/W]
B,H,W
00000000
ADRCCS40[R/W]
B,H,W
00000000
ADRCCS44[R/W]
B,H,W
00000000
ADRCCS48[R/W]
B,H,W
00000000
ADRCCS52[R/W]
B,H,W
00000000
ADRCCS56[R/W]
B,H,W
00000000
ADRCCS60[R/W]
B,H,W
00000000
0015A8H
0015ACH
0015B0H
0015B4H
0015B8H
0015BCH
0015C0H
0015C4H
0015C8H
0015CCH
0015D0H
0015D4H
Address offset value / Register name
+1
+2
ADRCCS33[R/W]
ADRCCS34[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS37[R/W]
ADRCCS38[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS41[R/W]
ADRCCS42[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS45[R/W]
ADRCCS46[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS49[R/W]
ADRCCS50[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS53[R/W]
ADRCCS54[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS57[R/W]
ADRCCS58[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCCS61[R/W]
ADRCCS62[R/W]
B,H,W
B,H,W
00000000
00000000
ADRCOT1 [R] B,H,W
00000000 00000000 00000000 00000000
ADRCIF1 [R,W] B,H,W
00000000 00000000 00000000 00000000
ADSCANS1 [R/W]
B,H,W
000----ADNCS16 [R/W]
B,H,W
0-000-00
ADNCS20 [R/W]
B,H,W
0-000-00
ADNCS24 [R/W]
B,H,W
0-000-00
ADNCS28 [R/W]
B,H,W
0-000-00
―
Block
ADRCCS35[R/W]
B,H,W
00000000
ADRCCS39[R/W]
B,H,W
00000000
ADRCCS43[R/W]
B,H,W
00000000
ADRCCS47[R/W]
B,H,W
00000000
ADRCCS51[R/W]
B,H,W
00000000
ADRCCS55[R/W]
B,H,W
00000000
ADRCCS59[R/W]
B,H,W
00000000
ADRCCS63[R/W]
B,H,W
00000000
12-bit A/D
converter
2/2 unit
―
ADNCS17 [R/W]
ADNCS18 [R/W]
ADNCS19 [R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADNCS21 [R/W]
ADNCS22 [R/W]
ADNCS23 [R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADNCS25 [R/W]
ADNCS26 [R/W]
ADNCS27 [R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADNCS29 [R/W]
ADNCS30 [R/W]
ADNCS31 [R/W]
B,H,W
B,H,W
B,H,W
0-000-00
0-000-00
0-000-00
ADPRTF1 [R] B,H,W
00000000 00000000 00000000 00000000
ADEOCF1 [R] B,H,W
11111111 11111111 11111111 11111111
ADCS1 [R] B,H,W
ADCH1 [R] B,H,W ADMD1 [R/W] B,H,W
0------- ----------00000
0---0000
ADSTPCS8 [R/W]
ADSTPCS9 [R/W]
ADSTPCS10 [R/W] ADSTPCS11 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
ADSTPCS12[R/W]
ADSTPCS13[R/W]
ADSTPCS14[R/W]
ADSTPCS15[R/W]
B,H,W
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
―
+3
95
D a t a S h e e t
Address
0015D8H
to
00174CH
001750H
001754H
001758H
00175CH
001760H
001764H
001768H
00176CH
001770H
001774H
96
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
―
―
SCR0/(IBCR0)[R/W]
SMR0[R/W]
B,H,W
B,H,W
0--00000
000-00-0
― /(RDR10/(TDR10))[R/W] B,H,W
-------- --------*3
SACSR0[R/W] B,H,W
0----000 00000000
STMCR0[R/W] B,H,W
00000000 00000000
― /(SCSTR30)/
― /(SCSTR20)/
(LAMSR0)
(LAMCR0)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR20)
―
[R/W] B,H,W
--------*3
―/(TBYTE30)/
―/(TBYTE20)
(LAMESR0)
/(LAMERT0)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR0[R/W] H, W
00000000 00000000
FCR10[R/W]
FCR00[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR0[R/W] B,H,W
00000000 00000000
―
+3
―
Block
Reserved
SSR0[R/W]
ESCR0/(IBSR0)[R/W] Multi-UART0
B,H,W
B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR00/(TDR00)[R/W] B,H,W
1
bits.
-------0 00000000*
STMR0[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR0/SFUR0)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR10)
― /(SCSTR00)/
reset.
/(SFLR10)
(SFLR00)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR10)
― /(SCSFR00)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE10)/
TBYTE00/(LAMRID0) reset.
(LAMIER0)
/(LAMTID0)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
mode is not set
― /(ISMK0)
― /(ISBA0)
immediately after
[R/W] B,H,W
[R/W] B,H,W
2
2
reset.
--------*
--------*
FBYTE0[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001778H
00177CH
001780H
001784H
001788H
00178CH
001790H
001794H
001798H
00179CH
+0
Address offset value / Register name
+1
+2
SCR1/(IBCR1) [R/W]
SMR1[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR11/(TDR11))[R/W] B,H,W
-------- --------*3
SACSR1[R/W] B,H,W
0----000 00000000
STMCR1[R/W] B,H,W
00000000 00000000
― /(SCSTR31)/
― /(SCSTR21)/
(LAMSR1)
(LAMCR1)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR21)[R/W]
―
B,H,W
--------*3
―/(TBYTE31)/
―/(TBYTE21)/
(LAMESR1)
(LAMERT1)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR1[R/W] H,W
00000000 00000000
FCR11[R/W]
FCR01[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR1[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
ESCR1/(IBSR1)[R/W] Multi-UART1
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR01/(TDR01)[R/W] B,H,W
bits.
-------0 00000000*1
STMR1[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR1/SFUR1)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR11)/
― /(SCSTR01)/
reset.
(SFLR11)
(SFLR01)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR11)
― /(SCSFR01)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE11)/
TBYTE01/(LAMRID1) reset.
(LAMIER1)
/(LAMTID1)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK1)[R/W]
― /(ISBA1)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR1[R/W] B,H,W
0-000011
FBYTE1[R/W] B,H,W
00000000 00000000
―
―
97
D a t a S h e e t
Address
0017A0H
0017A4H
0017A8H
0017ACH
0017B0H
0017B4H
0017B8H
0017BCH
0017C0H
0017C4H
98
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
SCR2/(IBCR2)[R/W]
SMR2[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR12/(TDR12))[R/W] B,H,W
-------- --------*3
SACSR2[R/W] B,H,W
0----000 00000000
STMCR2[R/W] B,H,W
00000000 00000000
― /(SCSTR32)/
― /(SCSTR22)/
(LAMSR2)
(LAMCR2)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR22)
―
[R/W] B,H,W
--------*3
―/(TBYTE32)/
―/(TBYTE22)/
(LAMESR2)
(LAMERT2)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR2[R/W] H, W
00000000 00000000
FCR12[R/W]
FCR02[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR2[R/W] B,H,W
00000000 00000000
+3
Block
ESCR2/(IBSR2)[R/W] Multi-UART2
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR02/(TDR02)[R/W] B,H,W
bits.
-------0 00000000*1
STMR2[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR2/SFUR2)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR12)/
― /(SCSTR02)/
reset.
(SFLR12)
(SFLR02)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR12)
― /(SCSFR02)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE12)/
TBYTE02/(LAMRID2) reset.
(LAMIER2)
/(LAMTID2)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK2)[R/W]
― /(ISBA2)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR2[R/W] B,H,W
0-000011
FBYTE2[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
0017C8H
0017CCH
0017D0H
0017D4H
0017D8H
0017DCH
0017E0H
0017E4H
0017E8H
0017ECH
+0
Address offset value / Register name
+1
+2
SCR3/(IBCR3) [R/W]
SMR3[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR13/(TDR13))[R/W] B,H,W
-------- --------*3
SACSR3[R/W] B,H,W
0----000 00000000
STMCR3[R/W] B,H,W
00000000 00000000
― /(SCSTR33)/
― /(SCSTR23)/
(LAMSR3)
(LAMCR3)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR23)
―
[R/W] B,H,W
--------*3
―/(TBYTE33)/
―/(TBYTE23)/
(LAMESR3)
(LAMERT3)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR3[R/W] H, W
00000000 00000000
FCR13[R/W]
FCR03[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR3[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
ESCR3/(IBSR3)[R/W] Multi-UART3
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR03/(TDR03)[R/W] B,H,W
bits.
-------0 00000000*1
STMR3[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR3/SFUR3)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR13)/
― /(SCSTR03)/
reset.
(SFLR13)
(SFLR03)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR13)
― /(SCSFR03)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE13)/
TBYTE03/(LAMRID3) reset.
(LAMIER3)
/(LAMTID3)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK3)[R/W]
― /(ISBA3)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR3[R/W] B,H,W
0-000011
FBYTE3[R/W] B,H,W
00000000 00000000
―
―
99
D a t a S h e e t
Address
0017F0H
0017F4H
0017F8H
0017FCH
001800H
001804H
001808H
00180CH
001810H
001814H
100
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
SCR4/(IBCR4) [R/W]
SMR4[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR14/(TDR14))[R/W] B,H,W
-------- --------*3
SACSR4[R/W] B,H,W
0----000 00000000
STMCR4[R/W] B,H,W
00000000 00000000
― /(SCSTR34)/
― /(SCSTR24)/
(LAMSR4)
(LAMCR4)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR24)
―
[R/W] B,H,W
--------*3
―/(TBYTE34)/
―/(TBYTE24)/
(LAMESR4)
(LAMERT4)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR4[R/W] H, W
00000000 00000000
FCR14[R/W]
FCR04[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR4[R/W] B,H,W
00000000 00000000
+3
Block
ESCR4/(IBSR4)[R/W] Multi-UART4
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR04/(TDR04)[R/W] B,H,W
bits.
-------0 00000000*1
STMR4[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR4/SFUR4)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR14)/
― /(SCSTR04)/
reset.
(SFLR14)
(SFLR04)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR14)
― /(SCSFR04)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE14)/
TBYTE04/(LAMRID4) reset.
(LAMIER4)
/(LAMTID4)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK4)[R/W]
― /(ISBA4)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR4[R/W] B,H,W
0-000011
FBYTE4[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001818H
00181CH
001820H
001824H
001828H
00182CH
001830H
001834H
001838H
00183CH
+0
Address offset value / Register name
+1
+2
SCR5/(IBCR5) [R/W]
SMR5[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR15/(TDR15))[R/W] B,H,W
-------- --------*3
SACSR5[R/W] B,H,W
0----000 00000000
STMCR5[R/W] B,H,W
00000000 00000000
― /(SCSTR35)/
― /(SCSTR25)/
(LAMSR5)
(LAMCR5)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR25)
―
[R/W] B,H,W
--------*3
―/(TBYTE35)/
―/(TBYTE25)/
(LAMESR5)
(LAMERT5)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR5[R/W] H, W
00000000 00000000
FCR15[R/W]
FCR05[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR5[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
ESCR5/(IBSR5)[R/W] Multi-UART5
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR05/(TDR05)[R/W] B,H,W
bits.
-------0 00000000*1
STMR5[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR5/SFUR5)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR15)/
― /(SCSTR05)/
reset.
(SFLR15)
(SFLR05)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR15)
― /(SCSFR05)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE15)/
TBYTE05/(LAMRID5) reset.
(LAMIER5)
/(LAMTID5)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK5)[R/W]
― /(ISBA5)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR5[R/W] B,H,W
0-000011
FBYTE5[R/W] B,H,W
00000000 00000000
―
―
101
D a t a S h e e t
Address
001840H
001844H
001848H
00184CH
001850H
001854H
001858H
00185CH
001860H
001864H
102
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
SCR6/(IBCR6) [R/W]
SMR6[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR16/(TDR16))[R/W] B,H,W
-------- --------*3
SACSR6[R/W] B,H,W
0----000 00000000
STMCR6[R/W] B,H,W
00000000 00000000
― /(SCSTR36)/
― /(SCSTR26)/
(LAMSR6)
(LAMCR6)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR26)
―
[R/W] B,H,W
--------*3
―/(TBYTE36)/
―/(TBYTE26)/
(LAMESR6)
(LAMERT6)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR6[R/W] H, W
00000000 00000000
FCR16[R/W]
FCR06[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR6[R/W] B,H,W
00000000 00000000
+3
Block
ESCR6/(IBSR6)[R/W] Multi-UART6
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR06/(TDR06)[R/W] B,H,W
bits.
-------0 00000000*1
STMR6[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR6/SFUR6)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR16)/
― /(SCSTR06)/
reset.
(SFLR16)
(SFLR06)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR16)
― /(SCSFR06)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE16)/
TBYTE06/(LAMRID6) reset.
(LAMIER6)
/(LAMTID6)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK6)[R/W]
― /(ISBA6)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR6[R/W] B,H,W
0-000011
FBYTE6[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001868H
00186CH
001870H
001874H
001878H
00187CH
001880H
001884H
001888H
00188CH
+0
Address offset value / Register name
+1
+2
SCR7/(IBCR7) [R/W]
SMR7[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR17/(TDR17))[R/W] B,H,W
-------- --------*3
SACSR7[R/W] B,H,W
0----000 00000000
STMCR7[R/W] B,H,W
00000000 00000000
― /(SCSTR37)/
― /(SCSTR27)/
(LAMSR7)
(LAMCR7)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR27)
―
[R/W] B,H,W
--------*3
―/(TBYTE37)/
―/(TBYTE27)/
(LAMESR7)
(LAMERT7)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR7[R/W] H, W
00000000 00000000
FCR17[R/W]
FCR07[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR7[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
ESCR7/(IBSR7)[R/W] Multi-UART7
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR07/(TDR07)[R/W] B,H,W
bits.
-------0 00000000*1
STMR7[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR7/SFUR7)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR17)/
― /(SCSTR07)/
reset.
(SFLR17)
(SFLR07)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR17)
― /(SCSFR07)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE17)/
TBYTE07/(LAMRID7) reset.
(LAMIER7)
/(LAMTID7)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK7)[R/W]
― /(ISBA7)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR7[R/W] B,H,W
0-000011
FBYTE7[R/W] B,H,W
00000000 00000000
―
―
103
D a t a S h e e t
Address
001890H
001894H
001898H
00189CH
0018A0H
0018A4H
0018A8H
0018ACH
0018B0H
0018B4H
104
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
SCR8/(IBCR8) [R/W]
SMR8[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR18/(TDR18))[R/W] B,H,W
-------- --------*3
SACSR8[R/W] B,H,W
0----000 00000000
STMCR8[R/W] B,H,W
00000000 00000000
― /(SCSTR38)/
― /(SCSTR28)/
(LAMSR8)
(LAMCR8)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR28)
―
[R/W] B,H,W
--------*3
―/(TBYTE38)/
―/(TBYTE28)/
(LAMESR8)
(LAMERT8)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR8[R/W] H,W
00000000 00000000
FCR18[R/W]
FCR08[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR8[R/W] B,H,W
00000000 00000000
+3
Block
ESCR8/(IBSR8)[R/W] Multi-UART8
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR08/(TDR08)[R/W] B,H,W
bits.
-------0 00000000*1
STMR8[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR8/SFUR8)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR18)/
― /(SCSTR08)/
reset.
(SFLR18)
(SFLR08)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR18)
― /(SCSFR08)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE18)/
TBYTE08/(LAMRID8) reset.
(LAMIER8)
/(LAMTID8)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK8)[R/W]
― /(ISBA8)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR8[R/W] B,H,W
0-000011
FBYTE8[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
0018B8H
0018BCH
0018C0H
0018C4H
0018C8H
0018CCH
0018D0H
0018D4H
0018D8H
0018DCH
+0
Address offset value / Register name
+1
+2
SCR9/(IBCR9) [R/W]
SMR9[R/W] B,H,W
B,H,W
000-00-0
0--00000
― /(RDR19/(TDR19))[R/W] B,H,W
-------- --------*3
SACSR9[R/W] B,H,W
0----000 00000000
STMCR9[R/W] B,H,W
00000000 00000000
― /(SCSTR39)/
― /(SCSTR29)/
(LAMSR9)
(LAMCR9)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR29)
―
[R/W] B,H,W
--------*3
―/(TBYTE39)/
―/(TBYTE29)/
(LAMESR9)
(LAMERT9)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR9[R/W] H, W
00000000 00000000
FCR19[R/W]
FCR09[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR9[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
ESCR9/(IBSR9)[R/W] Multi-UART9
B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR09/(TDR09)[R/W] B,H,W
bits.
-------0 00000000*1
STMR9[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR9/SFUR9)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
― /(SCSTR19)/
― /(SCSTR09)/
reset.
(SFLR19)
(SFLR09)
[R/W] B,H,W
[R/W] B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR19)
― /(SCSFR09)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE19)/
TBYTE09/(LAMRID9) reset.
(LAMIER9)
/(LAMTID9)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK9)[R/W]
― /(ISBA9)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR9[R/W] B,H,W
0-000011
FBYTE9[R/W] B,H,W
00000000 00000000
―
―
105
D a t a S h e e t
Address
0018E0H
0018E4H
0018E8H
0018ECH
0018F0H
0018F4H
0018F8H
0018FCH
001900H
001904H
106
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
SCR10/(IBCR10)
SMR10[R/W] B,H,W
[R/W] B,H,W
000-00-0
0--00000
― /(RDR110/(TDR110))[R/W] B,H,W
-------- --------*3
SACSR10[R/W] B,H,W
0----000 00000000
STMCR10[R/W] B,H,W
00000000 00000000
― /(SCSTR310)/
― /(SCSTR210)/
(LAMSR10)
(LAMCR10)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR210)
―
[R/W] B,H,W
--------*3
―/(TBYTE310)/
―/(TBYTE210)/
(LAMESR10)
(LAMERT10)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR10[R/W] H, W
00000000 00000000
FCR110[R/W]
FCR010[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR10[R/W] B,H,W
00000000 00000000
+3
Block
ESCR10/(IBSR10) Multi-UART10
[R/W] B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR010/(TDR010)[R/W] B,H,W
bits.
-------0 00000000*1
STMR10[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR10/SFUR10)[R/W] B,H,W
is not set
-------- --------*3 *4
― /(SCSTR110)/
― /(SCSTR010)/ immediately after
(SFLR110)[R/W]
(SFLR010)[R/W] reset.
B,H,W
B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR110)
― /(SCSFR010)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE110)/
TBYTE010/(LAMRID reset.
(LAMIER10)
10)/(LAMTID10)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK10)[R/W]
― /(ISBA10)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR10[R/W] B,H,W
0-000011
FBYTE10[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001908H
00190CH
001910H
001914H
001918H
00191CH
001920H
001924H
001928H
00192CH
+0
Address offset value / Register name
+1
+2
SCR11/(IBCR11)
SMR11[R/W] B,H,W
[R/W] B,H,W
000-00-0
0--00000
― /(RDR111/(TDR111))[R/W] B,H,W
-------- --------*3
SACSR11[R/W] B,H,W
0----000 00000000
STMCR11[R/W] B,H,W
00000000 00000000
― /(SCSTR311)/
― /(SCSTR211)/
(LAMSR11)
(LAMCR11)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
― /(SCSFR211)
―
[R/W] B,H,W
--------*3
―/(TBYTE311)/
―/(TBYTE211)/
(LAMESR11)
(LAMERT11)
[R/W] B,H,W
[R/W] B,H,W
--------*3
--------*3
BGR11[R/W] H, W
00000000 00000000
FCR111[R/W]
FCR011[R/W]
B,H,W
B,H,W
---00100
-0000000
FTICR11[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
ESCR11/(IBSR11) Multi-UART11
[R/W] B,H,W
*1: Byte access is
00000000
possible only for
access to lower 8
RDR011/(TDR011)[R/W] B,H,W
bits.
-------0 00000000*1
STMR11[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR11/SFUR11)[R/W] B,H,W
is not set
-------- --------*3 *4
― /(SCSTR111)/
― /(SCSTR011)/ immediately after
(SFLR111)[R/W]
(SFLR011)[R/W] reset.
B,H,W
B,H,W
*3: Reserved
--------*3
--------*3
because CSIO
― /(SCSFR111)
― /(SCSFR011)
mode is not set
[R/W] B,H,W
[R/W] B,H,W
3
3
immediately after
--------*
--------*
―/(TBYTE111)/
TBYTE011/(LAMRID reset.
(LAMIER11)
11)/(LAMTID11)
*4: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
because LIN2.1
--------*
00000000
― /(ISMK11)[R/W]
― /(ISBA11)[R/W] mode is not set
immediately after
B,H,W
B,H,W
2
2
reset.
--------*
--------*
SSR11[R/W] B,H,W
0-000011
FBYTE11[R/W] B,H,W
00000000 00000000
―
―
107
D a t a S h e e t
Address
001930H
001934H
001938H
00193CH
Address offset value / Register name
+1
+2
+0
SCR12/(IBCR12)
SMR12
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR112/(TDR112))[R/W] B,H,W
-------- --------*3
SACSR12[R/W] B,H,W
0----000 00000000
STMCR12[R/W] B,H,W
00000000 00000000
001940H
― /(SCSTR312)/
(LAMSR12)
[R/W] B,H,W
--------*3
001944H
―
001948H
―/(TBYTE312)/
(LAMESR12)
[R/W] B,H,W
--------*3
00194CH
001950H
001954H
108
CONFIDENTIAL
― /(SCSTR212)/
(LAMCR12)
[R/W] B,H,W
--------*3
― /(SCSFR212)
[R/W] B,H,W
--------*3
―/(TBYTE212)/
(LAMERT12)
[R/W] B,H,W
--------*3
BGR12[R/W] H,W
00000000 00000000
FCR112
FCR012
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR12[R/W] B,H,W
00000000 00000000
+3
Block
SSR12
ESCR12/(IBSR12) Multi-UART12
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR012/(TDR012)[R/W] B,H,W
bits.
-------0 00000000*1
STMR12[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR12/SFUR12)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR112)/(SFLR11 /(SCSTR012)/(SFLR01 reset.
2)
2)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR112)
― /(SCSFR012)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE112)/
TBYTE012/(LAMRID
(LAMIER12)
12)/(LAMTID12) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK12)
― /(ISBA12)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE12[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001958H
00195CH
001960H
001964H
Address offset value / Register name
+1
+2
+0
SCR13/(IBCR13)
SMR13
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR113/(TDR113))[R/W] B,H,W
-------- --------*3
SACSR13[R/W] B,H,W
0----000 00000000
STMCR13[R/W] B,H,W
00000000 00000000
001968H
― /(SCSTR313)/
(LAMSR13)
[R/W] B,H,W
--------*3
00196CH
―
001970H
―/(TBYTE313)/
(LAMESR13)
[R/W] B,H,W
--------*3
001974H
001978H
00197CH
― /(SCSTR213)/
(LAMCR13)
[R/W] B,H,W
--------*3
― /(SCSFR213)
[R/W] B,H,W
--------*3
―/(TBYTE213)/
(LAMERT13)
[R/W] B,H,W
--------*3
BGR13[R/W] H,W
00000000 00000000
FCR113
FCR013
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR13[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
SSR13
ESCR13/(IBSR13) Multi-UART13
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR013/(TDR013)[R/W] B,H,W
bits.
-------0 00000000*1
STMR13[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR13/SFUR13)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR113)/(SFLR11 /(SCSTR013)/(SFLR01 reset.
3)
3)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR113)
― /(SCSFR013)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE113)/
TBYTE013/(LAMRID
(LAMIER13)
13)/(LAMTID13) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK13)
― /(ISBA13)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE13[R/W] B,H,W
00000000 00000000
―
―
109
D a t a S h e e t
Address
001980H
001984H
001988H
00198CH
Address offset value / Register name
+1
+2
+0
SCR14/(IBCR14)
SMR14
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR114/(TDR114))[R/W] B,H,W
-------- --------*3
SACSR14[R/W] B,H,W
0----000 00000000
STMCR14[R/W] B,H,W
00000000 00000000
001990H
― /(SCSTR314)/
(LAMSR14)
[R/W] B,H,W
--------*3
001994H
―
001998H
―/(TBYTE314)/
(LAMESR14)
[R/W] B,H,W
--------*3
00199CH
0019A0H
0019A4H
110
CONFIDENTIAL
― /(SCSTR214)/
(LAMCR14)
[R/W] B,H,W
--------*3
― /(SCSFR214)
[R/W] B,H,W
--------*3
―/(TBYTE214)/
(LAMERT14)
[R/W] B,H,W
--------*3
BGR14[R/W] H,W
00000000 00000000
FCR114
FCR014
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR14[R/W] B,H,W
00000000 00000000
+3
Block
SSR14
ESCR14/(IBSR14) Multi-UART14
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR014/(TDR014)[R/W] B,H,W
bits.
-------0 00000000*1
STMR14[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR14/SFUR14)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR114)/(SFLR11 /(SCSTR014)/(SFLR01 reset.
4)
4)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR114)
― /(SCSFR014)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE114)/
TBYTE014/(LAMRID
(LAMIER14)
14)/(LAMTID14) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK14)
― /(ISBA14)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE14[R/W] B,H,W
00000000 00000000
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
0019A8H
0019ACH
0019B0H
0019B4H
Address offset value / Register name
+1
+2
+0
SCR15/(IBCR15)
SMR15
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-00-0
― /(RDR115/(TDR115))[R/W] B,H,W
-------- --------*3
SACSR15[R/W] B,H,W
0----000 00000000
STMCR15[R/W] B,H,W
00000000 00000000
0019B8H
― /(SCSTR315)/
(LAMSR15)
[R/W] B,H,W
--------*3
0019BCH
―
0019C0H
―/(TBYTE315)/
(LAMESR15)
[R/W] B,H,W
--------*3
0019C4H
0019C8H
0019CCH
― /(SCSTR215)/
(LAMCR15)
[R/W] B,H,W
--------*3
― /(SCSFR215)
[R/W] B,H,W
--------*3
―/(TBYTE215)/
(LAMERT15)
[R/W] B,H,W
--------*3
BGR15[R/W] H,W
00000000 00000000
FCR115
FCR015
[R/W] B,H,W
[R/W] B,H,W
---00100
-0000000
FTICR15[R/W] B,H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
Block
SSR15
ESCR15/(IBSR15) Multi-UART15
[R/W] B,H,W
[R/W] B,H,W
*1: Byte access is
0-000011
00000000
possible only for
access to lower 8
RDR015/(TDR015)[R/W] B,H,W
bits.
-------0 00000000*1
STMR15[R] B,H,W
*2: Reserved
00000000 00000000
because I2C mode
― /(SCSCR15/SFUR15)[R/W] B,H,W
is not set
-------- --------*3 *4
immediately after
―
―
/(SCSTR115)/(SFLR11 /(SCSTR015)/(SFLR01 reset.
5)
5)
*3: Reserved
[R/W] B,H,W
[R/W] B,H,W
3
3
because CSIO
--------*
--------*
mode is not set
― /(SCSFR115)
― /(SCSFR015)
immediately after
[R/W] B,H,W
[R/W] B,H,W
3
3
reset.
--------*
--------*
―/(TBYTE115)/
TBYTE015/(LAMRID
(LAMIER15)
15)/(LAMTID15) *4: Reserved
because LIN2.1
[R/W] B,H,W
[R/W] B,H,W
3
mode is not set
--------*
00000000
immediately after
― /(ISMK15)
― /(ISBA15)
reset.
[R/W] B,H,W
[R/W] B,H,W
2
2
--------*
--------*
FBYTE15[R/W] B,H,W
00000000 00000000
―
―
111
D a t a S h e e t
Address
0019D0H
0019D4H
0019D8H
0019DCH
0019E0H
0019E4H
0019E8H
0019ECH
0019F0H
0019F4H
0019F8H
0019FCH
001A00H
001A04H
001A08H
001A0CH
001A10H
001A14H
001A18H
001A1CH
001A20H
001A24H
001A28H
001A2CH
001A30H
001A34H
112
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
GTRS40 [R/W] B,H,W
-0000000 -0000000
GTRS42 [R/W] B,H,W
-0000000 -0000000
GTREN4 [R/W] H,W
00000000 00000000
GATEC0 [R/W]
―
B,H,W
------00
GATEC4 [R/W]
―
B,H,W
------00
―
―
GTRS0 [R/W] B,H,W
-0000000 -0000000
GTRS2 [R/W] B,H,W
-0000000 -0000000
GTRS4 [R/W] B,H,W
-0000000 -0000000
GTRS6 [R/W] B,H,W
-0000000 -0000000
GTRS8 [R/W] B,H,W
-0000000 -0000000
GTRS10 [R/W] B,H,W
-0000000 -0000000
GTRS12 [R/W] B,H,W
-0000000 -0000000
GTRS14 [R/W] B,H,W
-0000000 -0000000
GTRS16 [R/W] B,H,W
-0000000 -0000000
GTRS18 [R/W] B,H,W
-0000000 -0000000
GTRS20 [R/W] B,H,W
-0000000 -0000000
GTRS22 [R/W] B,H,W
-0000000 -0000000
GTRS24 [R/W] B,H,W
-0000000 -0000000
GTRS26 [R/W] B,H,W
-0000000 -0000000
GTRS28 [R/W] B,H,W
-0000000 -0000000
GTRS30 [R/W] B,H,W
-0000000 -0000000
GTRS32 [R/W] B,H,W
-0000000 -0000000
GTRS34 [R/W] B,H,W
-0000000 -0000000
GTRS36 [R/W] B,H,W
-0000000 -0000000
GTRS38 [R/W] B,H,W
-0000000 -0000000
+3
GTRS41 [R/W] B,H,W
-0000000 -0000000
GTRS43 [R/W] B,H,W
-0000000 -0000000
GTREN5 [R/W] H,W
-------- 00000000
GATEC2 [R/W]
―
B,H,W
------00
―
Block
PPG
controller
PPG GATE control
―
―
―
GTRS1 [R/W] B,H,W
-0000000 -0000000
GTRS3 [R/W] B,H,W
-0000000 -0000000
GTRS5 [R/W] B,H,W
-0000000 -0000000
GTRS7 [R/W] B,H,W
-0000000 -0000000
GTRS9 [R/W] B,H,W
-0000000 -0000000
GTRS11 [R/W] B,H,W
-0000000 -0000000
GTRS13 [R/W] B,H,W
-0000000 -0000000
GTRS15 [R/W] B,H,W
-0000000 -0000000
GTRS17 [R/W] B,H,W
-0000000 -0000000
GTRS19 [R/W] B,H,W
-0000000 -0000000
GTRS21 [R/W] B,H,W
-0000000 -0000000
GTRS23 [R/W] B,H,W
-0000000 -0000000
GTRS25 [R/W] B,H,W
-0000000 -0000000
GTRS27 [R/W] B,H,W
-0000000 -0000000
GTRS29 [R/W] B,H,W
-0000000 -0000000
GTRS31 [R/W] B,H,W
-0000000 -0000000
GTRS33 [R/W] B,H,W
-0000000 -0000000
GTRS35 [R/W] B,H,W
-0000000 -0000000
GTRS37 [R/W] B,H,W
-0000000 -0000000
GTRS39 [R/W] B,H,W
-0000000 -0000000
Reserved
PPG
controller
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001A38H
001A3CH
001A40H
001A44H
001A48H
001A4CH
001A50H
001A54H
001A58H
001A5CH
001A60H
001A64H
001A68H
001A6CH
001A70H
001A74H
001A78H
001A7CH
001A80H
001A84H
001A88H
001A8CH
001A90H
+0
Address offset value / Register name
+1
+2
GTREN0 [R/W] H,W
00000000 00000000
GTREN2 [R/W] H,W
00000000 00000000
PCN0 [R/W] B,H,W
00000000 000000-0
PDUT0 [W] H,W
XXXXXXXX XXXXXXXX
PCN200 [R/W] B,H,W
--000000 -----110
PTPC0 [R/W] H,W
00000000 00000000
PHCSR0 [W] H,W
XXXXXXXX XXXXXXXX
PHDUT0 [W] H,W
XXXXXXXX XXXXXXXX
PCMDDT0 [R/W] H,W
00000000 00000000
PCN1 [R/W] B,H,W
00000000 000000-0
PDUT1 [W] H,W
XXXXXXXX XXXXXXXX
PCN201 [R/W] B,H,W
--000000 -----110
PTPC1 [R/W] H,W
00000000 00000000
PHCSR1 [W] H,W
XXXXXXXX XXXXXXXX
PHDUT1 [W] H,W
XXXXXXXX XXXXXXXX
PCMDDT1 [R/W] H,W
00000000 00000000
PCN2 [R/W] B,H,W
00000000 000000-0
PDUT2 [W] H,W
XXXXXXXX XXXXXXXX
PCN202 [R/W] B,H,W
--000000 -----110
PTPC2 [R/W] H,W
00000000 00000000
PHCSR2 [W] H,W
XXXXXXXX XXXXXXXX
PHDUT2 [W] H,W
XXXXXXXX XXXXXXXX
PCMDDT2 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
GTREN1 [R/W] H,W
00000000 00000000
GTREN3 [R/W] H,W
00000000 00000000
PCSR0 [W] H,W
XXXXXXXX XXXXXXXX
PTMR0 [R] H,W
11111111 11111111
PSDR0 [R/W] H,W
00000000 00000000
PCMDWD0 [R/W] B,H,W
-------- ----0000
PLCSR0 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT0 [W] H,W
XXXXXXXX XXXXXXXX
―
PPG0
(Note) for
communication
PPG1
(Note) for
communication
―
PCSR2 [W] H,W
XXXXXXXX XXXXXXXX
PTMR2 [R] H,W
11111111 11111111
PSDR2 [R/W] H,W
00000000 00000000
PCMDWD2 [R/W] B,H,W
-------- ----0000
PLCSR2 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT2 [W] H,W
XXXXXXXX XXXXXXXX
―
PPG
controller
―
PCSR1 [W] H,W
XXXXXXXX XXXXXXXX
PTMR1 [R] H,W
11111111 11111111
PSDR1 [R/W] H,W
00000000 00000000
PCMDWD1 [R/W] B,H,W
-------- ----0000
PLCSR1 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT1 [W] H,W
XXXXXXXX XXXXXXXX
―
Block
PPG2
(Note) for
communication
―
113
D a t a S h e e t
Address
001A94H
001A98H
001A9CH
001AA0H
001AA4H
001AA8H
001AACH
001AB0H
001AB4H
001AB8H
001ABCH
001AC0H
001AC4H
001AC8H
001ACCH
001AD0H
001AD4H
001AD8H
001ADCH
001AE0H
001AE4H
001AE8H
001AECH
001AF0H
001AF4H
001AF8H
001AFCH
114
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN3 [R/W] B,H,W
00000000 000000-0
PDUT3 [W] H,W
XXXXXXXX XXXXXXXX
PCN203 [R/W] B,H,W
--000000 -----110
PTPC3 [R/W] H,W
00000000 00000000
PHCSR3 [W] H,W
XXXXXXXX XXXXXXXX
PHDUT3 [W] H,W
XXXXXXXX XXXXXXXX
PCMDDT3 [R/W] H,W
00000000 00000000
PCN4 [R/W] B,H,W
00000000 000000-0
PDUT4 [W] H,W
XXXXXXXX XXXXXXXX
PCN204 [R/W] B,H,W
--000000 -----110
PTPC4 [R/W] H,W
00000000 00000000
PCN5 [R/W] B,H,W
00000000 000000-0
PDUT5 [W] H,W
XXXXXXXX XXXXXXXX
PCN205 [R/W] B,H,W
--000000 -----110
PTPC5 [R/W] H,W
00000000 00000000
PCN6 [R/W] B,H,W
00000000 000000-0
PDUT6 [W] H,W
XXXXXXXX XXXXXXXX
PCN206 [R/W] B,H,W
--000000 -----110
PTPC6 [R/W] H,W
00000000 00000000
PCN7 [R/W] B,H,W
00000000 000000-0
PDUT7 [W] H,W
XXXXXXXX XXXXXXXX
PCN207 [R/W] B,H,W
--000000 -----110
PTPC7 [R/W] H,W
00000000 00000000
PCN8 [R/W] B,H,W
00000000 000000-0
PDUT8 [W] H,W
XXXXXXXX XXXXXXXX
PCN208 [R/W] B,H,W
--000000 -----110
PTPC8 [R/W] H,W
00000000 00000000
+3
PCSR3 [W] H,W
XXXXXXXX XXXXXXXX
PTMR3 [R] H,W
11111111 11111111
PSDR3 [R/W] H,W
00000000 00000000
PCMDWD3 [R/W] B,H,W
-------- ----0000
PLCSR3 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT3 [W] H,W
XXXXXXXX XXXXXXXX
―
PPG7
―
PCSR8 [W] H,W
XXXXXXXX XXXXXXXX
PTMR8 [R] H,W
11111111 11111111
PSDR8 [R/W] H,W
00000000 00000000
―
PPG6
―
PCSR7 [W] H,W
XXXXXXXX XXXXXXXX
PTMR7 [R] H,W
11111111 11111111
PSDR7 [R/W] H,W
00000000 00000000
―
PPG5
―
PCSR6 [W] H,W
XXXXXXXX XXXXXXXX
PTMR6 [R] H,W
11111111 11111111
PSDR6 [R/W] H,W
00000000 00000000
―
PPG4
―
PCSR5 [W] H,W
XXXXXXXX XXXXXXXX
PTMR5 [R] H,W
11111111 11111111
PSDR5 [R/W] H,W
00000000 00000000
―
PPG3
(Note) for
communication
―
PCSR4 [W] H,W
XXXXXXXX XXXXXXXX
PTMR4 [R] H,W
11111111 11111111
PSDR4 [R/W] H,W
00000000 00000000
―
Block
PPG8
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001B00H
001B04H
001B08H
001B0CH
001B10H
001B14H
001B18H
001B1CH
001B20H
001B24H
001B28H
001B2CH
001B30H
001B34H
001B38H
001B3CH
001B40H
001B44H
001B48H
001B4CH
001B50H
001B54H
001B58H
001B5CH
+0
Address offset value / Register name
+1
+2
PCN9 [R/W] B,H,W
00000000 000000-0
PDUT9 [W] H,W
XXXXXXXX XXXXXXXX
PCN209 [R/W] B,H,W
--000000 -----110
PTPC9 [R/W] H,W
00000000 00000000
PCN10 [R/W] B,H,W
00000000 000000-0
PDUT10 [W] H,W
XXXXXXXX XXXXXXXX
PCN210 [R/W] B,H,W
--000000 -----110
PTPC10 [R/W] H,W
00000000 00000000
PCN11 [R/W] B,H,W
00000000 000000-0
PDUT11 [W] H,W
XXXXXXXX XXXXXXXX
PCN211 [R/W] B,H,W
--000000 -----110
PTPC11 [R/W] H,W
00000000 00000000
PCN12 [R/W] B,H,W
00000000 000000-0
PDUT12 [W] H,W
XXXXXXXX XXXXXXXX
PCN212 [R/W] B,H,W
--000000 -----110
PTPC12 [R/W] H,W
00000000 00000000
PCN13 [R/W] B,H,W
00000000 000000-0
PDUT13 [W] H,W
XXXXXXXX XXXXXXXX
PCN213 [R/W] B,H,W
--000000 -----110
PTPC13 [R/W] H,W
00000000 00000000
PCN14 [R/W] B,H,W
00000000 000000-0
PDUT14 [W] H,W
XXXXXXXX XXXXXXXX
PCN214 [R/W] B,H,W
--000000 -----110
PTPC14 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
PCSR9 [W] H,W
XXXXXXXX XXXXXXXX
PTMR9 [R] H,W
11111111 11111111
PSDR9 [R/W] H,W
00000000 00000000
―
PPG13
―
PCSR14 [W] H,W
XXXXXXXX XXXXXXXX
PTMR14 [R] H,W
11111111 11111111
PSDR14 [R/W] H,W
00000000 00000000
―
PPG12
―
PCSR13 [W] H,W
XXXXXXXX XXXXXXXX
PTMR13 [R] H,W
11111111 11111111
PSDR13 [R/W] H,W
00000000 00000000
―
PPG11
―
PCSR12 [W] H,W
XXXXXXXX XXXXXXXX
PTMR12 [R] H,W
11111111 11111111
PSDR12 [R/W] H,W
00000000 00000000
―
PPG10
―
PCSR11 [W] H,W
XXXXXXXX XXXXXXXX
PTMR11 [R] H,W
11111111 11111111
PSDR11 [R/W] H,W
00000000 00000000
―
PPG9
―
PCSR10 [W] H,W
XXXXXXXX XXXXXXXX
PTMR10 [R] H,W
11111111 11111111
PSDR10 [R/W] H,W
00000000 00000000
―
Block
PPG14
―
115
D a t a S h e e t
Address
001B60H
001B64H
001B68H
001B6CH
001B70H
001B74H
001B78H
001B7CH
001B80H
001B84H
001B88H
001B8CH
001B90H
001B94H
001B98H
001B9CH
001BA0H
001BA4H
001BA8H
001BACH
001BB0H
001BB4H
001BB8H
001BBCH
116
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN15 [R/W] B,H,W
00000000 000000-0
PDUT15 [W] H,W
XXXXXXXX XXXXXXXX
PCN215 [R/W] B,H,W
--000000 -----110
PTPC15 [R/W] H,W
00000000 00000000
PCN16 [R/W] B,H,W
00000000 000000-0
PDUT16 [W] H,W
XXXXXXXX XXXXXXXX
PCN216 [R/W] B,H,W
--000000 -----110
PTPC16 [R/W] H,W
00000000 00000000
PCN17 [R/W] B,H,W
00000000 000000-0
PDUT17 [W] H,W
XXXXXXXX XXXXXXXX
PCN217 [R/W] B,H,W
--000000 -----110
PTPC17 [R/W] H,W
00000000 00000000
PCN18 [R/W] B,H,W
00000000 000000-0
PDUT18 [W] H,W
XXXXXXXX XXXXXXXX
PCN218 [R/W] B,H,W
--000000 -----110
PTPC18 [R/W] H,W
00000000 00000000
PCN19 [R/W] B,H,W
00000000 000000-0
PDUT19 [W] H,W
XXXXXXXX XXXXXXXX
PCN219 [R/W] B,H,W
--000000 -----110
PTPC19 [R/W] H,W
00000000 00000000
PCN20 [R/W] B,H,W
00000000 000000-0
PDUT20 [W] H,W
XXXXXXXX XXXXXXXX
PCN220 [R/W] B,H,W
--000000 -----110
PTPC20 [R/W] H,W
00000000 00000000
+3
PCSR15 [W] H,W
XXXXXXXX XXXXXXXX
PTMR15 [R] H,W
11111111 11111111
PSDR15 [R/W] H,W
00000000 00000000
―
PPG19
―
PCSR20 [W] H,W
XXXXXXXX XXXXXXXX
PTMR20 [R] H,W
11111111 11111111
PSDR20 [R/W] H,W
00000000 00000000
―
PPG18
―
PCSR19 [W] H,W
XXXXXXXX XXXXXXXX
PTMR19 [R] H,W
11111111 11111111
PSDR19 [R/W] H,W
00000000 00000000
―
PPG17
―
PCSR18 [W] H,W
XXXXXXXX XXXXXXXX
PTMR18 [R] H,W
11111111 11111111
PSDR18 [R/W] H,W
00000000 00000000
―
PPG16
―
PCSR17 [W] H,W
XXXXXXXX XXXXXXXX
PTMR17 [R] H,W
11111111 11111111
PSDR17 [R/W] H,W
00000000 00000000
―
PPG15
―
PCSR16 [W] H,W
XXXXXXXX XXXXXXXX
PTMR16 [R] H,W
11111111 11111111
PSDR16 [R/W] H,W
00000000 00000000
―
Block
PPG20
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001BC0H
001BC4H
001BC8H
001BCCH
001BD0H
001BD4H
001BD8H
001BDCH
001BE0H
001BE4H
001BE8H
001BECH
001BF0H
001BF4H
001BF8H
001BFCH
001C00H
001C04H
001C08H
001C0CH
001C10H
001C14H
001C18H
001C1CH
+0
Address offset value / Register name
+1
+2
PCN21 [R/W] B,H,W
00000000 000000-0
PDUT21 [W] H,W
XXXXXXXX XXXXXXXX
PCN221 [R/W] B,H,W
--000000 -----110
PTPC21 [R/W] H,W
00000000 00000000
PCN22 [R/W] B,H,W
00000000 000000-0
PDUT22 [W] H,W
XXXXXXXX XXXXXXXX
PCN222 [R/W] B,H,W
--000000 -----110
PTPC22 [R/W] H,W
00000000 00000000
PCN23 [R/W] B,H,W
00000000 000000-0
PDUT23 [W] H,W
XXXXXXXX XXXXXXXX
PCN223 [R/W] B,H,W
--000000 -----110
PTPC23 [R/W] H,W
00000000 00000000
PCN24 [R/W] B,H,W
00000000 000000-0
PDUT24 [W] H,W
XXXXXXXX XXXXXXXX
PCN224 [R/W] B,H,W
--000000 -----110
PTPC24 [R/W] H,W
00000000 00000000
PCN25 [R/W] B,H,W
00000000 000000-0
PDUT25 [W] H,W
XXXXXXXX XXXXXXXX
PCN225 [R/W] B,H,W
--000000 -----110
PTPC25 [R/W] H,W
00000000 00000000
PCN26 [R/W] B,H,W
00000000 000000-0
PDUT26 [W] H,W
XXXXXXXX XXXXXXXX
PCN226 [R/W] B,H,W
--000000 -----110
PTPC26 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
PCSR21 [W] H,W
XXXXXXXX XXXXXXXX
PTMR21 [R] H,W
11111111 11111111
PSDR21 [R/W] H,W
00000000 00000000
―
PPG25
―
PCSR26 [W] H,W
XXXXXXXX XXXXXXXX
PTMR26 [R] H,W
11111111 11111111
PSDR26 [R/W] H,W
00000000 00000000
―
PPG24
―
PCSR25 [W] H,W
XXXXXXXX XXXXXXXX
PTMR25 [R] H,W
11111111 11111111
PSDR25 [R/W] H,W
00000000 00000000
―
PPG23
―
PCSR24 [W] H,W
XXXXXXXX XXXXXXXX
PTMR24 [R] H,W
11111111 11111111
PSDR24 [R/W] H,W
00000000 00000000
―
PPG22
―
PCSR23 [W] H,W
XXXXXXXX XXXXXXXX
PTMR23 [R] H,W
11111111 11111111
PSDR23 [R/W] H,W
00000000 00000000
―
PPG21
―
PCSR22 [W] H,W
XXXXXXXX XXXXXXXX
PTMR22 [R] H,W
11111111 11111111
PSDR22 [R/W] H,W
00000000 00000000
―
Block
PPG26
―
117
D a t a S h e e t
Address
001C20H
001C24H
001C28H
001C2CH
001C30H
001C34H
001C38H
001C3CH
001C40H
001C44H
001C48H
001C4CH
001C50H
001C54H
001C58H
001C5CH
001C60H
001C64H
001C68H
001C6CH
001C70H
001C74H
001C78H
001C7CH
118
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN27 [R/W] B,H,W
00000000 000000-0
PDUT27 [W] H,W
XXXXXXXX XXXXXXXX
PCN227 [R/W] B,H,W
--000000 -----110
PTPC27 [R/W] H,W
00000000 00000000
PCN28 [R/W] B,H,W
00000000 000000-0
PDUT28 [W] H,W
XXXXXXXX XXXXXXXX
PCN228 [R/W] B,H,W
--000000 -----110
PTPC28 [R/W] H,W
00000000 00000000
PCN29 [R/W] B,H,W
00000000 000000-0
PDUT29 [W] H,W
XXXXXXXX XXXXXXXX
PCN229 [R/W] B,H,W
--000000 -----110
PTPC29 [R/W] H,W
00000000 00000000
PCN30 [R/W] B,H,W
00000000 000000-0
PDUT30 [W] H,W
XXXXXXXX XXXXXXXX
PCN230 [R/W] B,H,W
--000000 -----110
PTPC30 [R/W] H,W
00000000 00000000
PCN31 [R/W] B,H,W
00000000 000000-0
PDUT31 [W] H,W
XXXXXXXX XXXXXXXX
PCN231 [R/W] B,H,W
--000000 -----110
PTPC31 [R/W] H,W
00000000 00000000
PCN32 [R/W] B,H,W
00000000 000000-0
PDUT32 [W] H,W
XXXXXXXX XXXXXXXX
PCN232 [R/W] B,H,W
--000000 -----110
PTPC32 [R/W] H,W
00000000 00000000
+3
PCSR27 [W] H,W
XXXXXXXX XXXXXXXX
PTMR27 [R] H,W
11111111 11111111
PSDR27 [R/W] H,W
00000000 00000000
―
PPG31
―
PCSR32 [W] H,W
XXXXXXXX XXXXXXXX
PTMR32 [R] H,W
11111111 11111111
PSDR32 [R/W] H,W
00000000 00000000
―
PPG30
―
PCSR31 [W] H,W
XXXXXXXX XXXXXXXX
PTMR31 [R] H,W
11111111 11111111
PSDR31 [R/W] H,W
00000000 00000000
―
PPG29
―
PCSR30 [W] H,W
XXXXXXXX XXXXXXXX
PTMR30 [R] H,W
11111111 11111111
PSDR30 [R/W] H,W
00000000 00000000
―
PPG28
―
PCSR29 [W] H,W
XXXXXXXX XXXXXXXX
PTMR29 [R] H,W
11111111 11111111
PSDR29 [R/W] H,W
00000000 00000000
―
PPG27
―
PCSR28 [W] H,W
XXXXXXXX XXXXXXXX
PTMR28 [R] H,W
11111111 11111111
PSDR28 [R/W] H,W
00000000 00000000
―
Block
PPG32
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001C80H
001C84H
001C88H
001C8CH
001C90H
001C94H
001C98H
001C9CH
001CA0H
001CA4H
001CA8H
001CACH
001CB0H
001CB4H
001CB8H
001CBCH
001CC0H
001CC4H
001CC8H
001CCCH
001CD0H
001CD4H
001CD8H
001CDCH
+0
Address offset value / Register name
+1
+2
PCN33 [R/W] B,H,W
00000000 000000-0
PDUT33 [W] H,W
XXXXXXXX XXXXXXXX
PCN233 [R/W] B,H,W
--000000 -----110
PTPC33 [R/W] H,W
00000000 00000000
PCN34 [R/W] B,H,W
00000000 000000-0
PDUT34 [W] H,W
XXXXXXXX XXXXXXXX
PCN234 [R/W] B,H,W
--000000 -----110
PTPC34 [R/W] H,W
00000000 00000000
PCN35 [R/W] B,H,W
00000000 000000-0
PDUT35 [W] H,W
XXXXXXXX XXXXXXXX
PCN235 [R/W] B,H,W
--000000 -----110
PTPC35 [R/W] H,W
00000000 00000000
PCN36 [R/W] B,H,W
00000000 000000-0
PDUT36 [W] H,W
XXXXXXXX XXXXXXXX
PCN236 [R/W] B,H,W
--000000 -----110
PTPC36 [R/W] H,W
00000000 00000000
PCN37 [R/W] B,H,W
00000000 000000-0
PDUT37 [W] H,W
XXXXXXXX XXXXXXXX
PCN237 [R/W] B,H,W
--000000 -----110
PTPC37 [R/W] H,W
00000000 00000000
PCN38 [R/W] B,H,W
00000000 000000-0
PDUT38 [W] H,W
XXXXXXXX XXXXXXXX
PCN238 [R/W] B,H,W
--000000 -----110
PTPC38 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
PCSR33 [W] H,W
XXXXXXXX XXXXXXXX
PTMR33 [R] H,W
11111111 11111111
PSDR33 [R/W] H,W
00000000 00000000
―
PPG37
―
PCSR38 [W] H,W
XXXXXXXX XXXXXXXX
PTMR38 [R] H,W
11111111 11111111
PSDR38 [R/W] H,W
00000000 00000000
―
PPG36
―
PCSR37 [W] H,W
XXXXXXXX XXXXXXXX
PTMR37 [R] H,W
11111111 11111111
PSDR37 [R/W] H,W
00000000 00000000
―
PPG35
―
PCSR36 [W] H,W
XXXXXXXX XXXXXXXX
PTMR36 [R] H,W
11111111 11111111
PSDR36 [R/W] H,W
00000000 00000000
―
PPG34
―
PCSR35 [W] H,W
XXXXXXXX XXXXXXXX
PTMR35 [R] H,W
11111111 11111111
PSDR35 [R/W] H,W
00000000 00000000
―
PPG33
―
PCSR34 [W] H,W
XXXXXXXX XXXXXXXX
PTMR34 [R] H,W
11111111 11111111
PSDR34 [R/W] H,W
00000000 00000000
―
Block
PPG38
―
119
D a t a S h e e t
Address
001CE0H
001CE4H
001CE8H
001CECH
001CF0H
001CF4H
001CF8H
001CFCH
001D00H
001D04H
001D08H
001D0CH
001D10H
001D14H
001D18H
001D1CH
001D20H
001D24H
001D28H
001D2CH
001D30H
001D34H
001D38H
001D3CH
120
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN39 [R/W] B,H,W
00000000 000000-0
PDUT39 [W] H,W
XXXXXXXX XXXXXXXX
PCN239 [R/W] B,H,W
--000000 -----110
PTPC39 [R/W] H,W
00000000 00000000
PCN40 [R/W] B,H,W
00000000 000000-0
PDUT40 [W] H,W
XXXXXXXX XXXXXXXX
PCN240 [R/W] B,H,W
--000000 -----110
PTPC40 [R/W] H,W
00000000 00000000
PCN41 [R/W] B,H,W
00000000 000000-0
PDUT41 [W] H,W
XXXXXXXX XXXXXXXX
PCN241 [R/W] B,H,W
--000000 -----110
PTPC41 [R/W] H,W
00000000 00000000
PCN42 [R/W] B,H,W
00000000 000000-0
PDUT42 [W] H,W
XXXXXXXX XXXXXXXX
PCN242 [R/W] B,H,W
--000000 -----110
PTPC42 [R/W] H,W
00000000 00000000
PCN43 [R/W] B,H,W
00000000 000000-0
PDUT43 [W] H,W
XXXXXXXX XXXXXXXX
PCN243 [R/W] B,H,W
--000000 -----110
PTPC43 [R/W] H,W
00000000 00000000
PCN44 [R/W] B,H,W
00000000 000000-0
PDUT44 [W] H,W
XXXXXXXX XXXXXXXX
PCN244 [R/W] B,H,W
--000000 -----110
PTPC44 [R/W] H,W
00000000 00000000
+3
PCSR39 [W] H,W
XXXXXXXX XXXXXXXX
PTMR39 [R] H,W
11111111 11111111
PSDR39 [R/W] H,W
00000000 00000000
―
PPG43
―
PCSR44 [W] H,W
XXXXXXXX XXXXXXXX
PTMR44 [R] H,W
11111111 11111111
PSDR44 [R/W] H,W
00000000 00000000
―
PPG42
―
PCSR43 [W] H,W
XXXXXXXX XXXXXXXX
PTMR43 [R] H,W
11111111 11111111
PSDR43 [R/W] H,W
00000000 00000000
―
PPG41
―
PCSR42 [W] H,W
XXXXXXXX XXXXXXXX
PTMR42 [R] H,W
11111111 11111111
PSDR42 [R/W] H,W
00000000 00000000
―
PPG40
―
PCSR41 [W] H,W
XXXXXXXX XXXXXXXX
PTMR41 [R] H,W
11111111 11111111
PSDR41 [R/W] H,W
00000000 00000000
―
PPG39
―
PCSR40 [W] H,W
XXXXXXXX XXXXXXXX
PTMR40 [R] H,W
11111111 11111111
PSDR40 [R/W] H,W
00000000 00000000
―
Block
PPG44
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001D40H
001D44H
001D48H
001D4CH
001D50H
001D54H
001D58H
001D5CH
001D60H
001D64H
001D68H
001D6CH
001D70H
001D74H
001D78H
001D7CH
001D80H
001D84H
001D88H
001D8CH
001D90H
001D94H
001D98H
001D9CH
+0
Address offset value / Register name
+1
+2
PCN45 [R/W] B,H,W
00000000 000000-0
PDUT45 [W] H,W
XXXXXXXX XXXXXXXX
PCN245 [R/W] B,H,W
--000000 -----110
PTPC45 [R/W] H,W
00000000 00000000
PCN46 [R/W] B,H,W
00000000 000000-0
PDUT46 [W] H,W
XXXXXXXX XXXXXXXX
PCN246 [R/W] B,H,W
--000000 -----110
PTPC46 [R/W] H,W
00000000 00000000
PCN47 [R/W] B,H,W
00000000 000000-0
PDUT47 [W] H,W
XXXXXXXX XXXXXXXX
PCN247 [R/W] B,H,W
--000000 -----110
PTPC47 [R/W] H,W
00000000 00000000
PCN48 [R/W] B,H,W
00000000 000000-0
PDUT48 [W] H,W
XXXXXXXX XXXXXXXX
PCN248 [R/W] B,H,W
--000000 -----110
PTPC48 [R/W] H,W
00000000 00000000
PCN49 [R/W] B,H,W
00000000 000000-0
PDUT49 [W] H,W
XXXXXXXX XXXXXXXX
PCN249 [R/W] B,H,W
--000000 -----110
PTPC49 [R/W] H,W
00000000 00000000
PCN50 [R/W] B,H,W
00000000 000000-0
PDUT50 [W] H,W
XXXXXXXX XXXXXXXX
PCN250 [R/W] B,H,W
--000000 -----110
PTPC50 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
PCSR45 [W] H,W
XXXXXXXX XXXXXXXX
PTMR45 [R] H,W
11111111 11111111
PSDR45 [R/W] H,W
00000000 00000000
―
PPG49
―
PCSR50 [W] H,W
XXXXXXXX XXXXXXXX
PTMR50 [R] H,W
11111111 11111111
PSDR50 [R/W] H,W
00000000 00000000
―
PPG48
―
PCSR49 [W] H,W
XXXXXXXX XXXXXXXX
PTMR49 [R] H,W
11111111 11111111
PSDR49 [R/W] H,W
00000000 00000000
―
PPG47
―
PCSR48 [W] H,W
XXXXXXXX XXXXXXXX
PTMR48 [R] H,W
11111111 11111111
PSDR48 [R/W] H,W
00000000 00000000
―
PPG46
―
PCSR47 [W] H,W
XXXXXXXX XXXXXXXX
PTMR47 [R] H,W
11111111 11111111
PSDR47 [R/W] H,W
00000000 00000000
―
PPG45
―
PCSR46 [W] H,W
XXXXXXXX XXXXXXXX
PTMR46 [R] H,W
11111111 11111111
PSDR46 [R/W] H,W
00000000 00000000
―
Block
PPG50
―
121
D a t a S h e e t
Address
001DA0H
001DA4H
001DA8H
001DACH
001DB0H
001DB4H
001DB8H
001DBCH
001DC0H
001DC4H
001DC8H
001DCCH
001DD0H
001DD4H
001DD8H
001DDCH
001DE0H
001DE4H
001DE8H
001DECH
001DF0H
001DF4H
001DF8H
001DFCH
122
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN51 [R/W] B,H,W
00000000 000000-0
PDUT51 [W] H,W
XXXXXXXX XXXXXXXX
PCN251 [R/W] B,H,W
--000000 -----110
PTPC51 [R/W] H,W
00000000 00000000
PCN52 [R/W] B,H,W
00000000 000000-0
PDUT52 [W] H,W
XXXXXXXX XXXXXXXX
PCN252 [R/W] B,H,W
--000000 -----110
PTPC52 [R/W] H,W
00000000 00000000
PCN53 [R/W] B,H,W
00000000 000000-0
PDUT53 [W] H,W
XXXXXXXX XXXXXXXX
PCN253 [R/W] B,H,W
--000000 -----110
PTPC53 [R/W] H,W
00000000 00000000
PCN54 [R/W] B,H,W
00000000 000000-0
PDUT54 [W] H,W
XXXXXXXX XXXXXXXX
PCN254 [R/W] B,H,W
--000000 -----110
PTPC54 [R/W] H,W
00000000 00000000
PCN55 [R/W] B,H,W
00000000 000000-0
PDUT55 [W] H,W
XXXXXXXX XXXXXXXX
PCN255 [R/W] B,H,W
--000000 -----110
PTPC55 [R/W] H,W
00000000 00000000
PCN56 [R/W] B,H,W
00000000 000000-0
PDUT56 [W] H,W
XXXXXXXX XXXXXXXX
PCN256 [R/W] B,H,W
--000000 -----110
PTPC56 [R/W] H,W
00000000 00000000
+3
PCSR51 [W] H,W
XXXXXXXX XXXXXXXX
PTMR51 [R] H,W
11111111 11111111
PSDR51 [R/W] H,W
00000000 00000000
―
PPG55
―
PCSR56 [W] H,W
XXXXXXXX XXXXXXXX
PTMR56 [R] H,W
11111111 11111111
PSDR56 [R/W] H,W
00000000 00000000
―
PPG54
―
PCSR55 [W] H,W
XXXXXXXX XXXXXXXX
PTMR55 [R] H,W
11111111 11111111
PSDR55 [R/W] H,W
00000000 00000000
―
PPG53
―
PCSR54 [W] H,W
XXXXXXXX XXXXXXXX
PTMR54 [R] H,W
11111111 11111111
PSDR54 [R/W] H,W
00000000 00000000
―
PPG52
―
PCSR53 [W] H,W
XXXXXXXX XXXXXXXX
PTMR53 [R] H,W
11111111 11111111
PSDR53 [R/W] H,W
00000000 00000000
―
PPG51
―
PCSR52 [W] H,W
XXXXXXXX XXXXXXXX
PTMR52 [R] H,W
11111111 11111111
PSDR52 [R/W] H,W
00000000 00000000
―
Block
PPG56
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001E00H
001E04H
001E08H
001E0CH
001E10H
001E14H
001E18H
001E1CH
001E20H
001E24H
001E28H
001E2CH
001E30H
001E34H
001E38H
001E3CH
001E40H
001E44H
001E48H
001E4CH
001E50H
001E54H
001E58H
001E5CH
+0
Address offset value / Register name
+1
+2
PCN57 [R/W] B,H,W
00000000 000000-0
PDUT57 [W] H,W
XXXXXXXX XXXXXXXX
PCN257 [R/W] B,H,W
--000000 -----110
PTPC57 [R/W] H,W
00000000 00000000
PCN58 [R/W] B,H,W
00000000 000000-0
PDUT58 [W] H,W
XXXXXXXX XXXXXXXX
PCN258 [R/W] B,H,W
--000000 -----110
PTPC58 [R/W] H,W
00000000 00000000
PCN59 [R/W] B,H,W
00000000 000000-0
PDUT59 [W] H,W
XXXXXXXX XXXXXXXX
PCN259 [R/W] B,H,W
--000000 -----110
PTPC59 [R/W] H,W
00000000 00000000
PCN60 [R/W] B,H,W
00000000 000000-0
PDUT60 [W] H,W
XXXXXXXX XXXXXXXX
PCN260 [R/W] B,H,W
--000000 -----110
PTPC60 [R/W] H,W
00000000 00000000
PCN61 [R/W] B,H,W
00000000 000000-0
PDUT61 [W] H,W
XXXXXXXX XXXXXXXX
PCN261 [R/W] B,H,W
--000000 -----110
PTPC61 [R/W] H,W
00000000 00000000
PCN62 [R/W] B,H,W
00000000 000000-0
PDUT62 [W] H,W
XXXXXXXX XXXXXXXX
PCN262 [R/W] B,H,W
--000000 -----110
PTPC62 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
PCSR57 [W] H,W
XXXXXXXX XXXXXXXX
PTMR57 [R] H,W
11111111 11111111
PSDR57 [R/W] H,W
00000000 00000000
―
PPG61
―
PCSR62 [W] H,W
XXXXXXXX XXXXXXXX
PTMR62 [R] H,W
11111111 11111111
PSDR62 [R/W] H,W
00000000 00000000
―
PPG60
―
PCSR61 [W] H,W
XXXXXXXX XXXXXXXX
PTMR61 [R] H,W
11111111 11111111
PSDR61 [R/W] H,W
00000000 00000000
―
PPG59
―
PCSR60 [W] H,W
XXXXXXXX XXXXXXXX
PTMR60 [R] H,W
11111111 11111111
PSDR60 [R/W] H,W
00000000 00000000
―
PPG58
―
PCSR59 [W] H,W
XXXXXXXX XXXXXXXX
PTMR59 [R] H,W
11111111 11111111
PSDR59 [R/W] H,W
00000000 00000000
―
PPG57
―
PCSR58 [W] H,W
XXXXXXXX XXXXXXXX
PTMR58 [R] H,W
11111111 11111111
PSDR58 [R/W] H,W
00000000 00000000
―
Block
PPG62
―
123
D a t a S h e e t
Address
001E60H
001E64H
001E68H
001E6CH
001E70H
001E74H
001E78H
001E7CH
001E80H
001E84H
001E88H
001E8CH
001E90H
001E94H
001E98H
001E9CH
001EA0H
001EA4H
001EA8H
001EACH
001EB0H
001EB4H
001EB8H
001EBCH
124
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN63 [R/W] B,H,W
00000000 000000-0
PDUT63 [W] H,W
XXXXXXXX XXXXXXXX
PCN263 [R/W] B,H,W
--000000 -----110
PTPC63 [R/W] H,W
00000000 00000000
PCN64 [R/W] B,H,W
00000000 000000-0
PDUT64 [W] H,W
XXXXXXXX XXXXXXXX
PCN264 [R/W] B,H,W
--000000 -----110
PTPC64 [R/W] H,W
00000000 00000000
PCN65 [R/W] B,H,W
00000000 000000-0
PDUT65 [W] H,W
XXXXXXXX XXXXXXXX
PCN265 [R/W] B,H,W
--000000 -----110
PTPC65 [R/W] H,W
00000000 00000000
PCN66 [R/W] B,H,W
00000000 000000-0
PDUT66 [W] H,W
XXXXXXXX XXXXXXXX
PCN266 [R/W] B,H,W
--000000 -----110
PTPC66 [R/W] H,W
00000000 00000000
PCN67 [R/W] B,H,W
00000000 000000-0
PDUT67 [W] H,W
XXXXXXXX XXXXXXXX
PCN267 [R/W] B,H,W
--000000 -----110
PTPC67 [R/W] H,W
00000000 00000000
PCN68 [R/W] B,H,W
00000000 000000-0
PDUT68 [W] H,W
XXXXXXXX XXXXXXXX
PCN268 [R/W] B,H,W
--000000 -----110
PTPC68 [R/W] H,W
00000000 00000000
+3
PCSR63 [W] H,W
XXXXXXXX XXXXXXXX
PTMR63 [R] H,W
11111111 11111111
PSDR63 [R/W] H,W
00000000 00000000
―
PPG67
―
PCSR68 [W] H,W
XXXXXXXX XXXXXXXX
PTMR68 [R] H,W
11111111 11111111
PSDR68 [R/W] H,W
00000000 00000000
―
PPG66
―
PCSR67 [W] H,W
XXXXXXXX XXXXXXXX
PTMR67 [R] H,W
11111111 11111111
PSDR67 [R/W] H,W
00000000 00000000
―
PPG65
―
PCSR66 [W] H,W
XXXXXXXX XXXXXXXX
PTMR66 [R] H,W
11111111 11111111
PSDR66 [R/W] H,W
00000000 00000000
―
PPG64
―
PCSR65 [W] H,W
XXXXXXXX XXXXXXXX
PTMR65 [R] H,W
11111111 11111111
PSDR65 [R/W] H,W
00000000 00000000
―
PPG63
―
PCSR64 [W] H,W
XXXXXXXX XXXXXXXX
PTMR64 [R] H,W
11111111 11111111
PSDR64 [R/W] H,W
00000000 00000000
―
Block
PPG68
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001EC0H
001EC4H
001EC8H
001ECCH
001ED0H
001ED4H
001ED8H
001EDCH
001EE0H
001EE4H
001EE8H
001EECH
001EF0H
001EF4H
001EF8H
001EFCH
001F00H
001F04H
001F08H
001F0CH
001F10H
001F14H
001F18H
001F1CH
+0
Address offset value / Register name
+1
+2
PCN69 [R/W] B,H,W
00000000 000000-0
PDUT69 [W] H,W
XXXXXXXX XXXXXXXX
PCN269 [R/W] B,H,W
--000000 -----110
PTPC69 [R/W] H,W
00000000 00000000
PCN70 [R/W] B,H,W
00000000 000000-0
PDUT70 [W] H,W
XXXXXXXX XXXXXXXX
PCN270 [R/W] B,H,W
--000000 -----110
PTPC70 [R/W] H,W
00000000 00000000
PCN71 [R/W] B,H,W
00000000 000000-0
PDUT71 [W] H,W
XXXXXXXX XXXXXXXX
PCN271 [R/W] B,H,W
--000000 -----110
PTPC71 [R/W] H,W
00000000 00000000
PCN72 [R/W] B,H,W
00000000 000000-0
PDUT72 [W] H,W
XXXXXXXX XXXXXXXX
PCN272 [R/W] B,H,W
--000000 -----110
PTPC72 [R/W] H,W
00000000 00000000
PCN73 [R/W] B,H,W
00000000 000000-0
PDUT73 [W] H,W
XXXXXXXX XXXXXXXX
PCN273 [R/W] B,H,W
--000000 -----110
PTPC73 [R/W] H,W
00000000 00000000
PCN74 [R/W] B,H,W
00000000 000000-0
PDUT74 [W] H,W
XXXXXXXX XXXXXXXX
PCN274 [R/W] B,H,W
--000000 -----110
PTPC74 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
PCSR69 [W] H,W
XXXXXXXX XXXXXXXX
PTMR69 [R] H,W
11111111 11111111
PSDR69 [R/W] H,W
00000000 00000000
―
PPG73
―
PCSR74 [W] H,W
XXXXXXXX XXXXXXXX
PTMR74 [R] H,W
11111111 11111111
PSDR74 [R/W] H,W
00000000 00000000
―
PPG72
―
PCSR73 [W] H,W
XXXXXXXX XXXXXXXX
PTMR73 [R] H,W
11111111 11111111
PSDR73 [R/W] H,W
00000000 00000000
―
PPG71
―
PCSR72 [W] H,W
XXXXXXXX XXXXXXXX
PTMR72 [R] H,W
11111111 11111111
PSDR72 [R/W] H,W
00000000 00000000
―
PPG70
―
PCSR71 [W] H,W
XXXXXXXX XXXXXXXX
PTMR71 [R] H,W
11111111 11111111
PSDR71 [R/W] H,W
00000000 00000000
―
PPG69
―
PCSR70 [W] H,W
XXXXXXXX XXXXXXXX
PTMR70 [R] H,W
11111111 11111111
PSDR70 [R/W] H,W
00000000 00000000
―
Block
PPG74
―
125
D a t a S h e e t
Address
001F20H
001F24H
001F28H
001F2CH
001F30H
001F34H
001F38H
001F3CH
001F40H
001F44H
001F48H
001F4CH
001F50H
001F54H
001F58H
001F5CH
001F60H
001F64H
001F68H
001F6CH
001F70H
001F74H
001F78H
001F7CH
126
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN75 [R/W] B,H,W
00000000 000000-0
PDUT75 [W] H,W
XXXXXXXX XXXXXXXX
PCN275 [R/W] B,H,W
--000000 -----110
PTPC75 [R/W] H,W
00000000 00000000
PCN76 [R/W] B,H,W
00000000 000000-0
PDUT76 [W] H,W
XXXXXXXX XXXXXXXX
PCN276 [R/W] B,H,W
--000000 -----110
PTPC76 [R/W] H,W
00000000 00000000
PCN77 [R/W] B,H,W
00000000 000000-0
PDUT77 [W] H,W
XXXXXXXX XXXXXXXX
PCN277 [R/W] B,H,W
--000000 -----110
PTPC77 [R/W] H,W
00000000 00000000
PCN78 [R/W] B,H,W
00000000 000000-0
PDUT78 [W] H,W
XXXXXXXX XXXXXXXX
PCN278 [R/W] B,H,W
--000000 -----110
PTPC78 [R/W] H,W
00000000 00000000
PCN79 [R/W] B,H,W
00000000 000000-0
PDUT79 [W] H,W
XXXXXXXX XXXXXXXX
PCN279 [R/W] B,H,W
--000000 -----110
PTPC79 [R/W] H,W
00000000 00000000
PCN80 [R/W] B,H,W
00000000 000000-0
PDUT80 [W] H,W
XXXXXXXX XXXXXXXX
PCN280 [R/W] B,H,W
--000000 -----110
PTPC80 [R/W] H,W
00000000 00000000
+3
PCSR75 [W] H,W
XXXXXXXX XXXXXXXX
PTMR75 [R] H,W
11111111 11111111
PSDR75 [R/W] H,W
00000000 00000000
―
PPG79
―
PCSR80 [W] H,W
XXXXXXXX XXXXXXXX
PTMR80 [R] H,W
11111111 11111111
PSDR80 [R/W] H,W
00000000 00000000
―
PPG78
―
PCSR79 [W] H,W
XXXXXXXX XXXXXXXX
PTMR79 [R] H,W
11111111 11111111
PSDR79 [R/W] H,W
00000000 00000000
―
PPG77
―
PCSR78 [W] H,W
XXXXXXXX XXXXXXXX
PTMR78 [R] H,W
11111111 11111111
PSDR78 [R/W] H,W
00000000 00000000
―
PPG76
―
PCSR77 [W] H,W
XXXXXXXX XXXXXXXX
PTMR77 [R] H,W
11111111 11111111
PSDR77 [R/W] H,W
00000000 00000000
―
PPG75
―
PCSR76 [W] H,W
XXXXXXXX XXXXXXXX
PTMR76 [R] H,W
11111111 11111111
PSDR76 [R/W] H,W
00000000 00000000
―
Block
PPG80
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
001F80H
001F84H
001F88H
001F8CH
001F90H
001F94H
001F98H
001F9CH
001FA0H
001FA4H
001FA8H
001FACH
001FB0H
001FB4H
001FB8H
001FBCH
001FC0H
001FC4H
001FC8H
001FCCH
001FD0H
001FD4H
001FD8H
001FDCH
+0
Address offset value / Register name
+1
+2
PCN81 [R/W] B,H,W
00000000 000000-0
PDUT81 [W] H,W
XXXXXXXX XXXXXXXX
PCN281 [R/W] B,H,W
--000000 -----110
PTPC81 [R/W] H,W
00000000 00000000
PCN82 [R/W] B,H,W
00000000 000000-0
PDUT82 [W] H,W
XXXXXXXX XXXXXXXX
PCN282 [R/W] B,H,W
--000000 -----110
PTPC82 [R/W] H,W
00000000 00000000
PCN83 [R/W] B,H,W
00000000 000000-0
PDUT83 [W] H,W
XXXXXXXX XXXXXXXX
PCN283 [R/W] B,H,W
--000000 -----110
PTPC83 [R/W] H,W
00000000 00000000
PCN84 [R/W] B,H,W
00000000 000000-0
PDUT84 [W] H,W
XXXXXXXX XXXXXXXX
PCN284 [R/W] B,H,W
--000000 -----110
PTPC84 [R/W] H,W
00000000 00000000
PCN85 [R/W] B,H,W
00000000 000000-0
PDUT85 [W] H,W
XXXXXXXX XXXXXXXX
PCN285 [R/W] B,H,W
--000000 -----110
PTPC85 [R/W] H,W
00000000 00000000
PCN86 [R/W] B,H,W
00000000 000000-0
PDUT86 [W] H,W
XXXXXXXX XXXXXXXX
PCN286 [R/W] B,H,W
--000000 -----110
PTPC86 [R/W] H,W
00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
PCSR81 [W] H,W
XXXXXXXX XXXXXXXX
PTMR81 [R] H,W
11111111 11111111
PSDR81 [R/W] H,W
00000000 00000000
―
PPG85
―
PCSR86 [W] H,W
XXXXXXXX XXXXXXXX
PTMR86 [R] H,W
11111111 11111111
PSDR86 [R/W] H,W
00000000 00000000
―
PPG84
―
PCSR85 [W] H,W
XXXXXXXX XXXXXXXX
PTMR85 [R] H,W
11111111 11111111
PSDR85 [R/W] H,W
00000000 00000000
―
PPG83
―
PCSR84 [W] H,W
XXXXXXXX XXXXXXXX
PTMR84 [R] H,W
11111111 11111111
PSDR84 [R/W] H,W
00000000 00000000
―
PPG82
―
PCSR83 [W] H,W
XXXXXXXX XXXXXXXX
PTMR83 [R] H,W
11111111 11111111
PSDR83 [R/W] H,W
00000000 00000000
―
PPG81
―
PCSR82 [W] H,W
XXXXXXXX XXXXXXXX
PTMR82 [R] H,W
11111111 11111111
PSDR82 [R/W] H,W
00000000 00000000
―
Block
PPG86
―
127
D a t a S h e e t
Address
001FE0H
001FE4H
001FE8H
001FECH
001FF0H
to
001FFCH
128
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
PCN87 [R/W] B,H,W
00000000 000000-0
PDUT87 [W] H,W
XXXXXXXX XXXXXXXX
PCN287 [R/W] B,H,W
--000000 -----110
PTPC87 [R/W] H,W
00000000 00000000
―
―
+3
PCSR87 [W] H,W
XXXXXXXX XXXXXXXX
PTMR87 [R] H,W
11111111 11111111
PSDR87 [R/W] H,W
00000000 00000000
―
―
―
―
Block
PPG87
Reserved
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
002000H
002004H
002008H
00200CH
002010H
002014H
002018H
00201CH
002020H
002024H
002028H
00202CH
002030H,
002034H
002038H
00203CH
002040H
002044H
002048H
00204CH
002050H
002054H
002058H
00205CH
002060H,
002064H
002068H
to
00207CH
+0
Address offset value / Register name
+1
+2
CTRLR0 [R/W] B,H,W
-------- 000-0001
ERRCNT0 [R] B,H,W
00000000 00000000
INTR0 [R] B,H,W
00000000 00000000
BRPER0 [R/W] B,H,W
-------- ----0000
IF1CREQ0 [R/W] B,H,W
0------- 00000001
IF1MSK20 [R/W] B,H,W
11-11111 11111111
IF1ARB20 [R/W] B,H,W
00000000 00000000
IF1MCTR0 [R/W] B,H,W
00000000 0---0000
IF1DTA10 [R/W] B,H,W
00000000 00000000
IF1DTB10 [R/W] B,H,W
00000000 00000000
―
―
―
―
Block
STATR0 [R/W] B,H,W
-------- 00000000
BTR0 [R/W] B,H,W
-0100011 00000001
TESTR0 [R/W] B,H,W
-------- X00000-―
―
IF1CMSK0 [R/W] B,H,W
-------- 00000000
IF1MSK10 [R/W] B,H,W
11111111 11111111
IF1ARB10 [R/W] B,H,W
00000000 00000000
―
―
IF1DTA20 [R/W] B,H,W
00000000 00000000
IF1DTB20 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ0 [R/W] B,H,W
0------- 00000001
IF2MSK20 [R/W] B,H,W
11-11111 11111111
IF2ARB20 [R/W] B,H,W
00000000 00000000
IF2MCTR0 [R/W] B,H,W
00000000 0---0000
IF2DTA10 [R/W] B,H,W
00000000 00000000
IF2DTB10 [R/W] B,H,W
00000000 00000000
―
―
―
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
CAN0
(128msb)
―
―
―
―
IF2CMSK0 [R/W] B,H,W
-------- 00000000
IF2MSK10 [R/W] B,H,W
11111111 11111111
IF2ARB10 [R/W] B,H,W
00000000 00000000
―
―
IF2DTA20 [R/W] B,H,W
00000000 00000000
IF2DTB20 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF2 data mirror)
―
129
D a t a S h e e t
Address
002080H
002084H
002088H
00208CH
002090H
002094H
002098H
00209CH
0020A0H
0020A4H
0020A8H
0020ACH
0020B0H
0020B4H
0020B8H
0020BCH
0020C0H
to
0020FCH
130
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
TREQR20 [R] B,H,W
00000000 00000000
TREQR40 [R] B,H,W
00000000 00000000
TREQR60 [R] B,H,W
00000000 00000000
TREQR80 [R] B,H,W
00000000 00000000
NEWDT20 [R] B,H,W
00000000 00000000
NEWDT40 [R] B,H,W
00000000 00000000
NEWDT60 [R] B,H,W
00000000 00000000
NEWDT80 [R] B,H,W
00000000 00000000
INTPND20 [R] B,H,W
00000000 00000000
INTPND40 [R] B,H,W
00000000 00000000
INTPND60 [R] B,H,W
00000000 00000000
INTPND80 [R] B,H,W
00000000 00000000
MSGVAL20 [R] B,H,W
00000000 00000000
MSGVAL40 [R] B,H,W
00000000 00000000
MSGVAL60 [R] B,H,W
00000000 00000000
MSGVAL80 [R] B,H,W
00000000 00000000
+3
TREQR10 [R] B,H,W
00000000 00000000
TREQR30 [R] B,H,W
00000000 00000000
TREQR50 [R] B,H,W
00000000 00000000
TREQR70 [R] B,H,W
00000000 00000000
NEWDT10 [R] B,H,W
00000000 00000000
NEWDT30 [R] B,H,W
00000000 00000000
NEWDT50 [R] B,H,W
00000000 00000000
NEWDT70 [R] B,H,W
00000000 00000000
INTPND10 [R] B,H,W
00000000 00000000
INTPND30 [R] B,H,W
00000000 00000000
INTPND50 [R] B,H,W
00000000 00000000
INTPND70 [R] B,H,W
00000000 00000000
MSGVAL10 [R] B,H,W
00000000 00000000
MSGVAL30 [R] B,H,W
00000000 00000000
MSGVAL50 [R] B,H,W
00000000 00000000
MSGVAL70 [R] B,H,W
00000000 00000000
Block
CAN0
(128msb)
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
002100H
002104H
002108H
00210CH
002110H
002114H
002118H
00211CH
002120H
002124H
002128H
00212CH
002130H,
002134H
002138H
00213CH
002140H
002144H
002148H
00214CH
002150H
002154H
002158H
00215CH
002160H,
002164H
002168H
to
00217CH
+0
Address offset value / Register name
+1
+2
CTRLR1 [R/W] B,H,W
-------- 000-0001
ERRCNT1 [R] B,H,W
00000000 00000000
INTR1 [R] B,H,W
00000000 00000000
BRPER1 [R/W] B,H,W
-------- ----0000
IF1CREQ1 [R/W] B,H,W
0------- 00000001
IF1MSK21 [R/W] B,H,W
11-11111 11111111
IF1ARB21 [R/W] B,H,W
00000000 00000000
IF1MCTR1 [R/W] B,H,W
00000000 0---0000
IF1DTA11 [R/W] B,H,W
00000000 00000000
IF1DTB11 [R/W] B,H,W
00000000 00000000
―
―
―
―
Block
STATR1 [R/W] B,H,W
-------- 00000000
BTR1 [R/W] B,H,W
-0100011 00000001
TESTR1 [R/W] B,H,W
-------- X00000-―
―
IF1CMSK1 [R/W] B,H,W
-------- 00000000
IF1MSK11 [R/W] B,H,W
11111111 11111111
IF1ARB11 [R/W] B,H,W
00000000 00000000
―
―
IF1DTA21 [R/W] B,H,W
00000000 00000000
IF1DTB21 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ1 [R/W] B,H,W
0------- 00000001
IF2MSK21 [R/W] B,H,W
11-11111 11111111
IF2ARB21 [R/W] B,H,W
00000000 00000000
IF2MCTR1 [R/W] B,H,W
00000000 0---0000
IF2DTA11 [R/W] B,H,W
00000000 00000000
IF2DTB11 [R/W] B,H,W
00000000 00000000
―
―
―
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
CAN1
(128msb)
―
―
―
―
IF2CMSK1 [R/W] B,H,W
-------- 00000000
IF2MSK11 [R/W] B,H,W
11111111 11111111
IF2ARB11 [R/W] B,H,W
00000000 00000000
―
―
IF2DTA21 [R/W] B,H,W
00000000 00000000
IF2DTB21 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF2 data mirror)
―
131
D a t a S h e e t
Address
002180H
002184H
002188H
00218CH
002190H
002194H
002198H
00219CH
0021A0H
0021A4H
0021A8H
0021ACH
0021B0H
0021B4H
0021B8H
0021BCH
0021C0H
to
0021FCH
132
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
TREQR21 [R] B,H,W
00000000 00000000
TREQR41 [R] B,H,W
00000000 00000000
TREQR61 [R] B,H,W
00000000 00000000
TREQR81 [R] B,H,W
00000000 00000000
NEWDT21 [R] B,H,W
00000000 00000000
NEWDT41 [R] B,H,W
00000000 00000000
NEWDT61 [R] B,H,W
00000000 00000000
NEWDT81 [R] B,H,W
00000000 00000000
INTPND21 [R] B,H,W
00000000 00000000
INTPND41 [R] B,H,W
00000000 00000000
INTPND61 [R] B,H,W
00000000 00000000
INTPND81 [R] B,H,W
00000000 00000000
MSGVAL21 [R] B,H,W
00000000 00000000
MSGVAL41 [R] B,H,W
00000000 00000000
MSGVAL61 [R] B,H,W
00000000 00000000
MSGVAL81 [R] B,H,W
00000000 00000000
+3
TREQR11 [R] B,H,W
00000000 00000000
TREQR31 [R] B,H,W
00000000 00000000
TREQR51 [R] B,H,W
00000000 00000000
TREQR71 [R] B,H,W
00000000 00000000
NEWDT11 [R] B,H,W
00000000 00000000
NEWDT31 [R] B,H,W
00000000 00000000
NEWDT51 [R] B,H,W
00000000 00000000
NEWDT71 [R] B,H,W
00000000 00000000
INTPND11 [R] B,H,W
00000000 00000000
INTPND31 [R] B,H,W
00000000 00000000
INTPND51 [R] B,H,W
00000000 00000000
INTPND71 [R] B,H,W
00000000 00000000
MSGVAL11 [R] B,H,W
00000000 00000000
MSGVAL31 [R] B,H,W
00000000 00000000
MSGVAL51 [R] B,H,W
00000000 00000000
MSGVAL71 [R] B,H,W
00000000 00000000
Block
CAN1
(128msb)
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
002200H
002204H
002208H
00220CH
002210H
002214H
002218H
00221CH
002220H
002224H
002228H
00222CH
002230H,
002234H
002238H
00223CH
002240H
002244H
002248H
00224CH
002250H
002254H
002258H
00225CH
002260H,
002264H
002268H
to
00227CH
+0
Address offset value / Register name
+1
+2
CTRLR2 [R/W] B,H,W
-------- 000-0001
ERRCNT2 [R] B,H,W
00000000 00000000
INTR2 [R] B,H,W
00000000 00000000
BRPER2 [R/W] B,H,W
-------- ----0000
IF1CREQ2 [R/W] B,H,W
0------- 00000001
IF1MSK22 [R/W] B,H,W
11-11111 11111111
IF1ARB22 [R/W] B,H,W
00000000 00000000
IF1MCTR2 [R/W] B,H,W
00000000 0---0000
IF1DTA12 [R/W] B,H,W
00000000 00000000
IF1DTB12 [R/W] B,H,W
00000000 00000000
―
―
―
―
Block
STATR2 [R/W] B,H,W
-------- 00000000
BTR2 [R/W] B,H,W
-0100011 00000001
TESTR2 [R/W] B,H,W
-------- X00000-―
IF1CMSK2 [R/W] B,H,W
-------- 00000000
IF1MSK12 [R/W] B,H,W
11111111 11111111
IF1ARB12 [R/W] B,H,W
00000000 00000000
―
IF1DTA22 [R/W] B,H,W
00000000 00000000
IF1DTB22 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ2 [R/W] B,H,W
0------- 00000001
IF2MSK22 [R/W] B,H,W
11-11111 11111111
IF2ARB22 [R/W] B,H,W
00000000 00000000
IF2MCTR2 [R/W] B,H,W
00000000 0---0000
IF2DTA12 [R/W] B,H,W
00000000 00000000
IF2DTB12 [R/W] B,H,W
00000000 00000000
―
―
―
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
CAN2
(128msb)
―
―
―
―
IF2CMSK2 [R/W] B,H,W
-------- 00000000
IF2MSK12 [R/W] B,H,W
11111111 11111111
IF2ARB12 [R/W] B,H,W
00000000 00000000
―
IF2DTA22 [R/W] B,H,W
00000000 00000000
IF2DTB22 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF2 data mirror)
―
133
D a t a S h e e t
Address
002280H
002284H
002288H
00228CH
002290H
002294H
002298H
00229CH
0022A0H
0022A4H
0022A8H
0022ACH
0022B0H
0022B4H
0022B8H
0022BCH
0022C0H
to
0022FCH
134
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
TREQR22 [R] B,H,W
00000000 00000000
TREQR42 [R] B,H,W
00000000 00000000
TREQR62 [R] B,H,W
00000000 00000000
TREQR82 [R] B,H,W
00000000 00000000
NEWDT22 [R] B,H,W
00000000 00000000
NEWDT42 [R] B,H,W
00000000 00000000
NEWDT62 [R] B,H,W
00000000 00000000
NEWDT82 [R] B,H,W
00000000 00000000
INTPND22 [R] B,H,W
00000000 00000000
INTPND42 [R] B,H,W
00000000 00000000
INTPND62 [R] B,H,W
00000000 00000000
INTPND82 [R] B,H,W
00000000 00000000
MSGVAL22 [R] B,H,W
00000000 00000000
MSGVAL42 [R] B,H,W
00000000 00000000
MSGVAL62 [R] B,H,W
00000000 00000000
MSGVAL82 [R] B,H,W
00000000 00000000
+3
TREQR12 [R] B,H,W
00000000 00000000
TREQR32 [R] B,H,W
00000000 00000000
TREQR52 [R] B,H,W
00000000 00000000
TREQR72 [R] B,H,W
00000000 00000000
NEWDT12 [R] B,H,W
00000000 00000000
NEWDT32 [R] B,H,W
00000000 00000000
NEWDT52 [R] B,H,W
00000000 00000000
NEWDT72 [R] B,H,W
00000000 00000000
INTPND12 [R] B,H,W
00000000 00000000
INTPND32 [R] B,H,W
00000000 00000000
INTPND52 [R] B,H,W
00000000 00000000
INTPND72 [R] B,H,W
00000000 00000000
MSGVAL12 [R] B,H,W
00000000 00000000
MSGVAL32 [R] B,H,W
00000000 00000000
MSGVAL52 [R] B,H,W
00000000 00000000
MSGVAL72 [R] B,H,W
00000000 00000000
Block
CAN2
(128msb)
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
002300H
002304H
002308H
+0
Address offset value / Register name
+1
+2
DFCTLR [R/W] B,H,W
-0------ -------―
―
FLIFCTLR [R/W]
B,H,W
―
---0--00
―
―
FLIFFER1 [R/W]
B,H,W
-------―
00230CH
002310H
TRCR [R/W] B,H,W TRAR [R/W] B,H,W
00000000
00000000
002314H
to
0023FCH
002400H
002404H
002408H
―
SEEARX [R] B,H,W
00000000 00000000
EECSRX [R/W]
B,H,W
―
----00-―
March 28, 2014, MB91F528_DS705-00016-1v0-E
Block
DFSTR [R/W] B,H,W
-----001
WorkFlash
―
FLIFFER2 [R/W]
B,H,W
Flash / WorkFlash
-------Reserved
―
00240CH
to
0024FCH
CONFIDENTIAL
+3
TuningRAM
Reserved
DEEARX [R] B,H,W
00000000 00000000
EFEARX [R/W] B,H,W
00000000 00000000
XBS RAM
ECC control
EFECRX [R/W] B,H,W
-------0 00000000 00000000
―
Reserved
135
D a t a S h e e t
Address
002500H
002504H
002508H
00250CH
002510H
002514H
002518H
00251CH
002520H
002524H
002528H
00252CH
002530H,
002534H
002538H
00253CH
002540H
002544H
002548H
00254CH
002550H
002554H
002558H
00255CH
002560H,
002564H
002568H
00256CH
002570H
to
00257CH
136
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
CTRLR3 [R/W] B,H,W
-------- 000-0001
ERRCNT3 [R] B,H,W
00000000 00000000
INTR3 [R] B,H,W
00000000 00000000
BRPER3 [R/W] B,H,W
-------- ----0000
IF1CREQ3 [R/W] B,H,W
0------- 00000001
IF1MSK23 [R/W] B,H,W
11-11111 11111111
IF1ARB23 [R/W] B,H,W
00000000 00000000
IF1MCTR3 [R/W] B,H,W
00000000 0---0000
IF1DTA13 [R/W] B,H,W
00000000 00000000
IF1DTB13 [R/W] B,H,W
00000000 00000000
―
―
―
―
+3
Block
STATR3 [R/W] B,H,W
-------- 00000000
BTR3 [R/W] B,H,W
-0100011 00000001
TESTR3 [R/W] B,H,W
-------- X00000-―
―
IF1CMSK3 [R/W] B,H,W
-------- 00000000
IF1MSK13 [R/W] B,H,W
11111111 11111111
IF1ARB13 [R/W] B,H,W
00000000 00000000
―
―
IF1DTA23 [R/W] B,H,W
00000000 00000000
IF1DTB23 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ3 [R/W] B,H,W
0------- 00000001
IF2MSK23 [R/W] B,H,W
11-11111 11111111
IF2ARB23 [R/W] B,H,W
00000000 00000000
IF2MCTR3 [R/W] B,H,W
00000000 0---0000
IF2DTA13 [R/W] B,H,W
00000000 00000000
IF2DTB13 [R/W] B,H,W
00000000 00000000
―
―
―
―
―
―
―
―
IF2CMSK3 [R/W] B,H,W
-------- 00000000
IF2MSK13 [R/W] B,H,W
11111111 11111111
IF2ARB13 [R/W] B,H,W
00000000 00000000
―
CAN3
(128msb)
―
IF2DTA23 [R/W] B,H,W
00000000 00000000
IF2DTB23 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF2 data mirror)
―
―
―
―
―
―
―
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
002580H
002584H
002588H
00258CH
002590H
002594H
002598H
00259CH
0025A0H
0025A4H
0025A8H
0025ACH
0025B0H
0025B4H
0025B8H
0025BCH
+0
Address offset value / Register name
+1
+2
TREQR23 [R] B,H,W
00000000 00000000
TREQR43 [R] B,H,W
00000000 00000000
TREQR63 [R] B,H,W
00000000 00000000
TREQR83 [R] B,H,W
00000000 00000000
NEWDT23 [R] B,H,W
00000000 00000000
NEWDT43 [R] B,H,W
00000000 00000000
NEWDT63 [R] B,H,W
00000000 00000000
NEWDT83 [R] B,H,W
00000000 00000000
INTPND23 [R] B,H,W
00000000 00000000
INTPND43 [R] B,H,W
00000000 00000000
INTPND63 [R] B,H,W
00000000 00000000
INTPND83 [R] B,H,W
00000000 00000000
MSGVAL23 [R] B,H,W
00000000 00000000
MSGVAL43 [R] B,H,W
00000000 00000000
MSGVAL63 [R] B,H,W
00000000 00000000
MSGVAL83 [R] B,H,W
00000000 00000000
0025C0H
to
0025FCH
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
TREQR13 [R] B,H,W
00000000 00000000
TREQR33 [R] B,H,W
00000000 00000000
TREQR53 [R] B,H,W
00000000 00000000
TREQR73 [R] B,H,W
00000000 00000000
NEWDT13 [R] B,H,W
00000000 00000000
NEWDT33 [R] B,H,W
00000000 00000000
NEWDT53 [R] B,H,W
00000000 00000000
NEWDT73 [R] B,H,W
00000000 00000000
INTPND13 [R] B,H,W
00000000 00000000
INTPND33 [R] B,H,W
00000000 00000000
INTPND53 [R] B,H,W
00000000 00000000
INTPND73 [R] B,H,W
00000000 00000000
MSGVAL13 [R] B,H,W
00000000 00000000
MSGVAL33 [R] B,H,W
00000000 00000000
MSGVAL53 [R] B,H,W
00000000 00000000
MSGVAL73 [R] B,H,W
00000000 00000000
Block
CAN3
(128msb)
―
137
D a t a S h e e t
Address
002600H
002604H
002608H
00260CH
002610H
002614H
002618H
00261CH
002620H
002624H
002628H
00262CH
002630H,
002634H
002638H
00263CH
002640H
002644H
002648H
00264CH
002650H
002654H
002658H
00265CH
002660H,
002664H
002668H
00266CH
002670H
to
00267CH
138
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
CTRLR4 [R/W] B,H,W
-------- 000-0001
ERRCNT4 [R] B,H,W
00000000 00000000
INTR4 [R] B,H,W
00000000 00000000
BRPER4 [R/W] B,H,W
-------- ----0000
IF1CREQ4 [R/W] B,H,W
0------- 00000001
IF1MSK24 [R/W] B,H,W
11-11111 11111111
IF1ARB24 [R/W] B,H,W
00000000 00000000
IF1MCTR4 [R/W] B,H,W
00000000 0---0000
IF1DTA14 [R/W] B,H,W
00000000 00000000
IF1DTB14 [R/W] B,H,W
00000000 00000000
―
―
―
―
+3
Block
STATR4 [R/W] B,H,W
-------- 00000000
BTR4 [R/W] B,H,W
-0100011 00000001
TESTR4 [R/W] B,H,W
-------- X00000-―
―
IF1CMSK4 [R/W] B,H,W
-------- 00000000
IF1MSK14 [R/W] B,H,W
11111111 11111111
IF1ARB14 [R/W] B,H,W
00000000 00000000
―
―
IF1DTA24 [R/W] B,H,W
00000000 00000000
IF1DTB24 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ4 [R/W] B,H,W
0------- 00000001
IF2MSK24 [R/W] B,H,W
11-11111 11111111
IF2ARB24 [R/W] B,H,W
00000000 00000000
IF2MCTR4 [R/W] B,H,W
00000000 0---0000
IF2DTA14 [R/W] B,H,W
00000000 00000000
IF2DTB14 [R/W] B,H,W
00000000 00000000
―
―
―
―
―
―
―
―
IF2CMSK4 [R/W] B,H,W
-------- 00000000
IF2MSK14 [R/W] B,H,W
11111111 11111111
IF2ARB14 [R/W] B,H,W
00000000 00000000
―
CAN4
(128msb)
―
IF2DTA24 [R/W] B,H,W
00000000 00000000
IF2DTB24 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF2 data mirror)
―
―
―
―
―
―
―
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
002680H
002684H
002688H
00268CH
002690H
002694H
002698H
00269CH
0026A0H
0026A4H
0026A8H
0026ACH
0026B0H
0026B4H
0026B8H
0026BCH
+0
Address offset value / Register name
+1
+2
TREQR24 [R] B,H,W
00000000 00000000
TREQR44 [R] B,H,W
00000000 00000000
TREQR64 [R] B,H,W
00000000 00000000
TREQR84 [R] B,H,W
00000000 00000000
NEWDT24 [R] B,H,W
00000000 00000000
NEWDT44 [R] B,H,W
00000000 00000000
NEWDT64 [R] B,H,W
00000000 00000000
NEWDT84 [R] B,H,W
00000000 00000000
INTPND24 [R] B,H,W
00000000 00000000
INTPND44 [R] B,H,W
00000000 00000000
INTPND64 [R] B,H,W
00000000 00000000
INTPND84 [R] B,H,W
00000000 00000000
MSGVAL24 [R] B,H,W
00000000 00000000
MSGVAL44 [R] B,H,W
00000000 00000000
MSGVAL64 [R] B,H,W
00000000 00000000
MSGVAL84 [R] B,H,W
00000000 00000000
0026C0H
to
0026FCH
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
TREQR14 [R] B,H,W
00000000 00000000
TREQR34 [R] B,H,W
00000000 00000000
TREQR54 [R] B,H,W
00000000 00000000
TREQR74 [R] B,H,W
00000000 00000000
NEWDT14 [R] B,H,W
00000000 00000000
NEWDT34 [R] B,H,W
00000000 00000000
NEWDT54 [R] B,H,W
00000000 00000000
NEWDT74 [R] B,H,W
00000000 00000000
INTPND14 [R] B,H,W
00000000 00000000
INTPND34 [R] B,H,W
00000000 00000000
INTPND54 [R] B,H,W
00000000 00000000
INTPND74 [R] B,H,W
00000000 00000000
MSGVAL14 [R] B,H,W
00000000 00000000
MSGVAL34 [R] B,H,W
00000000 00000000
MSGVAL54 [R] B,H,W
00000000 00000000
MSGVAL74 [R] B,H,W
00000000 00000000
Block
CAN4
(128msb)
―
139
D a t a S h e e t
Address
002700H
002704H
002708H
00270CH
002710H
002714H
002718H
00271CH
002720H
002724H
002728H
00272CH
002730H,
002734H
002738H
00273CH
002740H
002744H
002748H
00274CH
002750H
002754H
002758H
00275CH
002760H,
002764H
002768H
00276CH
002770H
to
00277CH
140
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
CTRLR5 [R/W] B,H,W
-------- 000-0001
ERRCNT5 [R] B,H,W
00000000 00000000
INTR5 [R] B,H,W
00000000 00000000
BRPER5 [R/W] B,H,W
-------- ----0000
IF1CREQ5 [R/W] B,H,W
0------- 00000001
IF1MSK25 [R/W] B,H,W
11-11111 11111111
IF1ARB25 [R/W] B,H,W
00000000 00000000
IF1MCTR5 [R/W] B,H,W
00000000 0---0000
IF1DTA15 [R/W] B,H,W
00000000 00000000
IF1DTB15 [R/W] B,H,W
00000000 00000000
―
―
―
―
+3
Block
STATR5 [R/W] B,H,W
-------- 00000000
BTR5 [R/W] B,H,W
-0100011 00000001
TESTR5 [R/W] B,H,W
-------- X00000-―
―
IF1CMSK5 [R/W] B,H,W
-------- 00000000
IF1MSK15 [R/W] B,H,W
11111111 11111111
IF1ARB15 [R/W] B,H,W
00000000 00000000
―
―
IF1DTA25 [R/W] B,H,W
00000000 00000000
IF1DTB25 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF1 data mirror)
―
―
―
―
IF2CREQ5 [R/W] B,H,W
0------- 00000001
IF2MSK25 [R/W] B,H,W
11-11111 11111111
IF2ARB25 [R/W] B,H,W
00000000 00000000
IF2MCTR5 [R/W] B,H,W
00000000 0---0000
IF2DTA15 [R/W] B,H,W
00000000 00000000
IF2DTB15 [R/W] B,H,W
00000000 00000000
―
―
―
―
―
―
―
―
IF2CMSK5 [R/W] B,H,W
-------- 00000000
IF2MSK15 [R/W] B,H,W
11111111 11111111
IF2ARB15 [R/W] B,H,W
00000000 00000000
―
CAN5
(128msb)
―
IF2DTA25 [R/W] B,H,W
00000000 00000000
IF2DTB25 [R/W] B,H,W
00000000 00000000
―
―
―
―
Reserved (IF2 data mirror)
―
―
―
―
―
―
―
―
―
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
002780H
002784H
002788H
00278CH
002790H
002794H
002798H
00279CH
0027A0H
0027A4H
0027A8H
0027ACH
0027B0H
0027B4H
0027B8H
0027BCH
+0
Address offset value / Register name
+1
+2
TREQR25 [R] B,H,W
00000000 00000000
TREQR45 [R] B,H,W
00000000 00000000
TREQR65 [R] B,H,W
00000000 00000000
TREQR85 [R] B,H,W
00000000 00000000
NEWDT25 [R] B,H,W
00000000 00000000
NEWDT45 [R] B,H,W
00000000 00000000
NEWDT65 [R] B,H,W
00000000 00000000
NEWDT85 [R] B,H,W
00000000 00000000
INTPND25 [R] B,H,W
00000000 00000000
INTPND45 [R] B,H,W
00000000 00000000
INTPND65 [R] B,H,W
00000000 00000000
INTPND85 [R] B,H,W
00000000 00000000
MSGVAL25 [R] B,H,W
00000000 00000000
MSGVAL45 [R] B,H,W
00000000 00000000
MSGVAL65 [R] B,H,W
00000000 00000000
MSGVAL85 [R] B,H,W
00000000 00000000
0027C0H
to
002FFCH
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
TREQR15 [R] B,H,W
00000000 00000000
TREQR35 [R] B,H,W
00000000 00000000
TREQR55 [R] B,H,W
00000000 00000000
TREQR75 [R] B,H,W
00000000 00000000
NEWDT15 [R] B,H,W
00000000 00000000
NEWDT35 [R] B,H,W
00000000 00000000
NEWDT55 [R] B,H,W
00000000 00000000
NEWDT75 [R] B,H,W
00000000 00000000
INTPND15 [R] B,H,W
00000000 00000000
INTPND35 [R] B,H,W
00000000 00000000
INTPND55 [R] B,H,W
00000000 00000000
INTPND75 [R] B,H,W
00000000 00000000
MSGVAL15 [R] B,H,W
00000000 00000000
MSGVAL35 [R] B,H,W
00000000 00000000
MSGVAL55 [R] B,H,W
00000000 00000000
MSGVAL75 [R] B,H,W
00000000 00000000
Block
CAN5
(128msb)
―
141
D a t a S h e e t
Address
003000H
003004H
003008H
00300CH
003010H
003014H
003018H
00301CH
003020H
003024H
to
00302CH
003030H
003034H
003038H
00303CH
003040H
003044H
003048H,
00304CH
142
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
SEEARA [R] B,H,W
----0000 00000000
EECSRA [R/W]
B,H,W
―
----00--
+3
Block
DEEARA [R] B,H,W
----0000 00000000
EFEARA [R/W] B,H,W
----0000 00000000
EFECRA [R/W] B,H,W
-------0 00000000 00000000
TEAR0X[R] B,H,W
000----- -------- 00000000 00000000
TEAR1X[R] B,H,W
000----- -------- 00000000 00000000
TEAR2X[R] B,H,W
000----- -------- 00000000 00000000
TAEARX [R/W] B,H,W
TASARX [R/W] B,H,W
10111111 11111111
00000000 00000000
TFECRX [R/W]
TICRX [R/W]
TTCRX [R/W] B,H,W
B,H,W
B,H,W
------00 00001100
----0000
----0000
TSRCRX [W]
TKCCRX [R/W]
B,H,W
―
―
B,H,W
0------00----00
Backup RAM
ECC control
―
RAM/diagnosis
XBS RAM
―
Reserved
TEAR0A[R] B,H,W
000----- -------- ----0000 00000000
TEAR1A[R] B,H,W
000----- -------- ----0000 00000000
TEAR2A[R] B,H,W
000----- -------- ----0000 00000000
TAEARA[R/W] B,H,W
TASARA[R/W] B,H,W
----1111 11111111
----0000 00000000
TFECRA [R/W]
TICRA [R/W]
TTCRA [R/W] B,H,W
B,H,W
B,H,W
------00 00001100
----0000
----0000
TSRCRA [W]
TKCCRA [R/W]
B,H,W
―
―
B,H,W
0------00----00
RAM/diagnosis
Backup RAM
―
Reserved
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
003050H
003054H
003058H
00305CH
003060H
003064H
003068H
00306CH
003070H
003074H
+0
Address offset value / Register name
+1
+2
SEEARH [R] B,H,W
--000000 00000000
EECSRH [R/W]
B,H,W
―
----00--
DEEARH [R] B,H,W
--000000 00000000
EFEARH [R/W]
B,H,W
--000000 00000000
EFECRH [R/W] B,H,W
―
-------0 00000000 00000000
―
TEAR0H[R] B,H,W
000----- -------- --000000 00000000
TEAR1H[R] B,H,W
000----- -------- --000000 00000000
TEAR2H[R] B,H,W
000----- -------- --000000 00000000
TAEARH[R/W] B,H,W
TASARH[R/W] B,H,W
--111111 11111111
--000000 00000000
TFECRH [R/W]
TICRH [R/W]
TTCRH [R/W] B,H,W
B,H,W
B,H,W
------00 00001100
----0000
----0000
TSRCRH [W]
TKCCRH [R/W]
B,H,W
―
―
B,H,W
0------00----00
003078H
to
0030FCH
003100H
003104H
003108H
00310CH
003110H
003114H
003118H
00311CH
003120H
003124H
003128H
to
003FFCH
004000H
to
007FFCH
008000H
to
00CFFCH
―
BUSDIGSR0[R/W] H,W
00000000 0-----00
BUSDIGSR2[R/W] H,W
00000000 0-----00
―
―
Block
AHB RAM
ECC control
Reserved
RAM/diagnosis
AHB RAM
Reserved
BUSDIGSR1[R/W] H,W
00000000 0-----00
BUSTSTR0[R/W] H,W
00--0000 00000000
BUSADR0 [R] W
00000000 00000000 00000000 00000000
BUSADR1 [R] W
00000000 00000000 00000000 00000000
BUSADR2 [R] W
00000000 00000000 00000000 00000000
BUSDIGSR3[R/W] H,W
―
―
00000000 0-----00
BUSDIGSR4[R/W] H,W
BUSTSTR1[R/W] H,W
00000000 0-----00
00--000- 00000000
―
―
―
―
BUSADR3 [R] W
00000000 00000000 00000000 00000000
BUSADR4 [R] W
00000000 00000000 00000000 00000000
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
BUS diagnosis
―
Reserved
Backup-RAM
Backup RAM area
―
―
Reserved
143
D a t a S h e e t
Address
+0
00D004H
―
00D020H
00D024H
00D028H
00D02CH
00D030H
00D034H
00D038H
00D03CH
00D040H
00D044H
00D048H
00D04CH
00D050H
00D080H
00D084H
00D088H
00D08CH
00D090H
00D094H
00D098H
00D09CH
144
CONFIDENTIAL
―
―
―
―
―
SUCC1[R/W] W
----1100 01000000 00010-00 1---0000
SUCC2[R/W] W
----0001 ---00000 00000101 00000100
SUCC3[R/W] W
-------- -------- -------- 00010001
NEMC[R/W] W
-------- -------- -------- ----0000
PRTC1[R/W] W
000010-0 01001100 0000-110 00110011
PRTC2[R/W] W
--001111 00101101 --001010 -–001110
MHDC[R/W] W
---00000 00000000 -------- -0000000
―
Block
FlexRay
CIF
―
LCK[R/W] W
-------- -------- -------- 00000000
EIR[R/W] W
-----000 -----000 ----0000 00000000
SIR[R/W] W
------00 ------00 00000000 00000000
EILS[R/W] W
-----000 -----000 ----0000 00000000
SILS[R/W] W
------11 ------11 11111111 11111111
EIES[R/W] W
-----000 -----000 ----0000 00000000
EIER[R/W] W
-----000 -----000 ----0000 00000000
SIES[R/W] W
------00 ------00 00000000 00000000
SIER[R/W] W
------00 ------00 00000000 00000000
ILE[R/W] W
-------- -------- -------- ------00
T0C[R/W] W
--000000 00000000 -0000000 ------00
T1C[R/W] W
--000000 00000010 -------- ------00
STPW1[R/W] W
--000000 00000000 --000000 -0000000
STPW2[R] W
-----000 00000000 -----000 00000000
00D01CH
00D054H
to
00D07CH
+3
CIF0[R] W
00000100 11111111 01011011 11111111
CIF1[R/W] W
00000000 -------0 -0000000 --------
00D000H
00D008H
to
00D018H
Address offset value / Register name
+1
+2
Reserved
FlexRay
GIF
FlexRay
INT
―
Reserved
FlexRay
SUC
FlexRay
NEM
FlexRay
PRT
FlexRay
MHD
Reserved
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
+0
00D0A4H
00D0A8H
00D0ACH
00D0B0H
00D0B4H
00D0B8H
00D0BCH
00D0C0H
00D0C4H
00D0C8H
00D100H
00D104H
00D108H
00D10CH
00D110H
00D114H
00D118H
00D11CH
00D120H
00D124H
00D128H
00D12CH
―
―
―
CCSV[R] W
--000000 00010000 -100--00 00000000
CCEV[R] W
-------- -------- ---00000 00--0000
―
―
SCV[R] W
-----000 00000000 -----000 00000000
MTCCV[R] W
-------- --000000 --000000 00000000
RCV[R] W
-------- -------- ----0000 00000000
OCV[R] W
-------- -----000 00000000 00000000
SFS[R] W
-------- ----0000 00000000 00000000
SWNIT[R] W
-------- -------- ----0000 00000000
ACS[R/W] W
-------- -------- ---00000 ---00000
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
GTUC1[R/W] W
-------- ----0000 00000010 10000000
GTUC2[R/W] W
-------- ----0010 --000000 00001010
GTUC3[R/W] W
-0000010 -0000010 00000000 00000000
GTUC4[R/W] W
--000000 00001000 --000000 00000111
GTUC5[R/W] W
00001110 ---00000 00000000 00000000
GTUC6[R/W] W
-----000 00000010 -----000 00000000
GTUC7[R/W] W
------00 00000010 ------00 00000100
GTUC8[R/W] W
---00000 00000000 -------- --000010
GTUC9[R/W] W
-------- ------00 ---00001 -–000001
GTUC10[R/W] W
-----000 00000010 --000000 00000101
GTUC11[R/W] W
-----000 -----000 ------00 ------00
00D0A0H
00D0CCH
to
00D0FCH
Address offset value / Register name
+1
+2
Block
FlexRay
GTU
―
Reserved
FlexRay
SUC
Reserved
FlexRay
GTU
145
D a t a S h e e t
Address
00D130H
00D134H
00D138H
00D13CH
00D140H
00D144H
00D148H
00D14CH
00D150H
00D154H
00D158H
00D15CH
00D160H
00D164H
00D168H
00D16CH
146
CONFIDENTIAL
+0
Address offset value / Register name
+1
+2
ESID1[R] W
-------- -------- 00----00 00000000
ESID2[R] W
-------- -------- 00----00 00000000
ESID3[R] W
-------- -------- 00----00 00000000
ESID4[R] W
-------- -------- 00----00 00000000
ESID5[R] W
-------- -------- 00----00 00000000
ESID6[R] W
-------- -------- 00----00 00000000
ESID7[R] W
-------- -------- 00----00 00000000
ESID8[R] W
-------- -------- 00----00 00000000
ESID9[R] W
-------- -------- 00----00 00000000
ESID10[R] W
-------- -------- 00----00 00000000
ESID11[R] W
-------- -------- 00----00 00000000
ESID12[R] W
-------- -------- 00----00 00000000
ESID13[R] W
-------- -------- 00----00 00000000
ESID14[R] W
-------- -------- 00----00 00000000
ESID15[R] W
-------- -------- 00----00 00000000
―
+3
Block
FlexRay
GTU
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
+0
00D174H
00D178H
00D17CH
00D180H
00D184H
00D188H
00D18CH
00D190H
00D194H
00D198H
00D19CH
00D1A0H
00D1A4H
00D1A8H
00D1ACH
00D1B0H
00D1B4H
00D1B8H
―
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
+3
OSID1[R] W
-------- -------- 00----00 00000000
OSID2[R] W
-------- -------- 00----00 00000000
OSID3[R] W
-------- -------- 00----00 00000000
OSID4[R] W
-------- -------- 00----00 00000000
OSID5[R] W
-------- -------- 00----00 00000000
OSID6[R] W
-------- -------- 00----00 00000000
OSID7[R] W
-------- -------- 00----00 00000000
OSID8[R] W
-------- -------- 00----00 00000000
OSID9[R] W
-------- -------- 00----00 00000000
OSID10[R] W
-------- -------- 00----00 00000000
OSID11[R] W
-------- -------- 00----00 00000000
OSID12[R] W
-------- -------- 00----00 00000000
OSID13[R] W
-------- -------- 00----00 00000000
OSID14[R] W
-------- -------- 00----00 00000000
OSID15[R] W
-------- -------- 00----00 00000000
―
NMV1[R] W
00000000 00000000 00000000 00000000
NMV2[R] W
00000000 00000000 00000000 00000000
NMV3[R] W
00000000 00000000 00000000 00000000
00D170H
00D1BCH
to
00D2FCH
Address offset value / Register name
+1
+2
―
―
Block
FlexRay
GTU
Reserved
FlexRay
NEM
―
Reserved
147
D a t a S h e e t
Address
+0
00D304H
00D308H
00D30CH
00D310H
00D314H
00D318H
00D31CH
00D320H
00D324H
00D328H
00D32CH
00D330H
00D334H
00D338H
00D33CH
00D340H
00D344H
00D348H
00D34CH
―
00D3F4H
148
CONFIDENTIAL
―
―
―
―
―
Block
FlexRay
MHD
―
CREL[R] W
00010000 00111001 00000010 00000110
ENDN[R] W
10000111 01100101 01000011 00100001
00D3F0H
00D3F8H,
00D3FCH
+3
MRC[R/W] W
-----001 10000000 00000000 00000000
FRF[R/W] W
-------1 10000000 ---00000 00000000
FRFM[R/W] W
-------- -------- ---00000 000000-FCL[R/W] W
-------- -------- -------- 10000000
MHDS[R/W] W
-0000000 -0000000 -0000000 10000000
LDTS[R] W
-----000 00000000 -----000 00000000
FSR[R] W
-------- -------- 00000000 -----000
MHDF[R/W] W
-------- -------- -------0 00000000
TXRQ1[R] W
00000000 00000000 00000000 00000000
TXRQ2[R] W
00000000 00000000 00000000 00000000
TXRQ3[R] W
00000000 00000000 00000000 00000000
TXRQ4[R] W
00000000 00000000 00000000 00000000
NDAT1[R] W
00000000 00000000 00000000 00000000
NDAT2[R] W
00000000 00000000 00000000 00000000
NDAT3[R] W
00000000 00000000 00000000 00000000
NDAT4[R] W
00000000 00000000 00000000 00000000
MBSC1[R] W
00000000 00000000 00000000 00000000
MBSC2[R] W
00000000 00000000 00000000 00000000
MBSC3[R] W
00000000 00000000 00000000 00000000
MBSC4[R] W
00000000 00000000 00000000 00000000
00D300H
00D350H
to
00D3ECH
Address offset value / Register name
+1
+2
Reserved
FlexRay
GIF
―
Reserved
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Address
+0
00D400H
to
00D4FCH
WRHS1[R/W] W
--000000 -0000000 -----000 00000000
WRHS2[R/W] W
-------- -0000000 -----000 00000000
WRHS3[R/W] W
-------- -------- -----000 00000000
―
IBCM[R/W] W
-------- -----000 -------- -----000
IBCR[R/W] W
0------- -0000000 0------- -0000000
00D504H
00D508H
00D50CH
00D510H
00D514H
―
―
―
FlexRay
IBF
―
RDHS1[R] W
--000000 -0000000 -----000 00000000
RDHS2[R] W
-0000000 -0000000 -----000 00000000
RDHS3[R] W
--000000 --000000 -----000 00000000
MBS[R] W
--000000 --000000 00-00000 00000000
OBCM[R/W] W
-------- ------00 -------- ------00
OBCR[R/W] W
-------- -0000000 0-----00 -0000000
00D704H
00D708H
00D70CH
00D710H
00D714H
Reserved
FlexRay
OBF
―
―
―
―
Reserved
―
―
―
―
Reserved
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Block
RDDSn[1-64][R] W
00000000 00000000 00000000 00000000
00D700H
00D718H
to
00D7FCH
00D800H
to
00EFFCH
+3
WRDSn[1-64][R/W] W
00000000 00000000 00000000 00000000
00D500H
00D518H
to
00D5FCH
00D600H
to
00D6FCH
Address offset value / Register name
+1
+2
149
D a t a S h e e t
Address
00F000H
to
00FEFCH
00FF00H
00FF04H
to
00FF0CH
00FF10H
00FF14H
00FF18H
to
00FFF4H
00FFF8H
00FFFCH
+0
―
Address offset value / Register name
+1
+2
―
DSUCR [R/W] B,H,W
-------- -------0
+3
Block
―
―
Reserved [S]
―
―
OCDU [S]
―
Reserved [S]
PCSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PSSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
OCDU [S]
―
Reserved [S]
EDIR1 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDIR0 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
[S]:It is a system register. The illegal instruction exception (data access error) is generated in these registers in
the user mode when reading and writing to it.
150
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 INTERRUPT VECTOR TABLE
This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers.
 Interrupt vector
 MB91F52xR (144pin)
Interrupt factor
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of illegal instruction
NMI request
Error generation at internal bus diagnosis
XBS RAM double-bit error detection
Backup RAM double-bit error detection
AHB RAM double-bit error detection
TPU violation
External interrupt 0-7
External interrupt 8-15
External low-voltage detection interrupt
Reload timer 0/1/4/5
Reload timer 2/3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
0A
0B
0C
0D
0E
-
15
0F
16
Offset
Default
address for
TBR
RN
*
3FCH 000FFFFCH
3F8H 000FFFF8H
3F4H 000FFFF4H
3F0H 000FFFF0H
3ECH 000FFFECH
3E8H 000FFFE8H
3E4H 000FFFE4H
3E0H 000FFFE0H
3DCH 000FFFDCH
3D8H 000FFFD8H
3D4H 000FFFD4H
3D0H 000FFFD0H
3CCH 000FFFCCH
3C8H 000FFFC8H
3C4H 000FFFC4H
-
15(FH)
Fixed
3C0H
000FFFC0H
-
10
ICR00
3BCH
000FFFBCH
0
17
11
ICR01
3B8H
000FFFB8H
1*8
18
19
12
13
ICR02
ICR03
3B4H
3B0H
000FFFB4H
000FFFB0H
2*2
3*2
20
14
ICR04
3ACH
000FFFACH
4*1
21
15
ICR05
3A8H
000FFFA8H
5*1
22
16
ICR06
3A4H
000FFFA4H
6*1
23
17
ICR07
3A0H
000FFFA0H
7*1
151
D a t a S h e e t
Interrupt factor
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
FlexRay0
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
FlexRay1
Multi-function serial interface
ch.6 (transmission completed)
FlexRay timer 0
CAN0
CAN3
FlexRay timer 1
CAN1
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization completed
Error generation at Backup RAM diagnosis
AHB RAM diagnosis completed
AHB RAM initialization completed
Error generation at AHB RAM diagnosis
CAN4
CAN2
Up/down counter 0
Up/down counter 1
CAN5
FlexRay PLL gear/FlexRay PLL alarm
152
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
24
18
ICR08
39CH
000FFF9CH
8*1
25
19
ICR09
398H
000FFF98H
9*1
26
1A
ICR10
394H
000FFF94H
10*1
27
1B
ICR11
390H
000FFF90H
11
28
1C
ICR12
38CH
000FFF8CH
12*1
29
1D
ICR13
388H
000FFF88H
13
30
1E
ICR14
384H
000FFF84H
14*1
31
1F
ICR15
380H
000FFF80H
15*9
32
20
ICR16
37CH
000FFF7CH
16*1
33
21
ICR17
378H
000FFF78H
17*10
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Interrupt factor
Real time clock
Multi-function serial interface
ch.7 (reception completed)
Multi-function serial interface
ch.7 (status)
16-bit free-run timer 0 ("0" detection) / (compare
clear)
Multi-function serial interface
ch.7 (transmission completed)
PPG0/1/10/11/20/21/30/31/40/41
16-bit free-run timer 1 ("0" detection) / (compare
clear)
PPG2/3/12/13/22/23/32/33/43
16-bit free-run timer 2 ("0" detection) / (compare
clear)
PPG4/5/14/15/24/25/34/35/44
PPG6/7/16/17/26/27/36/37
PPG8/9/18/19/28/29
Multi-function serial interface
ch.8 (reception completed)
Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (Sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit free-run timer 3/5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching /measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching /measurement)
Multi-function serial interface
ch.10 (transmission completed)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H
22*1
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24*3
41
29
ICR25
358H
000FFF58H
25*3
42
43
44
2A
2B
2C
ICR26
ICR27
ICR28
354H
350H
34CH
000FFF54H
000FFF50H
000FFF4CH
26*3
27*3
28*3
45
2D
ICR29
348H
000FFF48H
29*1
46
2E
ICR30
344H
000FFF44H
30
47
2F
ICR31
340H
000FFF40H
31*1
*4
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H
34*6
51
33
ICR35
330H
000FFF30H
35*6
52
34
ICR36
32CH
000FFF2CH
36*1
53
35
ICR37
328H
000FFF28H
37
153
D a t a S h e e t
Interrupt factor
32-bit ICU8 (fetching /measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching /measurement)
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching /measurement)
Multi-function serial interface
ch.11 (transmission completed)
32-bit ICU5 (fetching /measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
32-bit OCU6/7/10/11 (match)
32-bit OCU8/9 (match)
Base timer 0 IRQ0
Base timer 0 IRQ1
Base timer 1 IRQ0
Base timer 1 IRQ1
-
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
54
36
ICR38
324H
000FFF24H
38*1
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H
310H
000FFF14H
000FFF10H
42
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45*5
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delayed interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOSTM*11)
64
40
-
2FCH
000FFEFCH
-
System reserved
(Used for REALOS)
65
41
-
2F8H
000FFEF8H
-
Used with the INT instruction.
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
*:
*1:
*2:
*3:
*4:
*5:
*6:
*8:
*9:
*10:
*11:
It does not support the DMA transfer request by the interrupt generated from a peripheral to which no RN
(Resource Number) is assigned.
The status of the multi-function serial interface does not support the DMA transfer by the I 2C reception and
FlexRay.
The reload timer ch.4 to ch.7 does not support the DMA transfer by the interrupt.
The PPG ch.24 to ch.87 does not support the DMA transfer by the interrupt.
The clock calibration unit does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the interrupt because of the RAM ECC bit error.
The 32-bit free-run timer ch.3 to ch.10 does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the external low-voltage detection interrupt.
It does not support the DMA transfer by the FlexRay interrupt.
It does not support the DMA transfer by the FlexRay timer interrupt.
REALOS is a trademark of Spansion LLC.
154
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 MB91F52xU (176pin)
Interrupt factor
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
8
9
0A
0B
0C
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of illegal instruction
NMI request
Error generation at internal bus diagnosis
XBS RAM double-bit error detection
Backup RAM double-bit error detection
AHB RAM double-bit error detection
TPU violation
14
0E
-
3C4H
000FFFC4H
-
15
0F
15(FH)
Fixed
3C0H
000FFFC0H
-
External interrupt 0-7
16
10
ICR00
3BCH 000FFFBCH
0
External interrupt 8-15
External low-voltage detection interrupt
-
17
11
ICR01
3B8H
000FFFB8H
1*8
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 2/3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
19
13
ICR03
3B0H
000FFFB0H
3*2
20
14
ICR04 3ACH 000FFFACH
4*1
21
15
ICR05
3A8H
000FFFA8H
5*1
22
16
ICR06
3A4H
000FFFA4H
6*1
23
17
ICR07
3A0H
000FFFA0H
7*1
24
18
ICR08
39CH
000FFF9CH
8*1
25
19
ICR09
398H
000FFF98H
9*1
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
155
D a t a S h e e t
Interrupt factor
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4 (reception completed)
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
Multi-function serial interface
ch.5 (reception completed)
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
FlexRay0
Multi-function serial interface
ch.6 (reception completed)
Multi-function serial interface
ch.6 (status)
FlexRay1
Multi-function serial interface
ch.6 (transmission completed)
FlexRay timer 0
CAN0
CAN3
FlexRay timer 1
CAN1
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization completed
Error generation at Backup RAM diagnosis
AHB RAM diagnosis completed
AHB RAM initialization completed
Error generation at AHB RAM diagnosis
CAN4
CAN2
Up/down counter 0
Up/down counter 1
CAN5
FlexRay PLL gear/FlexRay PLL alarm
Real time clock
Multi-function serial interface
ch.7 (reception completed)
Multi-function serial interface
ch.7 (status)
156
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
26
1A
ICR10
394H
000FFF94H
10*1
27
1B
ICR11
390H
000FFF90H
11
28
1C
ICR12
38CH
000FFF8CH
12*1
29
1D
ICR13
388H
000FFF88H
13
30
1E
ICR14
384H
000FFF84H
14*1
31
1F
ICR15
380H
000FFF80H
15*9
32
20
ICR16
37CH
000FFF7CH
16*1
33
21
ICR17
378H
000FFF78H 17*10
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H
22*1
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Interrupt factor
16-bit free-run timer 0 ("0" detection) / (compare
clear)
Multi-function serial interface
ch.7 (transmission completed)
PPG0/1/10/11/20/21/30/31/40/41
16-bit free-run timer 1 ("0" detection) / (compare
clear)
PPG2/3/12/13/22/23/32/33/42/43
16-bit free-run timer 2 ("0" detection) / (compare
clear)
PPG4/5/14/15/24/25/34/35/44/45
PPG6/7/16/17/26/27/36/37/46/47
PPG8/9/18/19/28/29/38/39
Multi-function serial interface
ch.8 (reception completed)
Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (Sub oscillation)
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit free-run timer 4
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit free-run timer 3/5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching /measurement)
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching /measurement)
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching /measurement)
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24*3
41
29
ICR25
358H
000FFF58H
25*3
42
43
44
2A
2B
2C
ICR26
ICR27
ICR28
354H
350H
34CH
000FFF54H
000FFF50H
000FFF4CH
26*3
27*3
28*3
45
2D
ICR29
348H
000FFF48H
29*1
46
2E
ICR30
344H
000FFF44H
30
47
2F
ICR31
340H
000FFF40H
31*1
*4
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H
34*6
51
33
ICR35
330H
000FFF30H
35*6
52
34
ICR36
32CH
000FFF2CH
36*1
53
35
ICR37
328H
000FFF28H
37
54
36
ICR38
324H
000FFF24H
38*1
157
D a t a S h e e t
Interrupt factor
32-bit ICU9 (fetching /measurement)
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching /measurement)
Multi-function serial interface
ch.11 (transmission completed)
32-bit ICU5 (fetching /measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
32-bit OCU6/7/10/11 (match)
32-bit OCU8/9 (match)
Base timer 0 IRQ0
Base timer 0 IRQ1
Base timer 1 IRQ0
Base timer 1 IRQ1
-
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H
310H
000FFF14H
000FFF10H
42
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45*5
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delayed interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS)
64
40
-
2FCH
000FFEFCH
-
System reserved
(Used for REALOS)
65
41
-
2F8H
000FFEF8H
-
Used with the INT instruction.
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
*:
*1:
*2:
*3:
*4:
*5:
*6:
*8:
*9:
*10:
It does not support the DMA transfer request by the interrupt generated from a peripheral to which no RN
(Resource Number) is assigned.
The status of the multi-function serial interface does not support the DMA transfer by the I 2C reception and
FlexRay.
The reload timer ch.4 to ch.7 does not support the DMA transfer by the interrupt.
The PPG ch.24 to ch.87 does not support the DMA transfer by the interrupt.
The clock calibration unit does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the interrupt because of the RAM ECC bit error.
The 32-bit free-run timer ch.3 to ch.10 does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the external low-voltage detection interrupt.
It does not support the DMA transfer by the FlexRay interrupt.
It does not support the DMA transfer by the FlexRay timer interrupt.
158
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 MB91F52xM (208pin)
Interrupt factor
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
8
9
0A
0B
0C
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of illegal instruction
NMI request
Error generation at internal bus diagnosis
XBS RAM double-bit error detection
Backup RAM double-bit error detection
AHB RAM double-bit error detection
TPU violation
14
0E
-
3C4H
000FFFC4H
-
15
0F
15(FH)
Fixed
3C0H
000FFFC0H
-
External interrupt 0-7
16
10
ICR00
3BCH 000FFFBCH
0
External interrupt 8-15
External low-voltage detection interrupt
External interrupt 16-23
17
11
ICR01
3B8H
000FFFB8H
1*8
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 2/3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
19
13
ICR03
3B0H
000FFFB0H
3*2
20
14
ICR04
3ACH 000FFFACH
4*1
21
15
ICR05
3A8H
000FFFA8H
5*1
22
16
ICR06
3A4H
000FFFA4H
6*1
23
17
ICR07
3A0H
000FFFA0H
7*1
24
18
ICR08
39CH
000FFF9CH
8*1
25
19
ICR09
398H
000FFF98H
9*1
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
159
D a t a S h e e t
Interrupt factor
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4/ ch.12 (reception completed)
Multi-function serial interface
ch.4/ ch.12 (status)
Multi-function serial interface
ch.4/ ch.12 (transmission completed)
Multi-function serial interface
ch.5/ ch.13 (reception completed)
Multi-function serial interface
ch.5/ ch.13 (status)
Multi-function serial interface
ch.5/ ch.13 (transmission completed)
FlexRay0
Multi-function serial interface
ch.6/ ch.14 (reception completed)
Multi-function serial interface
ch.6/ ch.14 (status)
FlexRay1
Multi-function serial interface
ch.6/ ch.14 (transmission completed)
FlexRay timer 0
CAN0
CAN3
FlexRay timer 1
CAN1
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization completed
Error generation at Backup RAM diagnosis
AHB RAM diagnosis completed
AHB RAM initialization completed
Error generation at AHB RAM diagnosis
CAN4
CAN2
Up/down counter 0/2
Up/down counter 1/3
CAN5
FlexRay PLL gear/FlexRay PLL alarm
Real time clock
Multi-function serial interface
ch.7/ ch.15 (reception completed)
Multi-function serial interface
ch.7/ ch.15 (status)
160
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
26
1A
ICR10
394H
000FFF94H
10*1
27
1B
ICR11
390H
000FFF90H
11
28
1C
ICR12
38CH
000FFF8CH
12*1
29
1D
ICR13
388H
000FFF88H
13
30
1E
ICR14
384H
000FFF84H
14*1
31
1F
ICR15
380H
000FFF80H
15*9
32
20
ICR16
37CH
000FFF7CH
16*1
33
21
ICR17
378H
000FFF78H 17*10
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H
22*1
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Interrupt factor
16-bit free-run timer 0 ("0" detection) / (compare
clear)
Multi-function serial interface
ch.7/ ch.15 (transmission completed)
PPG0/1/10/11/20/21/30/31/40/41/50/51/60/61
16-bit free-run timer 1 ("0" detection) / (compare
clear)
PPG2/3/12/13/22/23/32/33/42/43/52/53/62/63
16-bit free-run timer 2 ("0" detection) / (compare
clear)
PPG4/5/14/15/24/25/34/35/44/45/54/55
PPG6/7/16/17/26/27/36/37/46/47/56/57
PPG8/9/18/19/28/29/38/39/48/49/58/59
Multi-function serial interface
ch.8/ ch.16 (reception completed)
Multi-function serial interface
ch.8/ ch.16 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8/ ch.16 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (Sub oscillation)
Multi-function serial interface
ch.9/ ch.17 (reception completed)
Multi-function serial interface
ch.9/ ch.17 (status)
A/D converter
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9/ ch.17 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit free-run timer 4/6/8/10
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit free-run timer 3/5/7/9
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching /measurement)
Multi-function serial interface
ch.10/ ch.18 (reception completed)
Multi-function serial interface
ch.10/ ch.18 (status)
32-bit ICU7 (fetching /measurement)
Multi-function serial interface
ch.10/ ch.18 (transmission completed)
32-bit ICU8 (fetching /measurement)
Multi-function serial interface
ch.11/ ch.19 (reception completed)
Multi-function serial interface
ch.11/ ch.19 (status)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24*3
41
29
ICR25
358H
000FFF58H
25*3
42
43
44
2A
2B
2C
ICR26
ICR27
ICR28
354H
350H
34CH
000FFF54H
000FFF50H
000FFF4CH
26*3
27*3
28*3
45
2D
ICR29
348H
000FFF48H
29*1
46
2E
ICR30
344H
000FFF44H
30
47
2F
ICR31
340H
000FFF40H
31*1
*4
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H
34*6
51
33
ICR35
330H
000FFF30H
35*6
52
34
ICR36
32CH
000FFF2CH
36*1
53
35
ICR37
328H
000FFF28H
37
54
36
ICR38
324H
000FFF24H
38*1
161
D a t a S h e e t
Interrupt factor
32-bit ICU9 (fetching /measurement)
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4/10 (fetching /measurement)
Multi-function serial interface
ch.11/ ch.19 (transmission completed)
32-bit ICU5/11 (fetching /measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
48/49/50/51/52/53/54/55/56/57/58/59/60/61/62/63
32-bit OCU6/7/10/11 (match)
32-bit OCU8/9/12/13 (match)
Base timer 0 IRQ0
Base timer 0 IRQ1
Base timer 1 IRQ0
Base timer 1 IRQ1
-
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H
310H
000FFF14H
000FFF10H
42
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45*5
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delayed interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS)
64
40
-
2FCH
000FFEFCH
-
System reserved
(Used for REALOS)
65
41
-
2F8H
000FFEF8H
-
Used with the INT instruction.
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
*:
*1:
*2:
*3:
*4:
*5:
*6:
*8:
*9:
*10:
It does not support the DMA transfer request by the interrupt generated from a peripheral to which no RN
(Resource Number) is assigned.
The status of the multi-function serial interface does not support the DMA transfer by the I 2C reception and
FlexRay.
The reload timer ch.4 to ch.7 does not support the DMA transfer by the interrupt.
The PPG ch.24 to ch.87 does not support the DMA transfer by the interrupt.
The clock calibration unit does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the interrupt because of the RAM ECC bit error.
The 32-bit free-run timer ch.3 to ch.10 does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the external low-voltage detection interrupt.
It does not support the DMA transfer by the FlexRay interrupt.
It does not support the DMA transfer by the FlexRay timer interrupt.
162
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 MB91F52xY (416pin)
Interrupt factor
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
8
9
0A
0B
0C
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of illegal instruction
NMI request
Error generation at internal bus diagnosis
XBS RAM double-bit error detection
Backup RAM double-bit error detection
AHB RAM double-bit error detection
TPU violation
14
0E
-
3C4H
000FFFC4H
-
15
0F
15(FH)
3C0H
Fixed
000FFFC0H
-
External interrupt 0-7
16
10
ICR00 3BCH 000FFFBCH
0
External interrupt 8-15
External low-voltage detection interrupt
External interrupt 16-23
17
11
ICR01
3B8H 000FFFB8H
1*8
Reload timer 0/1/4/5
18
12
ICR02
3B4H 000FFFB4H
2*2
Reload timer 2/3/6/7
Multi-function serial interface
ch.0 (reception completed)
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
Multi-function serial interface
ch.1 (reception completed)
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
Multi-function serial interface
ch.2 (reception completed)
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
19
13
ICR03
3B0H 000FFFB0H
3*2
20
14
ICR04 3ACH 000FFFACH
4*1
21
15
ICR05 3A8H 000FFFA8H
5*1
22
16
ICR06 3A4H 000FFFA4H
6*1
23
17
ICR07 3A0H 000FFFA0H
7*1
24
18
ICR08
39CH
000FFF9CH
8*1
25
19
ICR09
398H
000FFF98H
9*1
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
163
D a t a S h e e t
Interrupt factor
Multi-function serial interface
ch.3 (reception completed)
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
ch.3 (transmission completed)
Multi-function serial interface
ch.4/ ch.12 (reception completed)
Multi-function serial interface
ch.4/ ch.12 (status)
Multi-function serial interface
ch.4/ ch.12 (transmission completed)
Multi-function serial interface
ch.5/ ch.13 (reception completed)
Multi-function serial interface
ch.5/ ch.13 (status)
Multi-function serial interface
ch.5/ ch.13 (transmission completed)
FlexRay0
Multi-function serial interface
ch.6/ ch.14 (reception completed)
Multi-function serial interface
ch.6/ ch.14 (status)
FlexRay1
Multi-function serial interface
ch.6/ ch.14 (transmission completed)
FlexRay timer 0
CAN0
CAN3
FlexRay timer 1
CAN1
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization completed
Error generation at Backup RAM diagnosis
AHB RAM diagnosis completed
AHB RAM initialization completed
Error generation at AHB RAM diagnosis
CAN4
CAN2
Up/down counter 0/2
Up/down counter 1/3
CAN5
FlexRay PLL gear/FlexRay PLL alarm
Real time clock
Multi-function serial interface
ch.7/ ch.15 (reception completed)
Multi-function serial interface
ch.7/ ch.15 (status)
164
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
26
1A
ICR10
394H
000FFF94H
10*1
27
1B
ICR11
390H
000FFF90H
11
28
1C
ICR12
38CH
000FFF8CH 12*1
29
1D
ICR13
388H
000FFF88H
13
30
1E
ICR14
384H
000FFF84H
14*1
31
1F
ICR15
380H
000FFF80H
15*9
32
20
ICR16
37CH
000FFF7CH 16*1
33
21
ICR17
378H
000FFF78H 17*10
34
22
ICR18
374H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H
22*1
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Interrupt factor
16-bit free-run timer 0 ("0" detection) / (compare clear)
Multi-function serial interface
ch.7/ ch.15 (transmission completed)
PPG
0/1/10/11/20/21/30/31/40/41/50/51/60/61/70/71/80/81
16-bit free-run timer 1 ("0" detection) / (compare clear)
PPG
2/3/12/13/22/23/32/33/42/43/52/53/62/63/72/73/82/83
16-bit free-run timer 2 ("0" detection) / (compare clear)
PPG
4/5/14/15/24/25/34/35/44/45/54/55/64/65/74/75/84/85
PPG
6/7/16/17/26/27/36/37/46/47/56/57/66/67/76/77/86/87
PPG
8/9/18/19/28/29/38/39/48/49/58/59/68/69/78/79
Multi-function serial interface
ch.8/ ch.16 (reception completed)
Multi-function serial interface
ch.8/ ch.16 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
Sub timer
PLL timer
Multi-function serial interface
ch.8/ ch.16 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (Sub oscillation)
Multi-function serial interface
ch.9/ ch.17 (reception completed)
Multi-function serial interface
ch.9/ ch.17 (status)
A/D converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
Clock calibration unit (CR oscillation)
Multi-function serial interface
ch.9/ ch.17 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit free-run timer 4/6/8/10
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit free-run timer 3/5/7/9
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching /measurement)
Multi-function serial interface
ch.10/ ch.18 (reception completed)
Multi-function serial interface
ch.10/ ch.18 (status)
32-bit ICU7 (fetching /measurement)
Multi-function serial interface
ch.10/ ch.18 (transmission completed)
32-bit ICU8 (fetching /measurement)
Multi-function serial interface
ch.11/ ch.19 (reception completed)
Multi-function serial interface
ch.11/ ch.19 (status)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
23
*
39
27
ICR23
360H
000FFF60H
40
28
ICR24
35CH
000FFF5CH 24*3
41
29
ICR25
358H
000FFF58H
25*3
42
2A
ICR26
354H
000FFF54H
26*3
43
2B
ICR27
350H
000FFF50H
27*3
44
2C
ICR28
34CH
000FFF4CH 28*3
45
2D
ICR29
348H
000FFF48H
29*1
46
2E
ICR30
344H
000FFF44H
30
47
2F
ICR31
340H
000FFF40H
31*1
*4
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33
50
32
ICR34
334H
000FFF34H
34*6
51
33
ICR35
330H
000FFF30H
35*6
52
34
ICR36
32CH
000FFF2CH 36*1
53
35
ICR37
328H
000FFF28H
37
54
36
ICR38
324H
000FFF24H
38*1
165
D a t a S h e e t
Interrupt factor
32-bit ICU9 (fetching /measurement)
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4/10 (fetching /measurement)
Multi-function serial interface
ch.11/ ch.19 (transmission completed)
32-bit ICU5/11 (fetching /measurement)
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
48/49/50/51/52/53/54/55/56/57/58/59/60/61/62/63
32-bit OCU6/7/10/11 (match)
32-bit OCU8/9/12/13 (match)
Base timer 0 IRQ0
Base timer 0 IRQ1
Base timer 1 IRQ0
Base timer 1 IRQ1
-
Interrupt
number
HexaDecimal
decimal
Interrupt
level
Offset
Default
address for
TBR
RN
*
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
59
3A
3B
ICR42
ICR43
314H
310H
000FFF14H
000FFF10H
42
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45*5
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delayed interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS)
64
40
-
2FCH 000FFEFCH
-
System reserved
(Used for REALOS)
65
41
-
2F8H
000FFEF8H
-
Used with the INT instruction.
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
*:
*1:
*2:
*3:
*4:
*5:
*6:
*8:
*9:
*10:
It does not support the DMA transfer request by the interrupt generated from a peripheral to which no RN
(Resource Number) is assigned.
The status of the multi-function serial interface does not support the DMA transfer by the I 2C reception and
FlexRay.
The reload timer ch.4 to ch.7 does not support the DMA transfer by the interrupt.
The PPG ch.24 to ch.87 does not support the DMA transfer by the interrupt.
The clock calibration unit does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the interrupt because of the RAM ECC bit error.
The 32-bit free-run timer ch.3 to ch.10 does not support the DMA transfer by the interrupt.
It does not support the DMA transfer by the external low-voltage detection interrupt.
It does not support the DMA transfer by the FlexRay interrupt.
It does not support the DMA transfer by the FlexRay timer interrupt.
166
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Min
Max
Unit
Power supply voltage *1,*2
VCC
VCCE
VSS-0.3
VSS-0.3
VSS+6.0
VCC
V
V
Analog power supply voltage *1,*2
AVCC
VSS-0.3
VSS+6.0
V
Analog reference voltage *1
AVRH
VSS-0.3
VSS-0.3
VSS+6.0
VCC+0.3
V
VSS-0.3
VCCE+0.3
VSS-0.3
VCC+0.3
V
VSS-0.3
VCCE+0.3
V
VSS-0.3
-
VCC+0.3
4.0
20
15
30
4
12
100
120
-15
-30
-4
-12
-100
-120
990
990
780
755
+105
+125
+150
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
°C
°C
°C
Input voltage *1
VI
Analog pin input voltage *1
Output voltage *1
Maximum clamp current
Total maximum clamp current
"L" level maximum output current *3
"L" level average output current *4
"L" level total output current *5
"H" level maximum output current*3
"H" level average output current*4
"H" level total output current *5
VIA5
Vo
ICLAMP
Σ|ICLAMP|
IOL1
IOL2
IOLAV1
IOLAV2
ΣIOL1
ΣIOL2
IOH1
IOH2
IOHAV1
IOHAV2
ΣIOH1
ΣIOH2
TA: -40°C to +105°C
Power
consumption
TA: -40°C to +125°C
PD
V
Remarks
AVRH ≤ AVCC ≤
VCC
AVRH ≤ AVCC
When VCCE pin
is a power supply
*9
When VCCE pin
is a power supply
*9
*6
*6
*8
*8, *10
*8, *12
*8, *11
-40
-40
*7
Storage temperature
Tstg
-55
*1: These parameters are based on the condition that VSS=AVSS=0.0V
*2: Caution must be taken that AVCC, AVRH and VCCE do not exceed VCC upon power-on and under other
circumstances.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
Operating temperature
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
TA
167
D a t a S h e e t
*6: · Corresponding pins: all general-purpose ports except P035, 041, 093, 122, P222, P227, P232 and P236.
· Use within recommended operating conditions.
· Use at DC voltage (current).
· The + B signal should always be applied by connecting a limiting resistor between the + B signal and the
microcontroller.
· The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.
· Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+ B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other
devices.
· Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is
supplied through the pin, the microcontroller may operate incompletely.
· Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on
reset may not function in the power supply voltage.
· Do not leave + B input pins open.
*7: When it is used under this condition, contact your sales representative.
*8: It is a standard when four-layer substrate is used.
*9: Please see to the item of "Product lineup" for details.
*10: It is a condition that can be used by limiting the product type of TEQFP and BGA.
*11: It is a condition that can be used by the package limitation of FPT-144P-M08 and FPT-176P-M07.
*12: It is a condition that can be used by limiting the package of FPT-208P-M06.
Sample recommended circuit
MB91520 series
Protective diode
Limiting resistor current
+B input (12 to 16V)
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
168
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
2. Recommended operating conditions
(VSS=AVSS=0.0V)
Parameter
Power supply voltage
Smoothing capacitor *2
Symbol
VCC
VCCE
AVCC
Value
Unit
Min
Max
4.5
5.5
V
3.0
3.6
V
2.7
5.5
V
4.7
(tolerance within ±50%)
CS
µF
Remarks
Recommended operation guarantee
range (When 5.0V is used)
Recommended operation guarantee
range (When 3.3V is used)
Operation guarantee range*1
Use a ceramic capacitor or a
capacitor that has the similar
frequency characteristics. Use a
capacitor with a capacitance
greater than CS as the smoothing
capacitor on the VCC pin.
-40
+105
°C
-40
+125
°C
*3
*1: When it is used outside recommended operation guarantee range (range of the operation guarantee),contact
your sales representative. Moreover, minimum value with an effective external low-voltage detection reset
becomes a voltage until generating low-voltage detection reset.
*2: See the following diagram for details on the connection of smoothing capacitor CS.
*3: When it is used under this condition, contact your sales representative.
Operating temperature
TA
 C Pin Connection Diagram
C
CS
VSS
VSS
AVSS
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under
any conditions other than these conditions may adversely affect reliability of device and could result in
device failure. No warranty is made with respect to any use, operating conditions or combinations not
represented on this data sheet. If you are considering application under any conditions other than listed
herein, please contact sales representatives beforehand.
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
169
D a t a S h e e t
3. DC characteristics
(TA: -40°C to +105°C, VCC= AVcc=5.0V±10%/ VCC= AVcc=3.3V±0.3V ,VSS=AVSS=0.0V)
Para
meter
Symb
ol
Pin
name
Conditions
VCC
Operating frequency
FCP=128MHz, Fcpp=32MHz, *3
at normal operation
Operating frequency
FCP=128MHz, Fcpp=32MHz, *3
at Flash write *2
Operating frequency
FCP=128MHz, Fcpp=32MHz, *3
at Flash erase *2
Operating frequency FCP=80MHz,
Fcpp=40MHz,
at normal operation
Operating frequency FCP=80MHz,
Fcpp=40MHz,
at Flash write *2
Operating frequency FCP=80MHz,
Fcpp=40MHz,
at Flash erase *2
Operating frequency FCP=64MHz,
Fcpp=32MHz,
at normal operation
Operating frequency FCP=64MHz,
Fcpp=32MHz,
at Flash write *2
Operating frequency FCP=64MHz,
Fcpp=32MHz,
at Flash erase *2
Operating frequency FCP=48MHz,
Fcpp=24MHz,
at normal operation
Operating frequency FCP=48MHz,
Fcpp=24MHz,
at Flash write *2
Operating frequency FCP=48MHz,
Fcpp=24MHz,
at Flash erase *2
Operating frequency FCP=80MHz,
Fcpp=40MHz, at CPU sleep mode
Operating frequency FCP=80MHz,
Fcpp=40MHz, at bus sleep mode
When using crystal
4MHz TA=+25°C*1
When using built-in
Watch
CR clock 50kHz
mode
TA=+25°C*1
When using sub
clock 32kHz
TA=+25°C*1
Stop mode
TA=+25°C*1
ICC5
Power
supply
current
ICCS5
ICCBS5
ICCT5
ICCH5
170
CONFIDENTIAL
Min
Value
Typ Max
Unit
-
85
122
mA
-
95
135
mA
-
95
135
mA
-
80
117
mA
-
90
130
mA
-
90
130
mA
-
73
110
mA
-
83
123
mA
-
83
123
mA
-
53
100
mA
-
63
113
mA
-
63
113
mA
-
57
94
mA
-
39
79
mA
-
2000
3600
-
640
2440
-
660
2460
-
640
2440
Remarks
µA
µA
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Para
meter
Symb
ol
Pin
name
ICCT52
Power
supply
current
VCC
ICCH52
Conditions
Watch
mode
(power
off)
Stop mode
(power
off)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Min
When using crystal
4MHz TA=+25°C*1
When using built-in
CR clock 50kHz ,
TA=+25°C*1
When using sub
clock 32kHz
TA=+25°C*1
*1
TA=+25°C
Value
Typ Max
-
1400
1600
-
63
203
-
80
220
-
60
200
Unit
Remarks
µA
LVD/
RTC
operation,
Backup
RAM
16KB
retention
µA
Backup
RAM
16KB
retention
171
D a t a S h e e t
(TA: -40°C to +125°C, VCC= AVcc=5.5V±10%/ VCC= AVcc=3.3V±0.3V ,VSS=AVSS=0.0V)
Para
meter
Symb
ol
Pin
name
Conditions
VCC
Operating frequency
FCP=128MHz, Fcpp=32MHz, *3
at normal operation
Operating frequency
FCP=128MHz, Fcpp=32MHz, *3
at Flash write *2
Operating frequency
FCP=128MHz, Fcpp=32MHz, *3
at Flash erase *2
Operating frequency FCP=80MHz,
Fcpp=40MHz,
at normal operation
Operating frequency FCP=80MHz,
Fcpp=40MHz,
at Flash write *2
Operating frequency FCP=80MHz,
Fcpp=40MHz,
at Flash erase *2
Operating frequency FCP=64MHz,
Fcpp=32MHz,
at normal operation
Operating frequency FCP=64MHz,
Fcpp=32MHz,
at Flash write *2
Operating frequency FCP=64MHz,
Fcpp=32MHz,
at Flash erase *2
Operating frequency FCP=48MHz,
Fcpp=24MHz,
at normal operation
Operating frequency FCP=48MHz,
Fcpp=24MHz,
at Flash write *2
Operating frequency FCP=48MHz,
Fcpp=24MHz,
at Flash erase *2
Operating frequency FCP=80MHz,
Fcpp=40MHz, at CPU sleep mode
Operating frequency FCP=80MHz,
Fcpp=40MHz, at bus sleep mode
When using crystal
4MHz TA=+25°C*1
When using built-in
Watch
CR clock 50kHz
mode
TA=+25°C*1
When using sub
clock 32kHz
TA=+25°C*1
Stop mode
TA=+25°C*1
ICC5
Power
supply
current
ICCS5
ICCBS5
ICCT5
ICCH5
172
CONFIDENTIAL
Min
Value
Typ Max
Unit
-
85
122
mA
-
95
135
mA
-
95
135
mA
-
80
117
mA
-
90
130
mA
-
90
130
mA
-
73
110
mA
-
83
123
mA
-
83
123
mA
-
53
100
mA
-
63
113
mA
-
63
113
mA
-
57
94
mA
-
39
79
mA
-
2000
3600
-
640
2440
-
660
2460
-
640
2440
Remarks
µA
µA
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Para
meter
Symb
ol
Pin
name
ICCT52
Power
supply
current
VCC
ICCH52
Conditions
Watch
mode
(power
off)
Stop mode
(power
off)
Min
When using crystal
4MHz TA=+25°C*1
When using built-in
CR clock 50kHz ,
TA=+25°C*1
When using sub
clock 32kHz
TA=+25°C*1
*1
TA=+25°C
Value
Typ Max
-
1400
1600
-
63
203
-
80
220
-
60
200
Unit
Remarks
µA
LVD/
RTC
operation,
Backup
RAM
16KB
retention
µA
Backup
RAM
16KB
retention
*1: It is a standard in BRAMSC (Backup RAM sleep control bit)=1(Enter the state of the sleep at the standby mode)
condition.
*2: It is a prohibition two flash or more writing/erasing the flash and the WorkFlash for the internally stored program at the
same time.
*3: There is a frequency limitation by the product type. Please see "4. AC Characteristics" for details.
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
173
D a t a S h e e t
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/Vcc=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Input leak
current
Input
capacitance 1
Symbol
Pin name
Min
Typ
Max
Unit
All input pins
VCC=AVCC=5.5V
VSS<VI<VCC
-5
-
5
µA
CIN1
Other than
VCC,VCCE,
VSS, AVCC,
AVSS, C
-
-
5
15
pF
RUP1
RSTX, NMIX
RUP2
P073,074,077
25
45
25
33
25
-
100
140
60
90
100
RUP3
Port pin other
than
P035,041,073,
074,077,093,
122,222,227,
232,236
VCC=5.0V±10%
Vcc=3.3V±0.3V
VCC=5.0V±10%
Vcc=3.3V±0.3V
VCC=5.0V±10%
Vcc=3.3V±0.3V
45
-
140
VCC
-0.5
-
Normal output
pin
VOH1
“H” level
output
voltage*1
P076,200,201,
204,205,210,
211,214,215,
220,221,225,
226,230,231,
234,235
P073,074,077
VOH2
VOH3
CONFIDENTIAL
Value
IIL
Pull-up
resistance
174
Conditions
Vcc=4.5V
IOH=-4.0mA
Vcc=3.0V
IOH=-2.0mA
Vcc=4.5V
IOH=-4.0mA
Vcc=3.0V
IOH=-2.0mA
Vcc=4.5V
IOH=-3.0mA
VCC
-0.5
VCC
-0.5
-
-
VCC
Remarks
kΩ
kΩ
kΩ
V
VCC
V
When I2C
function is
non-select
ed
VCC
V
I2C pin
output
When I2C
function is
non-select
ed
P076,200,201,
204,205,210,
211,214,215,
220,221,225,
226,230,231,
234,235
Vcc=4.5V
IOH=-3.0mA
VCC
-0.5
-
VCC
V
P103 to 106
Vcc=4.5V
IOH=-12.0mA
Vcc=3.0V
IOH=-8.0mA
VCC
-0.5
-
VCC
V
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Parameter
Symbol
Pin name
Normal output
pin
VOL1
“L” level
output voltage
P076,200,201,
204,205,210,
211,214,215,
220,221,225,
226,230,231,
234,235
P073,074,077
Vcc=4.5V
IOL=4.0mA
Vcc=3.0V
IOL=2.0mA
Vcc=4.5V
IOL=4.0mA
Vcc=3.0V
IOL=2.0mA
Vcc=4.5V
IOL=3.0mA
Value
Min
Typ
Max
0
-
0.4
Unit
0
-
0.4
V
When I2C
function is
non-select
ed
0
-
0.4
V
I2C pin
output
When I2C
function is
non-select
ed
Vcc=4.5V
IOH=-3.0mA
0
-
0.4
V
VOL3
P103 to 106
Vcc=4.5V
IOL=12.0mA
Vcc=3.0V
IOL=8.0mA
0
-
0.4
V
VIH1
P000,002,003,
005,020,022,
024,026,035,
041,045,055,
057,071-077,
081,082,093,
096,097,
100-102,
111,115,116,
122,126,130,
134,150,151,
153,200-202,
204-206,210-2
12,214-216,22
0-222,225-227
,230-232,234236,TCK,TDI,
TMS,TRST
CMOS
hysteresis input
level
0.7×
VCC
-
VCC
V
0.7×
VCC
-
VCC
V
-
VCC
V
-
VCC
V
0.8×
VCC
-
VCC
V
2
-
VCC
V
“H” level
input voltage*1
VIH2
VIH3
P001,004,006,
007,010-017,
052,114,120,
123,155
VIH4
Port other than
VIH1,VIH2,VIH3
VIH5
RSTX,NMIX,
MD0,MD1
VIHT
DEBUGIF
March 28, 2014, MB91F528_DS705-00016-1v0-E
CMOS
hysteresis input
level
Automotive
input level
Automotive
input level
CMOS
hysteresis input
level
TTL input level
Remarks
V
P076,200,201,
204,205,210,
211,214,215,
220,221,225,
226,230,231,
234,235
VOL2
CONFIDENTIAL
Conditions
0.8×
VCC
0.8×
VCC
175
D a t a S h e e t
Parameter
Symbol
Pin name
Conditions
VIL1
P000,002,003,
005,020,022,
024,026,035,
041,045,055,
057,071-077,
081,082,093,
096,097,
100-102,111,
115,116,122,
126,130,134,
150,151,153,
200-202,204-2
06,210-212,21
4-216,220-222
,225-227,230232,234-236,
TCK,TDI,TM
S,TRST
CMOS
hysteresis input
level
“L” level
input voltage*1
VIL2
VIL3
P001,004,006,
007,010-017,
052,114,120,
123,155
VIL4
Port other than
VIH1,VIH2,VIH3
VIL5
RSTX,NMIX,
MD0,MD1
VILT
DEBUGIF
CMOS
hysteresis input
level
Automotive
input level
Automotive
input level
CMOS
hysteresis input
level
TTL input level
Value
Unit
Min
Typ
Max
Vss
-
0.3×
VCC
V
Vss
-
0.3×
VCC
V
Vss
-
Vss
-
Vss
-
0.2×
VCC
V
Vss
-
0.8
V
0.5×
VCC
0.5×
VCC
Remarks
V
V
*1: It is provided by VCCE for the pin corresponding to the VCCE power supply instead of VCC. Please see "PRODUCT
LINEUP" for details.
176
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
4. AC Characteristics
(1) Main Clock Timing
(TA: -40°C to +125°C,VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS =AVSS=0.0V)
Parameter
Source oscillation
clock frequency
Source oscillation
clock cycle time
Sym
bol
Pin
name
FC
tCYL
Con
ditio
ns
Value
Unit
Min
Typ
Max
X0, X1
-
4
16
MHz
X0, X1
62.5
250
-
ns
FCP
2
128
FCPP
1
40
Internal operating
clock frequency*1
-
1
-
40
MHz
FCPT
-
tCP
tCPP
Internal operating
clock cycle time*1
-
1
32
7.82
500
25
1000
25
-
1000
ns
tCPT
31.25
CAN PLL jitter
(during lock)
tPJ
-
-10
1000
-
10
ns
Remarks
CPU clock *3
Peripheral bus
clock
External bus clock
(When VCC=5.0V is
used) *2
External bus clock
(When VCC=3.3V is
used)
CPU clock *4
Peripheral bus
clock
External bus clock
(When VCC=5.0V is
used)
External bus clock
(When VCC=3.3V is
used)
FCP=80MHz
(4MHzMultiplied
by 20)
Built-in CR
FCCR
50
100
150
kHz
oscillation frequency
*1: The maximum / minimum value is defined when using the main clock and PLL clock.
*2: Please use it with external load capacity 12pF or less for VCC=3.3V±0.3V (40MHz operation).
*3: MB91F52xR/MB91F52xU(LQFP) is 80MHz or less.
MB91F52xR/MB91F52xU(TEQFP) and MB91F52xM/MB91F52xY is 128MHz or less.
*4: MB91F52xR/MB91F52xU(LQFP) is 12.5ns or more.
MB91f52xR/MB91F52xU(TEDFP) and MB91F52xM/MB91F52xY is 7.82ns or more.
 X0,X1 clock timing
tCYL
X0
March 28, 2014, MB91F528_DS705-00016-1v0-E
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177
D a t a S h e e t
 CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
178
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D a t a S h e e t
(1-2) Sub clock timing
(TA: -40°C to +125°C,VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Source oscillation clock
frequency
Source oscillation clock
cycle time
Sym
bol
Pin
name
FCL
X0A, X1A
Con
ditio
ns
Value
Unit
Min
Typ
Max
-
32.768
-
kHz
-
30.52
-
µs
Remarks
tLCYL
X0A, X1A
 X0A,X1A clock timing
tLCYL
X0A
March 28, 2014, MB91F528_DS705-00016-1v0-E
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179
D a t a S h e e t
 Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
MB91F52xrecommended guaranteed
operation range
MB91F52x guaranteed operation
range
Power supply voltage V CC (V)
5.5
4.5
3.6
3.0
2.7
PLL guaranteed operation
range
2
4
80(MB91F52xR/MB91F52xU(LQFP))
128(MB91F52xR/MB91F52xU(TEQFP),
MB91F52xM/MB91F52xY)
Internal operation clock frequency FCP (MHz)
Note: The power supply voltage, which is the low-voltage detection setting voltage or lower, is in the
reset state.
Oscillation clock frequency vs. Internal operation clock frequency
Internal operation clock frequency
PLL clock
Main
Multipli Multipli
Multipli Multipli Multipli Multipli
Clock
...
ed by ed by
ed by 1 ed by 2 ed by 3 ed by 4
31
32
Oscillation
clock
frequency
4MHz
2MHz
4MHz
8MHz
12MHz
16MHz
...
124MHz 128MHz
 Example of oscillation circuit
X0
4MHz
C1=10pF
X1
R=0Ω
C2=10pF
Note: As to the product with its clock supervisor’s initial value is “ON”, when the oscillator is unable
to start within 20ms from the stop state the clock supervisor will detect the oscillation stop. As
a result, the CPU moves to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20ms.
Moreover, it is recommended to be designed after the match evaluation of the circuit is
requested to the departure pendulum maker when the oscillation circuit is composed.
180
CONFIDENTIAL
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D a t a S h e e t
AC characteristics are specified by the following measurement reference voltage values.
 Input Signal Waveform
Hysteresis Input Pin (Automotive)
 Output Signal Waveform
Output Pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis Input Pin (CMOS schmitt)
0.7Vcc
0.3Vcc
March 28, 2014, MB91F528_DS705-00016-1v0-E
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181
D a t a S h e e t
(2) Reset Input
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Con
Sym Pin
ditio
bol name
ns
Parameter
Reset input time
tRSTL
RSTX
–
Value
Unit
Remarks
Min
Max
10
–
µs
When normal
operation
Oscillation time of oscillator*
+100
100
–
µs
At Stop mode
–
µs At Watch mode
Width for reset
1
–
µs
input removal
*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred μs and several ms, and for an external clock, the time is 0 ms.
tRSTL
RSTX
0.2 vcc
 At Stop mode
0.2 vcc
tRSTL
RSTX
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 μs
Oscillation time
of oscillator
Internal reset
182
CONFIDENTIAL
Oscillation stabilization
waiting time
Instruction
execution
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
(3) Power-on Conditions
(TA: -40°C to +125°C , VSS=0.0V)
Parameter
Symbol
Pin
name
Conditions
Level detection
voltage
Level detection
hysteresis width
Level detection time
–
VCC
–
Slope detection
undetected standard
Power off time
Value
Unit
Min
Typ Max
–
2.024
2.2
2.376
V
VCC
–
–
100
–
mV
–
–
–
–
30
µs
–
VCC
–
–
4
tOFF
VCC
–
VCC = at level
detection release
level time
–
50
–
–
Remarks
*1
mV/µs *2
ms
*3
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope
detection. This is the standard when the power supply fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.
March 28, 2014, MB91F528_DS705-00016-1v0-E
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183
D a t a S h e e t
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR : MD0=0, SMR: SCINV=0, SCR:SPI=0
(TA: -40°C to +125°C , VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Serial clock cycle
time
SCK ↓ →
SOT delay time
Valid SIN →
SCK ↑ setup time
Symbol
Pin name
tSCYC
SCK0 to SCK19
tSLOVI
tIVSHI
SCK ↑ →
Valid SIN hold time
tSHIXI
Serial clock
"H"pulse width
tSHSL
Serial clock
"L" pulse width
tSLSH
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
SCK0 to SCK2,
SCK5 to SCK19
SIN0 to SIN2,
SIN5 to SIN19
SCK3, SCK4
SIN3, SIN4
Cond
itions
Value
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
33
ns
-
300
ns
10
-
ns
20
-
ns
-
SCK0 to SCK19
SIN0 to SIN19
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK19
SCK ↓ →
SOT delay time
tSLOVE
Valid SIN →
SCK ↑ setup time
tIVSHE
SCK ↑ →
Valid SIN hold time
tSHIXE
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
-
External shift clock
mode output pin:
CL=50pF
SCK0 to SCK19
SIN0 to SIN19
SCK fall time
tF
SCK0 to SCK19
-
5
ns
SCK rise time
tR
SCK0 to SCK19
-
5
ns
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters. Please use
ch.3 and ch.4 with maximum baud rate 400kbps or less.
See Hardware Manual for details.
184
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MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
0.8V
0.8V
tSLOVI
2.4V
SOTx
0.8V
tIVSHI
SINx
tSHIXI
VIH1
VIH1
VIL1
VIL1
 External shift clock mode
tSLSH
SCKx
tSHSL
VIH1
VIH1
VIL1
tF
VIL1
tSLOVE
SOTx
tR
2.4V
0.8V
tIVSHE
SINx
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
tSHIXE
VIH1
VIH1
VIL1
VIL1
185
D a t a S h e e t
(4-1-2) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR : MD0=0, SMR: SCINV=1, SCR:SPI=0
(TA: -40°C to +125°C , VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Serial clock cycle
time
SCK ↑ →
SOT delay time
Valid SIN →
SCK ↓ setup time
Symbol
Pin name
tSCYC
SCK0 to SCK19
tSHOVI
tIVSLI
SCK ↓ →
Valid SIN hold time
tSLIXI
Serial clock
"H"pulse width
tSHSL
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
SCK0 to SCK2,
SCK5 to SCK19
SIN0 to SIN2,
SIN5 to SIN19
SCK3, SCK4
SIN3, SIN4
Cond
itions
Value
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
33
ns
-
300
ns
10
-
ns
20
-
ns
-
SCK0 to SCK19
SIN0 to SIN19
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK19
Serial clock
"L" pulse width
SCK ↑ →
SOT delay time
tSLSH
tSHOVE
Valid SIN →
SCK ↓ setup time
tIVSLE
SCK ↓ →
Valid SIN hold time
tSLIXE
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
-
External shift clock
mode output pin:
CL=50pF
SCK0 to SCK19
SIN0 to SIN19
SCK fall time
tF
SCK0 to SCK19
-
5
ns
SCK rise time
tR
SCK0 to SCK19
-
5
ns
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters. Please use
ch.3 and ch.4 with maximum baud rate 400kbps or less.
See Hardware Manual for details.
186
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D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSHOVI
2.4V
SOTx
0.8V
tIVSLI
SINx
tSLIXI
VIH1
VIH1
VIL1
VIL1
 External shift clock mode
tSHSL
SCKx
tSLSH
VIH1
VIH1
VIL1
tR
VIL1
tSHOVE
SOTx
tF
2.4V
0.8V
tIVSLE
SINx
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
tSLIXE
VIH1
VIH1
VIL1
VIL1
187
D a t a S h e e t
(4-1-3) Bit setting: SMR : MD2=0, SMR:MD1=1, SMR : MD0=0, SMR:SCINV=0, SCR:SPI=1
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Serial clock cycle time
tSCYC
SCK0 to SCK19
SCK ↑ →
SOT delay time
Valid SIN →
SCK ↓ setup time
tSHOVI
tIVSLI
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
SCK0 to SCK2,
SCK5 to SCK19
SIN0 to SIN2,
SIN5 to SIN19
SCK3, SCK4
SIN3, SIN4
Con
ditio
ns
Value
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
SCK ↓ →
Valid SIN hold time
tSLIXI
SCK0 to SCK19
SIN0 to SIN19
0
-
ns
SOT→SCK↓
delay time
tSOVLI
SCK0 to SCK19
SOT0 to SOT19
2tCPP-30
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
2tCPP-10
-
ns
-
33
ns
-
300
ns
10
-
ns
20
-
ns
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK19
Serial clock
"L" pulse width
SCK ↑ →
SOT delay time
tSLSH
tSHOVE
Valid SIN →
SCK ↓ setup time
tIVSHE
SCK ↓ →
Valid SIN hold time
tSLIXE
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
-
External shift clock
mode output pin:
CL=50pF
SCK0 to SCK19
SIN0 to SIN19
SCK fall time
tF
SCK0 to SCK19
-
5
ns
SCK rise time
tR
SCK0 to SCK19
-
5
ns
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters. Please use
ch.3 and ch.4 with maximum baud rate 400kbps or less.
See Hardware Manual for details.
188
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D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
tSHOVI
0.8V
0.8V
tSOVLI
SOTx
2.4V
2.4V
0.8V
0.8V
tIVSLI
SINx
tSLIXI
VIH
VIH
VIL
VIL
 External shift clock mode
tSLSH
VIH
SCKx
VIH
VIL
VIL
tR
tSHOVE
2.4V
2.4V
0.8V
0.8V
IVSLE
ttIVSHE
SINx
VIH
VIL
tF
*
SOTx
tSHSL
tSLIXE
VIH
VIH
VIL
VIL
*: It writes in the TDR register and, then, it changes.
March 28, 2014, MB91F528_DS705-00016-1v0-E
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189
D a t a S h e e t
(4-1-4) Bit setting: SMR : MD2=0, SMR:MD1=1, SMR : MD0=0, SMR:SCINV=1, SCR:SPI=1
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Serial clock cycle time
tSCYC
SCK0 to SCK19
SCK↓→
SOT delay time
Valid SIN →
SCK↑setup time
tSLOVI
tIVSHI
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
SCK0 to SCK2,
SCK5 to SCK19
SIN0 to SIN2,
SIN5 to SIN19
SCK3, SCK4
SIN3, SIN4
Con
ditio
ns
Value
Unit
Min
Max
4tCPP
-
ns
-30
30
ns
-300
300
ns
34
-
ns
300
-
ns
SCK↑→
Valid SIN hold time
tSHIXI
SCK0 to SCK19
SIN0 to SIN19
0
-
ns
SOT→SCK↑
delay time
tSOVHI
SCK0 to SCK19
SOT0 to SOT19
2tCPP-30
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
2tCPP-10
-
ns
-
33
ns
-
300
ns
10
-
ns
20
-
ns
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK19
Serial clock
"L" pulse width
SCK↓→
SOT delay time
tSLSH
tSLOVE
Valid SIN →
SCK↑setup time
tIVSHE
SCK↑→
Valid SIN hold time
tSHIXE
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
SCK3, SCK4
SOT3, SOT4
-
External shift clock
mode output pin:
CL=50pF
SCK0 to SCK19
SIN0 to SIN19
SCK fall time
tF
SCK0 to SCK19
-
5
ns
SCK rise time
tR
SCK0 to SCK19
-
5
ns
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters. Please use
ch.3 and ch.4 with maximum baud rate 400kbps or less.
See Hardware Manual for details.
190
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSOVHI
SOTx
tSLOVI
2.4V
2.4V
0.8V
0.8V
tIVSHI
SINx
tSHIXI
VIH
VIH
VIL
VIL
 External shift clock mode
tSHSL
tSLSH
tR
VIH
SCKx
VIH
VIL
VIL
tSLOVE
2.4V
2.4V
0.8V
0.8V
tIVSHE
SINx
VIH
VIL
*
SOTx
tF
tF
tSHIXE
VIH
VIH
VIL
VIL
*: It writes in the TDR register and, then, it changes.
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
191
D a t a S h e e t
(4-1-5) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "H" : SMR,SCSFR:SCINV=0,
Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL=1
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
SCS↓→SCK↓
setup time
Sym
bol
tCSSI
Pin name
Con
ditio
ns
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCK↑→SCS↑
hold time
tCSHI
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
-
SCS
deselect time
tCSDI
SCS↓→SCK↓
setup time
tCSSE
SCK↑→SCS↑
hold time
tCSHE
SCS
deselect time
192
CONFIDENTIAL
tCSDE
Min
Max
tCSSU-50
tCSSU+0
*1
*1
tCSSU-50
tCSSU+300
*1
*1
tCSHD-10
*2
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK1 to SCK15,
SCK18, SCK19
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
Value
tCSHD+50
*2
tCSHD-300
tCSHD+50
*2
*2
Unit
ns
ns
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
-
ns
+0
-
3tCPP+30
Internal shift
clock mode
output pin :
CL=50pF
ns
tCSDS-50
3tCPP+30
Remarks
External shift
clock mode
output pin:
CL=50pF
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Parameter
SCS↓→SOT
delay time
Sym
bol
tDSE
Pin name
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SOT1, SOT2,
SOT5 to SOT15,
SOT18, SOT19
SCS3,
SCS40 to SCS43
SOT3, SOT4
SCS↑→SOT
delay time
SCK↓→SCS↓
clock switch time
tDEE
tSCC
Con
ditio
ns
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SOT1 to SOT15,
SOT18, SOT19
SCK1,SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
-
Value
Min
Max
-
40
Unit
ns
-
300
ns
+0
-
ns
3tCPP-10
3tCPP+50
Remarks
ns
-
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
Round operation
output pin:
CL=50pF
3tCPP-300
3tCPP+50
ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again.
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
193
D a t a S h e e t
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
Internal shift clock mode
SCS input
tCSDE
tCSHE
tCSSE
SCK input
SOT
(SPI=0)
tDEE
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
External shift clock mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
194
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
(4-1-6) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "L" : SMR,SCSFR:SCINV=1,
Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL=1
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
SCS↓→SCK↑
setup time
Sym
bol
tCSSI
Pin name
Con
ditio
ns
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCK↓→SCS↑
hold time
tCSHI
SCS
deselect time
tCSDI
SCS↓→SCK↑
setup time
tCSSE
SCK↓→SCS↑
hold time
tCSHE
SCS
deselect time
tCSDE
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK1 to SCK11
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Value
Min
Max
tCSSU-50
tCSSU+0
*1
*1
tCSSU-50
tCSSU+300
*1
*1
Unit
ns
ns
tCSHD-10
*2
tCSHD+50
*2
tCSHD-300
tCSHD+50
*2
*2
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
-
ns
+0
-
3tCPP+30
Internal shift
clock mode
output pin :
CL=50pF
ns
tCSDS-50
3tCPP+30
Remarks
External shift
clock mode
output pin:
CL=50pF
195
D a t a S h e e t
Parameter
SCS↓→SOT
delay time
Sym
bol
tDSE
Pin name
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SOT1, SOT2,
SOT5 to SOT15,
SOT18, SOT19
SCS3,
SCS40 to SCS43
SOT3, SOT4
SCS↑→SOT
delay time
SCK↑→SCS↓
clock switch time
tDEE
tSCC
Con
ditio
ns
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SOT1 to SOT15,
SOT18, SOT19
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
-
Value
Min
Max
-
40
Unit
ns
-
300
ns
+0
-
ns
3tCPP-10
3tCPP+50
Remarks
ns
-
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
Round operation
output pin:
CL=50pF
3tCPP-300
3tCPP+50
ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again.
Please see the hardware manual for details of above-mentioned *1,*2, and *3
196
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode
SCS input
tCSDE
tCSHE
tCSSE
SCK input
SOT
(SPI=0)
tDEE
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
External shift clock mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
197
D a t a S h e e t
(4-1-7) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "H" : SMR,SCSFR:SCINV=0,
Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL=0
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
SCS↑→SCK↓
setup time
SCK↑→SCS↓
hold time
Sym
bol
tCSSI
tCSHI
SCS
deselect time
tCSDI
SCS↑→SCK↓
setup time
tCSSE
SCK↑→SCS↓
hold time
tCSHE
SCS
deselect time
198
CONFIDENTIAL
tCSDE
Pin name
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK1 to SCK15,
SCK18, SCK19
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
Con
ditio
ns
-
Value
Min
Max
tCSSU-50
tCSSU+0
*1
*1
tCSSU-50
tCSSU+300
*1
*1
tCSHD-10
*2
tCSHD+50
*2
tCSHD-300
tCSHD+50
*2
*2
Unit
ns
ns
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
-
ns
+0
-
3tCPP+30
Internal shift
clock mode
output pin :
CL=50pF
ns
tCSDS-50
3tCPP+30
Remarks
External shift
clock mode
output pin:
CL=50pF
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Parameter
SCS↑→SOT
delay time
Sym
bol
tDSE
Pin name
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCK18, SCK19
SOT1, SOT2,
SOT5 to SOT15,
SOT18, SOT19
SCS3,
SCS40 to SCS43
SOT3, SOT4
SCS↓→SOT
delay time
SCK↓→SCS↑
clock switch time
tDEE
tSCC
Con
ditio
ns
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15
SCK18, SCK19
SOT1 to SOT15,
SOT18, SOT19
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1,SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
-
Value
Min
Max
-
40
Unit
ns
-
300
ns
+0
-
ns
3tCPP-10
3tCPP+50
Remarks
ns
-
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
Round operation
output pin:
CL=50pF
3tCPP-300
3tCPP+50
ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again.
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
199
D a t a S h e e t
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
SOT
(SPI=0)
tDEE
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
External shift clock mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
200
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
(4-1-8) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used: SCSCR:CSEN=1,
Serial clock output mark level "L" : SMR,SCSFR:SCINV=1,
Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL=0
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
SCS↑→SCK↑
setup time
Sym
bol
tCSSI
Pin name
Con
ditio
ns
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCK↓→SCS↓
hold time
tCSHI
SCS
deselect time
tCSDI
SCS↑→SCK↑
setup time
tCSSE
SCK↓→SCS↓
hold time
tCSHE
SCS
deselect time
tCSDE
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11,
SCS18, SCS19
SCK1 to SCK15,
SCK18, SCK19
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
Value
Min
Max
tCSSU-50
tCSSU+0
*1
*1
tCSSU-50
tCSSU+300
*1
*1
Unit
ns
ns
tCSHD-10
*2
tCSHD+50
*2
tCSHD-300
tCSHD+50
*2
*2
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
-
ns
+0
-
3tCPP+30
Internal shift
clock mode
output pin :
CL=50pF
ns
tCSDS-50
3tCPP+30
Remarks
External shift
clock mode
output pin:
CL=50pF
201
D a t a S h e e t
Parameter
SCS↑→SOT
delay time
Sym
bol
tDSE
Pin name
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SOT1, SOT2,
SOT5 to SOT15,
SOT18, SOT19
SCS3,
SCS40 to SCS43
SOT3, SOT4
SCS↓→SOT
delay time
SCK↑→SCS↑
clock switch time
tDEE
tSCC
Con
ditio
ns
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SOT1 to SOT15,
SOT18, SOT19
SCK1, SCK2,
SCK5 to SCK15,
SCK18, SCK19
SCS1, SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS15,
SCS18, SCS19
SCK3, SCK4
SCS3,
SCS40 to SCS43
-
Value
Min
Max
-
40
Unit
ns
-
300
ns
+0
-
ns
3tCPP-10
3tCPP+50
Remarks
ns
-
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
Round operation
output pin:
CL=50pF
3tCPP-300
3tCPP+50
ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again.
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
202
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Slave mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode, Example of switching clock by round operation (x,y=0,1,2,3)
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
203
D a t a S h e e t
(4-2) UART (Asynchronous serial interface) timing
Bit setting: SMR : MD2=0, SMR:MD1=0, SMR : MD0=0
Bit setting: SMR : MD2=0, SMR:MD1=0, SMR : MD0=1
When external clock is selected (BGR:EXT=1)
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Symb
ol
Pin name
Value
Conditio
ns
Unit
Min
Max
Serial clock
"L" pulse width
tSLSH
tCPP+10
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
-
SCK0 to SCK19
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
tR
output pin:
CL=50pF
tSLSH
VIH
VIH
SCK
tF
tSHSL
Remarks
VIH
VIL
VIL
VIL
When external clock is selected
(4-3) LIN Interface (v2.1)( Asynchronous Serial Interface for LIN (v2.1)) timing
Bit setting: SMR : MD2=0, SMR:MD1=1, SMR : MD0=1
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Symb
ol
Pin name
Value
Conditio
ns
Unit
Min
Max
Serial clock
"L" pulse width
tSLSH
tCPP+10
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
-
SCK0 to SCK19
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
tR
VIH
SCK
VIL
tF
tSHSL
Remarks
output pin:
CL=50pF
tSLSH
VIH
VIH
VIL
VIL
When external clock is selected
204
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
2
(4-4) I C timing
(TA: -40°C to +125°C,VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
SCL clock frequency
Repeat "start"
condition hold time
SDA ↓ → SCL ↓
Sym
bol
fSCL
tHDSTA
Pin name
Conditio
ns
SCK3 to SCK8,
SCK11 to SCK19
SOT3 to SOT8,
SOT11 to SOT19
(SDA),
SCK3 to SCK8,
SCK11 to SCK19
(SCL)
SCK3 to SCK8,
SCK11 to SCK19
(SCL)
SCK3 to SCK8,
SCK11 to SCK19
(SCL)
SCK3 to SCK8,
SCK11 to SCK19
(SCL)
SOT3 to SOT8,
C =50pF
SOT11 to SOT19 L
R=
(SDA)
(VP/IOL) *1
SCK3 to SCK8,
SCK11 to SCK19
(SCL)
SOT3 to SOT8,
SOT11 to SOT19
(SDA)
SCK3 to SCK8,
SCK11 to SCK19
(SCL)
SOT3 to SOT8,
SOT11 to SOT19
(SDA)
SCK3 to SCK8,
SCK11 to SCK19
(SCL)
Period of "L" for SCL
clock
tLOW
Period of "H" for SCL
clock
tHIGH
Repeat "start"
condition setup time
SCL ↑ → SDA ↓
tSUSTA
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
"Stop" condition setup
time
SCL ↑ → SDA ↑
tSUSTO
Bus-free time between
"stop" condition and
"start" condition
tBUF
–
Noise filter
tSP
–
–
Standard
mode
Min Max
High-speed
Rem
mode*3
Unit
arks
Min Max
0
100
0
400
kHz
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
4.0
–
0.6
–
μs
4.7
–
0.6
–
μs
0
3.45*2
0
0.9*3
μs
250
–
100
–
ns
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
2tCPP*4
–
2tCPP*4
–
ns
Notes: Only ch.3, ch.4 and ch.12-ch.19 are standard mode/high-speed mode correspondence. In ch.5-ch.8 and
ch.11, only a standard mode is correspondences.
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,
respectively.
Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCPP is the peripheral clock cycle time. Adjust the clock of the bus in the surrounding to 8MHz or more when
use I2C.
March 28, 2014, MB91F528_DS705-00016-1v0-E
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205
D a t a S h e e t
I2C timing
SDA
tSUDAT
tSUSTA
tBUF
tLOW
SCL
tHDSTA
206
CONFIDENTIAL
tHDDAT
tHIGH
tHDSTA
tSP
tSUSTO
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
(5) Timer input timing
(TA: -40°C to +125°C , VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIN0 to TIN7,
ICU0 to ICU11,
FRCK0 to
FRCK10,
TIOA0, TIOA1,
TIOB0, TIOB1,
AIN0 to AIN3,
BIN0 to BIN3,
ZIN0 to ZIN3
–
Input pulse width
Value
Min
Max
4tCPP
–
Unit
Remarks
ns
 Timer input timing
TINx,
ICUx,
FRCKx,
TIOAx,TIOBx
AINx,BINx,ZINx
tTIWH
tTIWL
VIH
VIH
VIL
VIL
(6) Trigger input timing
(TA: -40°C to +125°C, ,VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Input pulse width
Symbol Pin name Conditions
INT0 to
INT23,
ADTG0,
ADTG1,
RX0 to
RX5
tTRGH,
tTRGL
Value
Unit
Min
Max
5tCPP
–
ns
1
–
μs
Remarks
–
At stop mode
 Trigger input timing
tTRGL
tTRGH
INTx
ADTG
RXx
VIH
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
VIH
VIL
VIL
207
D a t a S h e e t
(7) NMI input timing
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Input pulse width
Symbol
Pin
name
Conditions
tNMIL
NMIX
–
Value
Min
Max
4tCPP
–
Unit
Remarks
ns
 NMIX input timing
tNMIL
NMIX
VIH5
VIH5
VIL5
208
CONFIDENTIAL
VIL5
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
(8) Low voltage detection (External low-voltage detection)
(TA: -40°C to +125°C , VSS=AVSS=0.0V)
Parameter
Power supply
voltage range
Symbol
Pin
name
VDP5
Detection voltage
VDL
Hysteresis width
VHYS
VCC
Value
Conditi
ons
Min
Typ
Max
-
2.7
-
5.5
*1
Unit
Remarks
V
-8%
2.8
+8%
V
-
0.1
-
V
When
power-supply
voltage falls
and detection
level is set
initially
When
power-supply
voltage rises
Low voltage
Td
30
µs
detection time
Power supply
VCC
-2
2
V/ms
*2
voltage regulation
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to
do a low voltage detection by detecting voltage (VDL).
(9) Low voltage detection (Internal low-voltage detection)
(TA: -40°C to +125°C, VSS=AVSS=0.0V)
Parameter
Symbol
Pin
name
Con
ditio
ns
Min
Typ
Max
Value
Unit
Power supply
voltage range
VRDP5
-
0.6
-
1.4
V
Detection voltage
VRDL
*
0.8
0.9
1.0
V
Hysteresis width
VRHYS
-
0.1
-
V
-
-
Remarks
When
power-supply
voltage falls
When
power-supply
voltage rises
Low voltage
30
µs
detection time
*: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
March 28, 2014, MB91F528_DS705-00016-1v0-E
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D a t a S h e e t
(10) External bus I/F (synchronous mode) timing
(TA: -40°C to +105°C, VCC=AVCC=5.0V±10%/VCC= AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
(external load capacitance 50pF)
Parameter
Symbol
Pin name
Value
Min
Max
Unit
VCC=5.0V±10%*1
25
Cycle time
tCYC
SYSCLK
Remarks
-
ns
31.25
VCC=3.3V±0.3V
ASX delay time
tCHASL,
tCHASH
SYSCLK,
ASX
0.5
18
ns
CS0X to CS3X
delay time
tCHCSL,
tCHCSH
SYSCLK,
CS0X to
CS3X
0.5
18
ns
A00 to A21
delay time
tCHAV,
tCHAX
SYSCLK,
A00 to A21
0.5
18
ns
RDX delay time
tCHRL,
tCHRH
SYSCLK,
RDX
0.5
18
ns
RDX
minimum pulse
tRLRH
RDX
tCYC×
2 - 20
-
ns
RWT=1, set RWT to 1
or more.*2
Data setup →
RDX↑time
tDSRH
18+tCYC
-
ns
Same as above
RDX↑→
data hold
tRHDH
0
-
ns
WRnX delay time
tCHWL,
tCHWH
SYSCLK,
WR0X,
WR1X
0.5
18
ns
WRnX
minimum pulse
tWLWH
WR0X,
WR1X
tCYC - 10
-
ns
SYSCLK↑→
data output time
tCHDV
0.5
18
ns
SYSCLK↑→
data hold time
tCHDX
-
18
ns
210
CONFIDENTIAL
RDX,
D16 to D31
SYSCLK,
D16 to D31
WWT=0 *2
Set WRCS to 1 or
more.
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Parameter
Symbol
SYSCLK↑→
address output time
tCHMAV
SYSCLK↑→
address hold time
Pin name
Value
Min
Max
0.5
18
Unit
ns
SYSCLK,
D16 to D31
tCHMAX
-
18
Remarks
ns
In multiplex mode, set
as follows:
 Set CSWR and
CSRD to 2 or more.
 ASCY must satisfy
the following
conditions because of
setting
ADCY > ASCY and
protocol violation
prevention.
ADCY +1 ≤ ACS +
CSRD
ADCY +1 ≤ ACS +
CSWR
ASCY + 1 ≤ ACS +
CSRD
ASCY + 1 ≤ ACS +
CSWR
See Hardware Manual
for details.
*1: Please use it with external load capacity 12pF or less for V CCE=3.3V±0.3V (40MHz operation).
*2: If the bus is expanded by automatic wait insertion or RDY input, add time (t CYC × the number of expanded
cycles) to the rated value.
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D a t a S h e e t
External bus I/F (synchronous mode, read operation, and multiplex mode) timing
t1
t3
t2
t4
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
CS0X
to CS3X
CS0X~CS3X
tCHCSH
RDCS=0
ACS=0
tCHRL
tCHRH
RWT=1
RDX
tRLRH
CSRD=2
ADCY=1
tCHMAV
D16D16~D31
to D31
tCHMAX
Read Data
Valid Address
tRHDH
tDSRH
External bus I/F (synchronous mode, read operation, and split mode) timing
t1
t3
t2
t4
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
CS0X
to CS3X
CS0X~CS3X
tCHCSH
RDCS=0
ACS=0
tCHRL
tCHRH
RWT=1
RDX
tRLRH
CSRD=0
tCHAV
A00
to A21
A00~A21
D16
to D31
D16~D31
tCHAX
Valid Address
Read Data
tDSRH
212
CONFIDENTIAL
tRHDH
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
External bus I/F (synchronous mode, write operation, and multiplex mode) timing
t1
t4
t3
t2
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
CS0X
to CS3X
CS0X~CS3X
tCHCSH
WRCS=1
ACS=0
tCHWL
WR0X
to WR1X
WR0X~WR1X
tCHMAV
D16
to D31
D16~D31
tCHWH
tWLWH
CSWR=2
WWT=0
ADCY=1
tCHDX
tCHDV
Write Data
Valid Address
External bus I/F (synchronous mode, write operation, and split mode) timing
t1
t4
t3
t2
tCYC
SYSCLK
tCHASH
tCHASL
ASCY=0
ASX
tCHCSL
tCHCSH
WRCS=1
CS0X~CS3X
CS0X
to CS3X
ACS=0
tCHWL
WR0X~WR1X
WR0X
to WR1X
tCHWH
tWLWH
CSWR=0
WWT=0
tCHAV
A00
to A21
A00~A21
tCHDV
D16~D31
D16
to D31
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
tCHAX
Valid Address
tCHDX
Write Data
213
D a t a S h e e t
(11) External bus I/F (asynchronous mode) timing
(TA: -40°C to +105°C,VCC=AVCC=5.0V±10%/VCC= AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
(external load capacitance 50pF)
Parameter
Symbol
Pin
name
Value
Unit
Min
VCC=5.0V±10%*1
25
Cycle time
tCYC
SYSCLK
-
ns
31.25
Address setup →
RDX↑time
tASRH
RDX↑→
Address hold
Remarks
Max
VCC=3.3V±0.3V
2×tCYC - 12
2×tCYC +
12
ns
RWT=1,
set RWT to 1 or more. *2
tRHAH
tCYC - 12
tCYC + 12
ns
Set RDCS to 1 or more.
Data setup→
RDX↑time
tDSRH
18 +
tCYC
-
ns
RWT=1,
set RWT to 1 or more.
RDX↑→
Data hold
tRHDH
0
-
ns
Address setup→
WRnX↑time
tASWH
tCYC - 12
tCYC + 12
ns
WWT=0 *2
WRnX↑→
Address hold
tWHAH
WR0X to
WR1X,
A00 to A21
tCYC - 12
tCYC + 12
ns
Set WRCS to 1 or more.
Data setup→
WRnX↑time
tDSWH
tCYC - 16
tCYC + 16
ns
WWT=0 *2
WRnX↑→
Data hold
tWHDH
WR0X to
WR1X,
D16 to D31
tCYC 16
tCYC +
16
ns
Set WRCS to 1 or more.
tCYC-16
tCYC+ 16
ns
ASCY=0
ns
In multiplex mode, set as
follows:
 Set CSWR and CSRD to
2 or more.
 ASCY must satisfy the
following conditions
because of setting
ADCY > ASCY and
protocol violation
prevention.
ADCY +1 ≤ ACS + CSRD
ADCY +1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS +
CSWR
See Hardware Manual for
details.
Address setup →
ASX↑time
ASX↑→Address hold
RDX,
A00 to A21
RDX,
D16 to D31
tMASASH
ASX,
D16 to D31
tMASHAH
tCYC-16
tCYC + 16
*1: Please use it with external load capacity 12pF or less for VCCE=3.3V±0.3V (40MHz operation).
*2: If the bus is expanded by automatic wait insertion or RDY input, add time (t CYC × the number of expanded
cycles) to the rated value.
214
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
External bus I/F (asynchronous mode, read operation, and multiplex mode) Timing
t1
t3
t2
t4
t5
tCYC
SYSCLK
ASCY=0
ASX
CS0X
to CS3X
CS0X~CS3X
RDCS=1
ACS=0
RWT=1
RDX
CSRD=2
ADCY=1
Read Data
Valid Address
D16~D31
D16
to D31
tRHDH
tMASASH
tMASHAH
tDSRH
External bus I/F (asynchronous mode, read operation, and split mode) Timing
t1
t3
t2
t4
t5
tCYC
SYSCLK
ASCY=0
ASX
CS0X
to CS3X
CS0X~CS3X
RDCS=1
ACS=0
RWT=1
RDX
A00
to A21
A00~A21
CSRD=0
Valid Address
tASRH
D16~D31
D16
to D31
tDSRH
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
tRHAH
Read Data
tRHDH
215
D a t a S h e e t
External bus I/F (asynchronous mode, write operation, and multiplex mode) Timing
t1
t3
t2
t4
tCYC
SYSCLK
ASCY=0
ASX
CS0X~CS3X
CS0X
to CS3X
CS3X
CS0X
to
WRCS=1
ACS=0
WR0X~WR1X
WR0X
to WR1X
CSWR=2
WWT=0
ADCY=1
Write Data
Valid Address
D16
to D31
D16~D31
tMASASH
tMASHAH
tWHDH
tDSWH
External bus I/F (Asynchronous mode, write operation, and split mode) Timing
t1
t3
t2
t4
tCYC
SYSCLK
ASCY=0
ASX
CS0X
to CS3X
CS0X~CS3X
WR0X
to WR1X
WR0X~WR1X
A00~A21
A00
to A21
WRCS=1
ACS=0
CSWR=0
WWT=0
Valid Address
tASWH
D16
to D31
D16~D31
tDSWH
216
CONFIDENTIAL
tWHAH
Write Data
tWHDH
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
(12) External bus I/F (ready) Timing
(TA: -40°C to +105°C,VCC=AVCC=5.0V ± 10%/VCC= AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
(external load capacitance 50pF)
Parameter
Symbol
Value
Pin
name
Min
Max
Unit
Cycle time
tCYC
SYSCLK
50
-
ns
RDY setup time →
SYSCLK↑
tRDYS
SYSCLK,
RDY
28
-
ns
SYSCLK↑→
RDY hold time
tRDYH
SYSCLK,
RDY
0
-
ns
Remarks
If using RDY, set
SYSCLK to 20 MHz or
less.
External bus I/F (ready) Timing
t1
t2
t3
t4
t5
t6
tCYC
SYSCLK
ASX
ASCY=0
CS0X~CS3X
RDCS=0
ACS=0
RDX
RWT=2
CSRD=2
RDY
Auto wait cycle
tRDYS
tRDYH
Added cycle by RDY
March 28, 2014, MB91F528_DS705-00016-1v0-E
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217
D a t a S h e e t
5. A/D Converter
(1) 12-bit A/D Converter Electrical Characteristics
(TA: -40°C to +125°C, VCC=AVCC=5.0V ± 10%/VCC= AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Sym
bol
Pin name
Resolution
-
Total error
Parameter
Value
Unit
Min
Typ
Max
-
-
-
12
bit
-
-
-
-
±12
LSB
Linearity error
-
-
-
-
± 4.0
LSB
Differential linearity error
-
AVRL11.5LSB
AVRH13.5LSB
0.7
-
LSB
-
± 1.9
AVRL+
12.5LSB
AVRH+
10.5LSB
-
Zero transition voltage
VOT
Full-scale transition voltage
VFST
Sampling time
tSMP
AN0 to
AN63
AN0 to
AN63
-
Compare time
tCMP
-
0.7
-
A/D conversion time
tCNV
1.4
Analog port input current
IAIN
Analog input voltage
VAIN
AN0 to
AN63
AN0 to
AN63
AVRH
AVSS/
AVRL
AVRH
Reference voltage
AVRL
IA
Power supply current
IAH
IR
IRH
Variation between channels
AVCC*3
-
AVRH
AN0 to
AN63
-
V
Remarks
V
1LSB=
(VFST-VOT)/
4094
µs
*1
-
µs
*1
-
-
µs
-1.0
-
+1.0
µA
*1
VAVSS ≤
VAIN ≤ VAVCC
AVRL
-
AVRH
V
3.0
-
5.5
V
-
0.0
-
V
-
0.47
0.63
mA
-
0.47
0.7
mA
-
-
2.5
µA
Per unit
TA: +105°C
Per unit
TA: +125°C
*2
-
1
1.96
mA
Per unit
-
-
1.6
µA
*2
-
-
4
LSB
-
*1: Time for each channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped.
*3: The power supply current described only current value on A/D converter.
The total AVcc current value must be calculated the power supply current for A/D converter and D/A
converter.
(Note) Please use the clock of 0.5MHz-20MHz for the output clock of A/D converter to guarantee accuracy.
218
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
(2) Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Linearity error
: Deviation of the actual conversion characteristics from a straight line that
connects the zero transition point ("0000 0000 0000"← →"0000 0000 0001") to
the full-scale transition point ("1111 1111 1110"← →"1111 1111 1111").
Differential linearity
error
: Deviation of the input voltage from the ideal value that is required to change the
output code by LSB.
Linearity error of digital output N =
VNT - {1LSB × (N - 1) + VOT}
1LSB
Differential linearity error of digital output N =
V(N + 1) T - VNT
[LSB]
- 1 LSB
[LSB]
1LSB
1LSB =
VOT
VFST
VFST - VOT
4094
: Voltage at which the digital output changes from “000H” to “001 H”.
: Voltage at which the digital output changes from “FFE H” to “FFF H”.
March 28, 2014, MB91F528_DS705-00016-1v0-E
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[V]
219
D a t a S h e e t
(3) Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
· When the external impedance is too high, the sampling period for analog voltages may not be
sufficient. In this case, it is recommended to connect the capacitor (approx. 0.1 μF) to the analog
input pin.
 Analog input circuit model
R
Comparator
Analog input
C
During sampling: ON
R
C
1.9kΩ (Max) 8.30pF (Max) (4.5V ≤ AVCC ≤ 5.5V)
4.3kΩ (Max) 8.30pF (Max) (3.0V ≤ AVCC ≤ 3.6V)
Note: Listed values must be considered as reference values.
12bit A/D
220
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
6. Flash memory
(1) Electrical Characteristics
Parameter
Min
Value
Typ
Max
Unit
–
200
800
ms
–
300
1100
ms
–
400
2000
ms
–
700
3700
ms
8-bit writing time
–
9
288
µs
16-bit writing time
–
12
384
µs
ECC writing time
–
9
288
µs
Sector erase time
Remarks
8 Kbytes sector*1,
excluding internal
preprogramming time
8 Kbytes sector*1,
including internal
preprogramming time
64 Kbytes sector*1,
excluding internal
preprogramming time
64 Kbytes sector*1,
including internal
preprogramming time
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
1,000
cycles/
20 years,
10,000
2
Erase cycle* /
cycles/
–
–
–
Average TA=+85°C*3
Data retain time
10 years,
100,000
cycles/
5 years
*1: The guaranteed value for erasure up to 100,000 cycles.
*2: Number of erase cycles for each sector.
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
(2) Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited.
In the application system where Vcc might be shut down while writing or erasing, be sure to turn the
power off by using an external voltage detection function.
To put it concretely, after the external power supply voltage falls below the detection
voltage (VDL*), hold Vcc at 2.7V or more within the duration calculated by the following expression:
Td*[µs] + (period of PCLK [µs] × 257) + 50 [µs]
*: See “4.AC Characteristics (8) Low-voltage detection (External low-voltage detection) ”
March 28, 2014, MB91F528_DS705-00016-1v0-E
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221
D a t a S h e e t
7. D/A converter
(TA:-40°C to +125°C,VCC=AVCC=5.0V±10%/VCC= AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Min
Value
Typ
Max
–
–
–
8
bit
-
–
–
–
± 3.0
LSB
-
-
–
–
0.47
2.37
0.58
2.90
0.69
3.43
µs
µs
Ro
DA0,
DA1
–
3.1
3.8
4.5
kΩ
IA
AVCC
–
–
475
580
µA
IAH
AVCC
–
–
–
7.5
µA
Symbol
Pin
name
Condition
Resolution
Differential linearity
error
-
-
-
Conversion time
Parameter
Output impedance
Power supply current
*1
Unit
Remarks
CL=20
CL=100
Each
channel
When
powerdown
Each
channel
*1: The power supply current described only current value on D/A converter.
The total AVcc current value must be calculated the power supply current for D/A converter and A/D
converter.
222
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
■EXAMPLE CHARACTERISTICS
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
 MB91F528
normal operation
100.00
(VCC = 5.5V)
PLL clock (128MHz)
PLL clock (80MHz)
ICC5 [mA]
PLL clock(64MHz)
PLL clock (48MHz)
10.00
-50
0
50
100
150
TA [ºC]
sleep mode
(VCC = 5.5V)
ICCS5/ICCBS5 [mA]
100.00
CPU Sleep(80MHz)
BUS Sleep (80MHz)
10.00
-50
0
50
100
150
TA [ºC]
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
223
D a t a S h e e t
 MB91F528
Watch mode
(VCC = 5.5V)
10.000
ICCT5 [mA]
Main osc (4MHz)
1.000
Sub osc (32kHz)
RC clock (50kHz)
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
Stop mode
(VCC = 5.5V)
ICCH5 [mA]
10.000
1.000
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
224
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
 MB91F528
Watch mode(power off)
1000.00
Main osc (4MHz)
100.00
ICCT52 [µA]
(VCC = 5.5V)
Sub osc (32kHz)
RC clock (50kHz)
10.00
1.00
0.10
0.01
-50
0
50
100
150
TA [ºC]
Stop mode(power off)
(VCC = 5.5V)
1000.00
ICCH52 [µA]
100.00
10.00
1.00
0.10
0.01
-50
0
50
100
150
TA [ºC]
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
225
D a t a S h e e t
 ORDERING INFORMATION
Part number
Sub clock
CSV Initial value
LVD Initial value
MB91F528YWCPB
Yes
ON
ON
MB91F528YYCPB
OFF
MB91F528YJCPB
OFF
MB91F528YLCPB
ON
MB91F527YYCPB
MB91F527YJCPB
OFF
None
ON
OFF
MB91F528YKCPB
ON
MB91F527YUCPB
OFF
MB91F527YKCPB
Yes
ON
OFF
MB91F528MLCPMC
ON
ON
OFF
MB91F527MWCPMC
ON
MB91F527MYCPMC
ON
OFF
MB91F527MJCPMC
OFF
MB91F527MLCPMC
ON
OFF
None
ON
MB91F528MUCPMC
ON
LQFP•208 pin,
Plastic (FPT-208P-M06)
OFF
OFF
MB91F528MKCPMC
ON
OFF
ON
MB91F527MUCPMC
CONFIDENTIAL
ON
OFF
MB91F528MJCPMC
226
ON
OFF
MB91F528MYCPMC
MB91F527MKCPMC
ON
OFF
MB91F527YHCPB
MB91F527MHCPMC
BGA•416 pin,
Plastic (BGA-416P-M05)
OFF
MB91F527YSCPB
MB91F527MSCPMC
ON
OFF
MB91F528YHCPB
MB91F528MHCPMC
ON
OFF
MB91F528YUCPB
MB91F528MSCPMC
ON
OFF
MB91F527YLCPB
MB91F528MWCPMC
ON
OFF
MB91F527YWCPB
MB91F528YSCPB
1
Package*
ON
OFF
OFF
ON
OFF
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Part number
Sub clock
CSV Initial value
LVD Initial value
MB91F528UWCPMC
Yes
ON
ON
MB91F528UYCPMC
OFF
MB91F528UJCPMC
OFF
MB91F528ULCPMC
ON
MB91F527UYCPMC
OFF
MB91F527ULCPMC
None
ON
OFF
MB91F528UKCPMC
ON
MB91F527UUCPMC
OFF
MB91F527UKCPMC
Yes
ON
OFF
MB91F528RLCPMC
ON
OFF
MB91F527RWCPMC
ON
MB91F527RYCPMC
ON
OFF
MB91F527RJCPMC
OFF
MB91F527RLCPMC
ON
OFF
None
ON
MB91F528RUCPMC
ON
LQFP•144 pin,
(Lead pitch 0.5mm)
Plastic (FPT-144P-M08)
OFF
OFF
MB91F528RKCPMC
ON
OFF
ON
MB91F527RUCPMC
CONFIDENTIAL
ON
OFF
MB91F528RJCPMC
March 28, 2014, MB91F528_DS705-00016-1v0-E
ON
OFF
MB91F528RYCPMC
MB91F527RKCPMC
ON
OFF
MB91F527UHCPMC
MB91F527RHCPMC
ON
OFF
MB91F527USCPMC
MB91F527RSCPMC
ON
LQFP•176 pin,
Plastic (FPT-176P-M07)
OFF
MB91F528UHCPMC
MB91F528RHCPMC
ON
OFF
MB91F528UUCPMC
MB91F528RSCPMC
ON
OFF
MB91F527UJCPMC
MB91F528RWCPMC
ON
OFF
MB91F527UWCPMC
MB91F528USCPMC
1
Package*
ON
OFF
OFF
ON
OFF
227
D a t a S h e e t
Part number
Sub clock
CSV Initial value
LVD Initial value
MB91F528RWCPMC1
Yes
ON
ON
MB91F528RYCPMC1
OFF
MB91F528RJCPMC1
OFF
MB91F528RLCPMC1
ON
MB91F527RYCPMC1
OFF
MB91F527RLCPMC1
None
ON
OFF
MB91F528RKCPMC1
ON
MB91F527RUCPMC1
OFF
MB91F527RKCPMC1
Yes
ON
OFF
MB91F528MLCEQ
ON
OFF
MB91F527MWCEQ
ON
MB91F527MYCEQ
ON
OFF
MB91F527MJCEQ
OFF
MB91F527MLCEQ
ON
OFF
None
ON
MB91F528MUCEQ
ON
TEQFP•208 pin,
Plastic (FPT-208P-M36)
OFF
OFF
MB91F528MKCEQ
ON
OFF
ON
MB91F527MUCEQ
CONFIDENTIAL
ON
OFF
MB91F528MJCEQ
228
ON
OFF
MB91F528MYCEQ
MB91F527MKCEQ
ON
OFF
MB91F527RHCPMC1
MB91F527MHCEQ
ON
OFF
MB91F527RSCPMC1
MB91F527MSCEQ
ON
LQFP•144 pin,
(Lead pitch 0.4mm)
Plastic (FPT-144P-M12)
OFF
MB91F528RHCPMC1
MB91F528MHCEQ
ON
OFF
MB91F528RUCPMC1
MB91F528MSCEQ
ON
OFF
MB91F527RJCPMC1
MB91F528MWCEQ
ON
OFF
MB91F527RWCPMC1
MB91F528RSCPMC1
1
Package*
ON
OFF
OFF
ON
OFF
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
Part number
Sub clock
CSV Initial value
LVD Initial value
MB91F528UWCEQ
Yes
ON
ON
MB91F528UYCEQ
OFF
MB91F528UJCEQ
OFF
MB91F528ULCEQ
ON
MB91F527UYCEQ
MB91F527UJCEQ
OFF
None
ON
OFF
MB91F528UKCEQ
ON
MB91F527UUCEQ
ON
ON
OFF
MB91F527UHCEQ
OFF
MB91F527UKCEQ
ON
OFF
Yes
ON
MB91F528RYCEQ
ON
OFF
MB91F528RJCEQ
OFF
MB91F528RLCEQ
ON
OFF
MB91F527RWCEQ
ON
MB91F527RYCEQ
ON
OFF
MB91F527RJCEQ
OFF
MB91F527RLCEQ
ON
OFF
None
ON
MB91F528RUCEQ
ON
TEQFP•144 pin,
Plastic (planning*2)
OFF
OFF
MB91F528RKCEQ
ON
OFF
ON
MB91F527RUCEQ
MB91F527RHCEQ
TEQFP•176 pin,
Plastic (FPT-176P-M18)
OFF
MB91F527USCEQ
MB91F527RSCEQ
ON
OFF
MB91F528UHCEQ
MB91F528RHCEQ
ON
OFF
MB91F528UUCEQ
MB91F528RSCEQ
ON
OFF
MB91F527ULCEQ
MB91F528RWCEQ
ON
OFF
MB91F527UWCEQ
MB91F528USCEQ
1
Package*
ON
OFF
OFF
ON
MB91F527RKCEQ
OFF
*1: For details of the package, see " PACKAGE DIMENSIONS ".
*2: TEQFP-144pin is planning. Please contact sales representatives about details.
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
229
D a t a S h e e t
 PACKAGE DIMENSIONS
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20 g
Code
(Reference)
P-LFQFP144-20×20-0.50
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
Lead pitch
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0°~8°
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
230
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
144-pin plastic LQFP
(FPT-144P-M12)
144-pin plastic LQFP
(FPT-144P-M12)
Lead pitch
0.40 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP144-16×16-0.40
Note 1) * : These dimensions include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
*16.00–0.10 .630 +.016
–.004 SQ
73
108
72
109
0.08(.003)
Details of "A" part
1.50
.059
+0.20
–0.10
+.008
–.004
(Mounting height)
INDEX
0~8 °
37
144
LEAD No.
1
0.60±0.15
(.024±.006)
36
0.40(.016)
C
"A"
0.18±0.035
.007±.001
+0.05
0.07(.003) M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144024S-c-3-5
0.145–0.03
+.002
.006 –.001
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
231
D a t a S h e e t
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.5 0
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
132
0.145±0.055
(.006±.002)
89
88
133
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
232
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
208-pin plastic LQFP
(FPT-208P-M06)
208-pin plastic LQFP
(FPT-208P-M06)
Lead pitch
0.50 mm
Package width ×
package length
28.0 × 28.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
2.55 g
Code
(Reference)
P-LFQFP208-28×28-0.50
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
30.00±0.20(1.181±.008)SQ
* 28.00±0.10(1.102±.004)SQ
156
0.145±0.055
(.006±.002)
105
104
157
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
INDEX
0°~8°
208
LEAD No.
53
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
"A"
0.60±0.15
(.024±.006)
52
1
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F208027S-c-3-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
233
D a t a S h e e t
176-pin plastic TEQFP
Lead pitch
0.50 mm
Package width ×
package length
24.00 mm × 24.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max.
Weight
1.86 g
Code
(Reference)
P-TEQFP176-24×24-0.50
(FPT-176P-M18)
176-pin plastic TEQFP
(FPT-176P-M18)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008) SQ
*24.00±0.10(.945±.004) SQ
(9.26(.365) SQ)
(8.06(.317) SQ)
89
132
Details of "A" part
133
88
1.50 +0.20
-0.10
(.059 +.008
-.004 )
(Mounting height)
0.25(.010)
0.08(.003)
INDEX
1
0.50
(.020)
C
"A"
45
176
44
0.22±0.05
(.009±.002)
0.08(.003)
0˚~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(STAND OFF)
0.145±0.055
(.006±.002)
M
2013 FUJITSU SEMICONDUCTOR LIMITED HMbF176-18Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
234
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
208-pin plastic TEQFP
Lead pitch
0.50 mm
Package width ×
package length
28.00 mm × 28.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max.
Weight
2.55 g
Code
(Reference)
P-TEQFP208-28×28-0.50
(FPT-208P-M36)
208-pin plastic TEQFP
(FPT-208P-M36)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
30.00±0.20(1.181±.008) SQ
(9.26(.365) SQ)
(8.06(.317) SQ)
*28.00±0.10(1.142±.004) SQ
105
156
Details of "A" part
157
104
1.50 +0.20
-0.10
(.059 +.008
-.004 )
(Mounting height)
0.25(.010)
0.08(.003)
INDEX
"A"
208
53
1
0.50
(.020)
C
52
0.22±0.05
(.009±.002)
0˚~8˚
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(STAND OFF)
0.145±0.055
(.006±.002)
0.08(.003) M
2013 FUJITSU SEMICONDUCTOR LIMITED HMbF208-36Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
March 28, 2014, MB91F528_DS705-00016-1v0-E
CONFIDENTIAL
235
D a t a S h e e t
Lead pitch
1.00 mm
Package width ×
package length
27.00 mm × 27.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
2.37 mm MAX
416-pin plastic PBGA
(BGA-416P-M05)
416-pin plastic PBGA
(BGA-416P-M05)
B
25.00(.984)
27.00(1.063)
1.00(.039)
REF
24.00±0.10(.945±.004)
A
1.00(.039)
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1.00(.039)
27.00
(1.063)
25.00
(.984)
24.00±0.10
(.945±.004)
INDEX
1.00(.039)
REF
0.20(.008) (4X)
AE AC AA W U R N L J G E C A
AF AD AB Y V T P M K H F D B
ø0.60±0.10(.024±.004)
0.25(.010) M C A B
0.10(.004) M C
C
C
0.15(.006) C
2.37(.093)
Max.
0.50±0.10
(.020±.004)
2006-2010 FUJITSU SEMICONDUCTOR LIMITED BGA416005Sc-2-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
236
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014
D a t a S h e e t
■Major Changes
Page
Revision 1.0
-
Section
-
March 28, 2014, MB91F528_DS705-00016-1v0-E
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Change Results
Initial release
237
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States
and other countries. Other names used are for informational purposes only and may be trademarks of their respective
owners.
238
CONFIDENTIAL
MB91F528_DS705-00016-1v0-E, March 28, 2014