ISL43640 ® Data Sheet January 23, 2006 FN6043.3 Low-Voltage, Single Supply, 4 to 1 Multiplexer, High Performance Analog Switch Features The Intersil ISL43640 is a precision, bidirectional, analog switch configured as a 4 channel multiplexer/demultiplexer. The ISL43640 is designed to operate from a single +2V to +12V supply. It is equipped with an inhibit pin to simultaneously open all signal paths. • ON Resistance (RON), VS = 5V . . . . . . . . . . . . . . . . 100Ω ON resistance is 115Ω with a +5V supply, 45Ω with a +12V supply, and 190Ω with a +3V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 1nA at 25°C or 2.5nA at 85°C. All digital inputs have 0.8V to 2.4V logic thresholds ensuring TTL/CMOS logic compatibility when using a single +5V supply. Some of the smallest packages are available, alleviating board space limitations, and making Intersil’s newest line of low-voltage switches an ideal solution. 4:1 MUX 60ns/30ns 3V RON 190Ω 3V tON/tOFF 120ns/45ns Packages 10 Ld MSOP, 16 Ld QFN 3x3 Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” • Application Note AN520 “CMOS Analog Multiplexers and Switches; Specifications and Application Considerations. • Application Note AN1034 “Analog Switch and Multiplexer Applications” 1 • Low Off Leakage Current . . . . . . . . . . . . . . . . . . . . . 2.5nA • Fast Switching Action (VS = 5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns • Guaranteed Break-Before-Make • TTL, CMOS Compatible • Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems 115Ω 4.5V tON/tOFF • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<3µW • Battery Powered, Handheld, and Portable Equipment 25ns/24ns 4.5V RON • Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V Applications 45Ω 12V tON/tOFF • Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 3pC (Max) • Pb-Free Plus Anneal Available (RoHS Compliant) TABLE 1. FEATURES AT A GLANCE 12V RON • RON Matching Between Channels. . . . . . . . . . . . . . . . . . <2Ω • Available in 10 Ld MSOP and 16 Ld QFN Packages Table 1 summarizes the performance of this switch. CONFIGURATION • Fully Specified at 3V, 5V, and 12V Supplies for 10% Tolerances • Test Equipment - Medical Ultrasound - Electrocardiograph - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE • Audio and Video Switching • Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL43640 (Note 1) NO0 ADD1 10 V+ NO2 1 COM ISL43640 (QFN) TOP VIEW V+ ISL43640 (MSOP) TOP VIEW 16 15 14 13 8 NO0 N.C. 1 12 ADD2 7 ADD1 N.C. 2 11 N.C. 6 ADD2 N.C. 3 10 N.C. NO2 4 9 INH 4 LOGIC GND 5 NOTE: 1. Switches Shown for Logic “0” Inputs. Truth Table 5 6 INH ADD2 ADD1 SWITCH ON 1 X X NONE 0 0 0 NO0 0 0 1 NO1 0 1 0 NO2 0 1 1 NO3 NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with VS between 3.3V and 11V. Pin Descriptions PIN PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL43640IU 3640 -40 to 85 10 Ld MSOP M10.118 ISL43640IU-T 3640 -40 to 85 10 Ld MSOP Tape & Reel M10.118 ISL43640IUZ (Note) 3640Z -40 to 85 10 Ld MSOP Pb-free) M10.118 ISL43640IUZ-T (Note) 3640Z -40 to 85 10 Ld MSOP Tape & Reel (Pb-free) M10.118 ISL43640IR 640I -40 to 85 16 Ld QFN L16.3X3 ISL43640IR-T 640I -40 to 85 16 Ld QFN Tape & Reel L16.3X3 ISL43640IRZ (Note) 640Z -40 to 85 16 Ld QFN (Pb-free) L16.3X3 ISL43640IRZ-T (Note) 640Z -40 to 85 16 Ld QFN Tape & Reel (Pb-free) L16.3X3 System Power Supply Input (+2V to +12V) Ground Connection INH Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. NO PART NO. FUNCTION GND COM 8 N.C. Ordering Information ISL43640 V+ 7 GND NO1 3 INH 9 COM NO1 NO3 2 NO3 Pinouts Analog Switch Common Pin Analog Switch Normally Open Pin ADD Address Input Pin N.C. No Internal Connection 2 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6043.3 January 23, 2006 ISL43640 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V Input Voltages INH, NO, NC, ADD (Note 2) . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 40mA Thermal Resistance (Typical) Operating Conditions θJA (°C/W) 10 Ld MSOP Package (Note 3) . . . . . . . . . . . . . . . . 190 16 Ld QFN Package (Note 4). . . . . . . . . . . . . . . . . . 62 Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C Moisture Sensitivity (See Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (MSOP - Lead Tips Only) Temperature Range ISL43640IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications +5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 6) MIN Full 0 - V+ V 25 - 115 125 Ω TYP (NOTE 6) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (See Figure 5) Full - - 150 Ω RON Matching Between Channels, ∆RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (Note 8) 25 - 1 3 Ω Full - - 5 Ω RON Flatness, RFLAT(ON) V+ = 5.5V, ICOM = 1.0mA, VNO or VNC = 1.5V, 2.5V, 3.5V, (Note 9) Ω 25 - 12 13 Full - 13 18 Ω 25 -1 - 1 nA Full -2.5 - 2.5 nA 25 -1 - 1 nA Full -2.5 - 2.5 nA 25 -1 - 1 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.4 - V Input Voltage Low, VINL Full - 1.3 0.8 V V+ = 5.5V, VIN = 0V or V+ Full -0.5 - 0.5 µA V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) 25 - 60 65 ns Full - - 80 ns 25 - 30 35 ns NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V, (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V, or Floating, (Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) Address Transition Time, tTRANS V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) Break-Before-Make Time Delay, tD 3 V+ = 5.5V, RL = 300Ω, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3, (See Figure 3) Full - - 40 ns 25 - 61 70 ns Full - - 85 ns Full 5 16 - ns FN6043.3 January 23, 2006 ISL43640 Electrical Specifications +5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz, (See Figure 4) TEMP (°C) (NOTE 6) MIN TYP 25 - 0.3 (NOTE 6) MAX UNITS 1 pC 25 - 75 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 4 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 11 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 20 - pF Full 2 - 12 V Full -1 0.0001 1 µA POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, all channels on or off NOTES: 5. VIN = input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25°C. 8. ∆RON = RON (MAX) - RON (MIN). 9. Flatness is defined as the difference between the maximum and minimum value of on-resistance over the specified analog signal range. Electrical Specifications +3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 6) MIN Full 0 - V+ V 25 - 190 220 Ω TYP (NOTE 6) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V, (See Figure 5) Full - - 250 Ω RON Matching Between Channels, ∆RON V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V, (Note 8) 25 - 1 3 Ω Full - - 5 Ω RON Flatness, RFLAT(ON) V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1.5V, (Note 9) Ω 25 - 48 90 Full - - 90 Ω 25 -1 - 1 nA Full -2.5 - 2.5 nA 25 -1 - 1 nA Full -2.5 - 2.5 nA 25 -1 - 1 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.0 1.0 - V Input Voltage Low, VINL Full - 0.8 0.5 V V+ = 3.6V, VIN = 0V or V+ Full -0.5 - 0.5 µA V+ = 2.7V, VNO or VNC = 1.5V, RL =300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) 25 - 144 155 ns Full - - 175 ns 25 - 53 60 ns NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V, (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or floating, (Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL =300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) Address Transition Time, tTRANS V+ = 2.7V, VNO or VNC = 1.5V, RL =300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) Break-Before-Make Time Delay, tD 4 V+ = 3.6V, RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V, VIN = 0 to 3, (See Figure 3) Full - - 65 ns 25 - 145 160 ns Full - - 190 ns Full 15 35 - ns FN6043.3 January 23, 2006 ISL43640 Electrical Specifications +3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz, (See Figure 4) TEMP (°C) (NOTE 6) MIN TYP 25 - 0.5 (NOTE 6) MAX UNITS 1 pC 25 - 75 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 4 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 11 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 20 - pF Full -1 0.0001 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, all channels on or off Electrical Specifications + 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 6) MIN Full TYP (NOTE 6) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG 0 - V+ V ON Resistance, RON V+ = 12.0V, ICOM = 1.0mA, VNO or VNC = 9V, (See Figure 5) 25 - 45 50 Ω Full - - 70 Ω RON Matching Between Channels, ∆RON V+ = 12.0V, ICOM = 1.0mA, VNO or VNC = 9V, (Note 8) 25 - 0.5 3 Ω Full - - 5 Ω RON Flatness, RFLAT(ON) V+ = 13.2V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V, (Note 9) Ω 25 - 5 6 Full - - 10 Ω 25 -1 - 1 nA Full -2.5 - 2.5 nA 25 -1 - 1 nA Full -2.5 - 2.5 nA 25 -1 - 1 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.9 2.5 - V Input Voltage Low, VINL Full - 2.3 0.8 V V+ = 13V, VIN = 0V or V+ Full -0.5 - 0.5 µA V+ = 10.8V, VNO or VNC = 10V, RL =300Ω, CL = 35pF, VIN = 0 to 4, (See Figure 1) 25 - 25 30 ns Full - 25 - NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 13.0V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V, (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 13.0V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V, (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 13.0V, VCOM = 1V, 12V, or VNO or VNC = 1V, 12V, or floating, (Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF V+ = 10.8V, VNO or VNC = 10V, RL =300Ω, CL = 35pF, VIN = 0 to 4, (See Figure 1) Address Transition Time, tTRANS V+ = 10.8V, VNO or VNC = 10V, RL =300Ω, CL = 35pF, VIN = 0 to 4, (See Figure 1) 35 ns 24 28 ns 30 ns 35 50 ns 55 ns Full - 25 - Full - V+ = 13.2V, RL = 300Ω, CL = 35pF, VNO or VNC = 10V, VIN = 0 to 4, (See Figure 3) Full 3 9 Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - 1.2 3 pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz, (See Figure 4) 25 - 75 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 4 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 11 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6) 25 - 20 - pF Full -1 0.0001 1 µA Break-Before-Make Time Delay, tD ns POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13.0V, VIN = 0V or V+, all channels on or off 5 FN6043.3 January 23, 2006 ISL43640 Test Circuits and Waveforms 3V LOGIC INPUT tr < 20ns tf < 20ns 50% V+ C 0V V+ tON NO0 NO1-NO3 90% SWITCH OUTPUT C VOUT INH 90% VOUT COM ADD1, GND ADD2 0V CL 35pF RL 300Ω LOGIC INPUT tOFF Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS tr < 20ns tf < 20ns 3V LOGIC INPUT 50% V+ C C 0V V+ tTRANS NO0 NO1-NO3 90% SWITCH OUTPUT VOUT ADD1 ADD2 90% COM GND INH CL 35pF RL 300Ω LOGIC INPUT 0V VOUT tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1D. ADDRESS TEST CIRCUIT FIGURE 1C. ADDRESS MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES V+ C 3V LOGIC INPUT OFF OFF ON SWITCH OUTPUT VOUT VOUT RG 0V ∆VOUT VG NO or NC COM ADD1 ADD2 INH GND CL LOGIC INPUT Q = ∆VOUT x CL FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION 6 FN6043.3 January 23, 2006 ISL43640 Test Circuits and Waveforms (Continued) V+ tr < 20ns tf < 20ns 3V C C LOGIC INPUT VOUT 0V NO0-NO3 V+ COM RL 300Ω ADD1 ADD2 80% SWITCH OUTPUT VOUT CL 35pF LOGIC INPUT 0V GND INH tD Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME V+ V+ C C SIGNAL GENERATOR RON = V1/1mA NO or NC NO or NC VNX 0V or V+ 1mA ADDX ANALYZER COM 0V or V+ V1 ADDX 0V or V+ GND INH COM RL FIGURE 4. OFF ISOLATION TEST CIRCUIT GND INH FIGURE 5. RON TEST CIRCUIT V+ C NO or NC 0V or V+ ADDX IMPEDANCE ANALYZER COM GND INH FIGURE 6. CAPACITANCE TEST CIRCUIT 7 FN6043.3 January 23, 2006 ISL43640 Detailed Description Power-Supply Considerations The ISL43640 operates from a single 2V to 12V supply with low on-resistance (115Ω) and high speed operation (tON = 60ns, tOFF = 30ns) with a +5V supply. The ISL43640 is especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.0V), low power consumption (3µW), low leakage currents (5nA max), and the tiny MSOP and QFN packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation (75dB). The ISL43640 construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL43640’s 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and GND (see Figure 7). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1kΩ 1kΩ OPTIONAL PROTECTION DIODE ADDX V+ The minimum recommended supply voltage is 2.0V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. The device cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds The ISL43640 is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (see Figure 10). At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails (see Figure 11). Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.The ISL43640 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 3V logic (0V to 3V) while operating with a 5V supply the device draws only 10µA of current (see Figure 11 for VIN = 3V). Similiar devices of competitors can draw 8 times this amount of current. High-Frequency Performance IN VNO or NC VCOM GND OPTIONAL PROTECTION DIODE FIGURE 7. OVERVOLTAGE PROTECTION 8 In 50Ω systems, signal response is reasonably flat even past 100MHz (see Figure 16). Figure 16 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off Isolation is the resistance to this feed through. Figure 17 details the high Off Isolation rejection provided by this family. At 10MHz, Off Isolation is about 55dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation due to the FN6043.3 January 23, 2006 ISL43640 voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Typical Performance Curves TA = 25°C, Unless Otherwise Specified 500 225 VCOM = (V+) - 1V V+ = 3.3V 200 ICOM = 1mA 175 400 ICOM = 1mA 85°C 150 25°C 200 85°C 100 -40°C 0 2 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE V+ = 5V 85°C 120 100 25°C -40°C V+ = 12V 25°C 4 2 6 VCOM (V) 8 10 12 FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE 3.0 70 VINH -40°C V+ = +5V 60 2.0 25°C 85°C 1.5 50 1.0 40 0.5 ICC (µA) VINH AND VINL (V) 75 140 80 60 80 70 85°C 60 50 40 -40°C 30 0 25°C 2.5 -40°C 100 300 RON (Ω) RON (Ω) 125 3.0 VINL 2.5 -40°C 2.0 30 20 25°C 1.5 10 1.0 85°C 0.5 0 2 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 FIGURE 10. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE 9 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VIN(ADD) (V) FIGURE 11. SUPPLY CURRENT vs DIGITAL ADDRESS INPUT VOLTAGE FN6043.3 January 23, 2006 ISL43640 Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 120 350 VCOM = (V+) - 1V VCOM = (V+) - 1V 110 300 100 90 250 tOFF (ns) tON (ns) 80 200 85°C 150 70 60 85°C 50 25°C 100 30 -40°C 50 25°C 40 -40°C 20 10 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 2 FIGURE 12. TURN - ON TIME vs SUPPLY VOLTAGE 3 4 5 6 7 V+ (V) 8 9 10 11 12 FIGURE 13. TURN - OFF TIME vs SUPPLY VOLTAGE 3 350 VCOM = (V+) - 1V 2 300 V+ = 12V 1 250 V+ = 5V 0 Q (pC) tTRANS (ns) 200 85°C 150 V+ = 3.3V -1 -2 25°C 100 -3 -40°C 50 -4 0 -5 2 3 4 5 6 7 8 9 10 11 0 12 2 4 6 V+ (V) 10 12 FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE 10 VIN = 0.2VP-P (V+ = 3V) V+ = 3V to 12V 20 VIN = 2.5VP-P (V+ = 3V) 30 GAIN VIN = 0.2VP-P (V+ = 13V) -3 VIN = 5VP-P (V+ = 13V) 0 PHASE 45 90 135 180 RL = 50Ω 1 10 100 FREQUENCY (MHz) FIGURE 16. FREQUENCY RESPONSE 10 600 OFF ISOLATION (dB) 0 PHASE (DEGREES) NORMALIZED GAIN (dB) FIGURE 14. ADDRESS TRANS TIME vs SUPPLY VOLTAGE +3 8 VCOM (V) 40 50 60 ISOLATION 70 80 90 100 110 1k 10k 100k 1M 10M 100M 500M FREQUENCY (Hz) FIGURE 17. OFF ISOLATION FN6043.3 January 23, 2006 ISL43640 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 193 PROCESS: Si Gate CMOS 11 FN6043.3 January 23, 2006 ISL43640 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X θ A2 A1 b -H- 0.10 (0.004) L SEATING PLANE C -A- e D 0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- END VIEW MILLIMETERS MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e L1 MIN 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - 0.07 - - R1 0.003 - 0.07 - - θ 5o 15o 5o 15o - α 0o 6o 0o 6o Rev. 0 12/02 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 12 FN6043.3 January 23, 2006 ISL43640 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.3x3 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C A D A 9 D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E 9 2X B TOP VIEW 0.15 C A A 0.90 1.00 - - - 0.05 - A2 - - 1.00 9 A3 0.20 REF 0.18 0 A3 SIDE VIEW 9 5 NX b 4X P D1 2.75 BSC 9 1.35 1.50 1.65 7, 8, 10 3.00 BSC - 2.75 BSC 1.35 1.50 9 1.65 7, 8, 10 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 16 2 Nd 4 3 Ne P - - 0.60 NX k θ - - 12 D2 2 N 5, 8 - 8 7 4 3 9 9 Rev. 1 6/04 4X P NOTES: 1 (DATUM A) 2 3 6 INDEX AREA NX L N e 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. (Ne-1)Xe REF. E2 E2/2 2. N is the number of terminals. 7 3. Nd and Ne refer to the number of terminals on each D and E. 8 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 9 CORNER OPTION 4X (Nd-1)Xe REF. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. BOTTOM VIEW A1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b 5 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. SECTION "C-C" C L 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. C L L1 0.30 3.00 BSC 0.10 M C A B D2 (DATUM B) A1 0.23 9 D e 0.08 C SEATING PLANE C C 0.80 E1 / / 0.10 C C NOTES A E2 A2 MAX A1 E 0.15 C B 8 NOMINAL D2 2X 4X MIN b E/2 E1 SYMBOL 10 L e L1 10 L 10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2 and D2 MAX dimension. e TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6043.3 January 23, 2006