TM MP8040 High Current Integrated Half Bridge + Driver The Future of Analog IC Technology TM DESCRIPTION FEATURES The MP8040 is a general purpose, high frequency half bridge power driver capable of driving a 9A load. The devices integrates both top and bottom N-Channel MOSFET power switches and is fully protected from both sourcing and sinking current by a preset cycle-by-cycle current limit. It has a wide input voltage range from 7.5V to 25V. • • • • • • • • • • • The MP8040 features a low-current shutdown mode, input under-voltage protection, thermal shutdown, and fault flag signal output. It interfaces with standard logic signals and is available in a small 8-pin SOIC with exposed pad package. APPLICATIONS • EVALUATION BOARD REFERENCE Board Number Dimensions EV0041 3.5”X x 3.5”Y x 1.2”Z ±9A Peak Current Output ±4.25A Continuous Current Output Up to 1.2MHz Switching Frequency Protected Integrated Power 100mΩ Switches All Switches Current Limited Integrated Under-Voltage Protection Integrated Thermal Protection 2.5µA Standby Mode True 2-Quadrant Operation Sources and Sinks Current Fault Indicator Output • • Class D Audio Driver o 25W/4Ω/10% Output Power Single Ended o 70W/4Ω/10% Output Power Full Bridge Full or Half Bridge DC-DC Switching Regulator Motor Driver “MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VSP 2 7 FAULT ENABLE PWM SIGNAL 8 6 1 + SP DRV FLT MP8040 SHDN BS PWM SW GND 5 3 47nF VOUT 4 MP8040_TAC_S01 MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 1 TM MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE SP Supply Voltage (VSP).............................. 28V SW Pin Voltage .............................. –0.3V to VSP SW to BS ....................................... –0.3V to +6V Voltage at All Other Pins ............... –0.3V to +6V Storage Temperature .............. –55°C to +150°C TOP VIEW PWM 1 8 FLT SP 2 7 DRV SW 3 6 SHDN GND 4 5 BS EXPOSED PAD ON BACKSIDE CONNECT TO PIN 4 Recommended Operating Conditions (2) SP Supply Voltage (VSP).................. 7.5V to 24V Peak Output Current...................... 9A Maximum Operating Temperature ............. –40°C to +85°C MP8040_PD01-SOIC8N Thermal Resistance (3) θJA θJC SOIC8N .................................. 50 ....... 8.... °C/W Part Number* MP8040DN * Package SOIC8N (Exposed Pad) Temperature –40°C to +85°C For Tape & Reel, add suffix –Z (eg. MP8040DN–Z) For Lead Free, add suffix –LF (eg. MP8040DN–LF–Z) Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. ELECTRICAL CHARACTERISTICS VSP = 12V, VSHDN = 0V, TA = +25°C, unless otherwise noted. Parameter SP Operating Current SP Shutdown Current SHDN, SP Threshold Low SHDN, SP Threshold High SHDN, SP Input Bias Current SW On Resistance SW Current Limit (4) SW Switching Frequency SW Maximum Duty Cycle (5) SW Rise/Fall Time PWM Pulse Width PWM to SW Delay Time Rising PWM to SW Delay Time Falling Thermal Shutdown Temperature (4) Symbol Condition Min VSHDN = 2V Typ 1.5 2.5 Max 2.5 10 1 2 VSP = 7.5V, High-Side and Low-Side VPWM = 5, (Sinking) VPWM = 0, (Sourcing) VPWM = 0 to 2V, 50% Duty Cycle VSP = 7.5V, VPWM = 2V, CSW 100nF, fSW = 3.3KHz VPWM = 0 to 5V VPWM = 0 to 2V, High or Low Pulse VPWM = 0 to 5V 1 0.1 9 9 1.2 Units mA µA V V µA Ω A A MHz 99.5 % 20 70 ns ns ns VPWM = 5 to 0V 70 ns TJ Rising, Hysteresis = 20°C 160 °C 200 Notes: 4) Guaranteed by design; not production tested. 5) SW drives low for 1.5µs every 300µs to charge the BS to SW capacitor. MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 2 TM MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER TYPICAL PERFORMANCE CHARACTERISTICS Circuit of Figure 4, TA = +25°C, unless otherwise noted. Delay Time SW Falling (VSP=8V) Delay Time SW Rising (VSP=8V) VPWM 2V/div. VPWM 2V/div. VSW 5V/div. VSW 5V/div. 10.0ns/div. 10.0ns/div. MP8040-TPC01 MP8040-TPC02 Delay Time SW Falling (VSP=25V) Delay Time SW Rising (VSP=25V) VPWM 2V/div. VPWM 2V/div. VSW 10V/div. VSW 10V/div. 10.0ns/div. 10.0ns/div. MP8040-TPC03 MP8040-TPC04 THD+N (%) 20 2 1 0.2 0.1 0.02 0.01 200m 1 2 10 20 OUTPUT POWER (W) 100 MP8040-TPC05 MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 3 TM MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER PIN FUNCTIONS Pin # Name 1 PWM 2 SP 3 SW 4 GND 5 BS 6 SHDN 7 DRV 8 FLT Description Driver Logic Input. Drive PWM with the signal that controls the MP8040 output. Drive PWM high to turn on the high-side switch; drive PWM low to turn on the low-side switch. Power Supply Input. Connect SP to the positive side of the input power supply. Bypass SP to GND as close to the IC as possible. Switched Output. SW is the power output of the MP8040. Connect the output LC filter to SW. SW is valid approximately 100µs after SP goes high. Ground. (Note: Connect the exposed pad on the bottom side to Pin 4). Bootstrap Supply. BS powers the high-side gate of the MP8040. Connect a 0.1µF or greater capacitor between BS and SW. Shutdown Input. SHDN enables/disables the MP8040. Drive SHDN low to turn on the MP8040, drive it high to turn it off. If not used, connect SHDN to GND. Gate Drive Supply Bypass. The voltage at DRV is supplied from an internal regulator from SP. DRV powers the internal circuitry and internal MOSFET gate drives. Bypass DRV to GND with a 0.1µF to 10µF capacitor. Fault Output. Active-low, open drain. A low output at FLT indicates that the MP8040 has detected a fault and has shutdown. Connect FLT to DRV through a 100kΩ resistor. OPERATION The MP8040 is a general purpose, power driver. It takes a logic input and drives a half bridge comprised of 0.1Ω high-side and low-side N-Channel MOSFET switches. It operates at frequencies up to 1.2MHz, can accept a DC supply voltage as high as 25V, and produce peak output current as high as 9A. 5 BS DBS BS UVLO INTERNAL 5V REG. CURRENT LIMIT & FEEDBACK DRV THERMAL SHUTDOWN UVLO 2 SP 7 HI DRIVE PWM 1 FLT 8 SHDN 6 3 SW LOGIC LO DRIVE 4 GND MP8040_F02 Figure 1—Function Block Diagram MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 4 TM MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER SW Output The SW output drives the load. It is controlled by the logic input signal at PWM. When the signal at PWM is high (above 2V), the high-side switch is turned on. When the signal at PWM is low (less than 0.4V), the low-side switch is turned on. The MP8040 uses internal N-Channel MOSFETs for both the high-side and low-side switches. The high-side MOSFET gate drive is powered from the voltage between SW and BS, allowing BS to rise above the SP input voltage to power the high-side MOSFET. To do this a bootstrap capacitor is connected between SW and BS. When the low-side switch is on, the capacitor is internally charged from the voltage at DRV, which is also internally generated. There is a dead time region (typically 40ns) where both the upper and lower switches are off (see Figure 2). Thermal Shutdown The MP8040 includes a thermal overload protection circuit. If the die temperature rises above 160°C, the output switches are turned off and the fault output is asserted. Once the thermal overload circuit is tripped, the die temperature must drop below 140°C before automatically restarting. VSP 2 SP MP8040 SW 3 GND 4 SW Both the high-side and low-side switches have internal current limits to prevent failure due to excessive load current. Once the current limit is reached, both output switches are turned off and the fault output is asserted (driven low). Shutdown The MP8040 includes a 2.5µA shutdown mode. When SHDN is high, both output switches are turned off and the input current drops to 2.5µA. When the MP8040 is shutdown, the internally generated voltage at DRV drops to 0V, and the fault output (FLT) is asserted (driven low). If the shutdown mode is not used, connect SHDN directly to GND. Fault Output The MP8040 includes a fault indicator output (FLT). This is an active-low open drain output. The MP8040 detects faults due to over-current (>9A), over-temperature (>160°C), undervoltage at SP (<6.5V), or if the part is disabled. Connect FLT to DRV or to an external voltage up to 6V through a 27kΩ or greater resistor. When any of the 3 fault conditions are detected, both output switches are turned off and the SW output is high-impedance. MP8040 Rev. 1.5 5/3/2005 VSP 3/4 VSP 1/2 VSP 1/4 VSP TIME DT (RISE) DT (FALL) DEAD TIME RISING = 20ns DEAD TIME FALLING = 40ns MP8040_F01 Figure 2—Dead Time www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 5 TM MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER TYPICAL APPLICATION CIRCUITS VSP VSP 7 2 + 2 7 SP DRV BS BS 5 8 ENABLE PWM SIGNAL 6 1 FLT FAULT FLT MP8040 SHDN PWM CONTROLLER SW 5 MP8040 6 SHDN ENABLE SW 3 VOUT 1 3 PWM SIGNAL + FAULT 8 + SP DRV PWM GND 4 PWM GND 4 MP8040_F03 MP8040_F04 Figure 3—Single Ended Audio Amplifier Figure 4—General Purpose DC to DC Converter VSP VSP + BS FAULT ENABLE 8 FLT 7 SP DRV 3 ENABLE 1 DIGITAL AUDIO SIGNAL DRV BS FAULT SW SP 5 MP8040 6 SHDN 8 FLT GND SHDN 1 PWM SIGNAL 4 SW GND 4 VSP 2 ENABLE 8 M + SP BS FAULT 5 2 7 FLT MP8040 6 SHDN 3 PWM VSP DRV 5 MP8040 6 PWM 7 + 2 2 7 SW + SP DRV BS 3 1 FAULT PWM 8 FLT GND 4 ENABLE MP8040_F05 5 MP8040 6 SHDN SW 3 1 PWM GND 4 MP8040_F06 Figure 5—80W Full Bridge Audio Amplifier MP8040 Rev. 1.5 5/3/2005 Figure 6—Full Bridge Motor Driver www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 6 TM MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER VSP + 2 7 SP DRV BS 8 I/O FAULT I2C MICRO CONTROLLER I/O FLT 5 MP8040 6 SHDN ON/OFF SW 3 1 PWM ADC1 ADC2 ADC3 PWM GND 4 MP8040_F07 Figure 7—CCFL Driver Circuit MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 7 TM MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER PACKAGE INFORMATION SOIC8N (EXPOSED PAD) NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8040 Rev. 1.5 5/3/2005 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. 8