ON NCV7471ADQ5R2G System basis chip Datasheet

NCV7471, NCV7471A
System Basis Chip with a
High-Speed CAN, Two LINs
and a Boost-Buck DC/DC
Converter
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NCV7471(A) is a System Basis Chip (SBC) integrating functions
typically found in automotive Electronic Control Units (ECUs) in the
body domain. NCV7471 provides and monitors the low−voltage
power supplies for the application microcontroller and other loads,
monitors the application software via a watchdog and includes
high−speed CAN and LIN transceivers allowing the ECU to host
multiple communication nodes or to act as a gateway unit. The
on−chip state controller ensures safe power−up sequence and supports
low−power modes with a configurable set of features including
wakeup from the communication buses or by a local digital signal
WU. The status of several NCV7471(A) internal blocks can be read by
the microcontroller through the serial peripheral interface or can be
used to generate an interrupt request.
SSOP36−EP
DQ SUFFIX
CASE 940AB
MARKING DIAGRAM
XXXX
AWLYYWWG
G
Features
• Control Logic
XXXX
♦
•
•
•
•
•
•
= NCV7471−5 or NCV7471A−5
Ensures safe power−up sequence and the correct reaction to
A
= Assembly Location
different supply conditions
WL
= Wafer Lot
YY
= Year
♦ Controls mode transitions including the power management and
WW
= Work Week
wakeup treatment − bus wakeups, local wakeups (via WU pin) and
G
= Pb−Free Package
cyclic wakeups (through the on−chip timer)
(Note:
Microdot
may be in either location)
♦ Generates reset and interrupt requests
Serial Peripheral Interface
ORDERING INFORMATION
♦ Operates with 16−bit frames
See detailed ordering and shipping information on page 50 of
♦ Ensures communication with the ECU’s microcontroller unit
this data sheet.
♦ Mode settings, chip status feedback and watchdog are accessible
through eight twelve−bits registers
♦ Can be used as a wake−up source or as a logical
5 V VOUT Supply from a DC/DC Converter
input polled through SPI
♦ Can deliver up to 500 mA with accuracy of ±2%
• Protection and Monitoring Functions
♦ Supplies typically the ECU’s microcontroller
♦ Monitoring of the main supply through the V_MID
5 V VOUT2 Low−drop Output Regulator
point
♦ Can supply external loads – e.g. sensors
♦
Monitoring of VOUT supply output with
♦ Controlled by SPI and the state machine
programmable
threshold
♦ Protected against short to the car battery
♦
VOUT2
supply
diagnosis through SPI and interrupt
A High−speed CAN Transceiver
♦
Thermal
warning
and thermal shutdown protection
♦ ISO11898−2 and ISO11898−5 compliant
♦
Programmable
watchdog
monitoring the ECU
♦ Communication speed up to 1 Mbps
software
♦ TxD dominant time−out protection
• NCV Prefix for Automotive and Other Applications
Two LIN Transceivers
Requiring Unique Site and Control Change
♦ LIN2.X and J2602 compliant
Requirements; AEC−Q100 Qualified and PPAP
♦ TxD dominant time−out protection
Capable
Wakeup Input WU
•
These Devices are Pb−Free, Halogen Free/BFR Free
♦ Edge−sensitive high−voltage input
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 4
1
Publication Order Number:
NCV7471/D
NCV7471, NCV7471A
1
36
V_MID
BOOST
CFG
FSO1
FSO2
FSO3
GND_SMPS
WU
VS
VS_VOUT2
GND
CANH
CANL
TEST/GND
LIN1
GND
LIN2
SWDM
RSTN
INTN
UVN_VOUT
SDI
SCK
SDO
CSN
BUCK
GND_SENSE
VOUT
VCC_CAN
VOUT2
TxDC
RxDC
TxDL1
RxDL1
TxDL2
RxDL2
18
19
Pin Connections
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Example Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Communication Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WU – Local Wakeup Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Event Flags and Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Junction Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FSO1/2/3 – Fail-Safe Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SWDM and CFG Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LIN Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Digital Control Timing and SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Digital IO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CFG and SWDM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FSO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
WU Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Device Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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NCV7471, NCV7471A
BOOST
V_MID
BUCK
VOUT
DC/DC CONVERTER
GND_SMPS
CFG
Supply monitoring
Auxiliary blocks
SWDM
VS
VS_VOUT2
RSTN
LDO
50 mA
VOUT2
INTN
WU
FSO1
FSO
UVN_VOUT
FSO
CONTROL
FSO
SDI
FSO2
FSO3
SDO
SCK
LIN transceiver
CSN
LIN transceiver
LIN1
LIN2
TxDL1
RxDL1
VCC_CAN
TxDL2
CANH
RxDL2
CAN transceiver
CANL
TxDC
RxDC
GND_SENSE
GND
NCV7471(A)
Figure 1. Block Diagram
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3
TEST/GND
NCV7471, NCV7471A
Table 1. PIN DESCRIPTION
Pin
Number
Pin Name
Pin Type
(LV = Low Voltage; HV = High Voltage)
1
RSTN
LV digital input/output; open drain;
internal pull−up
2
INTN
LV digital output; open drain; internal pull−up
3
UVN_VOUT
4
SDI
LV digital input; internal pull−down
SPI data input
5
SCK
LV digital input; internal pull−down
SPI clock input
6
SDO
LV digital output; push−pull with tri−state
SPI data output
7
CSN
LV digital input (HV tolerant); internal pull−up
8
BUCK
HV analog input/output
9
GND_SENSE
Ground connection
10
VOUT
LV supply input
Feedback of the DC/DC converter output; main 5 V LV
supply for the digital IO’s
11
VCC_CAN
LV supply input
Core supply for the CAN transceiver
12
VOUT2
LV supply output
13
TxDC
LV digital input; internal pull−up
Pin Function
System reset
Interrupt request to the MCU
VOUT under−voltage signal to the MCU
SPI chip select input
Connection of Lbuck coil to the integrated serial switch
Ground sense for the internal circuitry (e.g. VOUT2 regulator)
Output of the 5 V/50 mA low−drop regulator for external loads
Input of the data to be transmitted on CAN bus
14
RxDC
LV digital output; push−pull
15
TxDL1
LV digital input; internal pull−up
Output of data received from CAN bus
16
RxDL1
LV digital output; push−pull
17
TxDL2
LV digital input; internal pull−up
18
RxDL2
LV digital output; push−pull
19
SWDM
HV digital input; internal pull−down
Input of the data to be transmitted from LIN1 bus
Output of data received on LIN1 bus
Input of the data to be transmitted from LIN2 bus
Output of data received on LIN2 bus
Input to select the SW Development configuration
20
LIN2
LIN bus interface
21
GND
Ground connection
LIN2 bus line
22
LIN1
LIN bus interface
23
TEST/GND
LV digital input; internal pull−down
24
CANL
CAN bus interface
CANL line of the CAN bus
25
CANH
CAN bus interface
CANH line of the CAN bus
26
GND
Ground connection
Ground connection
27
VS_VOUT2
HV supply input
Separate line input for the VOUT2 low−drop regulator
28
VS
HV supply input
Line supply for the battery−related core blocks
Input for monitoring of external contacts
Ground connection
LIN1 bus line
Test−mode entry pin for production testing; should be
grounded in the application
29
WU
HV digital input
30
GND_SMPS
Ground connection
31
FSO3
HV digital output; open drain low−side
Indication of a fail−safe event by rectangular signal of 100 Hz
with 20% duty cycle; high−impedant in normal operation
32
FSO2
HV digital output; open drain low−side
Indication of a fail−safe event by rectangular signal of 1.25 Hz
with 50% duty cycle; high−impedant in normal operation
33
FSO1
HV digital output; open drain low−side
Indication of a fail−safe event by static Low level;
high−impedant in normal operation
34
CFG
HV digital input; internal pull−down
35
BOOST
HV analog input/output
Connection of Lboost coil to the integrated switch to ground.
36
V_MID
HV analog input/output
Intermediate point connecting the step−up and step−down
stages of the DC/DC converter
Power ground connection for the DC/DC converter
Configuration of fail−safe behavior; in SW Development,
CFG enables boost stage operation
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NCV7471, NCV7471A
APPLICATION INFORMATION
Figure 2. Example Application Diagram
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NCV7471, NCV7471A
External Components
Overview of external components from application schematic in Figure 2 is given in Table 2 together with their recommended
or required values.
Table 2. EXTERNAL COMPONENTS OVERVIEW
Component Name
Description
Value
Note
Drev
Reverse−protection diode
parameters application−specific;
e.g. 0.5 A / 50 V
Cin
Filtering capacitor for the DC/DC
converter input
≥ 1 mF ceramic;
e.g. 1 mF / 40 V
Lboost
Inductor for the converter boost stage;
EMC filtering inductance
recommended range 3.3 mH – 10 mH;
e.g. 3.3 mH / 0.77 A,
type B82422H1332+000
D1
Diode for the converter boost stage
Shottky or ultra−fast; parameters
application−specific; e.g. 0.5 A / 50 V
Cmid
Filtering and stabilization capacitor for the
converter intermediate voltage
≥ 1 mF ceramic;
e.g. 1 mF / 40 V
D2
Diode for the converter buck stage
Shottky or ultra−fast;
parameters application−specific;
e.g. 0.25 A / 50 V
Lbuck
Inductor for the converter buck stage
recommended range 10 mH – 22 mH;
e.g. 10 mH / 0.5 A,
type B82422H1103+000
Cout
Filtering and stabilization capacitor for the
converter output voltage
≥ 10 mF ceramic; e.g. 10 mF / 10 V
CVS
Filtering capacitor for the VS input
supplying LIN and auxiliary internal circuitry
recommended >100 nF ceramic
optional; depends on the
application PCB
Cin2
Filtering capacitor for the VOUT2
regulator input
recommended >100 nF ceramic
optional; depends on the
application PCB
Cout2
Filtering and stabilization capacitor for the
VOUT2 regulator output
>1 mF ceramic
(recommended 2.2 mF nominal)
required for
VOUT2 stability
RWU
Protection and filtering resistor
for the WU input
recommended 33 kW nominal
optional; depends on the
application needs
RFSO
Values and types depend
on the application needs
and conditions. Guidelines
for their selection can be
found in the product’s
application note.
The given examples are
suitable for VOUT loads of
up to 250 mA, and for
V_IN above 3.3 V.
depends on the
application needs
required only for master
LIN node
DPU_LIN
Pull−up diode on LIN line
RPU_LIN
Pull−up resistor on LIN line
1 kW nominal
CLIN
Filtering capacitor on LIN line
Typically 100 pF – 220 pF nominal
optional; is function of the
entire LIN network
CVCC_CAN
Filtering capacitor on the CAN transceiver
supply input
recommended >100 nF ceramic
optional; depends on the
application PCB
CAN termination
and protection
optional; is function of the
entire CAN network
RPU_DIG
Pull−up resistor for the open−drain digital
outputs (INTN, RSTN, UVN_VOUT)
recommended 10 kW nominal
optional; only if the
integrated pull−ups are
not sufficient for the
application
RSWDM
Protection resistor on SWDM input
recommended 10 kW nominal
optional; depends on the
application
RCFG
Protection resistor on CFG input
recommended 10 kW nominal
optional; depends on the
application
CFG connection details
can be found in the
product’s application note.
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NCV7471, NCV7471A
FUNCTIONAL DESCRIPTION
POWER SUPPLIES
circuit remains functional until V_MID falls back below
V_MID_PORL level, when the device enters the Shut−down
mode.
VS Supply Input
VS pin of NCV7471(A) is typically connected to the car
battery through a reverse−protection diode and can be
exposed to all relevant automotive disturbances (ISO7637
pulses, system ESD...). VS supplies mainly the integrated
LIN transceivers. Filtering capacitors should be connected
between VS and GND.
VOUT DC/DC Converter
The main application low−voltage supply is provided by
an integrated boost−buck DC/DC converter, delivering a
5 V output VOUT. The converter can work in two modes:
• Buck−only mode is the default mode of the VOUT
power−supply. In this mode, the boosting part of the
converter is never activated and the resulting VOUT
voltage can be only lower than the input line voltage.
Buck−only mode is applied during the initial power−up
(after the V_IN connection), wakeup from Sleep−mode
and also recovery from the Fail−safe mode.
• Boost−buck mode ensures that the correct VOUT
voltage is generated even if the input line voltage falls
below the required VOUT level. This mode can be
requested through the corresponding SPI control
register. If selected, the boost−buck mode is used
during Reset, Start−up, Normal, Standby, and Flash
modes. It is also preserved during VOUT
under−voltage recovery through Power−up mode. In
SW Development configuration, boost−buck mode can
be additionally enabled by High level on CFG pin. No
SPI communication is therefore necessary to select the
DC/DC mode in SW Development – see Table 3.
V_MID Supply Point
V_MID node is the connection point between the two
stages of the DC/DC converter. If only the buck (i.e.
step−down) function of the converter is active (because the
input voltage is sufficient or because boosting is not
enabled), V_MID level stays two diode drops below the
battery input to the application – see Figure 2. In case the
boost stage of the converter is active, V_MID voltage is
regulated to V_MID_reg (6.5 V typically).
V_MID pin is used to supply the core auxiliary blocks of
the device – namely the voltage reference, biasing, internal
regulator and the wakeup detector of the CAN bus. When the
DC/DC converter is boosting, it is ensured that the internal
core blocks remain functional even for low input supply level.
During power−up of the battery supply, V_MID point
must reach V_MID_PORH level in order for the circuit to
become functional – the internal state machine is initiated
and the converter is activated in buck−only mode. The
Table 3. CONTROL OF DC/DC CONVERTER MODES (“X” Means “Don’t Care”)
Device Configuration
SPI enBOOST Bit
Signal on CFG Pin
Low
Applied DC/DC Mode
Buck−Only
Config 1, 2, 3, 4
X
High
Boost−Buck
Low
SW Development
High
Low
Buck−Only
High
Boost−Buck
X
Boost−Buck
• VOUT is compared with a fixed threshold VOUT_FAIL
By default, the converter works with a fixed switching
frequency fsw_DCDC (typ. 485 kHz). Through the SPI
settings, a switching frequency modulation can be applied
with fixed modulation frequency of 10 kHz and three
selectable modulation depth values – 10%, 20% or 30% of
the nominal frequency.
VOUT level is monitored by an under−voltage detector
with multiple thresholds:
• Comparison with selectable threshold VOUT_RESx. By
default, the lowest threshold (typ. 3.1 V) applies for the
state machine control and the activation of the RSTN
signal. This reset threshold can be changed via SPI to
any of the four programmable values.
• A second monitoring signal – UVN_VOUT − is
generated based on comparison of the VOUT level with
the highest monitoring level (typ. 4.65 V).
(typ. 2 V). If VOUT stays below VOUT_FAIL level for
longer than t_VOUT_powerup, a VOUT short−circuit is
detected and Fail−safe mode is entered with the
corresponding fail−safe information stored in SPI.
Both UVN_VOUT and RSTN pins provide an open drain
output with integrated pull−up resistor. The split between
reset−generating level VOUT_RESx and an under−voltage
indication allows coping with VOUT dips in case of high
loads coinciding with low input line voltages. The function
of the VOUT and V_MID monitoring is illustrated in
Figure 3 and Figure 4. FSO1 output activation and Fail−safe
mode entry caused by VOUT undervoltage are shown in
Figure 5 and Figure 6 (NCV7471A only).
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NCV7471, NCV7471A
Figure 3. V_MID and VOUT Supply Monitoring (Filtering times are neglected)
Figure 4. VOUT Monitoring
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NCV7471, NCV7471A
Figure 5. VOUT Monitoring (NCV7471A Only)
Figure 6. VOUT Monitoring (NCV7471A Only)
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NCV7471, NCV7471A
VOUT2 Auxiliary Supply
VCC_CAN Transceiver Supply
An integrated low−drop regulator provides a second 5 V
supply VOUT2 to external loads, typically sensors. The
regulator’s input is taken from a dedicated pin VS_VOUT2,
which does not feature an explicit under−voltage
monitoring. VS_VOUT2 would be typically connected to
the VS pin or, in function of the application needs, might be
taken from other nodes like, e.g., the DC/DC converter’s
auxiliary node V_MID.
After a power−up or a reset event, as well as in Sleep
mode, VOUT2 regulator is switched off. In Start−up,
Normal, Standby and Flash modes, it can be freely activated
or deactivated via SPI control register.
VOUT2 is diagnosed for under−voltage and over−voltage
via comparators with fixed thresholds VOUT2_UV and
VOUT2_OV, respectively. Under−voltage detection is
working only when VOUT2 regulator is on, while the
over−voltage is monitored regardless the VOUT2 regulator
activation. Output of both detectors can be polled via SPI
status bits. Change of the detection status (in either
direction) is recorded as an SPI flag bit and, if enabled, can
lead to an interrupt.
The integrated CAN transceiver uses a dedicated supply
input VCC_CAN. The transceiver is supplied by
VCC_CAN when configured for full−speed transmission or
reception. When configured for wakeup detection, the
transceiver is internally supplied from the V_MID pin.
A 5 V supply must be externally connected to VCC_CAN
pin for the correct transceiver’s functionality in full−speed
mode (“CAN Normal” or “CAN Receive−only”).
VCC_CAN input has no dedicated monitoring and its
correct level shall be ensured by the application – e.g. if
VOUT is connected to VCC_CAN, then VOUT
under−voltage monitoring can also cover the correct
VCC_CAN level.
Communication Transceivers
High−Speed CAN Transceiver
NCV7471(A) contains a high−speed CAN transceiver
compliant with ISO11898−2 and ISO11898−5 standards,
consisting of a transmitter, receiver and wakeup detector.
The CAN transceiver can be connected to the bus line via a
pair of pins CANH and CANL, and to the digital control
through pins TxDC and RxDC. The functional mode of the
CAN transceiver depends on the chip operating mode and on
the status of the corresponding SPI bits – see Table 4, Table 5
and Figure 7.
Table 4. CAN TRANSCEIVER SPI CONTROL
SPI Control Bits
modCAN.1
CAN Transceiver Function in Operating Modes
modCAN.0
Power−up
Reset
Start−up
Normal Flash
Standby
Fail−safe
(except thermal shut−down)
Sleep
0
0
CAN Off
CAN Off
CAN Off
CAN Off
CAN Wakeup
0
1
CAN Off
CAN Wakeup
CAN Wakeup
CAN Wakeup
CAN Wakeup
1
0
CAN Off
CAN
Receive−only
CAN
Receive−only
CAN Off
CAN Wakeup
1
1
CAN Off
CAN Normal
CAN Off
CAN Off
CAN Wakeup
Table 5. CAN TRANSCEIVER MODES
Mode
Transceiver
RxDC Pin
TxDC Pin
CANH/CANL Pins
Supply
CAN Off
Fully off
High (if VOUT available)
Ignored
Biased to GND
n.a.
CAN Wakeup
Wakeup
detector active
Low if wakeup detected;
High otherwise
(if VOUT available)
Ignored
Biased to GND
V_MID
CAN Receive−Only
Receiver active
Received data
Ignored
Biased to VCC_CAN/2
VCC_CAN
CAN Normal
Transmitter and
Receiver active
Received data
Data to transmit;
checked for time−out
Biased to VCC_CAN/2
VCC_CAN
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10
NCV7471, NCV7471A
CAN Mode
CAN Off
CAN Wake−up
CAN Receive−only
CAN Normal
CAN Supply
V_MID
VCC_CAN
Bias of Bus
Pins
to GND
to VCC_CAN/2
CANH/CANL
TxDC
RxDC
Wakeup flag
read & cleared
CAN wakeup
detected
t_TxDC_timeout
Figure 7. CAN Transceiver Modes
The total length of the pattern may not exceed
t_CAN_wake_timeout. The CAN wakeup handling is
illustrated in Figure 8.
In function of the current operating mode, a CAN wakeup
can lead either to an interrupt request or to a reset. A CAN
wakeup is also indicated by a Low level on the RxDC pin
(which otherwise stays High as long as VOUT is available).
Logical level on TxDC pin is ignored. The bus pins remain
weakly biased to ground in the wakeup CAN mode.
In CAN Off mode, the CAN transceiver is fully
deactivated. Pin RxDC stays High (as long as VOUT is
provided) and logical level on TxDC is ignored. The bus
pins are weakly biased to ground via the input impedance.
In CAN Wakeup mode, the CAN transceiver, being
supplied purely from V_MID pin, detects wakeups on the
CAN lines. A valid wakeup on the CAN bus corresponds to
a pattern of two dominants at least t_CAN_wake_dom long,
interleaved by a recessive at least t_CAN_wake_rec long.
CAN wakeup
detected
< t_CAN_wake_dom
> t_CAN_wake_dom
> t_CAN_wake_dom
> t_CAN_wake_rec
CANH/CANL
dominant too
short
wakeup in
Start−up, Normal,
Standby, Flash
wakeup from
Sleep mode
< t_CAN_wake_timeout
RSTN
INTN
INTN
RxDC
Figure 8. CAN Wakeup Detection
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11
Wakeup flag
read&cleared
via SPI
NCV7471, NCV7471A
TxDC is Low for longer than t_TxDC_timeout), the
transmission is internally disabled. The reception from the
CAN bus remains functional and the internally set CAN
transceiver mode does not change. The transmission is again
enabled when TxDC becomes High.
In CAN Receive−Only mode, the receiver part of the
CAN block detects data on the bus with the full speed and
signals them on the RxDC pin. Logical level on TxDC pin
is ignored. The receiver is supplied from the VCC_CAN
supply input. The bus pins are biased to VCC_CAN/2 level
through the input circuitry.
In CAN Normal mode, the full CAN transceiver
functionality is available. Both reception and transmission
at the full speed can be used. Received data are signaled via
RxDC pin, while logical level on TxDC pin is translated into
the corresponding bus level (TxDC = High or Low leading
to a recessive or dominant being transmitted, respectively).
Both the receiving and the transmitting part are supplied
from the VCC_CAN supply input. The bus pins are biased
to VCC_CAN/2 level through the input circuitry. TxDC
input signal is monitored with a time−out timer. If a
dominant longer than t_TxDC_timeout is requested (i.e.
LIN Transceivers
NCV7471(A) integrates two on−chip LIN transceivers −
interfaces between physical LIN buses and the LIN protocol
controllers compatible to LIN2.1 and J2602 specifications
− consisting of a transmitter, receiver and wakeup detector.
Each LIN transceiver can be connected to the bus line via
LINx pin, and to the digital control through pins TxDLx and
RxDLx. The functional mode of the LIN transceivers
depends on the chip operating mode and on the status of the
corresponding SPI bits – see Table 6, Table 7, and Figure 9.
The LIN transceivers are supplied directly from the VS pin.
Table 6. LIN TRANSCEIVERS SPI CONTROL
SPI Control Bits x = 1 ... 2
modLINx.1
modLINx.0
LINx Transceiver Function in Operating Modes
Power−up
Reset
Start−up
Normal Flash
Standby
Sleep
Fail−safe
(except thermal shut−down)
0
0
LINx Off
LINx Off
LINx Off
LINx Off
LINx Wakeup
0
1
LINx Off
LINx Wakeup
LINx Wakeup
LINx Wakeup
LINx Wakeup
1
0
LINx Off
LINx
Receive−only
LINx
Receive−only
LINx Off
LINx Wakeup
1
1
LINx Off
LINx Normal
LINx Normal
LINx Off
LINx Wakeup
Table 7. LIN TRANSCEIVERS MODES
Mode
Transceiver
RxDLx Pin
TxDLx Pin
LINx Pin Bias
LINx Off
Fully off
High (if VOUT available)
Ignored
Pull−up current source to VS
LINx Wakeup
Wakeup
detector active
Low if wakeup detected;
High otherwise
(if VOUT available)
Ignored
Pull−up current source to VS
LINx Receive−Only
Receiver active
Received data
Ignored
Pull−up current source to VS
LINx Normal
Transmitter and
Receiver active
Received data
Data to transmit;
checked for time−out
(if enabled via SPI);
transmitted if
VS>VS_MON
30 kW pull−up
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12
NCV7471, NCV7471A
LINx Off
LINx Mode
Bus Pin
Pull−up
LINx Wake−up
LINx Receive−only
Current Source
LINx Normal
30 kW Resistor
recessive
LINx
dominant
TxDLx
RxDLx
LIN wakeup
detected
Wakeup flag
read & cleared
t_TxDL_timeout
if TxDL time−
out disabled
Figure 9. LIN Transceiver Modes
detected in case of a permanent LIN short to GND, because
a rising edge on LIN is necessary for the wakeup detection
– see Figure 10.
In function of the current operating mode, a LIN wakeup
can lead to an interrupt request or to a reset. A LIN wakeup
is also indicated by a Low level on the corresponding
RxDLx pin (which otherwise stays High as long as VOUT
is available). Logical level on TxDLx pin is ignored; bus pin
is internally pulled to VS with a current source.
In LINx Off mode, the respective LIN transceiver is fully
deactivated. Pin RxDLx stays High (as long as VOUT is
provided) and logical level on TxDLx is ignored. The bus
pin is internally pulled to VS with a current source (thus
limiting VS consumption in case of a permanent LINx short
to GND).
In LINx Wakeup mode, the LIN transceiver detects
wakeups on the LIN line. A valid wakeup on the LIN bus
corresponds to a dominant at least t_LIN_wake long,
followed by a recessive. Thus the wakeup will not be
< t_LIN_wake
LIN wakeup
detected
t_LIN_wake
recessive
LINx
wakeup in
Start−up, Normal,
Standby, Flash
wakeup from
Sleep mode
dominant
RSTN
INTN
INTN
RxDLx
Figure 10. LIN Wakeup Detection
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13
Wakeup flag
read&cleared
via SPI
NCV7471, NCV7471A
WU − Local Wakeup Input
In LINx Receive−Only mode, the receiver part of the
LINx block detects data on the bus with the normal speed
and signals them on the RxDLx pin. Logical level on TxDLx
pin is ignored; bus pin is internally pulled to VS with a
current source.
In LINx Normal mode, the full LIN transceiver
functionality is available. Both reception and transmission
at the normal speed can be used. Received data are signaled
via RxDLx pin, while logical level on TxDLx pin is
translated into the corresponding bus level (TxDLx = High
or Low leading to a recessive or dominant being transmitted,
respectively). The LINx pin is internally pulled to VS via a
30 kW resistive path. TxDLx input signal is monitored with
a time−out timer. If a dominant longer than t_TxDL_timeout
is requested (i.e. TxDLx is Low for longer than
t_TxDL_timeout), the transmission is internally disabled.
The reception from the LINx bus remains functional and the
internally set LINx transceiver mode does not change. The
transmission is again enabled when TxDLx becomes High.
The TxDL dominant time−out feature can be disabled via
SPI (a common setting for both LIN blocks).
Transmission onto the bus is blocked if VS supply falls
below VS_MON level. VS monitoring does not influence the
LIN reception or the TxDLx time−out detection. Indication
of the VS monitoring is accessible through SPI bit
statVS_LOW.
For applications with lower required bit rates, the
transmitted LIN signal slope can be decreased by a dedicated
SPI setting (“LIN low−slope mode”).
< t_WU_filt
t_WU_filt
WU pin is a high−voltage input typically used to monitor
an external contact or switch. A stable logical level of the
WU signal is ensured even without an external connection:
• if the WU level is High for longer than t_WU_filt, an
internal pull−up current source is connected to WU
• if the WU level stays Low for longer than t_WU_filt, an
internal pull−down current source is connected to WU
The logical level on pin WU can be polled through SPI or
used as a wakeup source:
• WU Signal Polling: in Start−up, Normal, Standby and
Flash modes, the current WU logical level is directly
reflected in SPI bit statWU, available for readout
• WU Edge Detection / Wake−up: by setting SPI bits
modWU.1 and modWU.0, edge detection is applied to
WU signal. The device can be set to detect rising,
falling or both edges on the WU signal. When the
selected edge is detected, the event is latched in SPI bit
flagWakeWU. In function of the current operating
mode, edge on WU leads to an interrupt request
(Start−up, Normal, Standby and Flash modes) or reset
(Sleep mode). More details on the event handling,
applicable also to WU edges, are given in the Event
Flags and Interrupt Requests section.
Handling of the WU pin signal is illustrated in Figure 11.
< t_WU_filt
t_WU_filt
WU
Vth_WU
(with hystheresis)
internal WU
connection
Pull−up current
Pull−down current
Pull−up current
SPI read−out
(if available)
t_WU_del
t_WU_del
WU rising edge
detected
WU falling edge
detected
Figure 11. WU Pin Handling
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NCV7471, NCV7471A
Operating Modes
The principal operating modes of NCV7471(A) are shown in Figure 12 and described in the following paragraphs.
wake−up or
V_MID < V_MID_PORL
thermal shut−down recovery
FAIL−SAFE
− VOUT: off
− VOUT2: off
− Watchdog: off
− RSTN: Low
− UVN_VOUT: Low
− SPI: off
− CAN, LINx, WU: wake−up
(except thermal shutdown)
Any
mode
Failure
Event
SHUT−DOWN
− VOUT: off
− VOUT2: off
− Watchdog: off
− RSTN: Low
− UVN_VOUT: Low
− SPI: off
− CAN, LINx: off
V_MID > V_MID_PORH
SPI
CONFIGURATION
SLEEP
− read and store SWDMN pin state
− read and store CFG pin state
− VOUT: off
− VOUT: off
− VOUT2: off
− Watchdog: off
− RSTN: Low
− UVN_VOUT: Low
− SPI: off
− CAN, LINx: per SPI
wake−up
VOUT < VOUT_RESx
WD service OK
(if enabled)
STANDBY
− VOUT: on
− VOUT2: per SPI
− Watchdog: time−out/off/cyclic
wake
− RSTN: High
Any Mode
with VOUT Active
SPI
− UVN_VOUT: UV indication
− SPI: on
− CAN, LINx: per SPI
− VOUT: on
− VOUT2: off
− Watchdog: off
− RSTN: Low
− UVN_VOUT: Low (=UV indication)
− SPI: off
− CAN, LINx: off
WD service OK
After Flash
SPI request
FLASH
− VOUT: on
− VOUT2: per SPI
− Watchdog: time−out
− RSTN: High
− UVN_VOUT: UV indication
− SPI: on
− CAN, LINx: per SPI
Flash mode
SPI request
SPI
− VOUT: on
− VOUT2: per SPI
− Watchdog: time−out
− RSTN: High
− UVN_VOUT: UV indication
− SPI: on
− CAN, LINx: per SPI
(normal in SWD configuration)
Figure 12. Operating Modes
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15
Wrong Mode
Request
t_VOUT_reset
elapsed
START−UP
WD service OK
− VOUT: on
− VOUT2: off
− Watchdog: off
− RSTN: Low
− UVN_VOUT: UV indication
− SPI: off
− CAN, LINx: off
Reset Mode
Requested
− VOUT: on
− VOUT2: per SPI
− Watchdog: window/time−out
− RSTN: High
− UVN_VOUT: UV indication
− SPI: on
− CAN, LINx: per SPI
RESET
start timer t_VOUT_reset
RSTN Pin
Forced Low
NORMAL
VOUT > VOUT_RESx
Missed
Watchdog
SPI
Normal mode
SPI request
SPI
POWER−UP
NCV7471, NCV7471A
Shut−Down Mode
watchdog and fail−safe behavior of the chip, respectively.
After leaving the Configuration mode, the device
configuration can be changed neither by the SPI
communication nor by signal modifications on the SWDM
and CFG pins and is kept until the next V_MID
under−voltage. The application software can also force
Configuration mode by an SPI request from Start−up or
Normal mode. Table 8 summarizes the available
configurations and their characteristics. After reading both
pins’ levels, NCV7471(A) automatically transitions into the
Power−up mode. Because the SMPS is off in Configuration
mode, SPI−initiated transition from a functional mode to
Configuration may result in a short dip on VOUT, which is
not disturbing the device operation and which is recovered
immediately after the Configuration mode is left.
CFG pin connection details can be found in the product’s
application note.
Two SPI bits are foreseen to reflect the state of SWDM
and CFG pins:
• statSWDM bit latches the SWDM pin logical value read
during Configuration mode. The bit remains unchanged
until the Configuration mode is entered again.
• statCFG bit either latches the CFG value read in
Configuration mode and remains unchanged afterwards
(in Config 1,2,3,4), or keeps reflecting the current CFG
signal throughout the IC operation (in SW
Development).
The Shut−down mode is a passive state, in which all
NCV7471(A) resources are inactive. The Shut−down mode
provides a defined starting point for the circuit in case of
supply under−voltage or the first supply connection.
Both on−chip power−supplies – VOUT and VOUT2 – are
switched off and the CAN/LINx transceiver pins (CANH,
CANL and LINx) remain passive so that they do not disturb
the communication of other nodes connected to the buses.
No wakeups can be detected. The SPI interface is disabled
(SDO pin remains high−impedant). Pins RSTN and
UVN_VOUT are forced Low – RSTN/UVN_VOUT Low
level is guaranteed, when V_MID supply is above
V_MID_DigOut_Low or VOUT pin is above
VOUT_DigOut_Low. Pins RxDx are kept High (i.e. at
VOUT level).
The Shut−down mode is entered asynchronously
whenever the V_MID level falls below the power−on−reset
level V_MID_PORL.
The Shut−down mode is left only when the V_MID
supply exceeds the high power−on−reset level
V_MID_PORH. When exiting the Shut−down mode,
NCV7471(A) always enters the Configuration mode.
Configuration Mode
Configuration is a transient mode, in which NCV7471(A)
reads logical input levels on pins SWDM and CFG. The
SWDM and CFG values in Configuration mode define
Table 8. POSSIBLE CONFIGURATIONS (“X” Means “Don’t care”)
FastFSON
SPI bit
Values Latched
in Configuration Mode
SWDM
Resulting
Configuration
Behavior
CFG
At Watchdog Failure
1st
At RSTN Clamped Low
1
0
1
Config 1
failure activates FSOx;
Fail−safe mode not entered
FSOx activated;
external reset controls the
operating mode
1
0
0
Config 2
1st failure puts the chip into
Fail−safe mode
FSOx activated;
Fail−safe mode entered
0
0
1
Config 3
2nd failure activates FSOx;
Fail−safe mode not entered
FSOx activated; external reset
controls the operating mode
0
0
0
Config 4
2nd failure activates FSOx and
puts the chip into Fail−safe mode
FSOx activated;
Fail−safe mode entered
X
1
X
SW Development
No FSOx activation; no Fail−safe
mode entry; stored in SPI, can
lead to interrupt (if enabled)
External reset controls the
operating mode; no FSOx
activation
Power−Up Mode
SPI interface is disabled (SDO pin remains high−impedant).
Pins RSTN and UVN_VOUT are forced Low. Pins RxDx
are kept High (i.e. at VOUT level).
The Power−up mode is entered from the Configuration
mode or after a wakeup from Sleep mode (in both cases,
VOUT DC/DC converter needs to be activated). It will be
also entered from any state with VOUT already active
(Normal, Standby, Reset, Start−up, Flash) if the VOUT level
falls below the VOUT_RESx level (the valid VOUT_RESx
level is set via SPI).
The Power−up mode ensures correct activation of the
on−chip VOUT DC/DC converter or recovery of VOUT
after an under−voltage event.
In the Power−up mode, the VOUT DC/DC converter is
switched on (or kept on) while VOUT2 regulator remains in
the previous state (e.g. VOUT2 is off coming from the
Shut−down and Configuration modes). The CAN/LINx
transceiver pins (CANH, CANL and LINx) remain passive
so that they do not disturb the communication of other nodes
connected to the buses. No wakeups can be detected. The
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16
NCV7471, NCV7471A
Start−Up Mode
The Power−up mode is correctly left when VOUT
exceeds the SPI−selected VOUT_RESx level. An
overload/short−circuit failure is detected if VOUT does not
reach the failure threshold VOUT_FAIL within time
t_VOUT_powerup. NCV7471(A) then goes to the Fail−safe
mode. VOUT staying between VOUT_FAIL and
VOUT_RESx levels will keep the device in the Power−up
mode, unless the thermal shutdown temperature is reached
(e.g. because of VOUT overload).
During the Start−up mode, the microcontroller supplied
by VOUT is expected to initialize correctly and to perform
successful communication via the SPI interface.
Start−up mode is the first mode in which SPI is enabled
and the watchdog is started. The application software is able
to read any SPI register. Write access to SPI depends on the
FSO_internal flag (i.e. whether a failure condition preceded
the Start−up mode – see the FSO1/2/3 − Fail−safe Outputs
section for details):
• In case FSO_internal = 0 (inactive), any SPI register
can be written and all features can be configured in the
Start−up mode (e.g. CAN/LIN transceivers can be
activated, VOUT2 can be activated)
• In case FSO_internal = 1 (active), all SPI write frames
will be ignored by the chip, with the exception of the
watchdog service frame (write access to the
MODE_CONTROL register).
Reset Mode
The Reset mode is a transient mode providing a defined
RSTN pulse for the application microcontroller.
VOUT supply is kept on, while VOUT2 regulator remains
in its previous state. The CAN/LINx transceiver pins
(CANH, CANL and LINx) are passive so that they do not
disturb the communication of other nodes connected to the
buses. No wakeups can be detected. The SPI interface is
disabled (SDO pin remains high−impedant). Pin RSTN is
forced Low while pin UVN_VOUT indicates the VOUT
under−voltage with respect to the highest reset level. Pins
RxDx are kept High (i.e. at VOUT level).
Reset mode will be entered as a consequence of one of the
following events:
• Power−up mode is exited
• RSTN pin is forced Low externally
• Flash mode has been requested via SPI
• Flash mode exit has been requested via SPI
• Reset mode has been requested via SPI
• An un−authorized operating mode has been requested
via SPI
• Watchdog has been missed in Config 1 or Config 3
The watchdog is activated and works in the timeout mode.
A correct watchdog service is expected from the MCU
before the watchdog period elapses. The correct
watchdog−serving SPI message should arrive in time and
should contain either a request to enter Normal mode or a
request to enter the Flash mode. The Start−up mode is then
exited into the requested mode.
If the microcontroller software fails to serve the watchdog
in time, the chip detects the “1st Watchdog Missed” event
which is handled according the configuration (SW
Development or Config 1/2/3/4) – see the FSO1/2/3 −
Fail−safe Outputs section.
In the SW Development configuration, the following
exceptions are applied for the Start−up mode:
• the device remains in the Start−up mode as long as the
watchdog is not served correctly – thus also in case no
microprocessor is connected.
• when entering the Start−up mode, CAN and both LIN
transceivers are automatically put to their Normal mode
Normally, the Reset mode is left after a defined time
t_VOUT_reset when the RSTN pin is internally released to
High – the chip then goes to the Start−up mode. Overdriving
the RSTN pin to Low externally will extend the Reset mode
duration. If RSTN is still forced Low externally even after
time t_VOUT_Clamped_Low elapses, a “RSTN clamped
Low” event is detected. The reaction depends on the chip
configuration (SW Development or Config 1/2/3/4).
“RSTN clamped Low” can lead to FSOx signal activation,
Fail−safe mode entry or just to the Reset mode being kept as
long as RSTN is driven Low – see Table 9.
If the Reset mode is entered due to external RSTN Low
pulse during Start−up mode, FSOx outputs are activated
(unless the device is in the SW Development configuration).
This condition fosters that the external MCU sends at least
one correct watchdog message before applying an external
reset.
Information about the cause of a reset pulse is stored in the
SPI registers and can be read by the application software.
The “Reset source” information is kept unchanged until the
next reset event.
As a result, device in SW Development mode keeps on
providing VOUT supply and full CAN and LIN
functionality even if no application software is available or
if no microprocessor is connected. In addition, no RSTN
pulses are generated and FSOx pins remain inactive.
Normal Mode
The Normal mode allows using all NCV7471(A)
resources (VOUT2, CAN transceiver, LINx transceivers)
which can be monitored and configured by the
microcontroller via the SPI interface. The watchdog is
working in the window mode with selectable period which
can be changed at each watchdog−service SPI message.
VOUT is kept on. INTN pin provides the Interrupt
Requests (IRQ’s) depending on the device status and the
interrupt mask settings. The application software can poll all
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NCV7471, NCV7471A
watchdog are de−activated. Depending on the SPI settings
prior to the Sleep mode entry, CAN and LINx transceivers
can be either switched off or configured for bus wakeup
detection.
Two types of wakeup can be used during the Sleep mode
– a local wakeup through the WU pin change, and a bus
wakeup (via a CAN or LINx bus). A detected wakeup will
cause entry into Power−up mode.
When Sleep mode is requested, at least one of the
following conditions must be fulfilled:
• CAN wakeup is enabled
• LIN wakeup is enabled at least on one of the LINx
channels
SPI status bits or enable the corresponding interrupt
requests. Pin RSTN remains High while pin UVN_VOUT
indicates the VOUT under−voltage with respect to the
highest reset level. WU pin and transceivers can be
configured for wake−up recognition which is then signalled
as an interrupt request.
In a software−controlled way, the microcontroller can
either keep NCV7471(A) in the Normal mode or request a
transition into another mode (including Reset and
Configuration).
Standby Mode
Standby is the first low−power mode of NCV7471(A). It
is entered after the corresponding SPI request is made in the
Normal mode. In the Standby mode, the application
microcontroller remains supplied by VOUT DC/DC
converter and can continue the SPI communication. VOUT
remains monitored by the reset and failure comparators. The
functionality of the LINx blocks remains fully available
while the CAN transceiver is limited – it can be put to
Receive−only, Wakeup or Off mode. Active CAN
transmission is not available.
Three types of wakeup can be used during the Standby
mode – a local wakeup through the WU pin change, a bus
wakeup (via a CAN or LINx bus) and a cyclic wakeup
generated by the watchdog timer. A detected wakeup will
cause an interrupt request through INTN pin.
During Standby mode, at least one of the following
conditions must be fulfilled:
• Watchdog is requested to be on
• Cyclic wakeup is enabled
• CAN wakeup is enabled
• LIN wakeup is enabled at least on one of the LINx
channels
If none of the above conditions is respected, all CAN and
LIN wakeups will be automatically enabled as well as WU
wakeup on both edges. Note, that allowing only the local
WU wakeup is not sufficient. Sleep mode can be only left
through a wakeup or V_MID under−voltage.
Fail−Safe Mode
Fail−safe mode ensures a defined reaction of
NCV7471(A) to a failure event. Both power supplies –
VOUT and VOUT2 – are switched off, and the Fail−safe
outputs are activated. RSTN and UVN_VOUT pins are
pulled Low in order to ensure that the microcontroller
software execution stops immediately.
Fail−safe mode will be entered as a consequence of one of
the following events:
• Watchdog has been missed in Config 2 or Config 4
• “RSTN clamped Low” has been detected in Config 2 or
Config 4
• “RSTN clamped High” has been detected
• VOUT power supply has not reached the failure level
VOUT_FAIL after t_VOUT_powerup – this situation
can be encountered during failed chip start−up or
during too long and deep under−voltage
• Fail−safe mode has been requested via SPI (in SW
Development only)
• Thermal shut−down has been encountered
If none of the above conditions is respected, all CAN and
LIN wakeups will be automatically enabled as well as WU
wakeup on both edges. Note, that allowing only the local
WU wakeup is not sufficient for successful Standby mode
entry without watchdog. This SPI setting condition is
monitored and fostered throughout the Standby mode
duration.
Standby will be kept as long as the microcontroller can
correctly serve the watchdog and the interrupts according
the SPI settings. Standby is left either by an SPI request for
a mode change or by a reset event.
All CAN and LINx transceivers are automatically
configured to wakeup detection; wakeup from WU pin is
also enabled on both edges. A detected bus or WU wakeup
will bring NCV7471(A) into Power−up mode. Only in case
of a thermal shut−down, no wakeups are detected and the
Fail−safe mode is exited as soon as the junction temperature
decreases below the warning level.
Throughout the Fail−safe mode, some SPI settings and
status bits are preserved, and become effective after
Fail−safe mode recovery. Namely CONTROL2 register
(with SMPS mode settings and VOUT reset level settings),
STATUS1 register (with wake−up flags and FSO flags) and
GENERAL PURPOSE register are not reset when Fail−safe
is entered, and keep their previous content. Fail−safe
Sleep Mode
Sleep mode is the second low−power mode of
NCV7471(A). The microcontroller is not supplied and most
resources are inactive beside the blocks needed for wakeup
detection.
Sleep mode can be entered from Normal mode by the
corresponding SPI request. Immediately after the Sleep
mode entry, RSTN and UVN_VOUT pins are pulled Low in
order to stop the microcontroller software. Both power
supplies – VOUT and VOUT2 – are switched off; SPI and
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NCV7471, NCV7471A
Flash mode can be entered by a specific SPI request in
Start−up or Normal mode. The entry into Flash is
accompanied by a reset pulse with “Flash requested” flag.
Similarly, Flash mode can be left by an SPI request which
will result in a reset pulse with “Flash exit requested” flag.
Reset−source information in the SPI flags then allows the
application to branch in function of the Flash mode. The
handling of Flash mode requests is shown in Figure 13.
In SW Development configuration, CAN and both LIN
transceivers are automatically put to their Normal mode
when the device enters Flash operating mode.
recovery is therefore different compared to wakeup from
Sleep mode, after which CONTROL2 is reset.
Flash Mode
Operating
Start−up/Normal
mode
Reset
Reset
Flash mode offers a relaxed watchdog timing enabling
transfer of bigger amounts of data between the
microcontroller software and, e.g., an external programmer
connected to a CAN or LIN bus. The watchdog is running
in time−out mode and its period can be selected from the full
range of available values including longer times compared
to Normal mode. The control of other resources – power
supplies, transceivers, WU pin, interrupt requests, etc. –
remains identical to Normal mode.
Flash
Flash
Flash
Flash
Start−up
Normal
SPI mode
request
Flash
Flash
Normal
Flash
Normal
Flash mode exited
n/a
Flash mode requested
XXXXX
Opmode SPI
Start−up/Normal
read−back
Flash
n/a
Reset source
flag in SPI
Flash
Start−up
Normal
RSTN
Figure 13. Flash Mode Sequence
Watchdog
The NCV7471(A) watchdog timer monitors the correct
function of the application software – the microcontroller is
required to send correct and timely watchdog−service (or
“WD trigger”) SPI messages. A failure in the watchdog
service is handled in function of the chip’s configuration
(see the Configuration Mode section): it leads to a reset, to
the Fail−safe mode entry or – in the SW Development
configuration – generates an interrupt event (maskable).
The available modes of the watchdog timer are shown in
Figure 14, with the watchdog period specified in Figure 15:
• Time−out mode watchdog: the microcontroller is
expected to send the watchdog−service SPI message
any time before the watchdog period elapses. The
time−out watchdog mode is automatically used during
Start−up and Flash modes. It can be used in Standby
and Normal modes. In Standby and Flash modes, the
watchdog period can be selected from a broader range
of values compared to the Normal mode.
• Window mode watchdog: the microcontroller must
•
•
send the required SPI message during an “open
window” – this window is situated between 50% and
100% of the watchdog period. A watchdog−service SPI
message sent before or after the open window is treated
as a watchdog failure. The window watchdog can be
used during the Normal mode.
Off: the watchdog will be inactive by default in
Shut−down, Configuration, Power−up, Reset, and
Fail−safe modes. It can be requested to be off in the
Standby mode.
Timer Wakeup: in the Standby mode, the watchdog
timer can be configured to generate wakeup events. In
the Standby mode an interrupt request will be generated
with a period defined by the watchdog setting.
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NCV7471, NCV7471A
Reset
mode
Flash mode
SPI request
Failed WD service (*)
After Flash
SPI request
Start−up mode
Failed WD service (*)
or SPI request
Time−out
Watchdog
Flash mode
default period used
Correct WD service
SPI
Period can be changed at
every watchdog service
Normal mode
Window or Time−out
Watchdog
Correct
WD service
SPI
(*) Exact handling
of a failed
watchdog service
depends on the
configuration
Time−out
Watchdog
Period can be changed at
every watchdog service
SPI
Wakeup
SPI
Cyclic IRQ
SPI
Time−out
Watchdog
Period fixed @
mode entry;
SPI period definition
ignored
Watchdog Off
Watchdog timer stopped;
SPI period definition
ignored in Standby;
SPI blocked in Sleep
Timer wakeup
Watchdog used to
generated wakeup
through INTN;
SPI period definition
ignored
Watchdog Off
Watchdog timer stopped;
SPI period definition
ignored in Sleep;
SPI blocked in Sleep
Sleep mode
Standby mode
Figure 14. Watchdog Modes
In the SW Development configuration, a failed watchdog
service does not lead either to Reset or to Fail−safe mode:
• A failed WD service event is stored into the
corresponding SPI register
• If the event is not masked, an interrupt request is
generated.
• If a time−out watchdog is missed in the Start−up
operating mode, Start−up mode is kept, and the
watchdog is restarted with the default time−out period.
• If a too early window WD service is encountered in the
Normal mode, a new watchdog period will be
immediately started with the newly written settings;
Normal mode is preserved
• If a window−watchdog is missed in the Normal mode
(no service arrives), a new watchdog period will be
immediately started with the current settings; Normal
mode is preserved
• If a time−out watchdog is missed in the Standby mode,
a new time−out watchdog period is immediately started
with the same period; Standby mode is preserved
A watchdog−service corresponds to a write access to SPI
CONTROL0 register, containing watchdog mode,
watchdog period and operating mode settings. The CSN
rising edge of the CONTROL0 SPI write access is
considered as the watchdog trigger moment. The watchdog
service is evaluated as successful if all below conditions are
fulfilled:
• The write SPI frame is valid
• The watchdog trigger moment falls into the correct
watchdog trigger interval (see Figure 15) – in the case
of the time−out watchdog, it arrives before the
watchdog period expires; in the case of the window
watchdog, it arrives during the second half of the
window interval. In both cases, tolerance of the
watchdog timing parameters shall be taken into
account.
• The requested watchdog mode and the requested
operating mode form an allowed combination
The watchdog period value written during a successful
watchdog service is immediately used during the subsequent
operation.
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NCV7471, NCV7471A
Reset or previous WD service
nominal t_WD_TOx
Time−out
WD period
Safe trigger of time−out WD
WD expired
t_WD_TOx
tolerance
Previous WD service
nominal t_WD_WINx
t_WD_WINx_trig
50% of nominal t_WD_WINx
Window WD
period
Closed window
(WD trigger would be too early)
Safe trigger of window WD
50% of
t_WD_WINx tolerance
recommended WD trigger
t_WD_WINx tolerance
Figure 15. Structure of the Time−out and Window Watchdog Period
System Reset
A reset to the application microcontroller is signaled by
Low level on the RSTN pin. RSTN pin is a bidirectional
digital pin using an open−drain output structure with an
internal pull−up resistor. An external reset source can
overrule the High level generated by NCV7471(A) on
RSTN pin. The RSTN logical level is then a superposition
of the internally and externally driven reset request.
The RSTN pin level is compared with the internally
driven RSTN signal – the comparison is used to control the
operating mode of the circuit and to monitor a clamped
condition of the RSTN pin – see Table 9.
With the exception of the SW Development
configuration, applying an external reset during the Start−up
mode will result in the FSO outputs activation. This
condition fosters that the external MCU sends at least one
correct watchdog message before applying an external reset.
Table 9. RSTN PIN FUNCTION (“X” Means “Don’t Care”)
RSTN
internally
driven
sensed
at the pin
Configuration
Mode
Action
Low
Low
X
X
Follow normal state diagram
High
High
X
X
Follow normal state diagram
RSTN pin
clamped High
Low
High
X
Configuration,
Power−up,
Reset, Sleep
Go to Fail−safe after t_RSTN_ClampedHigh
RSTN pin
clamped Low
High
Low
X
Normal,
Standby, Flash
Go to Reset mode after t_RSTN_filt
Config 1, 2, 3, 4
Start−up
Go to Reset mode after t_RSTN_filt;
activate FSO
SW
Development
Start−up
Go to Reset mode after t_RSTN_filt;
do NOT activate FSOx
Config 1 and 3
Trying to exit
Reset mode
Keep Reset mode;
activate FSOx after t_RSTN_ClampedLow
Config 2 and 4
Trying to exit
Reset mode
Keep Reset mode
Go to Fail−safe after t_RSTN_ClampedLow
SW
Development
Trying to exit
Reset mode
Keep Reset mode
do NOT go to Fail−safe
do NOT activate FSOx
RSTN pin
follows internal
drive
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NCV7471, NCV7471A
• Watchdog missed in SW Development configuration
Event Flags and Interrupt Requests
An interrupt request can be signaled by the NCV7471(A)
to the attached microcontroller via the open−drain output pin
INTN. The active level of the INTN pin is logical Low. Pin
INTN is provided with an internal pull−up resistor. An
additional external pull−up is recommended − see Figure 2.
The interrupt request generation is available during the
Start−up, Normal, Standby and Flash modes.
The following events are handled by the interrupt
sub−system:
• CAN, LIN and WU wakeups (cannot be masked)
• Timer wakeup in Standby mode (cannot be masked)
• VOUT2 supply crossing the under−voltage level in
either direction if VOUT2 is on
• VOUT2 supply crossing the over−voltage level in either
direction
• TxD dominant time−out for CAN or LINx (valid only if
the respective transceiver is configured in its normal
mode)
• The junction temperature crosses the thermal warning
level in either direction
• Internal DC/DC converter signals changing their status
– these events indicate entering or leaving limit
conditions for both stages of the converter (run−state of
the boost, overload of the boost or buck,
out−of−regulation state of buck)
unmasked events
INTN
U4
IRQ due to
U3 and U4 events
U2
U1
masked events
U3
IRQ due to
pending U2 request
M1
If an event is encountered, it always causes the
corresponding SPI flag go High. If the event is masked by
the SPI interrupt mask setting (the corresponding mask bit
is Low), pin INTN will not be forced Low and no interrupt
request will be issued. The interrupt flag remains available
for later readout until the next read−and−clear access
through the SPI interface. TxD dominant time−out flags will
remain set even after a read&clear access if the excessively
long dominant signal is still present on the corresponding
TxD pin. Note, that wakeup events cannot be masked. An
overview of event flags is given in Table 10.
In case an un−masked interrupt event takes place, not only
the corresponding event flag is set High, but also INTN pin
is driven Low for t_INTN_active, indicating an interrupt
request to the microcontroller. The microcontroller software
is expected to read and clear the interrupt status register,
otherwise the interrupt request remains pending (with the
exception of flagRES_SWD). Pending or new interrupt
requests will lead to a new INTN Low pulse no sooner than
t_INTN_inactive after the previous pulse. In this way, it is
ensured that multiple new or pending interrupts will not
slow−down the execution of the application software.
Control of the INTN pin in conjunction with the internal
flags is illustrated in Figure 16.
t_INTN_active
operating mode
t_INTN_inactive
t_INTN_active
read&clear
U3
read&clear
U2
read U2
read&clear
U1, M1
SPI access
t_INTN_inactive
t_INTN_active
Start−up/Normal/Standby/Flash
Figure 16. Interrupt Request Handling in Start−up, Normal, Standby and Flash Modes
In order to prevent that a pending interrupt request gets
ignored by the application software, NCV7471(A) offers the
following mechanisms:
• All event flags are preserved when transitioning from
Start−up to Normal mode – see Figure 17.
• All event flags are preserved when transitioning from
Standby to Normal mode – see Figure 17.
• All event flags are preserved when transitioning from
Normal to Standby mode. If Standby mode is requested
while an un−masked interrupt is pending, a new
•
interrupt request is issued according the
t_INTN_inactive timing – see Figure 18.
If Sleep mode is requested while a wakeup flag is
pending, the chip immediately performs a “wakeup
from Sleep” mode sequence – see Figure 19. In this
way, the information on the pending wakeup is not
missed by the application.
Any transition through the Reset mode erases all SPI event
flags, except the wakeup flags, and sets all maskable events
to masked (i.e. not causing an interrupt request).
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NCV7471, NCV7471A
Table 10. EVENT FLAGS SUMMARY
VOUT2
SMPS
TxDx Time−out
Event Flag Bit
flagTO_TxDC
flagTO_TxDL1
Related
Interrupt Mask Bit
Set Condition
Reset Condition
TxDx (Note 2) pin is kept Low for
longer than the time−out period
and
corresponding transceiver
in normal mode
read&clear access to
register STATUS0
and
{TxDx (Note 2)
dominant time−out
condition disappeared
or
transceiver mode other
then “normal”}
intenTO_TxDC
none
flagTO_TxDL2
intenTO_TxDL1
intenTO_TxDL2
flagBUCK_NOREG
statBUCK_NOREG
intenBUCK_NOREG
BUCK SMPS stage enters or leaves
range of no regulation (i.e. extreme
switching duty cycle); indicates
(in)ability to reach nominal VOUT
flagBUCK_OL
statBUCK_OL
intenBUCK_OL
BUCK SMPS stage enters or leaves
over−load condition (i.e. current
limitation encountered or disappeared)
flagBOOST_RUN
statBOOST_RUN
intenBOOST_RUN
BOOST SMPS stage changes activity
– it starts or stops
flagBOOST_OL
statBOOST_OL
intenBOOST_OL
BOOST SMPS stage enters or
leaves over−load condition (i.e.
current limitation encountered or
disappeared)
flagTWAR
statTWAR
intenTWAR
junction temperature crosses the
warning level in either direction
flagRES_SWD
(Note 4)
none
intenRES_SWD
incorrect watchdog service
encountered
and
device in SW Development
configuration
flagVOUT2_UV
statVOUT2_UV
intenVOUT2_UV
VOUT2 under−voltage detector
changes state in either direction
and
VOUT2 is switched on
flagVOUT2_OV
statVOUT2_OV
intenVOUT2_OV
VOUT2 over−voltage detector
changes state in either direction
flagSPIFail
(Note 5)
Wakeups
Related
Status Bit (Note 1)
none
SPI frame failure occurs:
− number of SPI clocks different
from 0 or 16, or
− SCK High when CSN changes
state
intenSPIFail
flagWakeWU
WU wakeup detected (Note 3)
flagWakeCAN
CAN wakeup detected (Note 3)
flagWakeLIN1
none
read&clear access to
register STATUS0
LIN1 wakeup detected (Note 3)
none
flagWakeLIN2
LIN2 wakeup detected (Note 3)
flagWakeTimer
Timer wakeup detected (Note 3)
Read&clear access to
register STATUS1
1. When a related status bit exists, the event is linked to a change (in either direction) of the status bit. Even if the event flag is cleared, the
corresponding status bit still indicates the current status of the observed feature and can be polled by SPI at any time.
2. “x” = “C”, “L1 or “L2”. In case of LIN transceivers, the time−out feature can be enabled/disabled by SPI.
3. The respective wakeup source must be enabled through the corresponding control SPI register – timer wakeup in CONTROL0; CAN, LIN1/2
and WU wakeups in CONTROL1
4. For a missed WD in SW Development, INTN pulse is generated only once per event – it is not repeated even if the corresponding flag is
still set. New INTN pulse occurs only if WD is missed again in SW Development.
5. During VOUT power−up (e.g. when going from Shut−down mode, or when waking−up from Sleep or Fail−safe mode), flagSPIFail can be
set because of transient toggling of internal CSN and SCK signals. It is therefore recommended to ignore flagSPIFail immediately after VOUT
power−up, until the STATUS0 register is reset. Except flagSPIFail, the remaining SPI register content is not influenced by the possible internal
toggling of CSN and SCK signals during power−up.
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U1
IRQ due to
pending U1 request
NCV7471, NCV7471A
unmasked events
SPI access
t_INTN_active
operating mode
read&clear
U1
Go to Normal
or Flash
INTN
t_INTN_active
t_INTN_inactive
Start−up/Standby
Normal/Flash
U1
IRQ due to
pending U1 request
Figure 17. Interrupt Request Handling during a Transition to Normal Mode
unmasked events
INTN
Go to
Standby
read&clear
U1
SPI access
t_INTN_active
operating mode
t_INTN_inactive
t_INTN_active
Normal
Standby
pending wakeup
RSTN due to
masks reset in SPI
wakeup event
Interrupt flags and
U1
Figure 18. Transition to Standby Mode with a Pending Interrupt Request
After reset, WU and CAN/LIN wakeups disabled;
pending flags will not cause additional INTN pulse
INTN
Go to
Sleep
read&clear
wakeup flag
SPI access
operating
mode
Normal
Sleep
(transient)
Reset
Start−up
RSTN
Figure 19. Attempted Transition to Sleep Mode with a Pending Wakeup Flag
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NCV7471, NCV7471A
• Thermal shut−down level Tj_SD. Junction temperature
Junction Temperature Monitoring
The device junction temperature is monitored in order to
avoid permanent degradation or damage of the chip. Two
distinct junction temperature thresholds are used:
• Thermal warning level Tj_WAR. The status of the
current junction temperature compared with the
Tj_WAR threshold is available in the corresponding
SPI status register. A change of the junction
temperature across the warning threshold in either
direction sets the SPI bit flagTWAR. If not masked, an
interrupt request can be generated in order to signal to
the application that the junction temperature exceeded
or cooled below the warning level.
Tj > Tj_WAR
exceeding the shut−down level puts the chip into
Fail−safe mode. In this specific case, no wakeups are
detected in the Fail−safe mode; the mode is auto−
matically left only when the junction cools down below
the warning level, thus providing a thermal margin for
the application software to cope with the event.
The junction temperature monitoring circuit is active in all
operating modes with VOUT supply switched on
(Power−up, Reset, Start−up, Standby, Flash) and also in the
Fail−safe, provided that it has been entered as the
consequence of a thermal shut−down. The function of the
junction temperature monitoring of NCV7471(A) is shown
in Figure 20.
flagTWAR −> 1;
interrupt request
(if enabled)
Tjunction above
warning threshold
SPI TWAR status bit = 0
SPI TWAR bit = 1
flagTWAR −> 1;
interrupt request
(if enabled)
Tj < Tj_WAR
Power−up, Reset, Start−up, Normal, Stand−by, Flash
Tj > Tj_SD
Tjunction below
warning threshold
Fail−safe mode
Tj < Tj_WAR
Tjunction above
shutdown threshold
no wakeup detection
VOUT, VOUT2: off
RSTN: Low
Figure 20. Junction Temperature Monitoring
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NCV7471, NCV7471A
FSO1/2/3 – Fail−Safe Outputs
NCV7471(A) offers three digital outputs dedicated to
control a fail−safe circuitry in the application under specific
failure conditions. All three outputs are high−voltage
low−side open drain drivers simultaneously activated by a
common internal signal FSO_internal and providing
different behavior:
• FSO1 is constantly pulled Low if FSO_internal is active
• FSO2 provides 50% rectangular signal with 1.25 Hz
•
frequency
FSO3 provides 20% rectangular signal with 100 Hz
frequency
Figure 21 illustrates the FSOx pins function with respect to
the internal FSO_internal signal.
Figure 21. Operation of FSOx Pins
• If FSO_internal was set by setting the FSO_ON SPI bit,
FSO_internal is set to High as soon as a failure condition
is recognized or as soon as an SPI command is given to
activate FSO. Overview of situations leading to
FSO_internal activation is given in Table 11. The handling
of the different failure conditions depends on the chip
configuration (see the Configuration Mode section) –
specifically in the SW development configuration, the
watchdog−related failures and “RSTN clamped Low”
failure do not lead either to the FSO_internal activation or
to the Fail−safe mode entry.
FSO_internal signal will be reset (and the FSOx outputs
are subsequently de−activated) under the following
conditions:
•
it will be reset by writing “0” to FSO_ON SPI bit
If FSO_internal was set because of a failure condition,
a read−and−clear access to the flagFSO SPI status bits
will reset it.
In Start−up mode, FSO_internal High level limits SPI
functionality – no register can be written or read&cleared
with the exception of CONTROL0 register. Attempts to
perform a write or read&clear access to other registers will
be ignored – including attempts to reset bit FSO_ON or the
flagFSO.x bits. This condition ensures that the application
software performs at least one successful watchdog service
after a failure occurs.
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NCV7471, NCV7471A
Table 11. CONDITIONS FOR ACTIVATION OF FSO_INTERNAL SIGNAL (“X” Means “Don’t Care”)
FSO Activation Event
Detected in Modes
Detected in Configurations
Fail−safe Mode Entered
Thermal Shutdown
(Tj > Tjsd)
Power−up
Reset
Start−up
Normal
Standby
Flash
all
yes
Fatal VOUT failure
(VOUT < VOUT_FAIL for longer than
t_VOUT_powerup)
Power−up entered from
all the modes
all
yes
VOUT undervoltage
(VOUT < VOUT_RESx for longer than
t_VOUT_powerup) (NCV7471A only)
Power−up entered from
Configuration, Sleep or
Fail−safe
all
no
VOUT undervoltage
(VOUT < VOUT_RESx for longer than
t_VOUT_UV_filt) (NCV7471A only)
Power−up entered from
Start−up, Normal, Standby,
Flash
all
no
RSTN Clamped High
Reset
all
yes
External RSTN without
previous WD service
Start−up
Config 1,2,3,4
no
RSTN Clamped Low
when trying to leave Reset
Config 1,3
no
Config 2,4
yes
Start−up
Normal
Flash
Standby (if WD on)
Config 1
no
Config 2
yes
Start−up
Normal
Flash
Standby (if WD on)
Config 3
no
Config 4
yes
Start−up
Normal
Standby
Flash
all
no
1st
Watchdog Missed
2nd Watchdog Missed
SPI control bit FSO set
SWDM and CFG Digital Inputs
SWDM and CFG pins are high−voltage compliant digital
inputs enabling NCV7471(A) flexibility with respect to the
fail−safe behavior. Their logical value (compared to a
low−voltage digital threshold) is sensed and latched
exclusively in the Configuration operating mode – i.e. when
the chip leaves the Shut−down mode. Subsequently, the
latched values are not changed by any signal on SWDM or
CFG pin or by any SPI communication.
Latched active level on SWDM pin (i.e. High input level
in the Configuration mode) causes the chip to enter the SW
development configuration regardless the state of CFG pin.
When the latched SWDM value is inactive (i.e. Low in the
Configuration mode), the latched CFG value then controls
whether a failure condition (missed watchdog or RSTN
clamped Low) results in the Fail−safe entry or only in a reset
pulse generation. More details are given in the Configuration
Mode and FSO1/2/3 – Fail−Safe Outputs sections.
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NCV7471, NCV7471A
SPI – Serial Peripheral Interface
As long as the CSN chip select is High, the SCK and SDI
inputs are not relevant and the SDO output is kept
high−impedant. The signals on the SDI and SCK inputs are
taken into account only when CSN chip select input is set to
Low. Data incoming on pin SDI are then sampled at the
falling edge of SCK clock signal; output data are shifted to
pin SDO at the rising edge of SCK clock signal. Bits are
transmitted MSB (most significant bit) first.
SPI Frame Format
The Serial Peripheral Interface ensures control of
NCV7471(A) operating modes, configuration of its
functions and read−out of internal status and system
information. The serial communication is achieved via SPI
frames shown in Figure 22.
CSN
SCK
SDI
SDO
HZ
X
A2
A1
A0
Read
Only DI11 DI10
SPI
ready
A2
A1
A0
Read
Only DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI9
DI8
DI7
DI6
header
DI5
DI4
DI3
DI2
DI1
DI0
X
HZ
data
Figure 22. SPI Frame Format
♦
One frame consists of exactly sixteen bits transferred from
the microcontroller to NCV7471(A) through input pin SDI.
The input bits are interpreted as follows:
• Immediately after CSN falling edge, SDO pin shows an
internal “SPI ready” flag. Under normal conditions,
when the inter−frame space is respected, the “SPI
ready” flag is set to High and the device is available for
SPI communication. If the SPI inter−frame space is
violated, the previous SPI data might not be processed
at the moment of the next CSN Low level; this situation
is signaled by Low “SPI ready” flag. If the application
software still attempts to perform SPI communication,
incoming data will be completely ignored and the SDO
signals “Low” throughout the SPI frame. The status of
the flag is latched at the CSN falling edge – the
application software might use short Low pulses on
CSN (without SCK) in order to poll the flag.
• Four most significant bits form the header of the SPI
frame. During the reception of the header bits, the SDI
signal is looped back to the SDO pin starting with the
first rising edge of SCK – except for the internal delay,
signals SDO and SDI are equal during the header
transmission. The header bits have the following
function:
♦ Bits A2, A1, and A0 form a 3−bit address of an
internal SPI register. NCV7471(A) contains eight
twelve−bit registers addressable by these three
header bits.
•
•
•
Bit “ReadOnly” contains the “read−only” flag. If
ReadOnly=High, the current SPI frame represents a
read−only access to the SPI register. If
ReadOnly=Low, then the current SPI frame
represents either a write or read−and−clear access to
an SPI register – the distinction between “write” and
“read−and−clear” access depends on the specific
register.
Bits DI11−DI0 are the SPI data. In case of a read−only
or read−and−clear access, these bits are ignored. In case
of a write−frame, these bits are taken as the new SPI
register content at the moment of the CSN rising edge
(when the frame is considered finished). Regardless the
access type, the output data DO11−DO0 represent the
SPI register content as valid at the beginning of the SPI
frame. The output bits are shifted−out at the rising edge
of the SCK clock so that they can be sampled by the
microcontroller at the SCK falling edge.
The following checks are performed on every SPI frame:
The SCK clock input must be Low at both edges of the
CSN chip select signal
There must be exactly sixteen SCK clock cycles when
CSN=Low (or no SCK edge if only the “SPI ready”
flag is polled).
If any of the above conditions is not fulfilled, the SPI frame
is considered incorrect and the “SPI Fail” event is internally
generated.
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28
0
1
CONTROL1
0
1
0
CONTROL2
0
1
1
CONTROL3
1
0
0
STATUS0
1
0
1
STATUS1
1
1
0
STATUS2
reserved
1
1
1
GENERAL PURPOSE
NOTE:
statBUCK_NOREG
statBUCK_OL
statBOOST_RUN
statBOOST_OL
statSWDM
statCFG
statWU
statTWAR
statVOUT2_UV
statVOUT2_OV
GPD.8
29
GPD.7
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GPD.6
“reserved” bits in input data are ignored; they are set to Low in output data.
GPD.5
GPD.4
GPD.3
GPD.2
GPD.1
GPD.0
flagSPIFail
intenSPIFail
intenVOUT2_OV
enBOOST
modDCDC.0
modDCDC.1
modLIN1.0
modLIN1.1
modLIN2.0
modLIN2.1
reserved
input
output
reserved
reserved
RES_SRC.0
RES_SRC.1
RES_SRC.2
RES_SRC.3 CHECKSUM
WD_PER.0
D1
flagWakeTimer
flagVOUT2_OV
ntenVOUT2_UV
VOUT_RES.0
disTO_TxDL
WD_PER.1
D2
flagWakeLIN2
flagVOUT2_UV
intenRES_SWD
VOUT_RES.1
enLIN_LSLP
WD_PER.2
D3
flagWakeLIN1
flagRES_SWD
intenTWAR
FAST_FSO
modCAN.0
D4
flagWakeCAN
flagTWAR
intenBOOST_OL
FSO_ON
WD_MOD.0
D5
flagWakeWU
flagBOOST_OL
intenBOOST_RUN
modCAN.1
WD_MOD.1
OPMODE.0
OPMODE.1
D6
flagFSO.0
flagBOOST_RUN
reserved
modWU.0
modWU.1
enVOUT2
D7
flagFSO.1
intenBUCK_OL
reserved
reserved
reserved
D8
flagBUCK_OL
intenBUCK_NOREG
intenTO_TxDL2
intenTO_TxDL1
Address
flagFSO.2
flagBUCK_NOREG
flagTO_TxDL2
flagTO_TxDL1
D9
flagFSO.3
reserved
reserved
D10
GPD.9
statVS_LOW
0
D11
GPD.10
CONTROL0
OPMODE.2
0
reserved
0
reserved
0
intenTO_TxDC
A0
flagTO_TxDC
A1
Register Name
reserved
A2
GPD.11
NCV7471, NCV7471A
SPI Register Mapping
Table 12. SPI REGISTERS MAPPING
Register Content
D0
NCV7471, NCV7471A
Table 13. SPI REGISTERS INITIALIZATION
Address
A2
A1
A0
Register
Name
0
0
0
0
0
1
0
6.
7.
8.
9.
1
0
Initialization
ReadOnly bit
Initialized in (Note 6)
Initial content
Low (Note 7)
CONTROL0
Reset mode
(except Flash
mode entry)
Watchdog set to
time−out @
256 ms nominal
Mode and Watchdog
settings (bits DI11−DI4)
written into the register if
checksum (bit DI3) is OK.
Input bits DI2−DI0 ignored.
CONTROL1
Power−up mode
all bits Low
(Note 9)
Bits DI11−DI0 written into
the register
Reset mode
all bits Low
(Note 9)
Configuration
all bits Low
Sleep
all bits Low
CONTROL2
Bits DI11−DI0 written into
the register
0
1
1
CONTROL3
Reset mode
all bits Low
Bits DI11−DI0 written into
the register
1
0
0
STATUS0
Reset mode
all bits Low
read&clear access;
all bits reset to Low (Note 8);
input data ignored
1
0
1
STATUS1
Configuration mode
all bits Low
read&clear access;
all bits reset to Low; input
data ignored
1
1
0
STATUS2
n.a.
Reflects status of
internal blocks
input data ignored
1
1
1
GENERAL
PURPOSE
Configuration
mode
register filled with
device ID data
Bits DI11−DI0 written into
the register
High
Input data
ignored;
current
register
content sent
to SPI output
In modes not explicitly listed in “Initialized in” column, the register content is preserved
Regardless the access type (the “ReadOnly” bit), the current register content is always sent to the SPI output
Bits containing TxD dominant timeout flags will remain set if the excessively long dominant signal persists on the respective TxDx pin
Exception: in SW Development configuration, CONTROL1 bits modCAN.x, modLIN1.x and modLIN2.x are all set to “High”, corresponding
to the default “Normal” mode of all transceivers
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NCV7471, NCV7471A
CONTROL0 Register (Address 000)
In case of incorrect checksum in written data, the device
By a write access to the CONTROL0 register
reacts identically to a wrong opmode situation. During a
(“ReadOnly” = Low), the application software can control
read−only access to the CONTROL0 register (“ReadOnly”
the operating mode of NCV7471(A) and the watchdog
= High), the input data are completely ignored and no check
settings. A write access represents a watchdog service. An
is performed on them.
operating mode change is therefore always synchronized
The output data of the CONTROL0 register – regardless
with the watchdog trigger message. In order to provide more
the access type − indicate the current operating mode, the
safety to the mode control, the input data are protected with
current watchdog settings and the cause of the last reset.
a check−sum (input bit DI3). The checksum must
The initialization of the CONTROL0 register content is
performed after every reset, when the watchdog type is fixed
correspond to the following formula (symbol “⊕” denoting
to time−out, and the watchdog period to nominally 256 ms.
the exclusive−or operation):
DI3 = DI11 ⊕ DI10 ⊕ DI9 ⊕ DI8 ⊕ DI7 ⊕ DI6 ⊕ DI5 ⊕ DI4
Table 14. CONTROL0 REGISTER: OPMODE.x Encoding
OPMODE.2
OPMODE.1
OPMODE.0
OPMODE.x
in Output
Data
0
0
0
forbidden
0
0
1
Normal
go to Normal
keep Normal
go to Normal
return from
Flash via
Reset and
Start−up
Normal
0
1
0
Standby
“Wrong Opmode”
Reset
go to Standby
keep Standby
“Wrong
Opmode”
Reset
Standby
0
1
1
Sleep
“Wrong Opmode”
Reset
go to Sleep
1
0
0
Flash
go to Flash via
Reset
go to Flash via
Reset
1
0
1
Fail−safe
in SW development configuration, go to Fail−safe;
otherwise “Wrong Opmode” Reset
not used
1
1
0
Reset
go to Reset
not used
1
1
1
Configuration
OPMODE.x in Input Data
Requested
Mode
Reaction
in Start−up
Reaction
in Normal
Reaction
in Standby
Reaction
in Flash
“Wrong Opmode” Reset
go to
Configuration
go to Configuration
Start−up
“Wrong Opmode” Reset
“Wrong
Opmode” Reset
Current
Mode
keep Flash
“Wrong Opmode” Reset
not used
Flash
not used
WD_MOD.1
WD_MOD.0
Table 15. CONTROL0 REGISTER: WD_MOD.x Encoding
Watchdog Timer Mode
0
0
Watchdog off
0
1
1
0
1
1
Limitations
(if not respected, the write access is considered as a missed watchdog)
Can be used only with a Standby or a Sleep mode request
Window Watchdog
Can be used only for Normal mode request
Time−out Watchdog
Must be used with every Flash mode request;
can be used with a Standby or Normal mode request;
default in Start−up mode
Timer Wakeup
Can be used only with a Standby mode request
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NCV7471, NCV7471A
WD_PER.2
WD_PER.1
WD_PER.0
Table 16. CONTROL0 REGISTER: WD_PER.x Encoding
Watchdog Period
0
0
0
WD_PER_0
8 ms
0
0
1
WD_PER_1
16 ms
0
1
0
WD_PER_2
32 ms
0
1
1
WD_PER_3
64 ms
1
0
0
WD_PER_4
128 ms
1
0
1
WD_PER_5
256 ms
WD_PER_5 is automatically used in Start−up mode
1
1
0
WD_PER_6
512 ms
1
1
1
WD_PER_7
1024 ms
Can be used only for Standby and Flash modes
(otherwise the watchdog SPI frame is considered wrong)
Nominal Duration
Note
RES_SRC.3
RES_SRC.2
RES_SRC.1
RES_SRC.0
Table 17. CONTROL0 REGISTER: RES_SRC.x Encoding
0
0
0
0
V_MID under−voltage recovery (V_IN connection)
12
0
0
0
1
External reset outside Start−up mode (not accompanied by FSO activation)
10
0
0
1
0
Recovery from Fail−safe (through wakeup or thermal shutdown recovery)
8
0
0
1
1
Wakeup from Sleep
7
0
1
0
0
Flash mode requested
6
0
1
0
1
Flash mode exited
5
0
1
1
0
Reset mode requested
4
0
1
1
1
Configuration requested
3
1
0
0
0
Failed Watchdog (WD missed, wrong WD mode or period requested) − will not be used in
SW Development configuration (Note 11)
2
1
0
0
1
Wrong operating mode requested; wrong checksum during write access to the Mode Control register
1
1
0
1
0
External reset in Start−up mode (accompanied by FSO activation if not in SW Development configuration)
9
1
0
1
1
reserved
−
1
1
0
0
reserved
−
1
1
0
1
reserved
−
1
1
1
0
reserved
−
1
1
1
1
VOUT under−voltage recovery
11
Cause of the Last RSTN Pulse
Reset Event
Priority
(Note 10)
10. The “Reset Event Priority” reflects the order, in which the reset events are processed by the on−chip digital. In case more events occur
simultaneously, the one with the lower priority number would be stored in CONTROL0 register.
11. WD period and WD mode settings are not checked in the following situations: Configuration mode request, Reset mode request, Flash exit
(i.e. Normal mode request in the course of Flash mode)
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NCV7471, NCV7471A
CONTROL1 Register (Address 001)
CONTROL1 register defines the mode of individual CAN and LINx transceivers, of the VOUT2 regulator and the WU pin.
The encoding of the CONTROL1 bits is defined in Table 18.
Table 18. CONTROL1 REGISTER ENCODING
enVOUT2
VOUT2 control
0
VOUT2 regulator is OFF
1
VOUT2 regulator is ON
modWU.1
modWU.0
0
0
WU wakeup detection disabled
0
1
WU monitored for falling edge
1
0
WU monitored for rising edge
1
1
WU monitored for both edges
modCAN.1
modCAN.0
0
0
CAN transceiver in Off mode
0
1
CAN transceiver in Wakeup mode
1
0
CAN transceiver in Receive−only mode
1
1
CAN transceiver in Normal mode
enLIN_LSLP
WU mode control
CAN transceiver mode
LIN slope control – common for both LIN channels
0
LIN transmission with normal bus signal slopes (according LIN2.1 specification)
1
LIN transmission with slow bus signal slopes (for limited bit−rate)
disTO_TxDL
LIN dominant time−out control – common for both LIN channels
0
Dominant time−out applied on TxDL pins
1
Dominant time−out not−applied on TxDL pins – unlimited dominant symbols can be transmitted
modLINx.1
modLINx.0
LINx transceiver mode (x=1,2)
0
0
LINx transceiver in Off mode
0
1
LINx transceiver in Wakeup mode
1
0
LINx transceiver in Receive−only mode
1
1
LINx transceiver in Normal mode
CONTROL1 register is initialized at every reset event with all−zeros content
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NCV7471, NCV7471A
CONTROL2 Register (Address 010)
Content of CONTROL2 register is defined in Table 19. The CONTROL2 register content is initialized to all−zeros content
in the Configuration and Sleep modes.
Table 19. CONTROL2 REGISTER ENCODING
Bit
Definition
FSO_ON
If High, FSOx outputs are forced active
If High, already the 1st missed watchdog will be treated as a failure;
the exact reaction depends on the configuration
FAST_FSO
VOUT_RES.1
VOUT_RES.0
0
0
VOUT_RES4 threshold selected (the lowest threshold) for RSTN indication
0
1
VOUT_RES3 threshold selected for RSTN indication
1
0
VOUT_RES2 threshold selected for RSTN indication
1
1
VOUT_RES1 threshold selected for RSTN indication
modDCDC.1
modDCDC.0
0
0
DCDC Converter switching with fixed frequency
0
1
Converter switching frequency modulated with modulation depth dmod_DCDC_1
1
0
Converter switching frequency modulated with modulation depth dmod_DCDC_2
1
1
Converter switching frequency modulated with modulation depth dmod_DCDC_3
enBOOST
Selection of VOUT under−voltage threshold for RSTN Pin
DCDC Converter mode selection
If High, BOOST (step−up) stage of the DCDC converter is enabled
CONTROL3 Register (Address 011)
The individual bits in the CONTROL3 register determine
whether the corresponding interrupt event leads to an
interrupt request via INTN pin or if it is only stored as a flag
for later SPI retrieval. If the bit is High, the interrupt request
is enabled. All bits of the CONTROL3 register are reset to
Low at every reset event (i.e. all interrupt sources are
disabled).
Table 20. CONTROL3 REGISTER ENCODING
Bit
Definition
intenTO_TxDC
Enables interrupt after dominant time−out on TxDC
intenTO_TxDL1
Enables interrupt after dominant time−out on TxDL1
intenTO_TxDL2
Enables interrupt after dominant time−out on TxDL2
intenBUCK_NOREG
intenBUCK_OL
intenBOOST_RUN
intenBOOST_OL
intenTWAR
Enables interrupt after a change of the internal converter signal indicating, that the buck stage cannot reach the
output nominal voltage (typically due to too low line voltage)
Enables interrupt after a change of the internal converter signal indicating, that the buck stage is overloaded
Enables interrupt when the boost stage is activated or de−activated – indicating a change in supply line conditions
Enables interrupt after a change of the internal converter signal indicating, that the boost stage is overloaded
Enables interrupt when the junction temperature crosses the thermal warning level (in either direction)
intenRES_SWD
In SW Development configuration only – incorrect watchdog service will lead to an interrupt request
(outside SW Development configuration, this event would lead to reset).
intenVOUT2_UV
Enables interrupt when VOUT2 crosses its under−voltage level (in either direction).
Event registered only if VOUT2 is on.
intenVOUT2_OV
Enables interrupt when VOUT2 crosses its over−voltage level (in either direction).
intenSPIFail
Enables interrupt when an SPI frame failure is encountered
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NCV7471, NCV7471A
STATUS0 Register (Address 100)
Specifically, flags corresponding to dominant time−outs
can be cleared only when the respective time−out
disappeared; otherwise, they will remain set even after
read&clear access and, if enabled, the interrupt linked to
them will remain pending.
STATUS0 register is reset to all−zeros content at every
reset event.
STATUS0 bits latch information on individual events
which can potentially lead to interrupt requests. All bits have
their position corresponding to the CONTROL3 register
bits. The details of the STATUS0 bits are given in Table 21.
A read−and−clear access to STATUS0 register is
considered “interrupt service” for all pending interrupt
requests. A read−only access does not change the flags and
the active interrupt requests remain pending.
Table 21. STATUS0 REGISTER ENCODING
Bit
Definition
flagTO_TxDC
TxDC dominant time−out occurred. The bit can be cleared only when the time−out condition disappeared
(or when the CAN transceiver mode was changed to other than “CAN Normal”).
flagTO_TxDL1
TxDL1 dominant time−out occurred. The bit can be cleared only when the time−out condition disappeared (or
when the LIN1 transceiver mode was changed to other than “LIN Normal”).
flagTO_TxDL2
TxDL2 dominant time−out occurred. The bit can be cleared only when the time−out condition disappeared (or
when the LIN2 transceiver mode was changed to other than “LIN Normal”).
flagBUCK_NOREG
Flags a change of the internal converter signal indicating, that the buck stage cannot reach the output nominal
voltage (typically due to too low line voltage)
flagBUCK_OL
flagBOOST_RUN
flagBOOST_OL
flagTWAR
Flags a change of the internal converter signal indicating, that the buck stage is overloaded
Boost stage toggled its state (was activated or de−activated) – indicating a change in supply line conditions
Flags a change of the internal converter signal indicating, that the boost stage is overloaded
Junction temperature crossed the thermal warning level (in either direction)
flagRES_SWD
In SW Development configuration only – incorrect watchdog service occurred
flagVOUT2_UV
VOUT2 crossed its under−voltage level (in either direction). Event registered only if VOUT2 is on.
flagVOUT2_OV
VOUT2 crossed its over−voltage level (in either direction).
flagSPIFail
SPI frame failure was encountered (Note 12)
12. During VOUT power−up (e.g. when going from Shut−down mode, or when waking−up from Sleep or Fail−safe mode), flagSPIFail can be
set because of transient toggling of internal CSN and SCK signals. It is therefore recommended to ignore flagSPIFail immediately after VOUT
power−up, until the STATUS0 register is reset. Except flagSPIFail, the remaining SPI register content is not influenced by the possible internal
toggling of CSN and SCK signals during power−up.
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NCV7471, NCV7471A
STATUS1 Register (Address 101)
STATUS1 register is initialized in Configuration mode to
all−zeros content. It is not reset in Reset or Start−up mode in
order to preserve the wakeup and failure flags coming from
Sleep or Fail−safe mode. Encoding of the FSO−related flag
bits is defined in Table 22.
STATUS1 register contains flags for fail−safe events and
wakeups. A specific bit (flag) is set High when the
corresponding event was recognized and is set to Low only
when the STATUS1 register is read and cleared. The
Table 22. STATUS1 REGISTER: flagFSO.x Encoding
flagFSO.3
flagFSO.2
flagFSO.1
flagFSO.0
0
0
0
0
no failure, FSOx inactive (unless over−ruled by FSO_ON bit)
Failure event leading to FSOx activation
0
0
0
1
FSOx active due to missed watchdog; without entry into Fail−safe mode
0
0
1
0
FSOx active due to “RSTN clamped Low”; without entry into Fail−safe mode
0
0
1
1
FSOx active due to external reset in Start−up mode; without entry into Fail−
safe mode (not detected in SW Development configuration)
0
1
0
0
reserved
0
1
0
1
reserved
0
1
1
0
reserved
0
1
1
1
reserved
1
0
0
0
FSOx active; coming from Fail−safe mode requested by SPI
1
0
0
1
FSOx active; coming from Fail−safe mode caused by missed watchdog
1
0
1
0
FSOx active; coming from Fail−safe mode caused by “RSTN clamped Low”
1
0
1
1
FSOx active; coming from Fail−safe mode caused by “RSTN clamped High”
1
1
0
0
FSOx active; coming from Fail−safe mode caused by thermal shutdown
1
1
0
1
FSOx active; coming from Fail−safe mode caused by VOUT undervoltage
time−out (short−circuit detected) or FSOx active due to VOUT undervoltage
(NCV7471A only)
1
1
1
0
reserved
1
1
1
1
reserved
request (in Normal or Standby mode) or by a reset pulse
(wakeups from Sleep mode). In Normal and Standby mode,
a wakeup causes pending interrupt request until a
read−and−clear access to STATUS1 register.
Wakeup flag bits are summarized in Table 23. Detection
of individual wakeup events is controlled by transceiver
mode settings (for LIN and CAN wakeup), WU pin mode
settings (for WU wakeup) and watchdog settings (for timer
wakeup). A wakeup event is indicated either by an interrupt
Table 23. STATUS1 REGISTER: Wakeup Flags
Bit
Definition
flagWakeWU
Wakeup on WU pin was detected (for non−zero setting of modWU.x SPI bits)
flagWakeCAN
Wakeup on CAN bus was detected (CAN transceiver in “CAN Wakeup” mode)
flagWakeLIN1
Wakeup on LIN1 bus was detected (LIN1 transceiver in “LIN Wakeup” mode)
flagWakeLIN2
Wakeup on LIN2 bus was detected (LIN2 transceiver in “LIN Wakeup” mode)
flagWakeTimer
Wakeup by timer (“Timer wakeup” selected through CONTROL0 register)
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NCV7471, NCV7471A
STATUS2 Register (Address 110)
STATUS2 register bits reflect the state of several internal blocks of the device. Read−and−clear or write access does not
change the register content. The STATUS2 bits are defined in Table 24.
Table 24. STATUS2 REGISTER ENCODING
Bit
statVS_LOW
statBUCK_NOREG
statBUCK_OL
statBOOST_RUN
statBOOST_OL
statSWDM
Definition
Indication of the VS monitoring output. If VS<VS_MON, then statVS_LOW = 1
Indication of the buck DCDC stage not being able to reach the nominal VOUT voltage
Indication of the buck DCDC stage overload
Indication that the boost DCDC stage is running
(boost stage must be enabled and the input voltage requires step−up operation)
Indication of the boost DCDC stage overload
Logical level of the SWDM pin latched during Configuration mode
statCFG
Logical level on the CFG pin latched during Configuration mode (in Config 1,2,3,4)
or
Current logical level on CFG pin (in SW Development)
statWU
Logical level on the WU pin
statTWAR
Output of the thermal warning comparator (if High, junction temperature is above the warning level)
statVOUT2_UV
Output of the VOUT2 under−voltage comparator (if High, VOUT2 is below the under−voltage level).
Available only if VOUT2 regulator is on.
statVOUT2_OV
Output of the VOUT2 over−voltage comparator (if High, VOUT2 is above the over−voltage level)
GENERAL PURPOSE Register (Address 111)
General Purpose register allows storing general 12−bit
information in the NCV7471(A) memory. The register is
initialized only in Configuration mode, when a device
version ID is loaded. Any data written to the register
overwrite the initial content and are kept throughout the
operation of the device until device enters Shut−down mode
or until Configuration is requested.
The device ID is:
• 0x103 or 0x143 for NCV7471,
• 0x144 or 0x184 for NCV7471A.
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NCV7471, NCV7471A
Table 25. ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Units
Maximum voltage at VS pin
−0.3
40
V
Maximum voltage at VS_VOUT2 pin
−0.3
40
V
Vmax_BOOST
Maximum voltage at BOOST pin
−0.3
V_MID+2
V
Vmax_V_MID
Maximum voltage at V_MID pin
−0.3
40
V
Vmax_BUCK
Maximum DC voltage at BUCK pin
Maximum transient voltage on BUCK pin (Note 13)
−1
−3
V_MID+0.3
V
Vmax_VOUT
Maximum voltage at VOUT pin
−0.3
6
V
Vmax_VOUT2
Maximum voltage at VOUT2 pin
−1
40
V
Maximum voltage at VCC_CAN pin
−0.3
6
V
Maximum voltage at CAN bus pins
(0 < VCC_CAN < 5.25 V; no time limit)
−50
50
V
Vmax_LINx
Maximum voltage at LIN bus pins
−45
45
V
Vmax_FSOx
Maximum voltage at FSOx pins
−0.3
40
V
Maximum voltage at WU pin
−40
40
V
Maximum voltage at CFG and SWDM pins
−0.3
40
V
Maximum voltage at digital input and open−drain pins
(TxDLx, TxDC, SCK, SDI, INTN, RSTN, UVN_VOUT)
−0.3
6
V
Maximum voltage at digital push−pull output pins
(RxDLx, RxDC, SDO)
−0.3
VOUT+0.3
V
Vmax_CSN
Maximum voltage at CSN pin
−0.3
40
V
Tjunc_max
Junction temperature
−40
+170
°C
Vmax_VS
Vmax_VS_VOUT2
Vmax_VCC_CAN
Vmax_CANH,
Vmax_CANL
Vmax_WU
Vmax_CFG; Vmax_SWDM
Vmax_digIn
Vmax_digOut
V_ESD
Parameter
System ESD on pins CANH, CANL, LIN1, LIN2, VOUT2, VS,
VS_VOUT2, WU as per IEC 61000−4−2: 330 W / 150 pF
≥ ±6
kV
Human body model on pins CANH, CANL, LIN1, LIN2
stressed towards GND with 1500 W / 100 pF
≥ ±6
kV
Human body model on pins VS, VS_VOUT2, WU
stressed towards GND with 1500 W / 100 pF
≥ ±4
kV
Human body model on all pins
as per JESD22−A114 / AEC−Q100−002
≥ ±2
kV
Charge device model on all pins
as per JESD22−C101 / AEC−Q100−011
≥ ±500
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
13. BUCK pin tolerates transient voltage excursions below −1 V, caused by the buck−converter switching and the non−ideal characteristics of
diode D2 (see Figure 2). It is not implied that a hard voltage source of less than −1 V can be connected to the pin externally.
Table 26. THERMAL CHARACTERISTICS
Symbol
RqJC
Parameter
Thermal resistance junction−to−case
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38
Value
Units
3.9
°C/W
NCV7471, NCV7471A
Table 27. OPERATING RANGES
Symbol
Parameter
Min
Max
Units
Vop_V_IN_boostbuck
V_IN operating voltage for boost/buck operation
2.5
28
V
Vop_V_IN_buck
V_IN operating voltage for buck−only operation
6
28
V
Operating voltage at VS pin
6
28
V
Operating DC voltage at VS_VOUT2 pin
6
28
V
Vop_VS
Vop_VS_VOUT2
Vop_BOOST
Operating voltage at BOOST pin
0
V_MID+V_D1
V
Vop_V_MID
Operating voltage at V_MID pin
5.5
28
V
Vop_BUCK
Operating voltage at BUCK pin
−V_D2
V_MID
V
Vop_VOUT
Regulated voltage at VOUT2 supply output
4.9
5.1
V
Vop_VOUT2
Regulated voltage at VOUT2 supply output
4.9
5.1
V
Operating voltage at VCC_CAN pin for normal and
receive only CAN modes
4.75
5.25
V
Operating voltage at VCC_CAN pin for wakeup and off
CAN modes
0
5.25
V
Vop_CANH,
Vop_CANL
Operating voltage at CAN bus pins
0
VCC_CAN
V
Vop_LINx
Operating voltage at LIN bus pins
0
VS
V
Vop_FSOx
Operating voltage at FSOx pins
0
VS
V
Operating voltage at WU pin
0
VS
V
Operating voltage at CFG and SWDM pins
0
VS
V
Vop_digIO
Operating voltage at digital input and output pins
(TxDLx, RxDLx, TxDC, RxDC, SCK, CSN, SDI, SDO,
INTN, RSTN, UVN_VOUT)
0
VOUT
V
Tjunc_op
Junction temperature
−40
+150
°C
Vop_VCC_CAN_normal
Vop_VCC_CAN_lowpower
Vop_WU
Vop_CFG;
Vop_SWDM
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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39
NCV7471, NCV7471A
ELECTRICAL CHARACTERISTICS
The characteristics defined in this section are guaranteed within the operating ranges listed in Table 27, unless stated
otherwise. Positive currents flow into the respective pin.
Power Supply
Table 28. SUPPLY MONITORING ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V_MID_PORH
V_MID threshold for the power−up of the circuit
V_MID rising
3.3
3.7
4
V
V_MID_PORL
V_MID threshold for the shut−down of the circuit
V_MID falling
2.2
2.65
3
V
VS_MON
Monitoring level on VS pin defining the operation
of the LIN transceivers
VS falling
3
5.2
V
VS_MON_hys
Hysteresis of the VS monitor
t_VS_MON_filt
VS monitoring filter time
0.12
16
25
ms
4.65
4.75
V
VOUT_RES1
VOUT monitoring threshold 1
VOUT falling
VOUT_RES2
VOUT monitoring threshold 2
VOUT falling
3.8
3.9
4.0
V
VOUT_RES3
VOUT monitoring threshold 3
VOUT falling
3.35
3.45
3.55
V
VOUT_RES4
VOUT monitoring threshold 4
VOUT falling
3.0
3.1
3.2
V
0.03
0.1
0.14
V
VOUT_RES_hys
VOUT_FAIL
t_VOUT_UV_filt
t_VOUT_powerup
t_VOUT_reset
VOUT2_UV
VOUT monitoring threshold hysteresis
VOUT failure threshold
4.55
V
VOUT rising
2
Undervoltage detection filter time
V
16
25
ms
VOUT undervoltage time−out for short−circuit recognition w.r.t. VOUT_FAIL threshold
1.35
1.5
1.65
s
RSTN pulse extension
4.5
5
5.5
ms
4.45
4.65
4.75
V
25
ms
VOUT2 under−voltage threshold
VOUT2 falling
VOUT2_UV_hys
VOUT2 under−voltage threshold hysteresis
0.1
t_VOUT2_UV_filt
Undervoltage detection filter time
16
VOUT2 over−voltage threshold
7
V
V
VOUT2_OV
VOUT2_OV_hys
VOUT2 over−voltage threshold hysteresis
0.1
t_VOUT2_OV_filt
Overvoltage detection filter time
32
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40
V
50
ms
NCV7471, NCV7471A
Table 29. DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4.9
5.0
5.1
V
500
mA
1.6
1.6
2.2
2.0
A
0.8
1.0
A
VOUT
DCDC output voltage
NCV7471(A) in Normal or Standby;
Suitable external components for
the required load current and input
voltage used.
I_OUT
DCDC output current available for external loads (see Figure 2)
NCV7471(A) in Normal or Standby;
function of external components
Imaxpeak_BOOST
Maximum peak−current detection
threshold in BOOST stage
Imaxpeak_BUCK
Maximum peak−current detection
threshold in BUCK stage
V_MID_reg
Ron_BOOST
Tj ≤ 0°C
Tj > 0°C
Middle voltage level
Boosting active
Ron_BUCK
On−resistance of the buck−stage switch
V_MID_Ron
V_MID level for parametrical on−resistance of the converter switches
fsw_DCDC
Constant switching frequency
fmod_DCDC
6.175
6.5
On−resistance of the boost−stage
switch
6.825
V
0.45
W
0.6
W
5
Modulation enabled via SPI
Modulation frequency
V
450
485
520
kHz
8
10
13
kHz
dmod_DCDC_1
Modulation depth 1
10
%
dmod_DCDC_2
Modulation depth 2
20
%
dmod_DCDC_3
Modulation depth 3
30
%
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 30. VOUT2 REGULATOR ELECTRICAL CHARACTERISTICS
Symbol
VOUT2
Parameter
VOUT2 regulator output voltage
Conditions
Min
Typ
Max
Unit
VOUT2 regulator active;
Iload(VOUT2) ≤ 5 mA
4.95
5.0
5.05
V
VOUT2 regulator active;
Iload(VOUT2) ≤ 50 mA
4.9
5.0
5.1
V
0.35
0.6
V
−80
mA
VOUT2_drop
Drop−out voltage between VS_VOUT2
and VOUT2
Iload(VOUT2) = 50 mA
Ilim_VOUT2
VOUT2 current limitation
VOUT2 regulator active
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NCV7471, NCV7471A
Table 31. CURRENT CONSUMPTIONS
Symbol
Parameter
Conditions
I_VS
(Note 14)
VS consumption in LIN normal mode
I_VS_VOUT2
(Note 14)
I_VCC_CAN
(Note 14)
I_IN
(Notes 14, 16)
Min
Typ
Max
Unit
LIN1 and LIN2 in Normal mode;
recessive on both LIN buses
3.2
mA
VS consumption with LIN in
Wakeup or Off mode
LIN1 and LIN2 in LIN−wakeup or Off mode;
no activity on both LIN buses
8
mA
VS_VOUT2 consumption if
VOUT2 is on
VOUT2 regulator is active
30 mA
+
1.1 x
I(VOUT2)
−
VS_VOUT2 consumption if
VOUT2 is off
VOUT2 regulator is off;
VS_VOUT2 ≤ 13.5 V; Tj ≤ 85°C
1
mA
VCC_CAN consumption for
dominant transmission
CAN in Normal mode driving dominant on
the CAN bus; 60 W load on the CAN pins
75
mA
VCC_CAN consumption for
recessive transmission
CAN in Receive−only mode or CAN in
Normal mode with recessive on the bus
10
mA
VCC_CAN consumption in
CAN Wakeup mode
CAN Wakeup mode
(CAN supplied from V_MID);
Device in Standby or Sleep mode;
no wakeup detected
2
mA
DCDC input current in
Standby or Normal mode
NCV7471(A) in Standby or Normal mode;
V_IN (Note 15) = 13.5 V; Tj ≤ 85°C;
no external VOUT load
enBoost = Low;
CAN in Off mode
70
95
mA
DCDC input current in
Sleep mode
NCV7471(A) in Sleep mode;
5.5 V ≤ V_IN (Note 15) ≤ 18 V; Tj ≤ 85°C;
enBoost = Low;
CAN in Off mode
55
70
mA
I_IN adder for CAN wakeup
NCV7471(A) in Normal, Standby or Sleep
mode; 5.5 V ≤ V_IN (Note 15) ≤ 18 V;
Tj ≤ 85°C; CAN in Wakeup mode
10
mA
I_IN adder for
BOOST stage
NCV7471(A) in Standby or Normal mode;
5.5 V ≤ V_IN (Note 15) ≤ 18 V; Tj ≤ 85°C;
enBoost = High; Boost−stage not switching
10
mA
14. The supply currents are depicted in Figure 2.
15. V_IN is the DCDC input voltage – see Figure 2.
16. I_IN is the total DCDC input current, covering the quiescent consumption of the device (through pins BOOST, V_MID, BUCK and VOUT),
the current into the external load, and the losses associated with the DCDC conversion.
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42
NCV7471, NCV7471A
CAN Transceiver
Table 32. CAN TRANSCEIVER ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CAN TRANSMITTER DC CHARACTERISTICS
Vo(reces)(CANH)
recessive bus voltage at pin CANH
V(TxDC) = VOUT
no load transmitter on
2
2.5
3
V
Vo(reces)(CANH)
recessive bus voltage at pin CANH
no load transmitter off
−0.1
0
0.1
V
Vo(reces)(CANL)
recessive bus voltage at pin CANL
V(TxDC) = VOUT
no load transmitter on
2
2.5
3
V
Vo(reces)(CANL)
recessive bus voltage at pin CANL
no load transmitter off
−0.1
0
0.1
V
Io(reces)(CANH)
recessive output current at pin
CANH
−35 V < V(CANH) < 35 V
(Note 17),
0 V < VCC_CAN < 5.25 V
−2.5
−
2.5
mA
Io(reces)(CANL)
recessive output current at pin
CANL
−35 V < V(CANL) < 35 V
(Note 17),
0 V < VCC_CAN < 5.25 V
−2.5
−
2.5
mA
Vo(dom)(CANH)
dominant output voltage at pin
CANH
V(TxDC) = 0 V
42.5 W < RL < 60 W
3
3.6
4.25
V
Vo(dom)(CANL)
dominant output voltage at pin
CANL
V(TxDC) = 0 V
42.5 W < RL < 60 W
0.5
1.4
1.75
V
Vo(dif)(bus_dom)
differential bus output voltage
(V(CANH) – V(CANL))
V(TxDC) = 0 V
42.5 W < RL < 60 W
1.5
2.25
3
V
Vo(sym)(bus_dom)
bus output voltage symmetry
(V(CANH) + V(CANL))
V(TxDC) = 0 V
0.9
1.1
VCC_CAN
Vo(dif)(bus_rec)
differential bus output voltage
(V(CANH) – V(CANL))
V(TxDC) = VOUT
recessive, no load
−120
0
50
mV
Io(SC)(CANH)
short−circuit output current at pin
CANH
V(CANH) = 0 V,
V(TxDC) = 0 V
−100
−70
−45
mA
Io(SC)(CANL)
short−circuit output current at pin
CANL
V(CANL) = 36 V,
V(TxDC) = 0 V
45
70
100
mA
CAN RECEIVER DC CHARACTERISTICS
Vi(dif)(th)
Differential receiver threshold
voltage
−12 V < V(CANH) < 12 V
−12 V < V(CANL) < 12 V
0.5
0.7
0.9
V
Vihcm(dif)(th)
Differential receiver threshold
voltage for high common mode
−35 V < V(CANH) < 35 V
−35 V < V(CANL) < 35 V
(Note 17)
0.4
0.7
1
V
Ri(cm)CANH
Common mode input resistance at
pin CANH
15
26
37
kW
Ri(cm)CANL
Common mode input resistance at
pin CANL
15
26
37
kW
Ri(cm)(m)
Matching between pin CANH and
pin CANL common mode input
resistance
−3
0
3
%
V(CANH) = V(CANL)
Ri(dif)
Differential input resistance
25
50
75
kW
CI(CANH)
input capacitance at pin CANH
V(TxDC) = VCC_CAN,
not tested in production
−
7.5
20
pF
CI(CANL)
input capacitance at pin CANL
V(TxDC) = VCC_CAN,
not tested in production
−
7.5
20
pF
CI(dif)
differential input capacitance
V(TxDC) = VCC_CAN,
not tested in production
−
3.75
10
pF
17. In production, the parameter is measured for common−mode range from −30 V to +35 V. The common mode range down to −35 V is guaranteed by design.
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NCV7471, NCV7471A
Table 32. CAN TRANSCEIVER ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−5
0
5
mA
−5
0
5
mA
CAN RECEIVER DC CHARACTERISTICS
ILI_CANH
Input leakage current at pin CANH
ILI_CANL
Input leakage current at pin CANL
0 W < R(VCC_CAN to GND)
< 1 MW
V(CANH) = V(CANL) = 5 V
Vi(dif)(th)
Differential receiver threshold
voltage for the wakeup detection
−12 V < V(CANH) < 12 V
−12 V < V(CANL) < 12 V
0.4
0.8
1.15
V
CAN TRANSCEIVER DYNAMIC CHARACTERISTICS
td(TxDC−BusOn)
delay TxDC to bus active
CL = 100 pF
between CANH − CANL
5
85
110
ns
td(TxDC−BusOff)
delay TxDC to bus inactive
CL = 100 pF
between CANH − CANL
5
30
110
ns
td(BusOn−RxDC)
delay bus active to RxDC
C(RxDC) = 15 pF
5
55
110
ns
td(BusOff−RxDC)
delay bus inactive to RxDC
C(RxDC) = 15 pF
5
100
110
ns
tdPD(TxDC−RxDC)dr
Propagation delay TxDC to RxDC
CL = 100 pF
between CANH − CANL
45
245
ns
tdPD(TxDC−RxDC)rd
Propagation delay TxDC to RxDC
CL = 100 pF
between CANH − CANL
45
230
ns
t_CAN_wake_dom
Dominant time for CAN wakeup
LP mode Vdif(dom) > 1.4 V
0.5
2.5
5
ms
LP mode Vdif(dom) > 1.2 V
0.5
3
5.8
ms
t_CAN_wake_rec
Recessive time for CAN wakeup
0.5
2.5
5
ms
t_CAN_wake_timeout
Maximum length of the CAN
wakeup pattern
0.9
1
1.1
ms
T_TxDC_timeout
TxDC dominant time for time out
2.9
3.7
4.5
ms
VTxDC = 0 V
17. In production, the parameter is measured for common−mode range from −30 V to +35 V. The common mode range down to −35 V is guaranteed by design.
recessive
TxDC
recessive
dominant
50%
50%
CANH
CANL
0.9 V
Vdiff=
V(CANH)−V(CANL)
0.5 V
RxDC
td(TxDC−BusOn)
td(TxDC−BusOff)
td(BusOn−RxDC)
td(TxDC−RxDC)rd
td(BusOff−RxDC)
td(TxDC−RxDC)dr
Figure 23. Definition of CAN Dynamic Parameters
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NCV7471, NCV7471A
LIN Transceivers
Table 33. LINx TRANSCEIVER ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.2
V
LINx TRANSMITTER DC CHARACTERISTICS
VLIN_dom_LoSup
LIN dominant output voltage
TxDLx = Low; VS = 7.3 V
VLIN_dom_HiSup
LIN dominant output voltage
TxDLx = Low; VS = 18 V
2.0
V
VLIN_REC
LIN recessive output voltage
TxDLx = High; I(LIN) = 0 mA
VS −
1.2
VS −
0.3
V
ILIN_lim
Short circuit current limitation
VLIN = VS = 18 V
40
200
mA
Rslave
Internal pull−up resistance
LIN Normal or Receive−only mode
20
47
kW
0.4
VS
33
LINx RECEIVER DC CHARACTERISTICS
Vbus_dom
Bus voltage for dominant state
Vbus_rec
Bus voltage for recessive state
Vrec_dom
Receiver threshold
LIN bus going from recessive to dominant
0.4
0.6
VS
Vrec_rec
Receiver threshold
LIN bus going from dominant to recessive
0.4
0.6
VS
Vrec_cnt
Receiver center voltage
(Vrec_dom + Vrec_rec)/2
0.475
0.525
VS
Vrec_hys
Receiver hysteresis
Vrec_rec − Vrec_dom
0.05
0.175
VS
ILIN_off_dom
LIN output current,
bus in dominant state
Normal LIN Mode, Driver Off;
VS = 12 V; VLIN = 0 V
−1
ILIN_off_dom_slp
LIN output current,
bus in dominant state
LIN Wake Mode, VS = 12 V; VLIN = 0 V
−20
ILIN_off_rec
LIN output current,
bus in recessive state
Driver Off;
VS < 18 V; VS < VLIN < 18 V
ILIN_no_GND
LIN current with missing GND
VS = GND = 12 V; 0 V < VLIN < 18 V
ILIN_no_VS
LIN current with missing VS
VS = GND = 0 V; 0 V < VLIN < 18 V
0.6
VS
mA
−15
−1
−2
mA
1
mA
1
mA
5
mA
LINx TRANSCEIVER DYNAMIC CHARACTERISTICS
D1
Duty Cycle 1 =
tBUS_REC(max) / (2 x TBit)
THREC(min) = 0.744 x VS
THDOM(min) = 0.581 x VS
TBit = 50 ms
V(VS) = 7 V to 18 V
0.396
0.5
D2
Duty Cycle 2 =
tBUS_REC(min) / (2 x TBit)
THREC(max) = 0.422 x VS
THDOM(max) = 0.284 x VS
TBit = 50 ms
V(VS) = 7.6 V to 18 V
0.5
0.581
D3
Duty Cycle 3 =
tBUS_REC(max) / (2 x TBit)
THREC(min) = 0.778 x VS
THDOM(min) = 0.616 x VS
TBit = 96 ms
V(VS) = 7 V to 18 V
0.417
0.5
D4
Duty Cycle 4 =
tBUS_REC(min) / (2 x TBit)
THREC(max) = 0.389 x VS
THDOM(max) = 0.251 x VS
TBit = 96 ms
V(VS) = 7.6 V to 18 V
0.5
0.590
T_fall
LIN falling edge
Normal Mode; VS = 12 V
22.5
ms
T_rise
LIN rising edge
Normal Mode; VS = 12 V
22.5
ms
T_sym
LIN slope symmetry
Normal Mode; VS = 12 V
−4
4
ms
Trec_prop_down
Propagation delay of receiver
Falling edge
0.1
6
ms
Rising edge
0.1
6
ms
2
ms
150
ms
Trec_prop_up
Trec_sym
Propagation delay symmetry
Trec_prop_down − Trec_prop_up
−2
t_LIN_wake
Dominant duration for wakeup
LIN in wakeup mode
30
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45
0
90
NCV7471, NCV7471A
Table 33. LINx TRANSCEIVER ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
6
13
20
ms
15
25
pF
LINx TRANSCEIVER DYNAMIC CHARACTERISTICS
T_TxDLx_timeout
TxDLx dominant time−out
TxDLx = Low; LIN dominant time−out enabled
C_LINx
Capacitance of the LINx pins
Guaranteed by design;
not tested in production
TxDLx
tBIT
tBIT
50%
t
LINx
tBUS_dom(max)
tBUS_rec(min)
THRec(max)
THDom(max)
Thresholds of
receiving node 1
THRec(min)
THDom(min)
Thresholds of
receiving node 2
t
tBUS_dom(min)
tBUS_rec(max)
Figure 24. Definition of LINx Duty Cycle Parameters
LINx
100%
60%
40%
60%
40%
0%
T_rise
T_fall
Figure 25. Definition of LINx Edge Parameters
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46
t
NCV7471, NCV7471A
LINx
VS
60% VS
40% VS
t
RxDLx
Trec_prop_down
Trec_prop_up
50%
t
Figure 26. Definition of LINx Receiver Timing Parameters
Digital Control Timing and SPI Timing
Table 34. DIGITAL CONTROL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t_WD_TO
t_WD_WIN
Duration of the total watchdog
period
WD_PER_0 selected in SPI
7.2
8
8.8
ms
WD_PER_1 selected in SPI
14.4
16
17.6
ms
WD_PER_2 selected in SPI
28.8
32
35.2
ms
WD_PER_3 selected in SPI
57.6
64
70.4
ms
WD_PER_4 selected in SPI
115.2
128
140.8
ms
WD_PER_5 selected in SPI
230.4
256
281.6
ms
WD_PER_6 selected in SPI
460.8
512
563.2
ms
WD_PER_7 selected in SPI
921.6
1024
1126.4
ms
FSO_internal = 1
1.125
1.25
1.375
Hz
f_FSO2
FSO2 toggling frequency
dc_FSO2
FSO2 duty cycle
45
50
55
%
f_FSO3
FSO3 toggling frequency
90
100
110
Hz
dc_FSO3
FSO3 duty cycle
18
20
22
%
t_INTN_active
Active (Low) pulse on INTN pin
0.9
1
1.1
ms
t_INTN_inactive
Minimum time between two
consecutive interrupt requests
4.5
5
5.5
ms
t_RSTN_filt
RSTN input signal filter time
1
10
ms
t_RSTN_Clamped_High
Timeout for “RSTN clamped
High” detection
0.9
1
1.1
ms
t_RSTN_Clamped_Low
Timeout for “RSTN clamped
Low” detection
225
250
275
ms
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NCV7471, NCV7471A
Table 35. SPI INTERFACE TIMING CHARACTERISTICS
Symbol
Parameter
Conditions
tCSN_SCK
First SPI clock edge after CSN active
100
ns
tSCK_CSN
Last SPI clock edge to CSN inactive
100
ns
tCSN_SDO
SDO output stable after CSN active
tCSN_High
Inter−frame space (CSN inactive)
10
ms
tSCK_High
Duration of SPI clock High level
100
ns
tSCK_Low
Duration of SPI clock Low level
100
ns
tSCK_per
SPI clock period
250
ns
tSDI_set
Setup time of SDI input towards SPI clock
50
ns
tSDI_hold
Hold time of SDI input towards SPI clock
50
ns
tSCK_SDO
delay of SDO output stable after an SPI clock edge
50
ns
Typ
Max
100
tCSN_SCK
tSCK_per
tSCK_CSN
Unit
ns
tCSN_High
tSCK_Low
tSCK_High
CSN
Min
SCK
SDI
tSDI_set
tSDI_hold
SDO
tCSN_SDO
tSCK_SDO
Figure 27. Definition of SPI Timing Parameters
Thermal Protection
Table 36. THERMAL PROTECTION CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
Tj_WAR
Junction temperature for thermal warning
Conditions
130
140
150
°C
Tj_SD
Junction temperature for thermal shut−down
150
160
170
°C
Typ
Max
Unit
0.8
V
Digital IO Pins
Table 37. ELECTRICAL CHARACTERISTICS OF LOW VOLTAGE DIGITAL INPUTS/OUTPUTS
Symbol
Parameter
Conditions
Min
VinL_pinx
Low−level input threshold
pinx = SDI, SCK, CSN, TxDC,
TxDL1/2, RSTN
0
VinH_pinx
High−level input threshold
VOUT
V
Rpullup_pinx
Integrated pull−up resistor
to VOUT
pinx = CSN, TxDC, TxDL1/2,
INTN, RSTN, UVN_VOUT
55
2
100
185
kW
Rpulldown_pinx
Integrated pull−down resistor
to GND
pinx = SDI, SCK
55
100
185
kW
IoutL_pinx
Low−level output driving
current
pinx is logical Low;
forced Vpinx = 0.4 V;
pinx = SDO, RxDC, RxDL1/2,
RSTN, INTN, UVN_VOUT
2
6
12
mA
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NCV7471, NCV7471A
Table 37. ELECTRICAL CHARACTERISTICS OF LOW VOLTAGE DIGITAL INPUTS/OUTPUTS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IoutH_pinx
High−level output driving
current
pinx is logical High;
forced Vpinx = VOUT−0.4 V;
pinx = SDO, RxDC, RxDL1/2
−12
−6
−2
mA
Ileak_HZ_pinx
Leakage in the tristate
pinx in HZ state;
forced 0 V < Vpinx < VOUT;
pinx = SDO
−10
10
mA
Ileak_OD
Leakage of an open−drain
output
open−drain pinx in High state;
forced Vpinx = VOUT; pinx =
INTN, RSTN, UVN_VOUT
−10
10
mA
V_MID_DigOut_Low
V_MID value guaranteeing
Low level on RSTN and
UVN_VOUT pins
Shut−down mode; RSTN and
UVN_VOUT connected to fixed
5 V through a 10 kW resistor.
1.9
V
2.7
V
VOUT_DigOut_Low
VOUT value guaranteeing
Low level on RSTN and
UVN_VOUT pins
If V_MID > V_MID_DigOut_Low
or VOUT > VOUT_DigOut_Low,
then RSTN and UVN_VOUT
stay below 400 mV
Not tested in production;
guaranteed by design
CFG and SWDM Pins
Table 38. ELECTRICAL CHARACTERISTICS OF CFG AND SWDM INPUTS
Symbol
Parameter
Conditions
Min
VinL_HV_pinx
Low−level input threshold
pinx = CFG, SWDM
VinH_HV_pinx
High−level input threshold
Rpulldown_HV_pinx
Internal pull−down to GND
Typ
Max
Unit
0
0.8
V
2
VS
V
pinx = CFG, SWDM
55
100
185
kW
Typ
Max
Unit
2
mA
FSO Pins
Table 39. FSOx PIN ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
I_FSOx_inactive
FSOx current in inactive state
FSOx inactive (no failure),
or
HZ−part of the FSO2/3 pattern.
0 V < V(FSOx) < 28 V
−2
V_FSOx_active
Voltage drop at FSOx when
active
FSO1 active or
Low−part of the FSO2/3 pattern;
I(FSOx) = 5 mA
0.4
V
FSO1 active or
Low−part of the FSO2/3 pattern;
I(FSOx) = 10 mA
0.8
V
Max
Unit
2
4
V
0.03
0.25
V
WU Pin
Table 40. WU PIN ELECTRICAL CHARACTERISTICS
Symbol
Vth_WU
Parameter
Conditions
WU pin threshold
Min
Typ
Vhys_WU
WU pin threshold hysteresis
t_WU_filt
WU wakeup filter time
10
50
ms
Ipu_WU
Pull−up current on WU pin
V(WU) = 4 V
−11
−3
mA
Ipd_WU
Pull−down current on WU pin
V(WU) = 2 V
3
11
mA
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NCV7471, NCV7471A
Table 41. DEVICE ORDERING INFORMATION
Part Number
NCV7471DQ5G
NCV7471DQ5R2G
NCV7471ADQ5R2G
Description
Package Type
System Basis Chip with Dual LIN,
HS−CAN and 500 mA Boost−Buck DCDC,
FSOx outputs not active during VOUT undervoltage
System Basis Chip with Dual LIN,
HS−CAN and 500 mA Boost−Buck DCDC,
FSOx outputs active during VOUT undervoltage
Shipping†
47 Units / Tube
SSOP36−EP
GREEN
1500 / Tape & Reel
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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50
NCV7471, NCV7471A
PACKAGE DIMENSIONS
SSOP36 EP
CASE 940AB
ISSUE O
0.20 C A-B
D
DETAIL B
A
36
X
19
X = A or B
E1
ÉÉÉ
ÉÉÉ
PIN 1
REFERENCE
1
e/2
E
DETAIL B
36X
0.25 C
18
e
36X
B
b
0.25
M
T A
B
S
S
NOTE 6
TOP VIEW
A
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE b DIMENSION AT MMC.
4. DIMENSION b SHALL BE MEASURED
BETWEEN 0.10 AND 0.25 FROM THE TIP.
5. DIMENSIONS D AND E1 DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. DIMENSIONS D AND E1 SHALL BE
DETERMINED AT DATUM H.
6. THIS CHAMFER FEATURE IS OPTIONAL. IF
IT IS NOT PRESENT, A PIN ONE IDENTIFIER
MUST BE LOACATED WITHIN THE INDICATED AREA.
D
4X
h
A2
DETAIL A
c
h
0.10 C
36X
SIDE VIEW
A1
C
SEATING
PLANE
END VIEW
D2
M1
DIM
A
A1
A2
b
c
D
D2
E
E1
E2
e
h
L
L2
M
M1
MILLIMETERS
MIN
MAX
--2.65
--0.10
2.35
2.60
0.18
0.36
0.23
0.32
10.30 BSC
5.70
5.90
10.30 BSC
7.50 BSC
3.90
4.10
0.50 BSC
0.25
0.75
0.50
0.90
0.25 BSC
0_
8_
5_
15 _
SOLDERING FOOTPRINT
5.90
M
GAUGE
PLANE
E2
L2
C
SEATING
PLANE
36X
DETAIL A
36X
1.06
L
4.10
10.76
BOTTOM VIEW
1
0.50
PITCH
36X
0.36
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
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For additional information, please contact your local
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NCV7471/D